1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
27 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
28 : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
29 TM(tm), RI(tm, *this) {
32 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
34 unsigned& destReg) const {
35 MachineOpCode oc = MI.getOpcode();
36 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
37 oc == X86::MOV32rr || oc == X86::MOV64rr ||
38 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
39 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
40 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
41 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
42 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
43 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
44 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
45 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
46 assert(MI.getNumOperands() >= 2 &&
47 MI.getOperand(0).isRegister() &&
48 MI.getOperand(1).isRegister() &&
49 "invalid register-register move instruction");
50 sourceReg = MI.getOperand(1).getReg();
51 destReg = MI.getOperand(0).getReg();
57 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
58 int &FrameIndex) const {
59 switch (MI->getOpcode()) {
72 case X86::MMX_MOVD64rm:
73 case X86::MMX_MOVQ64rm:
74 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
75 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
76 MI->getOperand(2).getImmedValue() == 1 &&
77 MI->getOperand(3).getReg() == 0 &&
78 MI->getOperand(4).getImmedValue() == 0) {
79 FrameIndex = MI->getOperand(1).getFrameIndex();
80 return MI->getOperand(0).getReg();
87 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
88 int &FrameIndex) const {
89 switch (MI->getOpcode()) {
102 case X86::MMX_MOVD64mr:
103 case X86::MMX_MOVQ64mr:
104 case X86::MMX_MOVNTQmr:
105 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
106 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
107 MI->getOperand(1).getImmedValue() == 1 &&
108 MI->getOperand(2).getReg() == 0 &&
109 MI->getOperand(3).getImmedValue() == 0) {
110 FrameIndex = MI->getOperand(0).getFrameIndex();
111 return MI->getOperand(4).getReg();
119 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
120 switch (MI->getOpcode()) {
133 case X86::MMX_MOVD64rm:
134 case X86::MMX_MOVQ64rm:
135 // Loads from constant pools are trivially rematerializable.
136 return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
137 MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
138 MI->getOperand(1).getReg() == 0 &&
139 MI->getOperand(2).getImmedValue() == 1 &&
140 MI->getOperand(3).getReg() == 0;
142 // All other instructions marked M_REMATERIALIZABLE are always trivially
147 /// isDefinedInEntryBlock - Goes through the entry block to see if the given
148 /// virtual register is indeed defined in the entry block.
150 bool X86InstrInfo::isDefinedInEntryBlock(const MachineBasicBlock &Entry,
151 unsigned VReg) const {
152 assert(MRegisterInfo::isVirtualRegister(VReg) &&
153 "Map only holds virtual registers!");
154 MachineInstrMap.grow(VReg);
155 if (MachineInstrMap[VReg]) return true;
157 MachineBasicBlock::const_iterator I = Entry.begin(), E = Entry.end();
159 for (; I != E; ++I) {
160 const MachineInstr &MI = *I;
161 unsigned NumOps = MI.getNumOperands();
163 for (unsigned i = 0; i < NumOps; ++i) {
164 const MachineOperand &MO = MI.getOperand(i);
166 if(MO.isRegister() && MO.isDef() &&
167 MRegisterInfo::isVirtualRegister(MO.getReg()) &&
168 MO.getReg() == VReg) {
169 MachineInstrMap[VReg] = &MI;
178 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
179 /// method is called to determine if the specific instance of this instruction
180 /// has side effects. This is useful in cases of instructions, like loads, which
181 /// generally always have side effects. A load from a constant pool doesn't have
182 /// side effects, though. So we need to differentiate it from the general case.
183 bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
184 switch (MI->getOpcode()) {
187 if (MI->getOperand(1).isRegister()) {
188 unsigned Reg = MI->getOperand(1).getReg();
190 // Loads from global addresses which aren't redefined in the function are
192 if (MRegisterInfo::isVirtualRegister(Reg) &&
193 isDefinedInEntryBlock(MI->getParent()->getParent()->front(), Reg) &&
194 MI->getOperand(2).isImmediate() &&
195 MI->getOperand(3).isRegister() &&
196 MI->getOperand(4).isGlobalAddress() &&
197 MI->getOperand(2).getImmedValue() == 1 &&
198 MI->getOperand(3).getReg() == 0)
212 case X86::MMX_MOVD64rm:
213 case X86::MMX_MOVQ64rm:
214 // Loads from constant pools have no side effects
215 return MI->getOperand(1).isRegister() &&
216 MI->getOperand(2).isImmediate() &&
217 MI->getOperand(3).isRegister() &&
218 MI->getOperand(4).isConstantPoolIndex() &&
219 MI->getOperand(1).getReg() == 0 &&
220 MI->getOperand(2).getImmedValue() == 1 &&
221 MI->getOperand(3).getReg() == 0;
224 // All other instances of these instructions are presumed to have side
229 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
230 /// is not marked dead.
231 static bool hasLiveCondCodeDef(MachineInstr *MI) {
232 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
233 MachineOperand &MO = MI->getOperand(i);
234 if (MO.isRegister() && MO.isDef() &&
235 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
242 /// convertToThreeAddress - This method must be implemented by targets that
243 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
244 /// may be able to convert a two-address instruction into a true
245 /// three-address instruction on demand. This allows the X86 target (for
246 /// example) to convert ADD and SHL instructions into LEA instructions if they
247 /// would require register copies due to two-addressness.
249 /// This method returns a null pointer if the transformation cannot be
250 /// performed, otherwise it returns the new instruction.
253 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
254 MachineBasicBlock::iterator &MBBI,
255 LiveVariables &LV) const {
256 MachineInstr *MI = MBBI;
257 // All instructions input are two-addr instructions. Get the known operands.
258 unsigned Dest = MI->getOperand(0).getReg();
259 unsigned Src = MI->getOperand(1).getReg();
261 MachineInstr *NewMI = NULL;
262 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
263 // we have better subtarget support, enable the 16-bit LEA generation here.
264 bool DisableLEA16 = true;
266 unsigned MIOpc = MI->getOpcode();
268 case X86::SHUFPSrri: {
269 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
270 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
272 unsigned A = MI->getOperand(0).getReg();
273 unsigned B = MI->getOperand(1).getReg();
274 unsigned C = MI->getOperand(2).getReg();
275 unsigned M = MI->getOperand(3).getImm();
276 if (B != C) return 0;
277 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
281 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
282 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
283 // the flags produced by a shift yet, so this is safe.
284 unsigned Dest = MI->getOperand(0).getReg();
285 unsigned Src = MI->getOperand(1).getReg();
286 unsigned ShAmt = MI->getOperand(2).getImm();
287 if (ShAmt == 0 || ShAmt >= 4) return 0;
289 NewMI = BuildMI(get(X86::LEA64r), Dest)
290 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
294 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
295 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
296 // the flags produced by a shift yet, so this is safe.
297 unsigned Dest = MI->getOperand(0).getReg();
298 unsigned Src = MI->getOperand(1).getReg();
299 unsigned ShAmt = MI->getOperand(2).getImm();
300 if (ShAmt == 0 || ShAmt >= 4) return 0;
302 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
303 X86::LEA64_32r : X86::LEA32r;
304 NewMI = BuildMI(get(Opc), Dest)
305 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
309 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
310 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
311 // the flags produced by a shift yet, so this is safe.
312 unsigned Dest = MI->getOperand(0).getReg();
313 unsigned Src = MI->getOperand(1).getReg();
314 unsigned ShAmt = MI->getOperand(2).getImm();
315 if (ShAmt == 0 || ShAmt >= 4) return 0;
318 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
319 SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
320 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
321 ? X86::LEA64_32r : X86::LEA32r;
322 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
323 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
326 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
327 Ins->copyKillDeadInfo(MI);
329 NewMI = BuildMI(get(Opc), leaOutReg)
330 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
333 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
334 Ext->copyKillDeadInfo(MI);
336 MFI->insert(MBBI, Ins); // Insert the insert_subreg
337 LV.instructionChanged(MI, NewMI); // Update live variables
338 LV.addVirtualRegisterKilled(leaInReg, NewMI);
339 MFI->insert(MBBI, NewMI); // Insert the new inst
340 LV.addVirtualRegisterKilled(leaOutReg, Ext);
341 MFI->insert(MBBI, Ext); // Insert the extract_subreg
344 NewMI = BuildMI(get(X86::LEA16r), Dest)
345 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
350 // The following opcodes also sets the condition code register(s). Only
351 // convert them to equivalent lea if the condition code register def's
353 if (hasLiveCondCodeDef(MI))
356 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
361 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
362 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
363 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
364 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
369 if (DisableLEA16) return 0;
370 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
371 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
375 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
376 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
377 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
378 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
383 if (DisableLEA16) return 0;
384 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
385 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
389 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
390 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
391 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
392 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
393 MI->getOperand(2).getReg());
397 if (DisableLEA16) return 0;
398 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
399 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
400 MI->getOperand(2).getReg());
404 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
405 if (MI->getOperand(2).isImmediate())
406 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
407 MI->getOperand(2).getImmedValue());
411 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
412 if (MI->getOperand(2).isImmediate()) {
413 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
414 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
415 MI->getOperand(2).getImmedValue());
420 if (DisableLEA16) return 0;
421 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
422 if (MI->getOperand(2).isImmediate())
423 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
424 MI->getOperand(2).getImmedValue());
427 if (DisableLEA16) return 0;
430 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
431 "Unknown shl instruction!");
432 unsigned ShAmt = MI->getOperand(2).getImmedValue();
433 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
435 AM.Scale = 1 << ShAmt;
437 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
438 : (MIOpc == X86::SHL32ri
439 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
440 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
448 NewMI->copyKillDeadInfo(MI);
449 LV.instructionChanged(MI, NewMI); // Update live variables
450 MFI->insert(MBBI, NewMI); // Insert the new inst
454 /// commuteInstruction - We have a few instructions that must be hacked on to
457 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
458 switch (MI->getOpcode()) {
459 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
460 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
461 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
462 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
463 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
464 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
467 switch (MI->getOpcode()) {
468 default: assert(0 && "Unreachable!");
469 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
470 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
471 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
472 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
473 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
474 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
476 unsigned Amt = MI->getOperand(3).getImmedValue();
477 unsigned A = MI->getOperand(0).getReg();
478 unsigned B = MI->getOperand(1).getReg();
479 unsigned C = MI->getOperand(2).getReg();
480 bool BisKill = MI->getOperand(1).isKill();
481 bool CisKill = MI->getOperand(2).isKill();
482 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
483 .addReg(B, false, false, BisKill).addImm(Size-Amt);
488 case X86::CMOVAE16rr:
489 case X86::CMOVAE32rr:
490 case X86::CMOVAE64rr:
494 case X86::CMOVNE16rr:
495 case X86::CMOVNE32rr:
496 case X86::CMOVNE64rr:
497 case X86::CMOVBE16rr:
498 case X86::CMOVBE32rr:
499 case X86::CMOVBE64rr:
506 case X86::CMOVGE16rr:
507 case X86::CMOVGE32rr:
508 case X86::CMOVGE64rr:
509 case X86::CMOVLE16rr:
510 case X86::CMOVLE32rr:
511 case X86::CMOVLE64rr:
518 case X86::CMOVNS16rr:
519 case X86::CMOVNS32rr:
520 case X86::CMOVNS64rr:
524 case X86::CMOVNP16rr:
525 case X86::CMOVNP32rr:
526 case X86::CMOVNP64rr: {
528 switch (MI->getOpcode()) {
530 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
531 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
532 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
533 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
534 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
535 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
536 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
537 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
538 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
539 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
540 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
541 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
542 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
543 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
544 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
545 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
546 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
547 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
548 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
549 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
550 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
551 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
552 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
553 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
554 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
555 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
556 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
557 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
558 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
559 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
560 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
561 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
562 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
563 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
564 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
565 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
566 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
567 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
568 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
569 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
570 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
571 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
574 MI->setInstrDescriptor(get(Opc));
575 // Fallthrough intended.
578 return TargetInstrInfo::commuteInstruction(MI);
582 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
584 default: return X86::COND_INVALID;
585 case X86::JE: return X86::COND_E;
586 case X86::JNE: return X86::COND_NE;
587 case X86::JL: return X86::COND_L;
588 case X86::JLE: return X86::COND_LE;
589 case X86::JG: return X86::COND_G;
590 case X86::JGE: return X86::COND_GE;
591 case X86::JB: return X86::COND_B;
592 case X86::JBE: return X86::COND_BE;
593 case X86::JA: return X86::COND_A;
594 case X86::JAE: return X86::COND_AE;
595 case X86::JS: return X86::COND_S;
596 case X86::JNS: return X86::COND_NS;
597 case X86::JP: return X86::COND_P;
598 case X86::JNP: return X86::COND_NP;
599 case X86::JO: return X86::COND_O;
600 case X86::JNO: return X86::COND_NO;
604 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
606 default: assert(0 && "Illegal condition code!");
607 case X86::COND_E: return X86::JE;
608 case X86::COND_NE: return X86::JNE;
609 case X86::COND_L: return X86::JL;
610 case X86::COND_LE: return X86::JLE;
611 case X86::COND_G: return X86::JG;
612 case X86::COND_GE: return X86::JGE;
613 case X86::COND_B: return X86::JB;
614 case X86::COND_BE: return X86::JBE;
615 case X86::COND_A: return X86::JA;
616 case X86::COND_AE: return X86::JAE;
617 case X86::COND_S: return X86::JS;
618 case X86::COND_NS: return X86::JNS;
619 case X86::COND_P: return X86::JP;
620 case X86::COND_NP: return X86::JNP;
621 case X86::COND_O: return X86::JO;
622 case X86::COND_NO: return X86::JNO;
626 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
627 /// e.g. turning COND_E to COND_NE.
628 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
630 default: assert(0 && "Illegal condition code!");
631 case X86::COND_E: return X86::COND_NE;
632 case X86::COND_NE: return X86::COND_E;
633 case X86::COND_L: return X86::COND_GE;
634 case X86::COND_LE: return X86::COND_G;
635 case X86::COND_G: return X86::COND_LE;
636 case X86::COND_GE: return X86::COND_L;
637 case X86::COND_B: return X86::COND_AE;
638 case X86::COND_BE: return X86::COND_A;
639 case X86::COND_A: return X86::COND_BE;
640 case X86::COND_AE: return X86::COND_B;
641 case X86::COND_S: return X86::COND_NS;
642 case X86::COND_NS: return X86::COND_S;
643 case X86::COND_P: return X86::COND_NP;
644 case X86::COND_NP: return X86::COND_P;
645 case X86::COND_O: return X86::COND_NO;
646 case X86::COND_NO: return X86::COND_O;
650 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
651 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
652 if (TID->Flags & M_TERMINATOR_FLAG) {
653 // Conditional branch is a special case.
654 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
656 if ((TID->Flags & M_PREDICABLE) == 0)
658 return !isPredicated(MI);
663 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
664 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
665 const X86InstrInfo &TII) {
666 if (MI->getOpcode() == X86::FP_REG_KILL)
668 return TII.isUnpredicatedTerminator(MI);
671 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
672 MachineBasicBlock *&TBB,
673 MachineBasicBlock *&FBB,
674 std::vector<MachineOperand> &Cond) const {
675 // If the block has no terminators, it just falls into the block after it.
676 MachineBasicBlock::iterator I = MBB.end();
677 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
680 // Get the last instruction in the block.
681 MachineInstr *LastInst = I;
683 // If there is only one terminator instruction, process it.
684 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
685 if (!isBranch(LastInst->getOpcode()))
688 // If the block ends with a branch there are 3 possibilities:
689 // it's an unconditional, conditional, or indirect branch.
691 if (LastInst->getOpcode() == X86::JMP) {
692 TBB = LastInst->getOperand(0).getMachineBasicBlock();
695 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
696 if (BranchCode == X86::COND_INVALID)
697 return true; // Can't handle indirect branch.
699 // Otherwise, block ends with fall-through condbranch.
700 TBB = LastInst->getOperand(0).getMachineBasicBlock();
701 Cond.push_back(MachineOperand::CreateImm(BranchCode));
705 // Get the instruction before it if it's a terminator.
706 MachineInstr *SecondLastInst = I;
708 // If there are three terminators, we don't know what sort of block this is.
709 if (SecondLastInst && I != MBB.begin() &&
710 isBrAnalysisUnpredicatedTerminator(--I, *this))
713 // If the block ends with X86::JMP and a conditional branch, handle it.
714 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
715 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
716 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
717 Cond.push_back(MachineOperand::CreateImm(BranchCode));
718 FBB = LastInst->getOperand(0).getMachineBasicBlock();
722 // If the block ends with two X86::JMPs, handle it. The second one is not
723 // executed, so remove it.
724 if (SecondLastInst->getOpcode() == X86::JMP &&
725 LastInst->getOpcode() == X86::JMP) {
726 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
728 I->eraseFromParent();
732 // Otherwise, can't handle this.
736 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
737 MachineBasicBlock::iterator I = MBB.end();
738 if (I == MBB.begin()) return 0;
740 if (I->getOpcode() != X86::JMP &&
741 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
744 // Remove the branch.
745 I->eraseFromParent();
749 if (I == MBB.begin()) return 1;
751 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
754 // Remove the branch.
755 I->eraseFromParent();
760 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
761 MachineBasicBlock *FBB,
762 const std::vector<MachineOperand> &Cond) const {
763 // Shouldn't be a fall through.
764 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
765 assert((Cond.size() == 1 || Cond.size() == 0) &&
766 "X86 branch conditions have one component!");
768 if (FBB == 0) { // One way branch.
770 // Unconditional branch?
771 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
773 // Conditional branch.
774 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
775 BuildMI(&MBB, get(Opc)).addMBB(TBB);
780 // Two-way Conditional branch.
781 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
782 BuildMI(&MBB, get(Opc)).addMBB(TBB);
783 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
787 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
788 if (MBB.empty()) return false;
790 switch (MBB.back().getOpcode()) {
791 case X86::TCRETURNri:
792 case X86::TCRETURNdi:
793 case X86::RET: // Return.
798 case X86::JMP: // Uncond branch.
799 case X86::JMP32r: // Indirect branch.
800 case X86::JMP64r: // Indirect branch (64-bit).
801 case X86::JMP32m: // Indirect branch through mem.
802 case X86::JMP64m: // Indirect branch through mem (64-bit).
804 default: return false;
809 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
810 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
811 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
815 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
816 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
817 if (Subtarget->is64Bit())
818 return &X86::GR64RegClass;
820 return &X86::GR32RegClass;