1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/MC/MCAsmInfo.h"
38 #define GET_INSTRINFO_CTOR
39 #include "X86GenInstrInfo.inc"
44 NoFusing("disable-spill-fusing",
45 cl::desc("Disable fusing of spill code into instructions"));
47 PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"),
52 ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden);
56 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
57 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
58 ? X86::ADJCALLSTACKDOWN64
59 : X86::ADJCALLSTACKDOWN32),
60 (tm.getSubtarget<X86Subtarget>().is64Bit()
61 ? X86::ADJCALLSTACKUP64
62 : X86::ADJCALLSTACKUP32)),
63 TM(tm), RI(tm, *this) {
65 TB_NOT_REVERSABLE = 1U << 31,
66 TB_FLAGS = TB_NOT_REVERSABLE
69 static const unsigned OpTbl2Addr[][2] = {
70 { X86::ADC32ri, X86::ADC32mi },
71 { X86::ADC32ri8, X86::ADC32mi8 },
72 { X86::ADC32rr, X86::ADC32mr },
73 { X86::ADC64ri32, X86::ADC64mi32 },
74 { X86::ADC64ri8, X86::ADC64mi8 },
75 { X86::ADC64rr, X86::ADC64mr },
76 { X86::ADD16ri, X86::ADD16mi },
77 { X86::ADD16ri8, X86::ADD16mi8 },
78 { X86::ADD16ri_DB, X86::ADD16mi | TB_NOT_REVERSABLE },
79 { X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE },
80 { X86::ADD16rr, X86::ADD16mr },
81 { X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE },
82 { X86::ADD32ri, X86::ADD32mi },
83 { X86::ADD32ri8, X86::ADD32mi8 },
84 { X86::ADD32ri_DB, X86::ADD32mi | TB_NOT_REVERSABLE },
85 { X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE },
86 { X86::ADD32rr, X86::ADD32mr },
87 { X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE },
88 { X86::ADD64ri32, X86::ADD64mi32 },
89 { X86::ADD64ri8, X86::ADD64mi8 },
90 { X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE },
91 { X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE },
92 { X86::ADD64rr, X86::ADD64mr },
93 { X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE },
94 { X86::ADD8ri, X86::ADD8mi },
95 { X86::ADD8rr, X86::ADD8mr },
96 { X86::AND16ri, X86::AND16mi },
97 { X86::AND16ri8, X86::AND16mi8 },
98 { X86::AND16rr, X86::AND16mr },
99 { X86::AND32ri, X86::AND32mi },
100 { X86::AND32ri8, X86::AND32mi8 },
101 { X86::AND32rr, X86::AND32mr },
102 { X86::AND64ri32, X86::AND64mi32 },
103 { X86::AND64ri8, X86::AND64mi8 },
104 { X86::AND64rr, X86::AND64mr },
105 { X86::AND8ri, X86::AND8mi },
106 { X86::AND8rr, X86::AND8mr },
107 { X86::DEC16r, X86::DEC16m },
108 { X86::DEC32r, X86::DEC32m },
109 { X86::DEC64_16r, X86::DEC64_16m },
110 { X86::DEC64_32r, X86::DEC64_32m },
111 { X86::DEC64r, X86::DEC64m },
112 { X86::DEC8r, X86::DEC8m },
113 { X86::INC16r, X86::INC16m },
114 { X86::INC32r, X86::INC32m },
115 { X86::INC64_16r, X86::INC64_16m },
116 { X86::INC64_32r, X86::INC64_32m },
117 { X86::INC64r, X86::INC64m },
118 { X86::INC8r, X86::INC8m },
119 { X86::NEG16r, X86::NEG16m },
120 { X86::NEG32r, X86::NEG32m },
121 { X86::NEG64r, X86::NEG64m },
122 { X86::NEG8r, X86::NEG8m },
123 { X86::NOT16r, X86::NOT16m },
124 { X86::NOT32r, X86::NOT32m },
125 { X86::NOT64r, X86::NOT64m },
126 { X86::NOT8r, X86::NOT8m },
127 { X86::OR16ri, X86::OR16mi },
128 { X86::OR16ri8, X86::OR16mi8 },
129 { X86::OR16rr, X86::OR16mr },
130 { X86::OR32ri, X86::OR32mi },
131 { X86::OR32ri8, X86::OR32mi8 },
132 { X86::OR32rr, X86::OR32mr },
133 { X86::OR64ri32, X86::OR64mi32 },
134 { X86::OR64ri8, X86::OR64mi8 },
135 { X86::OR64rr, X86::OR64mr },
136 { X86::OR8ri, X86::OR8mi },
137 { X86::OR8rr, X86::OR8mr },
138 { X86::ROL16r1, X86::ROL16m1 },
139 { X86::ROL16rCL, X86::ROL16mCL },
140 { X86::ROL16ri, X86::ROL16mi },
141 { X86::ROL32r1, X86::ROL32m1 },
142 { X86::ROL32rCL, X86::ROL32mCL },
143 { X86::ROL32ri, X86::ROL32mi },
144 { X86::ROL64r1, X86::ROL64m1 },
145 { X86::ROL64rCL, X86::ROL64mCL },
146 { X86::ROL64ri, X86::ROL64mi },
147 { X86::ROL8r1, X86::ROL8m1 },
148 { X86::ROL8rCL, X86::ROL8mCL },
149 { X86::ROL8ri, X86::ROL8mi },
150 { X86::ROR16r1, X86::ROR16m1 },
151 { X86::ROR16rCL, X86::ROR16mCL },
152 { X86::ROR16ri, X86::ROR16mi },
153 { X86::ROR32r1, X86::ROR32m1 },
154 { X86::ROR32rCL, X86::ROR32mCL },
155 { X86::ROR32ri, X86::ROR32mi },
156 { X86::ROR64r1, X86::ROR64m1 },
157 { X86::ROR64rCL, X86::ROR64mCL },
158 { X86::ROR64ri, X86::ROR64mi },
159 { X86::ROR8r1, X86::ROR8m1 },
160 { X86::ROR8rCL, X86::ROR8mCL },
161 { X86::ROR8ri, X86::ROR8mi },
162 { X86::SAR16r1, X86::SAR16m1 },
163 { X86::SAR16rCL, X86::SAR16mCL },
164 { X86::SAR16ri, X86::SAR16mi },
165 { X86::SAR32r1, X86::SAR32m1 },
166 { X86::SAR32rCL, X86::SAR32mCL },
167 { X86::SAR32ri, X86::SAR32mi },
168 { X86::SAR64r1, X86::SAR64m1 },
169 { X86::SAR64rCL, X86::SAR64mCL },
170 { X86::SAR64ri, X86::SAR64mi },
171 { X86::SAR8r1, X86::SAR8m1 },
172 { X86::SAR8rCL, X86::SAR8mCL },
173 { X86::SAR8ri, X86::SAR8mi },
174 { X86::SBB32ri, X86::SBB32mi },
175 { X86::SBB32ri8, X86::SBB32mi8 },
176 { X86::SBB32rr, X86::SBB32mr },
177 { X86::SBB64ri32, X86::SBB64mi32 },
178 { X86::SBB64ri8, X86::SBB64mi8 },
179 { X86::SBB64rr, X86::SBB64mr },
180 { X86::SHL16rCL, X86::SHL16mCL },
181 { X86::SHL16ri, X86::SHL16mi },
182 { X86::SHL32rCL, X86::SHL32mCL },
183 { X86::SHL32ri, X86::SHL32mi },
184 { X86::SHL64rCL, X86::SHL64mCL },
185 { X86::SHL64ri, X86::SHL64mi },
186 { X86::SHL8rCL, X86::SHL8mCL },
187 { X86::SHL8ri, X86::SHL8mi },
188 { X86::SHLD16rrCL, X86::SHLD16mrCL },
189 { X86::SHLD16rri8, X86::SHLD16mri8 },
190 { X86::SHLD32rrCL, X86::SHLD32mrCL },
191 { X86::SHLD32rri8, X86::SHLD32mri8 },
192 { X86::SHLD64rrCL, X86::SHLD64mrCL },
193 { X86::SHLD64rri8, X86::SHLD64mri8 },
194 { X86::SHR16r1, X86::SHR16m1 },
195 { X86::SHR16rCL, X86::SHR16mCL },
196 { X86::SHR16ri, X86::SHR16mi },
197 { X86::SHR32r1, X86::SHR32m1 },
198 { X86::SHR32rCL, X86::SHR32mCL },
199 { X86::SHR32ri, X86::SHR32mi },
200 { X86::SHR64r1, X86::SHR64m1 },
201 { X86::SHR64rCL, X86::SHR64mCL },
202 { X86::SHR64ri, X86::SHR64mi },
203 { X86::SHR8r1, X86::SHR8m1 },
204 { X86::SHR8rCL, X86::SHR8mCL },
205 { X86::SHR8ri, X86::SHR8mi },
206 { X86::SHRD16rrCL, X86::SHRD16mrCL },
207 { X86::SHRD16rri8, X86::SHRD16mri8 },
208 { X86::SHRD32rrCL, X86::SHRD32mrCL },
209 { X86::SHRD32rri8, X86::SHRD32mri8 },
210 { X86::SHRD64rrCL, X86::SHRD64mrCL },
211 { X86::SHRD64rri8, X86::SHRD64mri8 },
212 { X86::SUB16ri, X86::SUB16mi },
213 { X86::SUB16ri8, X86::SUB16mi8 },
214 { X86::SUB16rr, X86::SUB16mr },
215 { X86::SUB32ri, X86::SUB32mi },
216 { X86::SUB32ri8, X86::SUB32mi8 },
217 { X86::SUB32rr, X86::SUB32mr },
218 { X86::SUB64ri32, X86::SUB64mi32 },
219 { X86::SUB64ri8, X86::SUB64mi8 },
220 { X86::SUB64rr, X86::SUB64mr },
221 { X86::SUB8ri, X86::SUB8mi },
222 { X86::SUB8rr, X86::SUB8mr },
223 { X86::XOR16ri, X86::XOR16mi },
224 { X86::XOR16ri8, X86::XOR16mi8 },
225 { X86::XOR16rr, X86::XOR16mr },
226 { X86::XOR32ri, X86::XOR32mi },
227 { X86::XOR32ri8, X86::XOR32mi8 },
228 { X86::XOR32rr, X86::XOR32mr },
229 { X86::XOR64ri32, X86::XOR64mi32 },
230 { X86::XOR64ri8, X86::XOR64mi8 },
231 { X86::XOR64rr, X86::XOR64mr },
232 { X86::XOR8ri, X86::XOR8mi },
233 { X86::XOR8rr, X86::XOR8mr }
236 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
237 unsigned RegOp = OpTbl2Addr[i][0];
238 unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS;
239 assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?");
240 RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U);
242 // If this is not a reversible operation (because there is a many->one)
243 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
244 if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE)
247 // Index 0, folded load and store, no alignment requirement.
248 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
250 assert(!MemOp2RegOpTable.count(MemOp) &&
251 "Duplicated entries in unfolding maps?");
252 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
255 // If the third value is 1, then it's folding either a load or a store.
256 static const unsigned OpTbl0[][4] = {
257 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
258 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
259 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
260 { X86::CALL32r, X86::CALL32m, 1, 0 },
261 { X86::CALL64r, X86::CALL64m, 1, 0 },
262 { X86::WINCALL64r, X86::WINCALL64m, 1, 0 },
263 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
264 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
265 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
266 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
267 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
268 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
269 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
270 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
271 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
272 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
273 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
274 { X86::DIV16r, X86::DIV16m, 1, 0 },
275 { X86::DIV32r, X86::DIV32m, 1, 0 },
276 { X86::DIV64r, X86::DIV64m, 1, 0 },
277 { X86::DIV8r, X86::DIV8m, 1, 0 },
278 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
279 { X86::FsMOVAPDrr, X86::MOVSDmr | TB_NOT_REVERSABLE , 0, 0 },
280 { X86::FsMOVAPSrr, X86::MOVSSmr | TB_NOT_REVERSABLE , 0, 0 },
281 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
282 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
283 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
284 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
285 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
286 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
287 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
288 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
289 { X86::JMP32r, X86::JMP32m, 1, 0 },
290 { X86::JMP64r, X86::JMP64m, 1, 0 },
291 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
292 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
293 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
294 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
295 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
296 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
297 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
298 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
299 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
300 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
301 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
302 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
303 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, 0, 32 },
304 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, 0, 32 },
305 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, 0, 32 },
306 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
307 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
308 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
309 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
310 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
311 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
312 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, 0, 0 },
313 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, 0, 0 },
314 { X86::MUL16r, X86::MUL16m, 1, 0 },
315 { X86::MUL32r, X86::MUL32m, 1, 0 },
316 { X86::MUL64r, X86::MUL64m, 1, 0 },
317 { X86::MUL8r, X86::MUL8m, 1, 0 },
318 { X86::SETAEr, X86::SETAEm, 0, 0 },
319 { X86::SETAr, X86::SETAm, 0, 0 },
320 { X86::SETBEr, X86::SETBEm, 0, 0 },
321 { X86::SETBr, X86::SETBm, 0, 0 },
322 { X86::SETEr, X86::SETEm, 0, 0 },
323 { X86::SETGEr, X86::SETGEm, 0, 0 },
324 { X86::SETGr, X86::SETGm, 0, 0 },
325 { X86::SETLEr, X86::SETLEm, 0, 0 },
326 { X86::SETLr, X86::SETLm, 0, 0 },
327 { X86::SETNEr, X86::SETNEm, 0, 0 },
328 { X86::SETNOr, X86::SETNOm, 0, 0 },
329 { X86::SETNPr, X86::SETNPm, 0, 0 },
330 { X86::SETNSr, X86::SETNSm, 0, 0 },
331 { X86::SETOr, X86::SETOm, 0, 0 },
332 { X86::SETPr, X86::SETPm, 0, 0 },
333 { X86::SETSr, X86::SETSm, 0, 0 },
334 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
335 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
336 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
337 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
338 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
339 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
342 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
343 unsigned RegOp = OpTbl0[i][0];
344 unsigned MemOp = OpTbl0[i][1] & ~TB_FLAGS;
345 unsigned FoldedLoad = OpTbl0[i][2];
346 unsigned Align = OpTbl0[i][3];
347 assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?");
348 RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align);
350 // If this is not a reversible operation (because there is a many->one)
351 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
352 if (OpTbl0[i][1] & TB_NOT_REVERSABLE)
355 // Index 0, folded load or store.
356 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
357 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?");
358 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
361 static const unsigned OpTbl1[][3] = {
362 { X86::CMP16rr, X86::CMP16rm, 0 },
363 { X86::CMP32rr, X86::CMP32rm, 0 },
364 { X86::CMP64rr, X86::CMP64rm, 0 },
365 { X86::CMP8rr, X86::CMP8rm, 0 },
366 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
367 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
368 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
369 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
370 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
371 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
372 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
373 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
374 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
375 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
376 { X86::FsMOVAPDrr, X86::MOVSDrm | TB_NOT_REVERSABLE , 0 },
377 { X86::FsMOVAPSrr, X86::MOVSSrm | TB_NOT_REVERSABLE , 0 },
378 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
379 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
380 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
381 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
382 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
383 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
384 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
385 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
386 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
387 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
388 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
389 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
390 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
391 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
392 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
393 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
394 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
395 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
396 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
397 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
398 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
399 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
400 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, 16 },
401 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, 16 },
402 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
403 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
404 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
405 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
406 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
407 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
408 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
409 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
410 { X86::MOV16rr, X86::MOV16rm, 0 },
411 { X86::MOV32rr, X86::MOV32rm, 0 },
412 { X86::MOV64rr, X86::MOV64rm, 0 },
413 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
414 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
415 { X86::MOV8rr, X86::MOV8rm, 0 },
416 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
417 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
418 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, 32 },
419 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, 32 },
420 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
421 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
422 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
423 { X86::MOVDQArr, X86::MOVDQArm, 16 },
424 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, 16 },
425 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
426 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
427 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
428 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
429 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
430 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
431 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
432 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
433 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
434 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
435 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
436 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
437 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
438 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
439 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
440 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
441 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
442 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
443 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
444 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
445 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
446 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
447 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
448 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
449 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
450 { X86::RCPPSr, X86::RCPPSm, 16 },
451 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
452 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
453 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
454 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
455 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
456 { X86::SQRTPDr, X86::SQRTPDm, 16 },
457 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
458 { X86::SQRTPSr, X86::SQRTPSm, 16 },
459 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
460 { X86::SQRTSDr, X86::SQRTSDm, 0 },
461 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
462 { X86::SQRTSSr, X86::SQRTSSm, 0 },
463 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
464 { X86::TEST16rr, X86::TEST16rm, 0 },
465 { X86::TEST32rr, X86::TEST32rm, 0 },
466 { X86::TEST64rr, X86::TEST64rm, 0 },
467 { X86::TEST8rr, X86::TEST8rm, 0 },
468 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
469 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
470 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
471 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
472 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }
475 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
476 unsigned RegOp = OpTbl1[i][0];
477 unsigned MemOp = OpTbl1[i][1] & ~TB_FLAGS;
478 unsigned Align = OpTbl1[i][2];
479 assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries");
480 RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align);
482 // If this is not a reversible operation (because there is a many->one)
483 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
484 if (OpTbl1[i][1] & TB_NOT_REVERSABLE)
487 // Index 1, folded load
488 unsigned AuxInfo = 1 | (1 << 4);
489 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries");
490 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
493 static const unsigned OpTbl2[][3] = {
494 { X86::ADC32rr, X86::ADC32rm, 0 },
495 { X86::ADC64rr, X86::ADC64rm, 0 },
496 { X86::ADD16rr, X86::ADD16rm, 0 },
497 { X86::ADD16rr_DB, X86::ADD16rm | TB_NOT_REVERSABLE, 0 },
498 { X86::ADD32rr, X86::ADD32rm, 0 },
499 { X86::ADD32rr_DB, X86::ADD32rm | TB_NOT_REVERSABLE, 0 },
500 { X86::ADD64rr, X86::ADD64rm, 0 },
501 { X86::ADD64rr_DB, X86::ADD64rm | TB_NOT_REVERSABLE, 0 },
502 { X86::ADD8rr, X86::ADD8rm, 0 },
503 { X86::ADDPDrr, X86::ADDPDrm, 16 },
504 { X86::ADDPSrr, X86::ADDPSrm, 16 },
505 { X86::ADDSDrr, X86::ADDSDrm, 0 },
506 { X86::ADDSSrr, X86::ADDSSrm, 0 },
507 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
508 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
509 { X86::AND16rr, X86::AND16rm, 0 },
510 { X86::AND32rr, X86::AND32rm, 0 },
511 { X86::AND64rr, X86::AND64rm, 0 },
512 { X86::AND8rr, X86::AND8rm, 0 },
513 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
514 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
515 { X86::ANDPDrr, X86::ANDPDrm, 16 },
516 { X86::ANDPSrr, X86::ANDPSrm, 16 },
517 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
518 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
519 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
520 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
521 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
522 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
523 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
524 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
525 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
526 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
527 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
528 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
529 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
530 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
531 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
532 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
533 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
534 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
535 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
536 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
537 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
538 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
539 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
540 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
541 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
542 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
543 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
544 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
545 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
546 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
547 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
548 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
549 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
550 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
551 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
552 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
553 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
554 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
555 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
556 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
557 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
558 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
559 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
560 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
561 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
562 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
563 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
564 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
565 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
566 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
567 { X86::CMPSDrr, X86::CMPSDrm, 0 },
568 { X86::CMPSSrr, X86::CMPSSrm, 0 },
569 { X86::DIVPDrr, X86::DIVPDrm, 16 },
570 { X86::DIVPSrr, X86::DIVPSrm, 16 },
571 { X86::DIVSDrr, X86::DIVSDrm, 0 },
572 { X86::DIVSSrr, X86::DIVSSrm, 0 },
573 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
574 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
575 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
576 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
577 { X86::FsORPDrr, X86::FsORPDrm, 16 },
578 { X86::FsORPSrr, X86::FsORPSrm, 16 },
579 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
580 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
581 { X86::HADDPDrr, X86::HADDPDrm, 16 },
582 { X86::HADDPSrr, X86::HADDPSrm, 16 },
583 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
584 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
585 { X86::IMUL16rr, X86::IMUL16rm, 0 },
586 { X86::IMUL32rr, X86::IMUL32rm, 0 },
587 { X86::IMUL64rr, X86::IMUL64rm, 0 },
588 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
589 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
590 { X86::MAXPDrr, X86::MAXPDrm, 16 },
591 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
592 { X86::MAXPSrr, X86::MAXPSrm, 16 },
593 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
594 { X86::MAXSDrr, X86::MAXSDrm, 0 },
595 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
596 { X86::MAXSSrr, X86::MAXSSrm, 0 },
597 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
598 { X86::MINPDrr, X86::MINPDrm, 16 },
599 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
600 { X86::MINPSrr, X86::MINPSrm, 16 },
601 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
602 { X86::MINSDrr, X86::MINSDrm, 0 },
603 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
604 { X86::MINSSrr, X86::MINSSrm, 0 },
605 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
606 { X86::MULPDrr, X86::MULPDrm, 16 },
607 { X86::MULPSrr, X86::MULPSrm, 16 },
608 { X86::MULSDrr, X86::MULSDrm, 0 },
609 { X86::MULSSrr, X86::MULSSrm, 0 },
610 { X86::OR16rr, X86::OR16rm, 0 },
611 { X86::OR32rr, X86::OR32rm, 0 },
612 { X86::OR64rr, X86::OR64rm, 0 },
613 { X86::OR8rr, X86::OR8rm, 0 },
614 { X86::ORPDrr, X86::ORPDrm, 16 },
615 { X86::ORPSrr, X86::ORPSrm, 16 },
616 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
617 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
618 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
619 { X86::PADDBrr, X86::PADDBrm, 16 },
620 { X86::PADDDrr, X86::PADDDrm, 16 },
621 { X86::PADDQrr, X86::PADDQrm, 16 },
622 { X86::PADDSBrr, X86::PADDSBrm, 16 },
623 { X86::PADDSWrr, X86::PADDSWrm, 16 },
624 { X86::PADDWrr, X86::PADDWrm, 16 },
625 { X86::PANDNrr, X86::PANDNrm, 16 },
626 { X86::PANDrr, X86::PANDrm, 16 },
627 { X86::PAVGBrr, X86::PAVGBrm, 16 },
628 { X86::PAVGWrr, X86::PAVGWrm, 16 },
629 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
630 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
631 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
632 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
633 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
634 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
635 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
636 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
637 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
638 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
639 { X86::PMINSWrr, X86::PMINSWrm, 16 },
640 { X86::PMINUBrr, X86::PMINUBrm, 16 },
641 { X86::PMULDQrr, X86::PMULDQrm, 16 },
642 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
643 { X86::PMULHWrr, X86::PMULHWrm, 16 },
644 { X86::PMULLDrr, X86::PMULLDrm, 16 },
645 { X86::PMULLWrr, X86::PMULLWrm, 16 },
646 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
647 { X86::PORrr, X86::PORrm, 16 },
648 { X86::PSADBWrr, X86::PSADBWrm, 16 },
649 { X86::PSLLDrr, X86::PSLLDrm, 16 },
650 { X86::PSLLQrr, X86::PSLLQrm, 16 },
651 { X86::PSLLWrr, X86::PSLLWrm, 16 },
652 { X86::PSRADrr, X86::PSRADrm, 16 },
653 { X86::PSRAWrr, X86::PSRAWrm, 16 },
654 { X86::PSRLDrr, X86::PSRLDrm, 16 },
655 { X86::PSRLQrr, X86::PSRLQrm, 16 },
656 { X86::PSRLWrr, X86::PSRLWrm, 16 },
657 { X86::PSUBBrr, X86::PSUBBrm, 16 },
658 { X86::PSUBDrr, X86::PSUBDrm, 16 },
659 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
660 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
661 { X86::PSUBWrr, X86::PSUBWrm, 16 },
662 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
663 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
664 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
665 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
666 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
667 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
668 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
669 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
670 { X86::PXORrr, X86::PXORrm, 16 },
671 { X86::SBB32rr, X86::SBB32rm, 0 },
672 { X86::SBB64rr, X86::SBB64rm, 0 },
673 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
674 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
675 { X86::SUB16rr, X86::SUB16rm, 0 },
676 { X86::SUB32rr, X86::SUB32rm, 0 },
677 { X86::SUB64rr, X86::SUB64rm, 0 },
678 { X86::SUB8rr, X86::SUB8rm, 0 },
679 { X86::SUBPDrr, X86::SUBPDrm, 16 },
680 { X86::SUBPSrr, X86::SUBPSrm, 16 },
681 { X86::SUBSDrr, X86::SUBSDrm, 0 },
682 { X86::SUBSSrr, X86::SUBSSrm, 0 },
683 // FIXME: TEST*rr -> swapped operand of TEST*mr.
684 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
685 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
686 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
687 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
688 { X86::XOR16rr, X86::XOR16rm, 0 },
689 { X86::XOR32rr, X86::XOR32rm, 0 },
690 { X86::XOR64rr, X86::XOR64rm, 0 },
691 { X86::XOR8rr, X86::XOR8rm, 0 },
692 { X86::XORPDrr, X86::XORPDrm, 16 },
693 { X86::XORPSrr, X86::XORPSrm, 16 }
696 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
697 unsigned RegOp = OpTbl2[i][0];
698 unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS;
699 unsigned Align = OpTbl2[i][2];
701 assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!");
702 RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align);
704 // If this is not a reversible operation (because there is a many->one)
705 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
706 if (OpTbl2[i][1] & TB_NOT_REVERSABLE)
709 // Index 2, folded load
710 unsigned AuxInfo = 2 | (1 << 4);
711 assert(!MemOp2RegOpTable.count(MemOp) &&
712 "Duplicated entries in unfolding maps?");
713 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
718 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
719 unsigned &SrcReg, unsigned &DstReg,
720 unsigned &SubIdx) const {
721 switch (MI.getOpcode()) {
723 case X86::MOVSX16rr8:
724 case X86::MOVZX16rr8:
725 case X86::MOVSX32rr8:
726 case X86::MOVZX32rr8:
727 case X86::MOVSX64rr8:
728 case X86::MOVZX64rr8:
729 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
730 // It's not always legal to reference the low 8-bit of the larger
731 // register in 32-bit mode.
733 case X86::MOVSX32rr16:
734 case X86::MOVZX32rr16:
735 case X86::MOVSX64rr16:
736 case X86::MOVZX64rr16:
737 case X86::MOVSX64rr32:
738 case X86::MOVZX64rr32: {
739 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
742 SrcReg = MI.getOperand(1).getReg();
743 DstReg = MI.getOperand(0).getReg();
744 switch (MI.getOpcode()) {
748 case X86::MOVSX16rr8:
749 case X86::MOVZX16rr8:
750 case X86::MOVSX32rr8:
751 case X86::MOVZX32rr8:
752 case X86::MOVSX64rr8:
753 case X86::MOVZX64rr8:
754 SubIdx = X86::sub_8bit;
756 case X86::MOVSX32rr16:
757 case X86::MOVZX32rr16:
758 case X86::MOVSX64rr16:
759 case X86::MOVZX64rr16:
760 SubIdx = X86::sub_16bit;
762 case X86::MOVSX64rr32:
763 case X86::MOVZX64rr32:
764 SubIdx = X86::sub_32bit;
773 /// isFrameOperand - Return true and the FrameIndex if the specified
774 /// operand and follow operands form a reference to the stack frame.
775 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
776 int &FrameIndex) const {
777 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
778 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
779 MI->getOperand(Op+1).getImm() == 1 &&
780 MI->getOperand(Op+2).getReg() == 0 &&
781 MI->getOperand(Op+3).getImm() == 0) {
782 FrameIndex = MI->getOperand(Op).getIndex();
788 static bool isFrameLoadOpcode(int Opcode) {
801 case X86::VMOVAPSYrm:
802 case X86::VMOVAPDYrm:
803 case X86::VMOVDQAYrm:
804 case X86::MMX_MOVD64rm:
805 case X86::MMX_MOVQ64rm:
812 static bool isFrameStoreOpcode(int Opcode) {
825 case X86::VMOVAPSYmr:
826 case X86::VMOVAPDYmr:
827 case X86::VMOVDQAYmr:
828 case X86::MMX_MOVD64mr:
829 case X86::MMX_MOVQ64mr:
830 case X86::MMX_MOVNTQmr:
836 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
837 int &FrameIndex) const {
838 if (isFrameLoadOpcode(MI->getOpcode()))
839 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
840 return MI->getOperand(0).getReg();
844 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
845 int &FrameIndex) const {
846 if (isFrameLoadOpcode(MI->getOpcode())) {
848 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
850 // Check for post-frame index elimination operations
851 const MachineMemOperand *Dummy;
852 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
857 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
858 int &FrameIndex) const {
859 if (isFrameStoreOpcode(MI->getOpcode()))
860 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
861 isFrameOperand(MI, 0, FrameIndex))
862 return MI->getOperand(X86::AddrNumOperands).getReg();
866 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
867 int &FrameIndex) const {
868 if (isFrameStoreOpcode(MI->getOpcode())) {
870 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
872 // Check for post-frame index elimination operations
873 const MachineMemOperand *Dummy;
874 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
879 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
881 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
882 bool isPICBase = false;
883 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
884 E = MRI.def_end(); I != E; ++I) {
885 MachineInstr *DefMI = I.getOperand().getParent();
886 if (DefMI->getOpcode() != X86::MOVPC32r)
888 assert(!isPICBase && "More than one PIC base?");
895 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
896 AliasAnalysis *AA) const {
897 switch (MI->getOpcode()) {
910 case X86::VMOVAPSYrm:
911 case X86::VMOVUPSYrm:
912 case X86::VMOVAPDYrm:
913 case X86::VMOVDQAYrm:
914 case X86::MMX_MOVD64rm:
915 case X86::MMX_MOVQ64rm:
916 case X86::FsMOVAPSrm:
917 case X86::FsMOVAPDrm: {
918 // Loads from constant pools are trivially rematerializable.
919 if (MI->getOperand(1).isReg() &&
920 MI->getOperand(2).isImm() &&
921 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
922 MI->isInvariantLoad(AA)) {
923 unsigned BaseReg = MI->getOperand(1).getReg();
924 if (BaseReg == 0 || BaseReg == X86::RIP)
926 // Allow re-materialization of PIC load.
927 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
929 const MachineFunction &MF = *MI->getParent()->getParent();
930 const MachineRegisterInfo &MRI = MF.getRegInfo();
931 bool isPICBase = false;
932 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
933 E = MRI.def_end(); I != E; ++I) {
934 MachineInstr *DefMI = I.getOperand().getParent();
935 if (DefMI->getOpcode() != X86::MOVPC32r)
937 assert(!isPICBase && "More than one PIC base?");
947 if (MI->getOperand(2).isImm() &&
948 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
949 !MI->getOperand(4).isReg()) {
950 // lea fi#, lea GV, etc. are all rematerializable.
951 if (!MI->getOperand(1).isReg())
953 unsigned BaseReg = MI->getOperand(1).getReg();
956 // Allow re-materialization of lea PICBase + x.
957 const MachineFunction &MF = *MI->getParent()->getParent();
958 const MachineRegisterInfo &MRI = MF.getRegInfo();
959 return regIsPICBase(BaseReg, MRI);
965 // All other instructions marked M_REMATERIALIZABLE are always trivially
970 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
971 /// would clobber the EFLAGS condition register. Note the result may be
972 /// conservative. If it cannot definitely determine the safety after visiting
973 /// a few instructions in each direction it assumes it's not safe.
974 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
975 MachineBasicBlock::iterator I) {
976 MachineBasicBlock::iterator E = MBB.end();
978 // It's always safe to clobber EFLAGS at the end of a block.
982 // For compile time consideration, if we are not able to determine the
983 // safety after visiting 4 instructions in each direction, we will assume
985 MachineBasicBlock::iterator Iter = I;
986 for (unsigned i = 0; i < 4; ++i) {
987 bool SeenDef = false;
988 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
989 MachineOperand &MO = Iter->getOperand(j);
992 if (MO.getReg() == X86::EFLAGS) {
1000 // This instruction defines EFLAGS, no need to look any further.
1003 // Skip over DBG_VALUE.
1004 while (Iter != E && Iter->isDebugValue())
1007 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1012 MachineBasicBlock::iterator B = MBB.begin();
1014 for (unsigned i = 0; i < 4; ++i) {
1015 // If we make it to the beginning of the block, it's safe to clobber
1016 // EFLAGS iff EFLAGS is not live-in.
1018 return !MBB.isLiveIn(X86::EFLAGS);
1021 // Skip over DBG_VALUE.
1022 while (Iter != B && Iter->isDebugValue())
1025 bool SawKill = false;
1026 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1027 MachineOperand &MO = Iter->getOperand(j);
1028 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1029 if (MO.isDef()) return MO.isDead();
1030 if (MO.isKill()) SawKill = true;
1035 // This instruction kills EFLAGS and doesn't redefine it, so
1036 // there's no need to look further.
1040 // Conservative answer.
1044 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1045 MachineBasicBlock::iterator I,
1046 unsigned DestReg, unsigned SubIdx,
1047 const MachineInstr *Orig,
1048 const TargetRegisterInfo &TRI) const {
1049 DebugLoc DL = Orig->getDebugLoc();
1051 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1052 // Re-materialize them as movri instructions to avoid side effects.
1054 unsigned Opc = Orig->getOpcode();
1060 case X86::MOV64r0: {
1061 if (!isSafeToClobberEFLAGS(MBB, I)) {
1064 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1065 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1066 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1067 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1076 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1079 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1082 MachineInstr *NewMI = prior(I);
1083 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1086 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1087 /// is not marked dead.
1088 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1089 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1090 MachineOperand &MO = MI->getOperand(i);
1091 if (MO.isReg() && MO.isDef() &&
1092 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1099 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1100 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1101 /// to a 32-bit superregister and then truncating back down to a 16-bit
1104 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1105 MachineFunction::iterator &MFI,
1106 MachineBasicBlock::iterator &MBBI,
1107 LiveVariables *LV) const {
1108 MachineInstr *MI = MBBI;
1109 unsigned Dest = MI->getOperand(0).getReg();
1110 unsigned Src = MI->getOperand(1).getReg();
1111 bool isDead = MI->getOperand(0).isDead();
1112 bool isKill = MI->getOperand(1).isKill();
1114 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1115 ? X86::LEA64_32r : X86::LEA32r;
1116 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1117 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1118 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1120 // Build and insert into an implicit UNDEF value. This is OK because
1121 // well be shifting and then extracting the lower 16-bits.
1122 // This has the potential to cause partial register stall. e.g.
1123 // movw (%rbp,%rcx,2), %dx
1124 // leal -65(%rdx), %esi
1125 // But testing has shown this *does* help performance in 64-bit mode (at
1126 // least on modern x86 machines).
1127 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1128 MachineInstr *InsMI =
1129 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1130 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1131 .addReg(Src, getKillRegState(isKill));
1133 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1134 get(Opc), leaOutReg);
1137 llvm_unreachable(0);
1139 case X86::SHL16ri: {
1140 unsigned ShAmt = MI->getOperand(2).getImm();
1141 MIB.addReg(0).addImm(1 << ShAmt)
1142 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1146 case X86::INC64_16r:
1147 addRegOffset(MIB, leaInReg, true, 1);
1150 case X86::DEC64_16r:
1151 addRegOffset(MIB, leaInReg, true, -1);
1155 case X86::ADD16ri_DB:
1156 case X86::ADD16ri8_DB:
1157 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1160 case X86::ADD16rr_DB: {
1161 unsigned Src2 = MI->getOperand(2).getReg();
1162 bool isKill2 = MI->getOperand(2).isKill();
1163 unsigned leaInReg2 = 0;
1164 MachineInstr *InsMI2 = 0;
1166 // ADD16rr %reg1028<kill>, %reg1028
1167 // just a single insert_subreg.
1168 addRegReg(MIB, leaInReg, true, leaInReg, false);
1170 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1171 // Build and insert into an implicit UNDEF value. This is OK because
1172 // well be shifting and then extracting the lower 16-bits.
1173 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1175 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1176 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1177 .addReg(Src2, getKillRegState(isKill2));
1178 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1180 if (LV && isKill2 && InsMI2)
1181 LV->replaceKillInstruction(Src2, MI, InsMI2);
1186 MachineInstr *NewMI = MIB;
1187 MachineInstr *ExtMI =
1188 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1189 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1190 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1193 // Update live variables
1194 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1195 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1197 LV->replaceKillInstruction(Src, MI, InsMI);
1199 LV->replaceKillInstruction(Dest, MI, ExtMI);
1205 /// convertToThreeAddress - This method must be implemented by targets that
1206 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1207 /// may be able to convert a two-address instruction into a true
1208 /// three-address instruction on demand. This allows the X86 target (for
1209 /// example) to convert ADD and SHL instructions into LEA instructions if they
1210 /// would require register copies due to two-addressness.
1212 /// This method returns a null pointer if the transformation cannot be
1213 /// performed, otherwise it returns the new instruction.
1216 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1217 MachineBasicBlock::iterator &MBBI,
1218 LiveVariables *LV) const {
1219 MachineInstr *MI = MBBI;
1220 MachineFunction &MF = *MI->getParent()->getParent();
1221 // All instructions input are two-addr instructions. Get the known operands.
1222 unsigned Dest = MI->getOperand(0).getReg();
1223 unsigned Src = MI->getOperand(1).getReg();
1224 bool isDead = MI->getOperand(0).isDead();
1225 bool isKill = MI->getOperand(1).isKill();
1227 MachineInstr *NewMI = NULL;
1228 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1229 // we have better subtarget support, enable the 16-bit LEA generation here.
1230 // 16-bit LEA is also slow on Core2.
1231 bool DisableLEA16 = true;
1232 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1234 unsigned MIOpc = MI->getOpcode();
1236 case X86::SHUFPSrri: {
1237 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1238 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1240 unsigned B = MI->getOperand(1).getReg();
1241 unsigned C = MI->getOperand(2).getReg();
1242 if (B != C) return 0;
1243 unsigned A = MI->getOperand(0).getReg();
1244 unsigned M = MI->getOperand(3).getImm();
1245 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1246 .addReg(A, RegState::Define | getDeadRegState(isDead))
1247 .addReg(B, getKillRegState(isKill)).addImm(M);
1250 case X86::SHL64ri: {
1251 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1252 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1253 // the flags produced by a shift yet, so this is safe.
1254 unsigned ShAmt = MI->getOperand(2).getImm();
1255 if (ShAmt == 0 || ShAmt >= 4) return 0;
1257 // LEA can't handle RSP.
1258 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1259 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1262 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1263 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1264 .addReg(0).addImm(1 << ShAmt)
1265 .addReg(Src, getKillRegState(isKill))
1266 .addImm(0).addReg(0);
1269 case X86::SHL32ri: {
1270 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1271 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1272 // the flags produced by a shift yet, so this is safe.
1273 unsigned ShAmt = MI->getOperand(2).getImm();
1274 if (ShAmt == 0 || ShAmt >= 4) return 0;
1276 // LEA can't handle ESP.
1277 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1278 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1281 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1282 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1283 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1284 .addReg(0).addImm(1 << ShAmt)
1285 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1288 case X86::SHL16ri: {
1289 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1290 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1291 // the flags produced by a shift yet, so this is safe.
1292 unsigned ShAmt = MI->getOperand(2).getImm();
1293 if (ShAmt == 0 || ShAmt >= 4) return 0;
1296 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1297 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1298 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1299 .addReg(0).addImm(1 << ShAmt)
1300 .addReg(Src, getKillRegState(isKill))
1301 .addImm(0).addReg(0);
1305 // The following opcodes also sets the condition code register(s). Only
1306 // convert them to equivalent lea if the condition code register def's
1308 if (hasLiveCondCodeDef(MI))
1315 case X86::INC64_32r: {
1316 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1317 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1318 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1320 // LEA can't handle RSP.
1321 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1322 !MF.getRegInfo().constrainRegClass(Src,
1323 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1324 X86::GR32_NOSPRegisterClass))
1327 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1328 .addReg(Dest, RegState::Define |
1329 getDeadRegState(isDead)),
1334 case X86::INC64_16r:
1336 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1337 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1338 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1339 .addReg(Dest, RegState::Define |
1340 getDeadRegState(isDead)),
1345 case X86::DEC64_32r: {
1346 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1347 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1348 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1349 // LEA can't handle RSP.
1350 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1351 !MF.getRegInfo().constrainRegClass(Src,
1352 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1353 X86::GR32_NOSPRegisterClass))
1356 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1357 .addReg(Dest, RegState::Define |
1358 getDeadRegState(isDead)),
1363 case X86::DEC64_16r:
1365 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1366 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1367 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1368 .addReg(Dest, RegState::Define |
1369 getDeadRegState(isDead)),
1373 case X86::ADD64rr_DB:
1375 case X86::ADD32rr_DB: {
1376 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1378 TargetRegisterClass *RC;
1379 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1381 RC = X86::GR64_NOSPRegisterClass;
1383 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1384 RC = X86::GR32_NOSPRegisterClass;
1388 unsigned Src2 = MI->getOperand(2).getReg();
1389 bool isKill2 = MI->getOperand(2).isKill();
1391 // LEA can't handle RSP.
1392 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1393 !MF.getRegInfo().constrainRegClass(Src2, RC))
1396 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1397 .addReg(Dest, RegState::Define |
1398 getDeadRegState(isDead)),
1399 Src, isKill, Src2, isKill2);
1401 LV->replaceKillInstruction(Src2, MI, NewMI);
1405 case X86::ADD16rr_DB: {
1407 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1408 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1409 unsigned Src2 = MI->getOperand(2).getReg();
1410 bool isKill2 = MI->getOperand(2).isKill();
1411 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1412 .addReg(Dest, RegState::Define |
1413 getDeadRegState(isDead)),
1414 Src, isKill, Src2, isKill2);
1416 LV->replaceKillInstruction(Src2, MI, NewMI);
1419 case X86::ADD64ri32:
1421 case X86::ADD64ri32_DB:
1422 case X86::ADD64ri8_DB:
1423 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1424 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1425 .addReg(Dest, RegState::Define |
1426 getDeadRegState(isDead)),
1427 Src, isKill, MI->getOperand(2).getImm());
1431 case X86::ADD32ri_DB:
1432 case X86::ADD32ri8_DB: {
1433 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1434 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1435 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1436 .addReg(Dest, RegState::Define |
1437 getDeadRegState(isDead)),
1438 Src, isKill, MI->getOperand(2).getImm());
1443 case X86::ADD16ri_DB:
1444 case X86::ADD16ri8_DB:
1446 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1447 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1448 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1449 .addReg(Dest, RegState::Define |
1450 getDeadRegState(isDead)),
1451 Src, isKill, MI->getOperand(2).getImm());
1457 if (!NewMI) return 0;
1459 if (LV) { // Update live variables
1461 LV->replaceKillInstruction(Src, MI, NewMI);
1463 LV->replaceKillInstruction(Dest, MI, NewMI);
1466 MFI->insert(MBBI, NewMI); // Insert the new inst
1470 /// commuteInstruction - We have a few instructions that must be hacked on to
1474 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1475 switch (MI->getOpcode()) {
1476 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1477 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1478 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1479 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1480 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1481 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1484 switch (MI->getOpcode()) {
1485 default: llvm_unreachable("Unreachable!");
1486 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1487 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1488 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1489 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1490 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1491 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1493 unsigned Amt = MI->getOperand(3).getImm();
1495 MachineFunction &MF = *MI->getParent()->getParent();
1496 MI = MF.CloneMachineInstr(MI);
1499 MI->setDesc(get(Opc));
1500 MI->getOperand(3).setImm(Size-Amt);
1501 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1503 case X86::CMOVB16rr:
1504 case X86::CMOVB32rr:
1505 case X86::CMOVB64rr:
1506 case X86::CMOVAE16rr:
1507 case X86::CMOVAE32rr:
1508 case X86::CMOVAE64rr:
1509 case X86::CMOVE16rr:
1510 case X86::CMOVE32rr:
1511 case X86::CMOVE64rr:
1512 case X86::CMOVNE16rr:
1513 case X86::CMOVNE32rr:
1514 case X86::CMOVNE64rr:
1515 case X86::CMOVBE16rr:
1516 case X86::CMOVBE32rr:
1517 case X86::CMOVBE64rr:
1518 case X86::CMOVA16rr:
1519 case X86::CMOVA32rr:
1520 case X86::CMOVA64rr:
1521 case X86::CMOVL16rr:
1522 case X86::CMOVL32rr:
1523 case X86::CMOVL64rr:
1524 case X86::CMOVGE16rr:
1525 case X86::CMOVGE32rr:
1526 case X86::CMOVGE64rr:
1527 case X86::CMOVLE16rr:
1528 case X86::CMOVLE32rr:
1529 case X86::CMOVLE64rr:
1530 case X86::CMOVG16rr:
1531 case X86::CMOVG32rr:
1532 case X86::CMOVG64rr:
1533 case X86::CMOVS16rr:
1534 case X86::CMOVS32rr:
1535 case X86::CMOVS64rr:
1536 case X86::CMOVNS16rr:
1537 case X86::CMOVNS32rr:
1538 case X86::CMOVNS64rr:
1539 case X86::CMOVP16rr:
1540 case X86::CMOVP32rr:
1541 case X86::CMOVP64rr:
1542 case X86::CMOVNP16rr:
1543 case X86::CMOVNP32rr:
1544 case X86::CMOVNP64rr:
1545 case X86::CMOVO16rr:
1546 case X86::CMOVO32rr:
1547 case X86::CMOVO64rr:
1548 case X86::CMOVNO16rr:
1549 case X86::CMOVNO32rr:
1550 case X86::CMOVNO64rr: {
1552 switch (MI->getOpcode()) {
1554 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1555 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1556 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1557 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1558 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1559 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1560 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1561 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1562 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1563 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1564 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1565 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1566 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1567 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1568 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1569 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1570 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1571 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1572 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1573 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1574 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1575 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1576 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1577 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1578 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1579 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1580 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1581 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1582 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1583 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1584 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1585 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1586 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1587 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1588 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1589 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1590 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1591 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1592 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1593 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1594 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1595 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1596 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1597 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1598 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1599 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1600 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1601 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1604 MachineFunction &MF = *MI->getParent()->getParent();
1605 MI = MF.CloneMachineInstr(MI);
1608 MI->setDesc(get(Opc));
1609 // Fallthrough intended.
1612 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1616 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1618 default: return X86::COND_INVALID;
1619 case X86::JE_4: return X86::COND_E;
1620 case X86::JNE_4: return X86::COND_NE;
1621 case X86::JL_4: return X86::COND_L;
1622 case X86::JLE_4: return X86::COND_LE;
1623 case X86::JG_4: return X86::COND_G;
1624 case X86::JGE_4: return X86::COND_GE;
1625 case X86::JB_4: return X86::COND_B;
1626 case X86::JBE_4: return X86::COND_BE;
1627 case X86::JA_4: return X86::COND_A;
1628 case X86::JAE_4: return X86::COND_AE;
1629 case X86::JS_4: return X86::COND_S;
1630 case X86::JNS_4: return X86::COND_NS;
1631 case X86::JP_4: return X86::COND_P;
1632 case X86::JNP_4: return X86::COND_NP;
1633 case X86::JO_4: return X86::COND_O;
1634 case X86::JNO_4: return X86::COND_NO;
1638 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1640 default: llvm_unreachable("Illegal condition code!");
1641 case X86::COND_E: return X86::JE_4;
1642 case X86::COND_NE: return X86::JNE_4;
1643 case X86::COND_L: return X86::JL_4;
1644 case X86::COND_LE: return X86::JLE_4;
1645 case X86::COND_G: return X86::JG_4;
1646 case X86::COND_GE: return X86::JGE_4;
1647 case X86::COND_B: return X86::JB_4;
1648 case X86::COND_BE: return X86::JBE_4;
1649 case X86::COND_A: return X86::JA_4;
1650 case X86::COND_AE: return X86::JAE_4;
1651 case X86::COND_S: return X86::JS_4;
1652 case X86::COND_NS: return X86::JNS_4;
1653 case X86::COND_P: return X86::JP_4;
1654 case X86::COND_NP: return X86::JNP_4;
1655 case X86::COND_O: return X86::JO_4;
1656 case X86::COND_NO: return X86::JNO_4;
1660 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1661 /// e.g. turning COND_E to COND_NE.
1662 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1664 default: llvm_unreachable("Illegal condition code!");
1665 case X86::COND_E: return X86::COND_NE;
1666 case X86::COND_NE: return X86::COND_E;
1667 case X86::COND_L: return X86::COND_GE;
1668 case X86::COND_LE: return X86::COND_G;
1669 case X86::COND_G: return X86::COND_LE;
1670 case X86::COND_GE: return X86::COND_L;
1671 case X86::COND_B: return X86::COND_AE;
1672 case X86::COND_BE: return X86::COND_A;
1673 case X86::COND_A: return X86::COND_BE;
1674 case X86::COND_AE: return X86::COND_B;
1675 case X86::COND_S: return X86::COND_NS;
1676 case X86::COND_NS: return X86::COND_S;
1677 case X86::COND_P: return X86::COND_NP;
1678 case X86::COND_NP: return X86::COND_P;
1679 case X86::COND_O: return X86::COND_NO;
1680 case X86::COND_NO: return X86::COND_O;
1684 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1685 const MCInstrDesc &MCID = MI->getDesc();
1686 if (!MCID.isTerminator()) return false;
1688 // Conditional branch is a special case.
1689 if (MCID.isBranch() && !MCID.isBarrier())
1691 if (!MCID.isPredicable())
1693 return !isPredicated(MI);
1696 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1697 MachineBasicBlock *&TBB,
1698 MachineBasicBlock *&FBB,
1699 SmallVectorImpl<MachineOperand> &Cond,
1700 bool AllowModify) const {
1701 // Start from the bottom of the block and work up, examining the
1702 // terminator instructions.
1703 MachineBasicBlock::iterator I = MBB.end();
1704 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1705 while (I != MBB.begin()) {
1707 if (I->isDebugValue())
1710 // Working from the bottom, when we see a non-terminator instruction, we're
1712 if (!isUnpredicatedTerminator(I))
1715 // A terminator that isn't a branch can't easily be handled by this
1717 if (!I->getDesc().isBranch())
1720 // Handle unconditional branches.
1721 if (I->getOpcode() == X86::JMP_4) {
1725 TBB = I->getOperand(0).getMBB();
1729 // If the block has any instructions after a JMP, delete them.
1730 while (llvm::next(I) != MBB.end())
1731 llvm::next(I)->eraseFromParent();
1736 // Delete the JMP if it's equivalent to a fall-through.
1737 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1739 I->eraseFromParent();
1741 UnCondBrIter = MBB.end();
1745 // TBB is used to indicate the unconditional destination.
1746 TBB = I->getOperand(0).getMBB();
1750 // Handle conditional branches.
1751 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1752 if (BranchCode == X86::COND_INVALID)
1753 return true; // Can't handle indirect branch.
1755 // Working from the bottom, handle the first conditional branch.
1757 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1758 if (AllowModify && UnCondBrIter != MBB.end() &&
1759 MBB.isLayoutSuccessor(TargetBB)) {
1760 // If we can modify the code and it ends in something like:
1768 // Then we can change this to:
1775 // Which is a bit more efficient.
1776 // We conditionally jump to the fall-through block.
1777 BranchCode = GetOppositeBranchCondition(BranchCode);
1778 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1779 MachineBasicBlock::iterator OldInst = I;
1781 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1782 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1783 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1786 OldInst->eraseFromParent();
1787 UnCondBrIter->eraseFromParent();
1789 // Restart the analysis.
1790 UnCondBrIter = MBB.end();
1796 TBB = I->getOperand(0).getMBB();
1797 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1801 // Handle subsequent conditional branches. Only handle the case where all
1802 // conditional branches branch to the same destination and their condition
1803 // opcodes fit one of the special multi-branch idioms.
1804 assert(Cond.size() == 1);
1807 // Only handle the case where all conditional branches branch to the same
1809 if (TBB != I->getOperand(0).getMBB())
1812 // If the conditions are the same, we can leave them alone.
1813 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1814 if (OldBranchCode == BranchCode)
1817 // If they differ, see if they fit one of the known patterns. Theoretically,
1818 // we could handle more patterns here, but we shouldn't expect to see them
1819 // if instruction selection has done a reasonable job.
1820 if ((OldBranchCode == X86::COND_NP &&
1821 BranchCode == X86::COND_E) ||
1822 (OldBranchCode == X86::COND_E &&
1823 BranchCode == X86::COND_NP))
1824 BranchCode = X86::COND_NP_OR_E;
1825 else if ((OldBranchCode == X86::COND_P &&
1826 BranchCode == X86::COND_NE) ||
1827 (OldBranchCode == X86::COND_NE &&
1828 BranchCode == X86::COND_P))
1829 BranchCode = X86::COND_NE_OR_P;
1833 // Update the MachineOperand.
1834 Cond[0].setImm(BranchCode);
1840 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1841 MachineBasicBlock::iterator I = MBB.end();
1844 while (I != MBB.begin()) {
1846 if (I->isDebugValue())
1848 if (I->getOpcode() != X86::JMP_4 &&
1849 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1851 // Remove the branch.
1852 I->eraseFromParent();
1861 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1862 MachineBasicBlock *FBB,
1863 const SmallVectorImpl<MachineOperand> &Cond,
1864 DebugLoc DL) const {
1865 // Shouldn't be a fall through.
1866 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1867 assert((Cond.size() == 1 || Cond.size() == 0) &&
1868 "X86 branch conditions have one component!");
1871 // Unconditional branch?
1872 assert(!FBB && "Unconditional branch with multiple successors!");
1873 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
1877 // Conditional branch.
1879 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1881 case X86::COND_NP_OR_E:
1882 // Synthesize NP_OR_E with two branches.
1883 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
1885 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
1888 case X86::COND_NE_OR_P:
1889 // Synthesize NE_OR_P with two branches.
1890 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
1892 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
1896 unsigned Opc = GetCondBranchFromCond(CC);
1897 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
1902 // Two-way Conditional branch. Insert the second branch.
1903 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
1909 /// isHReg - Test if the given register is a physical h register.
1910 static bool isHReg(unsigned Reg) {
1911 return X86::GR8_ABCD_HRegClass.contains(Reg);
1914 // Try and copy between VR128/VR64 and GR64 registers.
1915 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg) {
1916 // SrcReg(VR128) -> DestReg(GR64)
1917 // SrcReg(VR64) -> DestReg(GR64)
1918 // SrcReg(GR64) -> DestReg(VR128)
1919 // SrcReg(GR64) -> DestReg(VR64)
1921 if (X86::GR64RegClass.contains(DestReg)) {
1922 if (X86::VR128RegClass.contains(SrcReg)) {
1923 // Copy from a VR128 register to a GR64 register.
1924 return X86::MOVPQIto64rr;
1925 } else if (X86::VR64RegClass.contains(SrcReg)) {
1926 // Copy from a VR64 register to a GR64 register.
1927 return X86::MOVSDto64rr;
1929 } else if (X86::GR64RegClass.contains(SrcReg)) {
1930 // Copy from a GR64 register to a VR128 register.
1931 if (X86::VR128RegClass.contains(DestReg))
1932 return X86::MOV64toPQIrr;
1933 // Copy from a GR64 register to a VR64 register.
1934 else if (X86::VR64RegClass.contains(DestReg))
1935 return X86::MOV64toSDrr;
1941 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1942 MachineBasicBlock::iterator MI, DebugLoc DL,
1943 unsigned DestReg, unsigned SrcReg,
1944 bool KillSrc) const {
1945 // First deal with the normal symmetric copies.
1947 if (X86::GR64RegClass.contains(DestReg, SrcReg))
1949 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
1951 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
1953 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
1954 // Copying to or from a physical H register on x86-64 requires a NOREX
1955 // move. Otherwise use a normal move.
1956 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1957 TM.getSubtarget<X86Subtarget>().is64Bit())
1958 Opc = X86::MOV8rr_NOREX;
1961 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
1962 Opc = X86::MOVAPSrr;
1963 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
1964 Opc = X86::VMOVAPSYrr;
1965 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
1966 Opc = X86::MMX_MOVQ64rr;
1968 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg);
1971 BuildMI(MBB, MI, DL, get(Opc), DestReg)
1972 .addReg(SrcReg, getKillRegState(KillSrc));
1976 // Moving EFLAGS to / from another register requires a push and a pop.
1977 if (SrcReg == X86::EFLAGS) {
1978 if (X86::GR64RegClass.contains(DestReg)) {
1979 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
1980 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1982 } else if (X86::GR32RegClass.contains(DestReg)) {
1983 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
1984 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1988 if (DestReg == X86::EFLAGS) {
1989 if (X86::GR64RegClass.contains(SrcReg)) {
1990 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
1991 .addReg(SrcReg, getKillRegState(KillSrc));
1992 BuildMI(MBB, MI, DL, get(X86::POPF64));
1994 } else if (X86::GR32RegClass.contains(SrcReg)) {
1995 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
1996 .addReg(SrcReg, getKillRegState(KillSrc));
1997 BuildMI(MBB, MI, DL, get(X86::POPF32));
2002 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2003 << " to " << RI.getName(DestReg) << '\n');
2004 llvm_unreachable("Cannot emit physreg copy instruction");
2007 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2008 const TargetRegisterClass *RC,
2009 bool isStackAligned,
2010 const TargetMachine &TM,
2012 switch (RC->getSize()) {
2014 llvm_unreachable("Unknown spill size");
2016 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2017 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2018 // Copying to or from a physical H register on x86-64 requires a NOREX
2019 // move. Otherwise use a normal move.
2020 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2021 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2022 return load ? X86::MOV8rm : X86::MOV8mr;
2024 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2025 return load ? X86::MOV16rm : X86::MOV16mr;
2027 if (X86::GR32RegClass.hasSubClassEq(RC))
2028 return load ? X86::MOV32rm : X86::MOV32mr;
2029 if (X86::FR32RegClass.hasSubClassEq(RC))
2030 return load ? X86::MOVSSrm : X86::MOVSSmr;
2031 if (X86::RFP32RegClass.hasSubClassEq(RC))
2032 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2033 llvm_unreachable("Unknown 4-byte regclass");
2035 if (X86::GR64RegClass.hasSubClassEq(RC))
2036 return load ? X86::MOV64rm : X86::MOV64mr;
2037 if (X86::FR64RegClass.hasSubClassEq(RC))
2038 return load ? X86::MOVSDrm : X86::MOVSDmr;
2039 if (X86::VR64RegClass.hasSubClassEq(RC))
2040 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2041 if (X86::RFP64RegClass.hasSubClassEq(RC))
2042 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2043 llvm_unreachable("Unknown 8-byte regclass");
2045 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2046 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2048 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2049 // If stack is realigned we can use aligned stores.
2051 return load ? X86::MOVAPSrm : X86::MOVAPSmr;
2053 return load ? X86::MOVUPSrm : X86::MOVUPSmr;
2055 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2056 // If stack is realigned we can use aligned stores.
2058 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2060 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2064 static unsigned getStoreRegOpcode(unsigned SrcReg,
2065 const TargetRegisterClass *RC,
2066 bool isStackAligned,
2067 TargetMachine &TM) {
2068 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2072 static unsigned getLoadRegOpcode(unsigned DestReg,
2073 const TargetRegisterClass *RC,
2074 bool isStackAligned,
2075 const TargetMachine &TM) {
2076 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2079 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2080 MachineBasicBlock::iterator MI,
2081 unsigned SrcReg, bool isKill, int FrameIdx,
2082 const TargetRegisterClass *RC,
2083 const TargetRegisterInfo *TRI) const {
2084 const MachineFunction &MF = *MBB.getParent();
2085 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2086 "Stack slot too small for store");
2087 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= 16) ||
2088 RI.canRealignStack(MF);
2089 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2090 DebugLoc DL = MBB.findDebugLoc(MI);
2091 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2092 .addReg(SrcReg, getKillRegState(isKill));
2095 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2097 SmallVectorImpl<MachineOperand> &Addr,
2098 const TargetRegisterClass *RC,
2099 MachineInstr::mmo_iterator MMOBegin,
2100 MachineInstr::mmo_iterator MMOEnd,
2101 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2102 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2103 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2105 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2106 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2107 MIB.addOperand(Addr[i]);
2108 MIB.addReg(SrcReg, getKillRegState(isKill));
2109 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2110 NewMIs.push_back(MIB);
2114 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2115 MachineBasicBlock::iterator MI,
2116 unsigned DestReg, int FrameIdx,
2117 const TargetRegisterClass *RC,
2118 const TargetRegisterInfo *TRI) const {
2119 const MachineFunction &MF = *MBB.getParent();
2120 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= 16) ||
2121 RI.canRealignStack(MF);
2122 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2123 DebugLoc DL = MBB.findDebugLoc(MI);
2124 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2127 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2128 SmallVectorImpl<MachineOperand> &Addr,
2129 const TargetRegisterClass *RC,
2130 MachineInstr::mmo_iterator MMOBegin,
2131 MachineInstr::mmo_iterator MMOEnd,
2132 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2133 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2134 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2136 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2137 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2138 MIB.addOperand(Addr[i]);
2139 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2140 NewMIs.push_back(MIB);
2144 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2145 int FrameIx, uint64_t Offset,
2146 const MDNode *MDPtr,
2147 DebugLoc DL) const {
2149 AM.BaseType = X86AddressMode::FrameIndexBase;
2150 AM.Base.FrameIndex = FrameIx;
2151 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2152 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2156 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2157 const SmallVectorImpl<MachineOperand> &MOs,
2159 const TargetInstrInfo &TII) {
2160 // Create the base instruction with the memory operand as the first part.
2161 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2162 MI->getDebugLoc(), true);
2163 MachineInstrBuilder MIB(NewMI);
2164 unsigned NumAddrOps = MOs.size();
2165 for (unsigned i = 0; i != NumAddrOps; ++i)
2166 MIB.addOperand(MOs[i]);
2167 if (NumAddrOps < 4) // FrameIndex only
2170 // Loop over the rest of the ri operands, converting them over.
2171 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2172 for (unsigned i = 0; i != NumOps; ++i) {
2173 MachineOperand &MO = MI->getOperand(i+2);
2176 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2177 MachineOperand &MO = MI->getOperand(i);
2183 static MachineInstr *FuseInst(MachineFunction &MF,
2184 unsigned Opcode, unsigned OpNo,
2185 const SmallVectorImpl<MachineOperand> &MOs,
2186 MachineInstr *MI, const TargetInstrInfo &TII) {
2187 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2188 MI->getDebugLoc(), true);
2189 MachineInstrBuilder MIB(NewMI);
2191 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2192 MachineOperand &MO = MI->getOperand(i);
2194 assert(MO.isReg() && "Expected to fold into reg operand!");
2195 unsigned NumAddrOps = MOs.size();
2196 for (unsigned i = 0; i != NumAddrOps; ++i)
2197 MIB.addOperand(MOs[i]);
2198 if (NumAddrOps < 4) // FrameIndex only
2207 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2208 const SmallVectorImpl<MachineOperand> &MOs,
2210 MachineFunction &MF = *MI->getParent()->getParent();
2211 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2213 unsigned NumAddrOps = MOs.size();
2214 for (unsigned i = 0; i != NumAddrOps; ++i)
2215 MIB.addOperand(MOs[i]);
2216 if (NumAddrOps < 4) // FrameIndex only
2218 return MIB.addImm(0);
2222 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2223 MachineInstr *MI, unsigned i,
2224 const SmallVectorImpl<MachineOperand> &MOs,
2225 unsigned Size, unsigned Align) const {
2226 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2227 bool isTwoAddrFold = false;
2228 unsigned NumOps = MI->getDesc().getNumOperands();
2229 bool isTwoAddr = NumOps > 1 &&
2230 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2232 // FIXME: AsmPrinter doesn't know how to handle
2233 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2234 if (MI->getOpcode() == X86::ADD32ri &&
2235 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2238 MachineInstr *NewMI = NULL;
2239 // Folding a memory location into the two-address part of a two-address
2240 // instruction is different than folding it other places. It requires
2241 // replacing the *two* registers with the memory location.
2242 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2243 MI->getOperand(0).isReg() &&
2244 MI->getOperand(1).isReg() &&
2245 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2246 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2247 isTwoAddrFold = true;
2248 } else if (i == 0) { // If operand 0
2249 if (MI->getOpcode() == X86::MOV64r0)
2250 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2251 else if (MI->getOpcode() == X86::MOV32r0)
2252 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2253 else if (MI->getOpcode() == X86::MOV16r0)
2254 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2255 else if (MI->getOpcode() == X86::MOV8r0)
2256 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2260 OpcodeTablePtr = &RegOp2MemOpTable0;
2261 } else if (i == 1) {
2262 OpcodeTablePtr = &RegOp2MemOpTable1;
2263 } else if (i == 2) {
2264 OpcodeTablePtr = &RegOp2MemOpTable2;
2267 // If table selected...
2268 if (OpcodeTablePtr) {
2269 // Find the Opcode to fuse
2270 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2271 OpcodeTablePtr->find(MI->getOpcode());
2272 if (I != OpcodeTablePtr->end()) {
2273 unsigned Opcode = I->second.first;
2274 unsigned MinAlign = I->second.second;
2275 if (Align < MinAlign)
2277 bool NarrowToMOV32rm = false;
2279 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2280 if (Size < RCSize) {
2281 // Check if it's safe to fold the load. If the size of the object is
2282 // narrower than the load width, then it's not.
2283 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2285 // If this is a 64-bit load, but the spill slot is 32, then we can do
2286 // a 32-bit load which is implicitly zero-extended. This likely is due
2287 // to liveintervalanalysis remat'ing a load from stack slot.
2288 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2290 Opcode = X86::MOV32rm;
2291 NarrowToMOV32rm = true;
2296 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2298 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2300 if (NarrowToMOV32rm) {
2301 // If this is the special case where we use a MOV32rm to load a 32-bit
2302 // value and zero-extend the top bits. Change the destination register
2304 unsigned DstReg = NewMI->getOperand(0).getReg();
2305 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2306 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2309 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2316 if (PrintFailedFusing && !MI->isCopy())
2317 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2322 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2324 const SmallVectorImpl<unsigned> &Ops,
2325 int FrameIndex) const {
2326 // Check switch flag
2327 if (NoFusing) return NULL;
2329 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2330 switch (MI->getOpcode()) {
2331 case X86::CVTSD2SSrr:
2332 case X86::Int_CVTSD2SSrr:
2333 case X86::CVTSS2SDrr:
2334 case X86::Int_CVTSS2SDrr:
2336 case X86::RCPSSr_Int:
2340 case X86::RSQRTSSr_Int:
2342 case X86::SQRTSSr_Int:
2346 const MachineFrameInfo *MFI = MF.getFrameInfo();
2347 unsigned Size = MFI->getObjectSize(FrameIndex);
2348 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2349 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2350 unsigned NewOpc = 0;
2351 unsigned RCSize = 0;
2352 switch (MI->getOpcode()) {
2353 default: return NULL;
2354 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2355 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2356 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2357 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2359 // Check if it's safe to fold the load. If the size of the object is
2360 // narrower than the load width, then it's not.
2363 // Change to CMPXXri r, 0 first.
2364 MI->setDesc(get(NewOpc));
2365 MI->getOperand(1).ChangeToImmediate(0);
2366 } else if (Ops.size() != 1)
2369 SmallVector<MachineOperand,4> MOs;
2370 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2371 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2374 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2376 const SmallVectorImpl<unsigned> &Ops,
2377 MachineInstr *LoadMI) const {
2378 // Check switch flag
2379 if (NoFusing) return NULL;
2381 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2382 switch (MI->getOpcode()) {
2383 case X86::CVTSD2SSrr:
2384 case X86::Int_CVTSD2SSrr:
2385 case X86::CVTSS2SDrr:
2386 case X86::Int_CVTSS2SDrr:
2388 case X86::RCPSSr_Int:
2392 case X86::RSQRTSSr_Int:
2394 case X86::SQRTSSr_Int:
2398 // Determine the alignment of the load.
2399 unsigned Alignment = 0;
2400 if (LoadMI->hasOneMemOperand())
2401 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2403 switch (LoadMI->getOpcode()) {
2404 case X86::AVX_SET0PSY:
2405 case X86::AVX_SET0PDY:
2411 case X86::V_SETALLONES:
2412 case X86::AVX_SET0PS:
2413 case X86::AVX_SET0PD:
2414 case X86::AVX_SET0PI:
2415 case X86::AVX_SETALLONES:
2419 case X86::VFsFLD0SD:
2423 case X86::VFsFLD0SS:
2429 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2430 unsigned NewOpc = 0;
2431 switch (MI->getOpcode()) {
2432 default: return NULL;
2433 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2434 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2435 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2436 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2438 // Change to CMPXXri r, 0 first.
2439 MI->setDesc(get(NewOpc));
2440 MI->getOperand(1).ChangeToImmediate(0);
2441 } else if (Ops.size() != 1)
2444 // Make sure the subregisters match.
2445 // Otherwise we risk changing the size of the load.
2446 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2449 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2450 switch (LoadMI->getOpcode()) {
2454 case X86::V_SETALLONES:
2455 case X86::AVX_SET0PS:
2456 case X86::AVX_SET0PD:
2457 case X86::AVX_SET0PI:
2458 case X86::AVX_SET0PSY:
2459 case X86::AVX_SET0PDY:
2460 case X86::AVX_SETALLONES:
2463 case X86::VFsFLD0SD:
2464 case X86::VFsFLD0SS: {
2465 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2466 // Create a constant-pool entry and operands to load from it.
2468 // Medium and large mode can't fold loads this way.
2469 if (TM.getCodeModel() != CodeModel::Small &&
2470 TM.getCodeModel() != CodeModel::Kernel)
2473 // x86-32 PIC requires a PIC base register for constant pools.
2474 unsigned PICBase = 0;
2475 if (TM.getRelocationModel() == Reloc::PIC_) {
2476 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2479 // FIXME: PICBase = getGlobalBaseReg(&MF);
2480 // This doesn't work for several reasons.
2481 // 1. GlobalBaseReg may have been spilled.
2482 // 2. It may not be live at MI.
2486 // Create a constant-pool entry.
2487 MachineConstantPool &MCP = *MF.getConstantPool();
2489 unsigned Opc = LoadMI->getOpcode();
2490 if (Opc == X86::FsFLD0SS || Opc == X86::VFsFLD0SS)
2491 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2492 else if (Opc == X86::FsFLD0SD || Opc == X86::VFsFLD0SD)
2493 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2494 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2495 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2497 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2499 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES);
2500 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
2501 Constant::getNullValue(Ty);
2502 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2504 // Create operands to load from the constant pool entry.
2505 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2506 MOs.push_back(MachineOperand::CreateImm(1));
2507 MOs.push_back(MachineOperand::CreateReg(0, false));
2508 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2509 MOs.push_back(MachineOperand::CreateReg(0, false));
2513 // Folding a normal load. Just copy the load's address operands.
2514 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2515 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
2516 MOs.push_back(LoadMI->getOperand(i));
2520 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2524 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2525 const SmallVectorImpl<unsigned> &Ops) const {
2526 // Check switch flag
2527 if (NoFusing) return 0;
2529 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2530 switch (MI->getOpcode()) {
2531 default: return false;
2538 // FIXME: AsmPrinter doesn't know how to handle
2539 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2540 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2546 if (Ops.size() != 1)
2549 unsigned OpNum = Ops[0];
2550 unsigned Opc = MI->getOpcode();
2551 unsigned NumOps = MI->getDesc().getNumOperands();
2552 bool isTwoAddr = NumOps > 1 &&
2553 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2555 // Folding a memory location into the two-address part of a two-address
2556 // instruction is different than folding it other places. It requires
2557 // replacing the *two* registers with the memory location.
2558 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2559 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2560 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2561 } else if (OpNum == 0) { // If operand 0
2566 case X86::MOV64r0: return true;
2569 OpcodeTablePtr = &RegOp2MemOpTable0;
2570 } else if (OpNum == 1) {
2571 OpcodeTablePtr = &RegOp2MemOpTable1;
2572 } else if (OpNum == 2) {
2573 OpcodeTablePtr = &RegOp2MemOpTable2;
2576 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
2578 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
2581 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2582 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2583 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2584 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2585 MemOp2RegOpTable.find(MI->getOpcode());
2586 if (I == MemOp2RegOpTable.end())
2588 unsigned Opc = I->second.first;
2589 unsigned Index = I->second.second & 0xf;
2590 bool FoldedLoad = I->second.second & (1 << 4);
2591 bool FoldedStore = I->second.second & (1 << 5);
2592 if (UnfoldLoad && !FoldedLoad)
2594 UnfoldLoad &= FoldedLoad;
2595 if (UnfoldStore && !FoldedStore)
2597 UnfoldStore &= FoldedStore;
2599 const MCInstrDesc &MCID = get(Opc);
2600 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2601 if (!MI->hasOneMemOperand() &&
2602 RC == &X86::VR128RegClass &&
2603 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2604 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2605 // conservatively assume the address is unaligned. That's bad for
2608 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
2609 SmallVector<MachineOperand,2> BeforeOps;
2610 SmallVector<MachineOperand,2> AfterOps;
2611 SmallVector<MachineOperand,4> ImpOps;
2612 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2613 MachineOperand &Op = MI->getOperand(i);
2614 if (i >= Index && i < Index + X86::AddrNumOperands)
2615 AddrOps.push_back(Op);
2616 else if (Op.isReg() && Op.isImplicit())
2617 ImpOps.push_back(Op);
2619 BeforeOps.push_back(Op);
2621 AfterOps.push_back(Op);
2624 // Emit the load instruction.
2626 std::pair<MachineInstr::mmo_iterator,
2627 MachineInstr::mmo_iterator> MMOs =
2628 MF.extractLoadMemRefs(MI->memoperands_begin(),
2629 MI->memoperands_end());
2630 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2632 // Address operands cannot be marked isKill.
2633 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
2634 MachineOperand &MO = NewMIs[0]->getOperand(i);
2636 MO.setIsKill(false);
2641 // Emit the data processing instruction.
2642 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
2643 MachineInstrBuilder MIB(DataMI);
2646 MIB.addReg(Reg, RegState::Define);
2647 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2648 MIB.addOperand(BeforeOps[i]);
2651 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2652 MIB.addOperand(AfterOps[i]);
2653 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2654 MachineOperand &MO = ImpOps[i];
2655 MIB.addReg(MO.getReg(),
2656 getDefRegState(MO.isDef()) |
2657 RegState::Implicit |
2658 getKillRegState(MO.isKill()) |
2659 getDeadRegState(MO.isDead()) |
2660 getUndefRegState(MO.isUndef()));
2662 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2663 unsigned NewOpc = 0;
2664 switch (DataMI->getOpcode()) {
2666 case X86::CMP64ri32:
2673 MachineOperand &MO0 = DataMI->getOperand(0);
2674 MachineOperand &MO1 = DataMI->getOperand(1);
2675 if (MO1.getImm() == 0) {
2676 switch (DataMI->getOpcode()) {
2679 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2681 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2683 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2684 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2686 DataMI->setDesc(get(NewOpc));
2687 MO1.ChangeToRegister(MO0.getReg(), false);
2691 NewMIs.push_back(DataMI);
2693 // Emit the store instruction.
2695 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
2696 std::pair<MachineInstr::mmo_iterator,
2697 MachineInstr::mmo_iterator> MMOs =
2698 MF.extractStoreMemRefs(MI->memoperands_begin(),
2699 MI->memoperands_end());
2700 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2707 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2708 SmallVectorImpl<SDNode*> &NewNodes) const {
2709 if (!N->isMachineOpcode())
2712 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2713 MemOp2RegOpTable.find(N->getMachineOpcode());
2714 if (I == MemOp2RegOpTable.end())
2716 unsigned Opc = I->second.first;
2717 unsigned Index = I->second.second & 0xf;
2718 bool FoldedLoad = I->second.second & (1 << 4);
2719 bool FoldedStore = I->second.second & (1 << 5);
2720 const MCInstrDesc &MCID = get(Opc);
2721 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2722 unsigned NumDefs = MCID.NumDefs;
2723 std::vector<SDValue> AddrOps;
2724 std::vector<SDValue> BeforeOps;
2725 std::vector<SDValue> AfterOps;
2726 DebugLoc dl = N->getDebugLoc();
2727 unsigned NumOps = N->getNumOperands();
2728 for (unsigned i = 0; i != NumOps-1; ++i) {
2729 SDValue Op = N->getOperand(i);
2730 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
2731 AddrOps.push_back(Op);
2732 else if (i < Index-NumDefs)
2733 BeforeOps.push_back(Op);
2734 else if (i > Index-NumDefs)
2735 AfterOps.push_back(Op);
2737 SDValue Chain = N->getOperand(NumOps-1);
2738 AddrOps.push_back(Chain);
2740 // Emit the load instruction.
2742 MachineFunction &MF = DAG.getMachineFunction();
2744 EVT VT = *RC->vt_begin();
2745 std::pair<MachineInstr::mmo_iterator,
2746 MachineInstr::mmo_iterator> MMOs =
2747 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2748 cast<MachineSDNode>(N)->memoperands_end());
2749 if (!(*MMOs.first) &&
2750 RC == &X86::VR128RegClass &&
2751 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2752 // Do not introduce a slow unaligned load.
2754 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2755 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2756 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2757 NewNodes.push_back(Load);
2759 // Preserve memory reference information.
2760 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2763 // Emit the data processing instruction.
2764 std::vector<EVT> VTs;
2765 const TargetRegisterClass *DstRC = 0;
2766 if (MCID.getNumDefs() > 0) {
2767 DstRC = getRegClass(MCID, 0, &RI);
2768 VTs.push_back(*DstRC->vt_begin());
2770 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2771 EVT VT = N->getValueType(i);
2772 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
2776 BeforeOps.push_back(SDValue(Load, 0));
2777 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2778 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2780 NewNodes.push_back(NewNode);
2782 // Emit the store instruction.
2785 AddrOps.push_back(SDValue(NewNode, 0));
2786 AddrOps.push_back(Chain);
2787 std::pair<MachineInstr::mmo_iterator,
2788 MachineInstr::mmo_iterator> MMOs =
2789 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2790 cast<MachineSDNode>(N)->memoperands_end());
2791 if (!(*MMOs.first) &&
2792 RC == &X86::VR128RegClass &&
2793 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2794 // Do not introduce a slow unaligned store.
2796 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2797 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2800 &AddrOps[0], AddrOps.size());
2801 NewNodes.push_back(Store);
2803 // Preserve memory reference information.
2804 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2810 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2811 bool UnfoldLoad, bool UnfoldStore,
2812 unsigned *LoadRegIndex) const {
2813 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2814 MemOp2RegOpTable.find(Opc);
2815 if (I == MemOp2RegOpTable.end())
2817 bool FoldedLoad = I->second.second & (1 << 4);
2818 bool FoldedStore = I->second.second & (1 << 5);
2819 if (UnfoldLoad && !FoldedLoad)
2821 if (UnfoldStore && !FoldedStore)
2824 *LoadRegIndex = I->second.second & 0xf;
2825 return I->second.first;
2829 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2830 int64_t &Offset1, int64_t &Offset2) const {
2831 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2833 unsigned Opc1 = Load1->getMachineOpcode();
2834 unsigned Opc2 = Load2->getMachineOpcode();
2836 default: return false;
2846 case X86::MMX_MOVD64rm:
2847 case X86::MMX_MOVQ64rm:
2848 case X86::FsMOVAPSrm:
2849 case X86::FsMOVAPDrm:
2855 case X86::VMOVAPSYrm:
2856 case X86::VMOVUPSYrm:
2857 case X86::VMOVAPDYrm:
2858 case X86::VMOVDQAYrm:
2859 case X86::VMOVDQUYrm:
2863 default: return false;
2873 case X86::MMX_MOVD64rm:
2874 case X86::MMX_MOVQ64rm:
2875 case X86::FsMOVAPSrm:
2876 case X86::FsMOVAPDrm:
2882 case X86::VMOVAPSYrm:
2883 case X86::VMOVUPSYrm:
2884 case X86::VMOVAPDYrm:
2885 case X86::VMOVDQAYrm:
2886 case X86::VMOVDQUYrm:
2890 // Check if chain operands and base addresses match.
2891 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2892 Load1->getOperand(5) != Load2->getOperand(5))
2894 // Segment operands should match as well.
2895 if (Load1->getOperand(4) != Load2->getOperand(4))
2897 // Scale should be 1, Index should be Reg0.
2898 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2899 Load1->getOperand(2) == Load2->getOperand(2)) {
2900 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2903 // Now let's examine the displacements.
2904 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2905 isa<ConstantSDNode>(Load2->getOperand(3))) {
2906 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2907 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2914 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2915 int64_t Offset1, int64_t Offset2,
2916 unsigned NumLoads) const {
2917 assert(Offset2 > Offset1);
2918 if ((Offset2 - Offset1) / 8 > 64)
2921 unsigned Opc1 = Load1->getMachineOpcode();
2922 unsigned Opc2 = Load2->getMachineOpcode();
2924 return false; // FIXME: overly conservative?
2931 case X86::MMX_MOVD64rm:
2932 case X86::MMX_MOVQ64rm:
2936 EVT VT = Load1->getValueType(0);
2937 switch (VT.getSimpleVT().SimpleTy) {
2939 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
2940 // have 16 of them to play with.
2941 if (TM.getSubtargetImpl()->is64Bit()) {
2944 } else if (NumLoads) {
2964 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2965 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2966 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2967 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2969 Cond[0].setImm(GetOppositeBranchCondition(CC));
2974 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2975 // FIXME: Return false for x87 stack register classes for now. We can't
2976 // allow any loads of these registers before FpGet_ST0_80.
2977 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2978 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2981 /// getGlobalBaseReg - Return a virtual register initialized with the
2982 /// the global base register value. Output instructions required to
2983 /// initialize the register in the function entry block, if necessary.
2985 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
2987 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
2988 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
2989 "X86-64 PIC uses RIP relative addressing");
2991 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2992 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
2993 if (GlobalBaseReg != 0)
2994 return GlobalBaseReg;
2996 // Create the register. The code to initialize it is inserted
2997 // later, by the CGBR pass (below).
2998 MachineRegisterInfo &RegInfo = MF->getRegInfo();
2999 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3000 X86FI->setGlobalBaseReg(GlobalBaseReg);
3001 return GlobalBaseReg;
3004 // These are the replaceable SSE instructions. Some of these have Int variants
3005 // that we don't include here. We don't want to replace instructions selected
3007 static const unsigned ReplaceableInstrs[][3] = {
3008 //PackedSingle PackedDouble PackedInt
3009 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3010 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3011 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3012 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3013 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3014 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3015 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3016 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3017 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3018 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3019 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3020 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3021 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3022 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3023 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3024 // AVX 128-bit support
3025 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3026 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3027 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3028 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3029 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3030 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3031 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3032 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3033 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3034 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3035 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3036 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3037 { X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
3038 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3039 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3040 // AVX 256-bit support
3041 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
3042 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
3043 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
3044 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
3045 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
3046 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
3049 // FIXME: Some shuffle and unpack instructions have equivalents in different
3050 // domains, but they require a bit more work than just switching opcodes.
3052 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3053 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3054 if (ReplaceableInstrs[i][domain-1] == opcode)
3055 return ReplaceableInstrs[i];
3059 std::pair<uint16_t, uint16_t>
3060 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3061 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3062 return std::make_pair(domain,
3063 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3066 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3067 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3068 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3069 assert(dom && "Not an SSE instruction");
3070 const unsigned *table = lookup(MI->getOpcode(), dom);
3071 assert(table && "Cannot change domain");
3072 MI->setDesc(get(table[Domain-1]));
3075 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3076 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3077 NopInst.setOpcode(X86::NOOP);
3080 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3082 default: return false;
3084 case X86::DIVSDrm_Int:
3086 case X86::DIVSDrr_Int:
3088 case X86::DIVSSrm_Int:
3090 case X86::DIVSSrr_Int:
3092 case X86::SQRTPDm_Int:
3094 case X86::SQRTPDr_Int:
3096 case X86::SQRTPSm_Int:
3098 case X86::SQRTPSr_Int:
3100 case X86::SQRTSDm_Int:
3102 case X86::SQRTSDr_Int:
3104 case X86::SQRTSSm_Int:
3106 case X86::SQRTSSr_Int:
3112 hasHighOperandLatency(const InstrItineraryData *ItinData,
3113 const MachineRegisterInfo *MRI,
3114 const MachineInstr *DefMI, unsigned DefIdx,
3115 const MachineInstr *UseMI, unsigned UseIdx) const {
3116 return isHighLatencyDef(DefMI->getOpcode());
3120 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3121 /// global base register for x86-32.
3122 struct CGBR : public MachineFunctionPass {
3124 CGBR() : MachineFunctionPass(ID) {}
3126 virtual bool runOnMachineFunction(MachineFunction &MF) {
3127 const X86TargetMachine *TM =
3128 static_cast<const X86TargetMachine *>(&MF.getTarget());
3130 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3131 "X86-64 PIC uses RIP relative addressing");
3133 // Only emit a global base reg in PIC mode.
3134 if (TM->getRelocationModel() != Reloc::PIC_)
3137 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3138 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3140 // If we didn't need a GlobalBaseReg, don't insert code.
3141 if (GlobalBaseReg == 0)
3144 // Insert the set of GlobalBaseReg into the first MBB of the function
3145 MachineBasicBlock &FirstMBB = MF.front();
3146 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3147 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3148 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3149 const X86InstrInfo *TII = TM->getInstrInfo();
3152 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3153 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3157 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3158 // only used in JIT code emission as displacement to pc.
3159 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3161 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3162 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3163 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3164 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3165 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3166 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3167 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3173 virtual const char *getPassName() const {
3174 return "X86 PIC Global Base Reg Initialization";
3177 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3178 AU.setPreservesCFG();
3179 MachineFunctionPass::getAnalysisUsage(AU);
3186 llvm::createGlobalBaseRegPass() { return new CGBR(); }