1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetAsmInfo.h"
34 NoFusing("disable-spill-fusing",
35 cl::desc("Disable fusing of spill code into instructions"));
37 PrintFailedFusing("print-failed-fuse-candidates",
38 cl::desc("Print instructions that the allocator wants to"
39 " fuse, but the X86 backend currently can't"),
42 ReMatPICStubLoad("remat-pic-stub-load",
43 cl::desc("Re-materialize load from stub in PIC mode"),
44 cl::init(false), cl::Hidden);
47 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
48 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
49 TM(tm), RI(tm, *this) {
50 SmallVector<unsigned,16> AmbEntries;
51 static const unsigned OpTbl2Addr[][2] = {
52 { X86::ADC32ri, X86::ADC32mi },
53 { X86::ADC32ri8, X86::ADC32mi8 },
54 { X86::ADC32rr, X86::ADC32mr },
55 { X86::ADC64ri32, X86::ADC64mi32 },
56 { X86::ADC64ri8, X86::ADC64mi8 },
57 { X86::ADC64rr, X86::ADC64mr },
58 { X86::ADD16ri, X86::ADD16mi },
59 { X86::ADD16ri8, X86::ADD16mi8 },
60 { X86::ADD16rr, X86::ADD16mr },
61 { X86::ADD32ri, X86::ADD32mi },
62 { X86::ADD32ri8, X86::ADD32mi8 },
63 { X86::ADD32rr, X86::ADD32mr },
64 { X86::ADD64ri32, X86::ADD64mi32 },
65 { X86::ADD64ri8, X86::ADD64mi8 },
66 { X86::ADD64rr, X86::ADD64mr },
67 { X86::ADD8ri, X86::ADD8mi },
68 { X86::ADD8rr, X86::ADD8mr },
69 { X86::AND16ri, X86::AND16mi },
70 { X86::AND16ri8, X86::AND16mi8 },
71 { X86::AND16rr, X86::AND16mr },
72 { X86::AND32ri, X86::AND32mi },
73 { X86::AND32ri8, X86::AND32mi8 },
74 { X86::AND32rr, X86::AND32mr },
75 { X86::AND64ri32, X86::AND64mi32 },
76 { X86::AND64ri8, X86::AND64mi8 },
77 { X86::AND64rr, X86::AND64mr },
78 { X86::AND8ri, X86::AND8mi },
79 { X86::AND8rr, X86::AND8mr },
80 { X86::DEC16r, X86::DEC16m },
81 { X86::DEC32r, X86::DEC32m },
82 { X86::DEC64_16r, X86::DEC64_16m },
83 { X86::DEC64_32r, X86::DEC64_32m },
84 { X86::DEC64r, X86::DEC64m },
85 { X86::DEC8r, X86::DEC8m },
86 { X86::INC16r, X86::INC16m },
87 { X86::INC32r, X86::INC32m },
88 { X86::INC64_16r, X86::INC64_16m },
89 { X86::INC64_32r, X86::INC64_32m },
90 { X86::INC64r, X86::INC64m },
91 { X86::INC8r, X86::INC8m },
92 { X86::NEG16r, X86::NEG16m },
93 { X86::NEG32r, X86::NEG32m },
94 { X86::NEG64r, X86::NEG64m },
95 { X86::NEG8r, X86::NEG8m },
96 { X86::NOT16r, X86::NOT16m },
97 { X86::NOT32r, X86::NOT32m },
98 { X86::NOT64r, X86::NOT64m },
99 { X86::NOT8r, X86::NOT8m },
100 { X86::OR16ri, X86::OR16mi },
101 { X86::OR16ri8, X86::OR16mi8 },
102 { X86::OR16rr, X86::OR16mr },
103 { X86::OR32ri, X86::OR32mi },
104 { X86::OR32ri8, X86::OR32mi8 },
105 { X86::OR32rr, X86::OR32mr },
106 { X86::OR64ri32, X86::OR64mi32 },
107 { X86::OR64ri8, X86::OR64mi8 },
108 { X86::OR64rr, X86::OR64mr },
109 { X86::OR8ri, X86::OR8mi },
110 { X86::OR8rr, X86::OR8mr },
111 { X86::ROL16r1, X86::ROL16m1 },
112 { X86::ROL16rCL, X86::ROL16mCL },
113 { X86::ROL16ri, X86::ROL16mi },
114 { X86::ROL32r1, X86::ROL32m1 },
115 { X86::ROL32rCL, X86::ROL32mCL },
116 { X86::ROL32ri, X86::ROL32mi },
117 { X86::ROL64r1, X86::ROL64m1 },
118 { X86::ROL64rCL, X86::ROL64mCL },
119 { X86::ROL64ri, X86::ROL64mi },
120 { X86::ROL8r1, X86::ROL8m1 },
121 { X86::ROL8rCL, X86::ROL8mCL },
122 { X86::ROL8ri, X86::ROL8mi },
123 { X86::ROR16r1, X86::ROR16m1 },
124 { X86::ROR16rCL, X86::ROR16mCL },
125 { X86::ROR16ri, X86::ROR16mi },
126 { X86::ROR32r1, X86::ROR32m1 },
127 { X86::ROR32rCL, X86::ROR32mCL },
128 { X86::ROR32ri, X86::ROR32mi },
129 { X86::ROR64r1, X86::ROR64m1 },
130 { X86::ROR64rCL, X86::ROR64mCL },
131 { X86::ROR64ri, X86::ROR64mi },
132 { X86::ROR8r1, X86::ROR8m1 },
133 { X86::ROR8rCL, X86::ROR8mCL },
134 { X86::ROR8ri, X86::ROR8mi },
135 { X86::SAR16r1, X86::SAR16m1 },
136 { X86::SAR16rCL, X86::SAR16mCL },
137 { X86::SAR16ri, X86::SAR16mi },
138 { X86::SAR32r1, X86::SAR32m1 },
139 { X86::SAR32rCL, X86::SAR32mCL },
140 { X86::SAR32ri, X86::SAR32mi },
141 { X86::SAR64r1, X86::SAR64m1 },
142 { X86::SAR64rCL, X86::SAR64mCL },
143 { X86::SAR64ri, X86::SAR64mi },
144 { X86::SAR8r1, X86::SAR8m1 },
145 { X86::SAR8rCL, X86::SAR8mCL },
146 { X86::SAR8ri, X86::SAR8mi },
147 { X86::SBB32ri, X86::SBB32mi },
148 { X86::SBB32ri8, X86::SBB32mi8 },
149 { X86::SBB32rr, X86::SBB32mr },
150 { X86::SBB64ri32, X86::SBB64mi32 },
151 { X86::SBB64ri8, X86::SBB64mi8 },
152 { X86::SBB64rr, X86::SBB64mr },
153 { X86::SHL16rCL, X86::SHL16mCL },
154 { X86::SHL16ri, X86::SHL16mi },
155 { X86::SHL32rCL, X86::SHL32mCL },
156 { X86::SHL32ri, X86::SHL32mi },
157 { X86::SHL64rCL, X86::SHL64mCL },
158 { X86::SHL64ri, X86::SHL64mi },
159 { X86::SHL8rCL, X86::SHL8mCL },
160 { X86::SHL8ri, X86::SHL8mi },
161 { X86::SHLD16rrCL, X86::SHLD16mrCL },
162 { X86::SHLD16rri8, X86::SHLD16mri8 },
163 { X86::SHLD32rrCL, X86::SHLD32mrCL },
164 { X86::SHLD32rri8, X86::SHLD32mri8 },
165 { X86::SHLD64rrCL, X86::SHLD64mrCL },
166 { X86::SHLD64rri8, X86::SHLD64mri8 },
167 { X86::SHR16r1, X86::SHR16m1 },
168 { X86::SHR16rCL, X86::SHR16mCL },
169 { X86::SHR16ri, X86::SHR16mi },
170 { X86::SHR32r1, X86::SHR32m1 },
171 { X86::SHR32rCL, X86::SHR32mCL },
172 { X86::SHR32ri, X86::SHR32mi },
173 { X86::SHR64r1, X86::SHR64m1 },
174 { X86::SHR64rCL, X86::SHR64mCL },
175 { X86::SHR64ri, X86::SHR64mi },
176 { X86::SHR8r1, X86::SHR8m1 },
177 { X86::SHR8rCL, X86::SHR8mCL },
178 { X86::SHR8ri, X86::SHR8mi },
179 { X86::SHRD16rrCL, X86::SHRD16mrCL },
180 { X86::SHRD16rri8, X86::SHRD16mri8 },
181 { X86::SHRD32rrCL, X86::SHRD32mrCL },
182 { X86::SHRD32rri8, X86::SHRD32mri8 },
183 { X86::SHRD64rrCL, X86::SHRD64mrCL },
184 { X86::SHRD64rri8, X86::SHRD64mri8 },
185 { X86::SUB16ri, X86::SUB16mi },
186 { X86::SUB16ri8, X86::SUB16mi8 },
187 { X86::SUB16rr, X86::SUB16mr },
188 { X86::SUB32ri, X86::SUB32mi },
189 { X86::SUB32ri8, X86::SUB32mi8 },
190 { X86::SUB32rr, X86::SUB32mr },
191 { X86::SUB64ri32, X86::SUB64mi32 },
192 { X86::SUB64ri8, X86::SUB64mi8 },
193 { X86::SUB64rr, X86::SUB64mr },
194 { X86::SUB8ri, X86::SUB8mi },
195 { X86::SUB8rr, X86::SUB8mr },
196 { X86::XOR16ri, X86::XOR16mi },
197 { X86::XOR16ri8, X86::XOR16mi8 },
198 { X86::XOR16rr, X86::XOR16mr },
199 { X86::XOR32ri, X86::XOR32mi },
200 { X86::XOR32ri8, X86::XOR32mi8 },
201 { X86::XOR32rr, X86::XOR32mr },
202 { X86::XOR64ri32, X86::XOR64mi32 },
203 { X86::XOR64ri8, X86::XOR64mi8 },
204 { X86::XOR64rr, X86::XOR64mr },
205 { X86::XOR8ri, X86::XOR8mi },
206 { X86::XOR8rr, X86::XOR8mr }
209 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
210 unsigned RegOp = OpTbl2Addr[i][0];
211 unsigned MemOp = OpTbl2Addr[i][1];
212 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
214 assert(false && "Duplicated entries?");
215 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
216 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
217 std::make_pair(RegOp,
219 AmbEntries.push_back(MemOp);
222 // If the third value is 1, then it's folding either a load or a store.
223 static const unsigned OpTbl0[][3] = {
224 { X86::CALL32r, X86::CALL32m, 1 },
225 { X86::CALL64r, X86::CALL64m, 1 },
226 { X86::CMP16ri, X86::CMP16mi, 1 },
227 { X86::CMP16ri8, X86::CMP16mi8, 1 },
228 { X86::CMP16rr, X86::CMP16mr, 1 },
229 { X86::CMP32ri, X86::CMP32mi, 1 },
230 { X86::CMP32ri8, X86::CMP32mi8, 1 },
231 { X86::CMP32rr, X86::CMP32mr, 1 },
232 { X86::CMP64ri32, X86::CMP64mi32, 1 },
233 { X86::CMP64ri8, X86::CMP64mi8, 1 },
234 { X86::CMP64rr, X86::CMP64mr, 1 },
235 { X86::CMP8ri, X86::CMP8mi, 1 },
236 { X86::CMP8rr, X86::CMP8mr, 1 },
237 { X86::DIV16r, X86::DIV16m, 1 },
238 { X86::DIV32r, X86::DIV32m, 1 },
239 { X86::DIV64r, X86::DIV64m, 1 },
240 { X86::DIV8r, X86::DIV8m, 1 },
241 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
242 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
243 { X86::IDIV16r, X86::IDIV16m, 1 },
244 { X86::IDIV32r, X86::IDIV32m, 1 },
245 { X86::IDIV64r, X86::IDIV64m, 1 },
246 { X86::IDIV8r, X86::IDIV8m, 1 },
247 { X86::IMUL16r, X86::IMUL16m, 1 },
248 { X86::IMUL32r, X86::IMUL32m, 1 },
249 { X86::IMUL64r, X86::IMUL64m, 1 },
250 { X86::IMUL8r, X86::IMUL8m, 1 },
251 { X86::JMP32r, X86::JMP32m, 1 },
252 { X86::JMP64r, X86::JMP64m, 1 },
253 { X86::MOV16ri, X86::MOV16mi, 0 },
254 { X86::MOV16rr, X86::MOV16mr, 0 },
255 { X86::MOV16to16_, X86::MOV16_mr, 0 },
256 { X86::MOV32ri, X86::MOV32mi, 0 },
257 { X86::MOV32rr, X86::MOV32mr, 0 },
258 { X86::MOV32to32_, X86::MOV32_mr, 0 },
259 { X86::MOV64ri32, X86::MOV64mi32, 0 },
260 { X86::MOV64rr, X86::MOV64mr, 0 },
261 { X86::MOV8ri, X86::MOV8mi, 0 },
262 { X86::MOV8rr, X86::MOV8mr, 0 },
263 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
264 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
265 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
266 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
267 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
268 { X86::MOVSDrr, X86::MOVSDmr, 0 },
269 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
270 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
271 { X86::MOVSSrr, X86::MOVSSmr, 0 },
272 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
273 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
274 { X86::MUL16r, X86::MUL16m, 1 },
275 { X86::MUL32r, X86::MUL32m, 1 },
276 { X86::MUL64r, X86::MUL64m, 1 },
277 { X86::MUL8r, X86::MUL8m, 1 },
278 { X86::SETAEr, X86::SETAEm, 0 },
279 { X86::SETAr, X86::SETAm, 0 },
280 { X86::SETBEr, X86::SETBEm, 0 },
281 { X86::SETBr, X86::SETBm, 0 },
282 { X86::SETEr, X86::SETEm, 0 },
283 { X86::SETGEr, X86::SETGEm, 0 },
284 { X86::SETGr, X86::SETGm, 0 },
285 { X86::SETLEr, X86::SETLEm, 0 },
286 { X86::SETLr, X86::SETLm, 0 },
287 { X86::SETNEr, X86::SETNEm, 0 },
288 { X86::SETNPr, X86::SETNPm, 0 },
289 { X86::SETNSr, X86::SETNSm, 0 },
290 { X86::SETPr, X86::SETPm, 0 },
291 { X86::SETSr, X86::SETSm, 0 },
292 { X86::TAILJMPr, X86::TAILJMPm, 1 },
293 { X86::TEST16ri, X86::TEST16mi, 1 },
294 { X86::TEST32ri, X86::TEST32mi, 1 },
295 { X86::TEST64ri32, X86::TEST64mi32, 1 },
296 { X86::TEST8ri, X86::TEST8mi, 1 }
299 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
300 unsigned RegOp = OpTbl0[i][0];
301 unsigned MemOp = OpTbl0[i][1];
302 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
304 assert(false && "Duplicated entries?");
305 unsigned FoldedLoad = OpTbl0[i][2];
306 // Index 0, folded load or store.
307 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
308 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
309 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
310 std::make_pair(RegOp, AuxInfo))).second)
311 AmbEntries.push_back(MemOp);
314 static const unsigned OpTbl1[][2] = {
315 { X86::CMP16rr, X86::CMP16rm },
316 { X86::CMP32rr, X86::CMP32rm },
317 { X86::CMP64rr, X86::CMP64rm },
318 { X86::CMP8rr, X86::CMP8rm },
319 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
320 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
321 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
322 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
323 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
324 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
325 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
326 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
327 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
328 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
329 { X86::FsMOVAPDrr, X86::MOVSDrm },
330 { X86::FsMOVAPSrr, X86::MOVSSrm },
331 { X86::IMUL16rri, X86::IMUL16rmi },
332 { X86::IMUL16rri8, X86::IMUL16rmi8 },
333 { X86::IMUL32rri, X86::IMUL32rmi },
334 { X86::IMUL32rri8, X86::IMUL32rmi8 },
335 { X86::IMUL64rri32, X86::IMUL64rmi32 },
336 { X86::IMUL64rri8, X86::IMUL64rmi8 },
337 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
338 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
339 { X86::Int_COMISDrr, X86::Int_COMISDrm },
340 { X86::Int_COMISSrr, X86::Int_COMISSrm },
341 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
342 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
343 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
344 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
345 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
346 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
347 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
348 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
349 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
350 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
351 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
352 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
353 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
354 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
355 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
356 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
357 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
358 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
359 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
360 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
361 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
362 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
363 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
364 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
365 { X86::MOV16rr, X86::MOV16rm },
366 { X86::MOV16to16_, X86::MOV16_rm },
367 { X86::MOV32rr, X86::MOV32rm },
368 { X86::MOV32to32_, X86::MOV32_rm },
369 { X86::MOV64rr, X86::MOV64rm },
370 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
371 { X86::MOV64toSDrr, X86::MOV64toSDrm },
372 { X86::MOV8rr, X86::MOV8rm },
373 { X86::MOVAPDrr, X86::MOVAPDrm },
374 { X86::MOVAPSrr, X86::MOVAPSrm },
375 { X86::MOVDDUPrr, X86::MOVDDUPrm },
376 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
377 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
378 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
379 { X86::MOVSDrr, X86::MOVSDrm },
380 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
381 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
382 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
383 { X86::MOVSSrr, X86::MOVSSrm },
384 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
385 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
386 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
387 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
388 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
389 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
390 { X86::MOVUPDrr, X86::MOVUPDrm },
391 { X86::MOVUPSrr, X86::MOVUPSrm },
392 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
393 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
394 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
395 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
396 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
397 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
398 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
399 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
400 { X86::PSHUFDri, X86::PSHUFDmi },
401 { X86::PSHUFHWri, X86::PSHUFHWmi },
402 { X86::PSHUFLWri, X86::PSHUFLWmi },
403 { X86::RCPPSr, X86::RCPPSm },
404 { X86::RCPPSr_Int, X86::RCPPSm_Int },
405 { X86::RSQRTPSr, X86::RSQRTPSm },
406 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
407 { X86::RSQRTSSr, X86::RSQRTSSm },
408 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
409 { X86::SQRTPDr, X86::SQRTPDm },
410 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
411 { X86::SQRTPSr, X86::SQRTPSm },
412 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
413 { X86::SQRTSDr, X86::SQRTSDm },
414 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
415 { X86::SQRTSSr, X86::SQRTSSm },
416 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
417 { X86::TEST16rr, X86::TEST16rm },
418 { X86::TEST32rr, X86::TEST32rm },
419 { X86::TEST64rr, X86::TEST64rm },
420 { X86::TEST8rr, X86::TEST8rm },
421 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
422 { X86::UCOMISDrr, X86::UCOMISDrm },
423 { X86::UCOMISSrr, X86::UCOMISSrm }
426 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
427 unsigned RegOp = OpTbl1[i][0];
428 unsigned MemOp = OpTbl1[i][1];
429 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
431 assert(false && "Duplicated entries?");
432 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
433 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
434 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
435 std::make_pair(RegOp, AuxInfo))).second)
436 AmbEntries.push_back(MemOp);
439 static const unsigned OpTbl2[][2] = {
440 { X86::ADC32rr, X86::ADC32rm },
441 { X86::ADC64rr, X86::ADC64rm },
442 { X86::ADD16rr, X86::ADD16rm },
443 { X86::ADD32rr, X86::ADD32rm },
444 { X86::ADD64rr, X86::ADD64rm },
445 { X86::ADD8rr, X86::ADD8rm },
446 { X86::ADDPDrr, X86::ADDPDrm },
447 { X86::ADDPSrr, X86::ADDPSrm },
448 { X86::ADDSDrr, X86::ADDSDrm },
449 { X86::ADDSSrr, X86::ADDSSrm },
450 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
451 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
452 { X86::AND16rr, X86::AND16rm },
453 { X86::AND32rr, X86::AND32rm },
454 { X86::AND64rr, X86::AND64rm },
455 { X86::AND8rr, X86::AND8rm },
456 { X86::ANDNPDrr, X86::ANDNPDrm },
457 { X86::ANDNPSrr, X86::ANDNPSrm },
458 { X86::ANDPDrr, X86::ANDPDrm },
459 { X86::ANDPSrr, X86::ANDPSrm },
460 { X86::CMOVA16rr, X86::CMOVA16rm },
461 { X86::CMOVA32rr, X86::CMOVA32rm },
462 { X86::CMOVA64rr, X86::CMOVA64rm },
463 { X86::CMOVAE16rr, X86::CMOVAE16rm },
464 { X86::CMOVAE32rr, X86::CMOVAE32rm },
465 { X86::CMOVAE64rr, X86::CMOVAE64rm },
466 { X86::CMOVB16rr, X86::CMOVB16rm },
467 { X86::CMOVB32rr, X86::CMOVB32rm },
468 { X86::CMOVB64rr, X86::CMOVB64rm },
469 { X86::CMOVBE16rr, X86::CMOVBE16rm },
470 { X86::CMOVBE32rr, X86::CMOVBE32rm },
471 { X86::CMOVBE64rr, X86::CMOVBE64rm },
472 { X86::CMOVE16rr, X86::CMOVE16rm },
473 { X86::CMOVE32rr, X86::CMOVE32rm },
474 { X86::CMOVE64rr, X86::CMOVE64rm },
475 { X86::CMOVG16rr, X86::CMOVG16rm },
476 { X86::CMOVG32rr, X86::CMOVG32rm },
477 { X86::CMOVG64rr, X86::CMOVG64rm },
478 { X86::CMOVGE16rr, X86::CMOVGE16rm },
479 { X86::CMOVGE32rr, X86::CMOVGE32rm },
480 { X86::CMOVGE64rr, X86::CMOVGE64rm },
481 { X86::CMOVL16rr, X86::CMOVL16rm },
482 { X86::CMOVL32rr, X86::CMOVL32rm },
483 { X86::CMOVL64rr, X86::CMOVL64rm },
484 { X86::CMOVLE16rr, X86::CMOVLE16rm },
485 { X86::CMOVLE32rr, X86::CMOVLE32rm },
486 { X86::CMOVLE64rr, X86::CMOVLE64rm },
487 { X86::CMOVNE16rr, X86::CMOVNE16rm },
488 { X86::CMOVNE32rr, X86::CMOVNE32rm },
489 { X86::CMOVNE64rr, X86::CMOVNE64rm },
490 { X86::CMOVNP16rr, X86::CMOVNP16rm },
491 { X86::CMOVNP32rr, X86::CMOVNP32rm },
492 { X86::CMOVNP64rr, X86::CMOVNP64rm },
493 { X86::CMOVNS16rr, X86::CMOVNS16rm },
494 { X86::CMOVNS32rr, X86::CMOVNS32rm },
495 { X86::CMOVNS64rr, X86::CMOVNS64rm },
496 { X86::CMOVP16rr, X86::CMOVP16rm },
497 { X86::CMOVP32rr, X86::CMOVP32rm },
498 { X86::CMOVP64rr, X86::CMOVP64rm },
499 { X86::CMOVS16rr, X86::CMOVS16rm },
500 { X86::CMOVS32rr, X86::CMOVS32rm },
501 { X86::CMOVS64rr, X86::CMOVS64rm },
502 { X86::CMPPDrri, X86::CMPPDrmi },
503 { X86::CMPPSrri, X86::CMPPSrmi },
504 { X86::CMPSDrr, X86::CMPSDrm },
505 { X86::CMPSSrr, X86::CMPSSrm },
506 { X86::DIVPDrr, X86::DIVPDrm },
507 { X86::DIVPSrr, X86::DIVPSrm },
508 { X86::DIVSDrr, X86::DIVSDrm },
509 { X86::DIVSSrr, X86::DIVSSrm },
510 { X86::FsANDNPDrr, X86::FsANDNPDrm },
511 { X86::FsANDNPSrr, X86::FsANDNPSrm },
512 { X86::FsANDPDrr, X86::FsANDPDrm },
513 { X86::FsANDPSrr, X86::FsANDPSrm },
514 { X86::FsORPDrr, X86::FsORPDrm },
515 { X86::FsORPSrr, X86::FsORPSrm },
516 { X86::FsXORPDrr, X86::FsXORPDrm },
517 { X86::FsXORPSrr, X86::FsXORPSrm },
518 { X86::HADDPDrr, X86::HADDPDrm },
519 { X86::HADDPSrr, X86::HADDPSrm },
520 { X86::HSUBPDrr, X86::HSUBPDrm },
521 { X86::HSUBPSrr, X86::HSUBPSrm },
522 { X86::IMUL16rr, X86::IMUL16rm },
523 { X86::IMUL32rr, X86::IMUL32rm },
524 { X86::IMUL64rr, X86::IMUL64rm },
525 { X86::MAXPDrr, X86::MAXPDrm },
526 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
527 { X86::MAXPSrr, X86::MAXPSrm },
528 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
529 { X86::MAXSDrr, X86::MAXSDrm },
530 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
531 { X86::MAXSSrr, X86::MAXSSrm },
532 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
533 { X86::MINPDrr, X86::MINPDrm },
534 { X86::MINPDrr_Int, X86::MINPDrm_Int },
535 { X86::MINPSrr, X86::MINPSrm },
536 { X86::MINPSrr_Int, X86::MINPSrm_Int },
537 { X86::MINSDrr, X86::MINSDrm },
538 { X86::MINSDrr_Int, X86::MINSDrm_Int },
539 { X86::MINSSrr, X86::MINSSrm },
540 { X86::MINSSrr_Int, X86::MINSSrm_Int },
541 { X86::MULPDrr, X86::MULPDrm },
542 { X86::MULPSrr, X86::MULPSrm },
543 { X86::MULSDrr, X86::MULSDrm },
544 { X86::MULSSrr, X86::MULSSrm },
545 { X86::OR16rr, X86::OR16rm },
546 { X86::OR32rr, X86::OR32rm },
547 { X86::OR64rr, X86::OR64rm },
548 { X86::OR8rr, X86::OR8rm },
549 { X86::ORPDrr, X86::ORPDrm },
550 { X86::ORPSrr, X86::ORPSrm },
551 { X86::PACKSSDWrr, X86::PACKSSDWrm },
552 { X86::PACKSSWBrr, X86::PACKSSWBrm },
553 { X86::PACKUSWBrr, X86::PACKUSWBrm },
554 { X86::PADDBrr, X86::PADDBrm },
555 { X86::PADDDrr, X86::PADDDrm },
556 { X86::PADDQrr, X86::PADDQrm },
557 { X86::PADDSBrr, X86::PADDSBrm },
558 { X86::PADDSWrr, X86::PADDSWrm },
559 { X86::PADDWrr, X86::PADDWrm },
560 { X86::PANDNrr, X86::PANDNrm },
561 { X86::PANDrr, X86::PANDrm },
562 { X86::PAVGBrr, X86::PAVGBrm },
563 { X86::PAVGWrr, X86::PAVGWrm },
564 { X86::PCMPEQBrr, X86::PCMPEQBrm },
565 { X86::PCMPEQDrr, X86::PCMPEQDrm },
566 { X86::PCMPEQWrr, X86::PCMPEQWrm },
567 { X86::PCMPGTBrr, X86::PCMPGTBrm },
568 { X86::PCMPGTDrr, X86::PCMPGTDrm },
569 { X86::PCMPGTWrr, X86::PCMPGTWrm },
570 { X86::PINSRWrri, X86::PINSRWrmi },
571 { X86::PMADDWDrr, X86::PMADDWDrm },
572 { X86::PMAXSWrr, X86::PMAXSWrm },
573 { X86::PMAXUBrr, X86::PMAXUBrm },
574 { X86::PMINSWrr, X86::PMINSWrm },
575 { X86::PMINUBrr, X86::PMINUBrm },
576 { X86::PMULDQrr, X86::PMULDQrm },
577 { X86::PMULDQrr_int, X86::PMULDQrm_int },
578 { X86::PMULHUWrr, X86::PMULHUWrm },
579 { X86::PMULHWrr, X86::PMULHWrm },
580 { X86::PMULLDrr, X86::PMULLDrm },
581 { X86::PMULLDrr_int, X86::PMULLDrm_int },
582 { X86::PMULLWrr, X86::PMULLWrm },
583 { X86::PMULUDQrr, X86::PMULUDQrm },
584 { X86::PORrr, X86::PORrm },
585 { X86::PSADBWrr, X86::PSADBWrm },
586 { X86::PSLLDrr, X86::PSLLDrm },
587 { X86::PSLLQrr, X86::PSLLQrm },
588 { X86::PSLLWrr, X86::PSLLWrm },
589 { X86::PSRADrr, X86::PSRADrm },
590 { X86::PSRAWrr, X86::PSRAWrm },
591 { X86::PSRLDrr, X86::PSRLDrm },
592 { X86::PSRLQrr, X86::PSRLQrm },
593 { X86::PSRLWrr, X86::PSRLWrm },
594 { X86::PSUBBrr, X86::PSUBBrm },
595 { X86::PSUBDrr, X86::PSUBDrm },
596 { X86::PSUBSBrr, X86::PSUBSBrm },
597 { X86::PSUBSWrr, X86::PSUBSWrm },
598 { X86::PSUBWrr, X86::PSUBWrm },
599 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
600 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
601 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
602 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
603 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
604 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
605 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
606 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
607 { X86::PXORrr, X86::PXORrm },
608 { X86::SBB32rr, X86::SBB32rm },
609 { X86::SBB64rr, X86::SBB64rm },
610 { X86::SHUFPDrri, X86::SHUFPDrmi },
611 { X86::SHUFPSrri, X86::SHUFPSrmi },
612 { X86::SUB16rr, X86::SUB16rm },
613 { X86::SUB32rr, X86::SUB32rm },
614 { X86::SUB64rr, X86::SUB64rm },
615 { X86::SUB8rr, X86::SUB8rm },
616 { X86::SUBPDrr, X86::SUBPDrm },
617 { X86::SUBPSrr, X86::SUBPSrm },
618 { X86::SUBSDrr, X86::SUBSDrm },
619 { X86::SUBSSrr, X86::SUBSSrm },
620 // FIXME: TEST*rr -> swapped operand of TEST*mr.
621 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
622 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
623 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
624 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
625 { X86::XOR16rr, X86::XOR16rm },
626 { X86::XOR32rr, X86::XOR32rm },
627 { X86::XOR64rr, X86::XOR64rm },
628 { X86::XOR8rr, X86::XOR8rm },
629 { X86::XORPDrr, X86::XORPDrm },
630 { X86::XORPSrr, X86::XORPSrm }
633 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
634 unsigned RegOp = OpTbl2[i][0];
635 unsigned MemOp = OpTbl2[i][1];
636 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
638 assert(false && "Duplicated entries?");
639 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
640 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
641 std::make_pair(RegOp, AuxInfo))).second)
642 AmbEntries.push_back(MemOp);
645 // Remove ambiguous entries.
646 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
649 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
651 unsigned& destReg) const {
652 switch (MI.getOpcode()) {
659 case X86::MOV16to16_:
660 case X86::MOV32to32_:
664 // FP Stack register class copies
665 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
666 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
667 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
669 case X86::FsMOVAPSrr:
670 case X86::FsMOVAPDrr:
673 case X86::MOVSS2PSrr:
674 case X86::MOVSD2PDrr:
675 case X86::MOVPS2SSrr:
676 case X86::MOVPD2SDrr:
677 case X86::MMX_MOVD64rr:
678 case X86::MMX_MOVQ64rr:
679 assert(MI.getNumOperands() >= 2 &&
680 MI.getOperand(0).isRegister() &&
681 MI.getOperand(1).isRegister() &&
682 "invalid register-register move instruction");
683 sourceReg = MI.getOperand(1).getReg();
684 destReg = MI.getOperand(0).getReg();
689 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
690 int &FrameIndex) const {
691 switch (MI->getOpcode()) {
704 case X86::MMX_MOVD64rm:
705 case X86::MMX_MOVQ64rm:
706 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
707 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
708 MI->getOperand(2).getImm() == 1 &&
709 MI->getOperand(3).getReg() == 0 &&
710 MI->getOperand(4).getImm() == 0) {
711 FrameIndex = MI->getOperand(1).getIndex();
712 return MI->getOperand(0).getReg();
719 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
720 int &FrameIndex) const {
721 switch (MI->getOpcode()) {
734 case X86::MMX_MOVD64mr:
735 case X86::MMX_MOVQ64mr:
736 case X86::MMX_MOVNTQmr:
737 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
738 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
739 MI->getOperand(1).getImm() == 1 &&
740 MI->getOperand(2).getReg() == 0 &&
741 MI->getOperand(3).getImm() == 0) {
742 FrameIndex = MI->getOperand(0).getIndex();
743 return MI->getOperand(4).getReg();
751 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
753 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
754 bool isPICBase = false;
755 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
756 E = MRI.def_end(); I != E; ++I) {
757 MachineInstr *DefMI = I.getOperand().getParent();
758 if (DefMI->getOpcode() != X86::MOVPC32r)
760 assert(!isPICBase && "More than one PIC base?");
766 /// isGVStub - Return true if the GV requires an extra load to get the
768 static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
769 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
773 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
774 switch (MI->getOpcode()) {
787 case X86::MMX_MOVD64rm:
788 case X86::MMX_MOVQ64rm: {
789 // Loads from constant pools are trivially rematerializable.
790 if (MI->getOperand(1).isReg() &&
791 MI->getOperand(2).isImm() &&
792 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
793 (MI->getOperand(4).isCPI() ||
794 (MI->getOperand(4).isGlobal() &&
795 isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
796 unsigned BaseReg = MI->getOperand(1).getReg();
799 // Allow re-materialization of PIC load.
800 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
802 const MachineFunction &MF = *MI->getParent()->getParent();
803 const MachineRegisterInfo &MRI = MF.getRegInfo();
804 bool isPICBase = false;
805 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
806 E = MRI.def_end(); I != E; ++I) {
807 MachineInstr *DefMI = I.getOperand().getParent();
808 if (DefMI->getOpcode() != X86::MOVPC32r)
810 assert(!isPICBase && "More than one PIC base?");
820 if (MI->getOperand(1).isReg() &&
821 MI->getOperand(2).isImm() &&
822 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
823 !MI->getOperand(4).isReg()) {
824 // lea fi#, lea GV, etc. are all rematerializable.
825 unsigned BaseReg = MI->getOperand(1).getReg();
828 // Allow re-materialization of lea PICBase + x.
829 const MachineFunction &MF = *MI->getParent()->getParent();
830 const MachineRegisterInfo &MRI = MF.getRegInfo();
831 return regIsPICBase(BaseReg, MRI);
837 // All other instructions marked M_REMATERIALIZABLE are always trivially
842 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
843 /// would clobber the EFLAGS condition register. Note the result may be
844 /// conservative. If it cannot definitely determine the safety after visiting
845 /// two instructions it assumes it's not safe.
846 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
847 MachineBasicBlock::iterator I) {
848 // For compile time consideration, if we are not able to determine the
849 // safety after visiting 2 instructions, we will assume it's not safe.
850 for (unsigned i = 0; i < 2; ++i) {
852 // Reached end of block, it's safe.
854 bool SeenDef = false;
855 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
856 MachineOperand &MO = I->getOperand(j);
857 if (!MO.isRegister())
859 if (MO.getReg() == X86::EFLAGS) {
867 // This instruction defines EFLAGS, no need to look any further.
872 // Conservative answer.
876 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
877 MachineBasicBlock::iterator I,
879 const MachineInstr *Orig) const {
880 unsigned SubIdx = Orig->getOperand(0).isReg()
881 ? Orig->getOperand(0).getSubReg() : 0;
882 bool ChangeSubIdx = SubIdx != 0;
883 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
884 DestReg = RI.getSubReg(DestReg, SubIdx);
888 // MOV32r0 etc. are implemented with xor which clobbers condition code.
889 // Re-materialize them as movri instructions to avoid side effects.
890 bool Emitted = false;
891 switch (Orig->getOpcode()) {
897 if (!isSafeToClobberEFLAGS(MBB, I)) {
899 switch (Orig->getOpcode()) {
901 case X86::MOV8r0: Opc = X86::MOV8ri; break;
902 case X86::MOV16r0: Opc = X86::MOV16ri; break;
903 case X86::MOV32r0: Opc = X86::MOV32ri; break;
904 case X86::MOV64r0: Opc = X86::MOV64ri32; break;
906 BuildMI(MBB, I, get(Opc), DestReg).addImm(0);
914 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
915 MI->getOperand(0).setReg(DestReg);
920 MachineInstr *NewMI = prior(I);
921 NewMI->getOperand(0).setSubReg(SubIdx);
925 /// isInvariantLoad - Return true if the specified instruction (which is marked
926 /// mayLoad) is loading from a location whose value is invariant across the
927 /// function. For example, loading a value from the constant pool or from
928 /// from the argument area of a function if it does not change. This should
929 /// only return true of *all* loads the instruction does are invariant (if it
930 /// does multiple loads).
931 bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const {
932 // This code cares about loads from three cases: constant pool entries,
933 // invariant argument slots, and global stubs. In order to handle these cases
934 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
935 // operand and base our analysis on it. This is safe because the address of
936 // none of these three cases is ever used as anything other than a load base
937 // and X86 doesn't have any instructions that load from multiple places.
939 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
940 const MachineOperand &MO = MI->getOperand(i);
941 // Loads from constant pools are trivially invariant.
946 return isGVStub(MO.getGlobal(), TM);
948 // If this is a load from an invariant stack slot, the load is a constant.
950 const MachineFrameInfo &MFI =
951 *MI->getParent()->getParent()->getFrameInfo();
952 int Idx = MO.getIndex();
953 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
957 // All other instances of these instructions are presumed to have other
962 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
963 /// is not marked dead.
964 static bool hasLiveCondCodeDef(MachineInstr *MI) {
965 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
966 MachineOperand &MO = MI->getOperand(i);
967 if (MO.isRegister() && MO.isDef() &&
968 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
975 /// convertToThreeAddress - This method must be implemented by targets that
976 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
977 /// may be able to convert a two-address instruction into a true
978 /// three-address instruction on demand. This allows the X86 target (for
979 /// example) to convert ADD and SHL instructions into LEA instructions if they
980 /// would require register copies due to two-addressness.
982 /// This method returns a null pointer if the transformation cannot be
983 /// performed, otherwise it returns the new instruction.
986 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
987 MachineBasicBlock::iterator &MBBI,
988 LiveVariables *LV) const {
989 MachineInstr *MI = MBBI;
990 MachineFunction &MF = *MI->getParent()->getParent();
991 // All instructions input are two-addr instructions. Get the known operands.
992 unsigned Dest = MI->getOperand(0).getReg();
993 unsigned Src = MI->getOperand(1).getReg();
994 bool isDead = MI->getOperand(0).isDead();
995 bool isKill = MI->getOperand(1).isKill();
997 MachineInstr *NewMI = NULL;
998 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
999 // we have better subtarget support, enable the 16-bit LEA generation here.
1000 bool DisableLEA16 = true;
1002 unsigned MIOpc = MI->getOpcode();
1004 case X86::SHUFPSrri: {
1005 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1006 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1008 unsigned B = MI->getOperand(1).getReg();
1009 unsigned C = MI->getOperand(2).getReg();
1010 if (B != C) return 0;
1011 unsigned A = MI->getOperand(0).getReg();
1012 unsigned M = MI->getOperand(3).getImm();
1013 NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
1014 .addReg(B, false, false, isKill).addImm(M);
1017 case X86::SHL64ri: {
1018 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1019 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1020 // the flags produced by a shift yet, so this is safe.
1021 unsigned ShAmt = MI->getOperand(2).getImm();
1022 if (ShAmt == 0 || ShAmt >= 4) return 0;
1024 NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
1025 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
1028 case X86::SHL32ri: {
1029 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1030 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1031 // the flags produced by a shift yet, so this is safe.
1032 unsigned ShAmt = MI->getOperand(2).getImm();
1033 if (ShAmt == 0 || ShAmt >= 4) return 0;
1035 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1036 X86::LEA64_32r : X86::LEA32r;
1037 NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead)
1038 .addReg(0).addImm(1 << ShAmt)
1039 .addReg(Src, false, false, isKill).addImm(0);
1042 case X86::SHL16ri: {
1043 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1044 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1045 // the flags produced by a shift yet, so this is safe.
1046 unsigned ShAmt = MI->getOperand(2).getImm();
1047 if (ShAmt == 0 || ShAmt >= 4) return 0;
1050 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1051 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1052 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1053 ? X86::LEA64_32r : X86::LEA32r;
1054 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1055 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1057 // Build and insert into an implicit UNDEF value. This is OK because
1058 // well be shifting and then extracting the lower 16-bits.
1059 BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg);
1060 MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg)
1061 .addReg(leaInReg).addReg(Src, false, false, isKill)
1062 .addImm(X86::SUBREG_16BIT);
1064 NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
1065 .addReg(leaInReg, false, false, true).addImm(0);
1067 MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG))
1068 .addReg(Dest, true, false, false, isDead)
1069 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
1071 // Update live variables
1072 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1073 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1075 LV->replaceKillInstruction(Src, MI, InsMI);
1077 LV->replaceKillInstruction(Dest, MI, ExtMI);
1081 NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
1082 .addReg(0).addImm(1 << ShAmt)
1083 .addReg(Src, false, false, isKill).addImm(0);
1088 // The following opcodes also sets the condition code register(s). Only
1089 // convert them to equivalent lea if the condition code register def's
1091 if (hasLiveCondCodeDef(MI))
1094 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1099 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1100 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1101 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1102 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1103 .addReg(Dest, true, false, false, isDead),
1108 case X86::INC64_16r:
1109 if (DisableLEA16) return 0;
1110 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1111 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1112 .addReg(Dest, true, false, false, isDead),
1117 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1118 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1119 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1120 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1121 .addReg(Dest, true, false, false, isDead),
1126 case X86::DEC64_16r:
1127 if (DisableLEA16) return 0;
1128 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1129 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1130 .addReg(Dest, true, false, false, isDead),
1134 case X86::ADD32rr: {
1135 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1136 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1137 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1138 unsigned Src2 = MI->getOperand(2).getReg();
1139 bool isKill2 = MI->getOperand(2).isKill();
1140 NewMI = addRegReg(BuildMI(MF, get(Opc))
1141 .addReg(Dest, true, false, false, isDead),
1142 Src, isKill, Src2, isKill2);
1144 LV->replaceKillInstruction(Src2, MI, NewMI);
1147 case X86::ADD16rr: {
1148 if (DisableLEA16) return 0;
1149 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1150 unsigned Src2 = MI->getOperand(2).getReg();
1151 bool isKill2 = MI->getOperand(2).isKill();
1152 NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r))
1153 .addReg(Dest, true, false, false, isDead),
1154 Src, isKill, Src2, isKill2);
1156 LV->replaceKillInstruction(Src2, MI, NewMI);
1159 case X86::ADD64ri32:
1161 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1162 if (MI->getOperand(2).isImmediate())
1163 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
1164 .addReg(Dest, true, false, false, isDead),
1165 Src, isKill, MI->getOperand(2).getImm());
1169 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1170 if (MI->getOperand(2).isImmediate()) {
1171 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1172 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1173 .addReg(Dest, true, false, false, isDead),
1174 Src, isKill, MI->getOperand(2).getImm());
1179 if (DisableLEA16) return 0;
1180 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1181 if (MI->getOperand(2).isImmediate())
1182 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1183 .addReg(Dest, true, false, false, isDead),
1184 Src, isKill, MI->getOperand(2).getImm());
1187 if (DisableLEA16) return 0;
1189 case X86::SHL64ri: {
1190 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
1191 "Unknown shl instruction!");
1192 unsigned ShAmt = MI->getOperand(2).getImm();
1193 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1195 AM.Scale = 1 << ShAmt;
1197 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1198 : (MIOpc == X86::SHL32ri
1199 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1200 NewMI = addFullAddress(BuildMI(MF, get(Opc))
1201 .addReg(Dest, true, false, false, isDead), AM);
1203 NewMI->getOperand(3).setIsKill(true);
1211 if (!NewMI) return 0;
1213 if (LV) { // Update live variables
1215 LV->replaceKillInstruction(Src, MI, NewMI);
1217 LV->replaceKillInstruction(Dest, MI, NewMI);
1220 MFI->insert(MBBI, NewMI); // Insert the new inst
1224 /// commuteInstruction - We have a few instructions that must be hacked on to
1228 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1229 switch (MI->getOpcode()) {
1230 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1231 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1232 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1233 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1234 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1235 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1238 switch (MI->getOpcode()) {
1239 default: assert(0 && "Unreachable!");
1240 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1241 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1242 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1243 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1244 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1245 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1247 unsigned Amt = MI->getOperand(3).getImm();
1248 unsigned A = MI->getOperand(0).getReg();
1249 unsigned B = MI->getOperand(1).getReg();
1250 unsigned C = MI->getOperand(2).getReg();
1251 bool AisDead = MI->getOperand(0).isDead();
1252 bool BisKill = MI->getOperand(1).isKill();
1253 bool CisKill = MI->getOperand(2).isKill();
1254 // If machine instrs are no longer in two-address forms, update
1255 // destination register as well.
1257 // Must be two address instruction!
1258 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
1259 "Expecting a two-address instruction!");
1263 MachineFunction &MF = *MI->getParent()->getParent();
1264 return BuildMI(MF, get(Opc))
1265 .addReg(A, true, false, false, AisDead)
1266 .addReg(C, false, false, CisKill)
1267 .addReg(B, false, false, BisKill).addImm(Size-Amt);
1269 case X86::CMOVB16rr:
1270 case X86::CMOVB32rr:
1271 case X86::CMOVB64rr:
1272 case X86::CMOVAE16rr:
1273 case X86::CMOVAE32rr:
1274 case X86::CMOVAE64rr:
1275 case X86::CMOVE16rr:
1276 case X86::CMOVE32rr:
1277 case X86::CMOVE64rr:
1278 case X86::CMOVNE16rr:
1279 case X86::CMOVNE32rr:
1280 case X86::CMOVNE64rr:
1281 case X86::CMOVBE16rr:
1282 case X86::CMOVBE32rr:
1283 case X86::CMOVBE64rr:
1284 case X86::CMOVA16rr:
1285 case X86::CMOVA32rr:
1286 case X86::CMOVA64rr:
1287 case X86::CMOVL16rr:
1288 case X86::CMOVL32rr:
1289 case X86::CMOVL64rr:
1290 case X86::CMOVGE16rr:
1291 case X86::CMOVGE32rr:
1292 case X86::CMOVGE64rr:
1293 case X86::CMOVLE16rr:
1294 case X86::CMOVLE32rr:
1295 case X86::CMOVLE64rr:
1296 case X86::CMOVG16rr:
1297 case X86::CMOVG32rr:
1298 case X86::CMOVG64rr:
1299 case X86::CMOVS16rr:
1300 case X86::CMOVS32rr:
1301 case X86::CMOVS64rr:
1302 case X86::CMOVNS16rr:
1303 case X86::CMOVNS32rr:
1304 case X86::CMOVNS64rr:
1305 case X86::CMOVP16rr:
1306 case X86::CMOVP32rr:
1307 case X86::CMOVP64rr:
1308 case X86::CMOVNP16rr:
1309 case X86::CMOVNP32rr:
1310 case X86::CMOVNP64rr: {
1312 switch (MI->getOpcode()) {
1314 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1315 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1316 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1317 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1318 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1319 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1320 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1321 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1322 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1323 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1324 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1325 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1326 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1327 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1328 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1329 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1330 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1331 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1332 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1333 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1334 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1335 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1336 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1337 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1338 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1339 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1340 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1341 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1342 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1343 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1344 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1345 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1346 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
1347 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1348 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1349 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1350 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1351 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1352 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
1353 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1354 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1355 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1358 MI->setDesc(get(Opc));
1359 // Fallthrough intended.
1362 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1366 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1368 default: return X86::COND_INVALID;
1369 case X86::JE: return X86::COND_E;
1370 case X86::JNE: return X86::COND_NE;
1371 case X86::JL: return X86::COND_L;
1372 case X86::JLE: return X86::COND_LE;
1373 case X86::JG: return X86::COND_G;
1374 case X86::JGE: return X86::COND_GE;
1375 case X86::JB: return X86::COND_B;
1376 case X86::JBE: return X86::COND_BE;
1377 case X86::JA: return X86::COND_A;
1378 case X86::JAE: return X86::COND_AE;
1379 case X86::JS: return X86::COND_S;
1380 case X86::JNS: return X86::COND_NS;
1381 case X86::JP: return X86::COND_P;
1382 case X86::JNP: return X86::COND_NP;
1383 case X86::JO: return X86::COND_O;
1384 case X86::JNO: return X86::COND_NO;
1388 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1390 default: assert(0 && "Illegal condition code!");
1391 case X86::COND_E: return X86::JE;
1392 case X86::COND_NE: return X86::JNE;
1393 case X86::COND_L: return X86::JL;
1394 case X86::COND_LE: return X86::JLE;
1395 case X86::COND_G: return X86::JG;
1396 case X86::COND_GE: return X86::JGE;
1397 case X86::COND_B: return X86::JB;
1398 case X86::COND_BE: return X86::JBE;
1399 case X86::COND_A: return X86::JA;
1400 case X86::COND_AE: return X86::JAE;
1401 case X86::COND_S: return X86::JS;
1402 case X86::COND_NS: return X86::JNS;
1403 case X86::COND_P: return X86::JP;
1404 case X86::COND_NP: return X86::JNP;
1405 case X86::COND_O: return X86::JO;
1406 case X86::COND_NO: return X86::JNO;
1410 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1411 /// e.g. turning COND_E to COND_NE.
1412 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1414 default: assert(0 && "Illegal condition code!");
1415 case X86::COND_E: return X86::COND_NE;
1416 case X86::COND_NE: return X86::COND_E;
1417 case X86::COND_L: return X86::COND_GE;
1418 case X86::COND_LE: return X86::COND_G;
1419 case X86::COND_G: return X86::COND_LE;
1420 case X86::COND_GE: return X86::COND_L;
1421 case X86::COND_B: return X86::COND_AE;
1422 case X86::COND_BE: return X86::COND_A;
1423 case X86::COND_A: return X86::COND_BE;
1424 case X86::COND_AE: return X86::COND_B;
1425 case X86::COND_S: return X86::COND_NS;
1426 case X86::COND_NS: return X86::COND_S;
1427 case X86::COND_P: return X86::COND_NP;
1428 case X86::COND_NP: return X86::COND_P;
1429 case X86::COND_O: return X86::COND_NO;
1430 case X86::COND_NO: return X86::COND_O;
1434 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1435 const TargetInstrDesc &TID = MI->getDesc();
1436 if (!TID.isTerminator()) return false;
1438 // Conditional branch is a special case.
1439 if (TID.isBranch() && !TID.isBarrier())
1441 if (!TID.isPredicable())
1443 return !isPredicated(MI);
1446 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1447 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1448 const X86InstrInfo &TII) {
1449 if (MI->getOpcode() == X86::FP_REG_KILL)
1451 return TII.isUnpredicatedTerminator(MI);
1454 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1455 MachineBasicBlock *&TBB,
1456 MachineBasicBlock *&FBB,
1457 std::vector<MachineOperand> &Cond) const {
1458 // If the block has no terminators, it just falls into the block after it.
1459 MachineBasicBlock::iterator I = MBB.end();
1460 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
1463 // Get the last instruction in the block.
1464 MachineInstr *LastInst = I;
1466 // If there is only one terminator instruction, process it.
1467 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
1468 if (!LastInst->getDesc().isBranch())
1471 // If the block ends with a branch there are 3 possibilities:
1472 // it's an unconditional, conditional, or indirect branch.
1474 if (LastInst->getOpcode() == X86::JMP) {
1475 TBB = LastInst->getOperand(0).getMBB();
1478 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
1479 if (BranchCode == X86::COND_INVALID)
1480 return true; // Can't handle indirect branch.
1482 // Otherwise, block ends with fall-through condbranch.
1483 TBB = LastInst->getOperand(0).getMBB();
1484 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1488 // Get the instruction before it if it's a terminator.
1489 MachineInstr *SecondLastInst = I;
1491 // If there are three terminators, we don't know what sort of block this is.
1492 if (SecondLastInst && I != MBB.begin() &&
1493 isBrAnalysisUnpredicatedTerminator(--I, *this))
1496 // If the block ends with X86::JMP and a conditional branch, handle it.
1497 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
1498 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
1499 TBB = SecondLastInst->getOperand(0).getMBB();
1500 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1501 FBB = LastInst->getOperand(0).getMBB();
1505 // If the block ends with two X86::JMPs, handle it. The second one is not
1506 // executed, so remove it.
1507 if (SecondLastInst->getOpcode() == X86::JMP &&
1508 LastInst->getOpcode() == X86::JMP) {
1509 TBB = SecondLastInst->getOperand(0).getMBB();
1511 I->eraseFromParent();
1515 // Otherwise, can't handle this.
1519 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1520 MachineBasicBlock::iterator I = MBB.end();
1521 if (I == MBB.begin()) return 0;
1523 if (I->getOpcode() != X86::JMP &&
1524 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1527 // Remove the branch.
1528 I->eraseFromParent();
1532 if (I == MBB.begin()) return 1;
1534 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1537 // Remove the branch.
1538 I->eraseFromParent();
1542 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
1543 MachineOperand &MO) {
1544 if (MO.isRegister())
1545 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
1546 MO.isKill(), MO.isDead(), MO.getSubReg());
1547 else if (MO.isImmediate())
1548 MIB = MIB.addImm(MO.getImm());
1549 else if (MO.isFrameIndex())
1550 MIB = MIB.addFrameIndex(MO.getIndex());
1551 else if (MO.isGlobalAddress())
1552 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
1553 else if (MO.isConstantPoolIndex())
1554 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
1555 else if (MO.isJumpTableIndex())
1556 MIB = MIB.addJumpTableIndex(MO.getIndex());
1557 else if (MO.isExternalSymbol())
1558 MIB = MIB.addExternalSymbol(MO.getSymbolName());
1560 assert(0 && "Unknown operand for X86InstrAddOperand!");
1566 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1567 MachineBasicBlock *FBB,
1568 const std::vector<MachineOperand> &Cond) const {
1569 // Shouldn't be a fall through.
1570 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1571 assert((Cond.size() == 1 || Cond.size() == 0) &&
1572 "X86 branch conditions have one component!");
1574 if (FBB == 0) { // One way branch.
1576 // Unconditional branch?
1577 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
1579 // Conditional branch.
1580 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1581 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1586 // Two-way Conditional branch.
1587 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1588 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1589 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
1593 void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1594 MachineBasicBlock::iterator MI,
1595 unsigned DestReg, unsigned SrcReg,
1596 const TargetRegisterClass *DestRC,
1597 const TargetRegisterClass *SrcRC) const {
1598 if (DestRC == SrcRC) {
1600 if (DestRC == &X86::GR64RegClass) {
1602 } else if (DestRC == &X86::GR32RegClass) {
1604 } else if (DestRC == &X86::GR16RegClass) {
1606 } else if (DestRC == &X86::GR8RegClass) {
1608 } else if (DestRC == &X86::GR32_RegClass) {
1609 Opc = X86::MOV32_rr;
1610 } else if (DestRC == &X86::GR16_RegClass) {
1611 Opc = X86::MOV16_rr;
1612 } else if (DestRC == &X86::RFP32RegClass) {
1613 Opc = X86::MOV_Fp3232;
1614 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
1615 Opc = X86::MOV_Fp6464;
1616 } else if (DestRC == &X86::RFP80RegClass) {
1617 Opc = X86::MOV_Fp8080;
1618 } else if (DestRC == &X86::FR32RegClass) {
1619 Opc = X86::FsMOVAPSrr;
1620 } else if (DestRC == &X86::FR64RegClass) {
1621 Opc = X86::FsMOVAPDrr;
1622 } else if (DestRC == &X86::VR128RegClass) {
1623 Opc = X86::MOVAPSrr;
1624 } else if (DestRC == &X86::VR64RegClass) {
1625 Opc = X86::MMX_MOVQ64rr;
1627 assert(0 && "Unknown regclass");
1630 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
1634 // Moving EFLAGS to / from another register requires a push and a pop.
1635 if (SrcRC == &X86::CCRRegClass) {
1636 assert(SrcReg == X86::EFLAGS);
1637 if (DestRC == &X86::GR64RegClass) {
1638 BuildMI(MBB, MI, get(X86::PUSHFQ));
1639 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
1641 } else if (DestRC == &X86::GR32RegClass) {
1642 BuildMI(MBB, MI, get(X86::PUSHFD));
1643 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
1646 } else if (DestRC == &X86::CCRRegClass) {
1647 assert(DestReg == X86::EFLAGS);
1648 if (SrcRC == &X86::GR64RegClass) {
1649 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
1650 BuildMI(MBB, MI, get(X86::POPFQ));
1652 } else if (SrcRC == &X86::GR32RegClass) {
1653 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
1654 BuildMI(MBB, MI, get(X86::POPFD));
1659 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1660 if (SrcRC == &X86::RSTRegClass) {
1661 // Copying from ST(0)/ST(1).
1662 assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
1663 "Can only copy from ST(0)/ST(1) right now");
1664 bool isST0 = SrcReg == X86::ST0;
1666 if (DestRC == &X86::RFP32RegClass)
1667 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1668 else if (DestRC == &X86::RFP64RegClass)
1669 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1671 assert(DestRC == &X86::RFP80RegClass);
1672 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1674 BuildMI(MBB, MI, get(Opc), DestReg);
1678 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1679 if (DestRC == &X86::RSTRegClass) {
1680 // Copying to ST(0). FIXME: handle ST(1) also
1681 assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
1683 if (SrcRC == &X86::RFP32RegClass)
1684 Opc = X86::FpSET_ST0_32;
1685 else if (SrcRC == &X86::RFP64RegClass)
1686 Opc = X86::FpSET_ST0_64;
1688 assert(SrcRC == &X86::RFP80RegClass);
1689 Opc = X86::FpSET_ST0_80;
1691 BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
1695 assert(0 && "Not yet supported!");
1699 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
1700 unsigned StackAlign) {
1702 if (RC == &X86::GR64RegClass) {
1704 } else if (RC == &X86::GR32RegClass) {
1706 } else if (RC == &X86::GR16RegClass) {
1708 } else if (RC == &X86::GR8RegClass) {
1710 } else if (RC == &X86::GR32_RegClass) {
1711 Opc = X86::MOV32_mr;
1712 } else if (RC == &X86::GR16_RegClass) {
1713 Opc = X86::MOV16_mr;
1714 } else if (RC == &X86::RFP80RegClass) {
1715 Opc = X86::ST_FpP80m; // pops
1716 } else if (RC == &X86::RFP64RegClass) {
1717 Opc = X86::ST_Fp64m;
1718 } else if (RC == &X86::RFP32RegClass) {
1719 Opc = X86::ST_Fp32m;
1720 } else if (RC == &X86::FR32RegClass) {
1722 } else if (RC == &X86::FR64RegClass) {
1724 } else if (RC == &X86::VR128RegClass) {
1725 // FIXME: Use movaps once we are capable of selectively
1726 // aligning functions that spill SSE registers on 16-byte boundaries.
1727 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
1728 } else if (RC == &X86::VR64RegClass) {
1729 Opc = X86::MMX_MOVQ64mr;
1731 assert(0 && "Unknown regclass");
1738 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1739 MachineBasicBlock::iterator MI,
1740 unsigned SrcReg, bool isKill, int FrameIdx,
1741 const TargetRegisterClass *RC) const {
1742 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1743 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
1744 .addReg(SrcReg, false, false, isKill);
1747 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1749 SmallVectorImpl<MachineOperand> &Addr,
1750 const TargetRegisterClass *RC,
1751 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1752 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1753 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
1754 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1755 MIB = X86InstrAddOperand(MIB, Addr[i]);
1756 MIB.addReg(SrcReg, false, false, isKill);
1757 NewMIs.push_back(MIB);
1760 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
1761 unsigned StackAlign) {
1763 if (RC == &X86::GR64RegClass) {
1765 } else if (RC == &X86::GR32RegClass) {
1767 } else if (RC == &X86::GR16RegClass) {
1769 } else if (RC == &X86::GR8RegClass) {
1771 } else if (RC == &X86::GR32_RegClass) {
1772 Opc = X86::MOV32_rm;
1773 } else if (RC == &X86::GR16_RegClass) {
1774 Opc = X86::MOV16_rm;
1775 } else if (RC == &X86::RFP80RegClass) {
1776 Opc = X86::LD_Fp80m;
1777 } else if (RC == &X86::RFP64RegClass) {
1778 Opc = X86::LD_Fp64m;
1779 } else if (RC == &X86::RFP32RegClass) {
1780 Opc = X86::LD_Fp32m;
1781 } else if (RC == &X86::FR32RegClass) {
1783 } else if (RC == &X86::FR64RegClass) {
1785 } else if (RC == &X86::VR128RegClass) {
1786 // FIXME: Use movaps once we are capable of selectively
1787 // aligning functions that spill SSE registers on 16-byte boundaries.
1788 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
1789 } else if (RC == &X86::VR64RegClass) {
1790 Opc = X86::MMX_MOVQ64rm;
1792 assert(0 && "Unknown regclass");
1799 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1800 MachineBasicBlock::iterator MI,
1801 unsigned DestReg, int FrameIdx,
1802 const TargetRegisterClass *RC) const{
1803 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1804 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
1807 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1808 SmallVectorImpl<MachineOperand> &Addr,
1809 const TargetRegisterClass *RC,
1810 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1811 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1812 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
1813 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1814 MIB = X86InstrAddOperand(MIB, Addr[i]);
1815 NewMIs.push_back(MIB);
1818 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1819 MachineBasicBlock::iterator MI,
1820 const std::vector<CalleeSavedInfo> &CSI) const {
1824 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1825 unsigned SlotSize = is64Bit ? 8 : 4;
1827 MachineFunction &MF = *MBB.getParent();
1828 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1829 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1831 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1832 for (unsigned i = CSI.size(); i != 0; --i) {
1833 unsigned Reg = CSI[i-1].getReg();
1834 // Add the callee-saved register as live-in. It's killed at the spill.
1836 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1841 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1842 MachineBasicBlock::iterator MI,
1843 const std::vector<CalleeSavedInfo> &CSI) const {
1847 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1849 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1850 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1851 unsigned Reg = CSI[i].getReg();
1852 BuildMI(MBB, MI, get(Opc), Reg);
1857 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
1858 SmallVector<MachineOperand,4> &MOs,
1859 MachineInstr *MI, const TargetInstrInfo &TII) {
1860 // Create the base instruction with the memory operand as the first part.
1861 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
1862 MachineInstrBuilder MIB(NewMI);
1863 unsigned NumAddrOps = MOs.size();
1864 for (unsigned i = 0; i != NumAddrOps; ++i)
1865 MIB = X86InstrAddOperand(MIB, MOs[i]);
1866 if (NumAddrOps < 4) // FrameIndex only
1867 MIB.addImm(1).addReg(0).addImm(0);
1869 // Loop over the rest of the ri operands, converting them over.
1870 unsigned NumOps = MI->getDesc().getNumOperands()-2;
1871 for (unsigned i = 0; i != NumOps; ++i) {
1872 MachineOperand &MO = MI->getOperand(i+2);
1873 MIB = X86InstrAddOperand(MIB, MO);
1875 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1876 MachineOperand &MO = MI->getOperand(i);
1877 MIB = X86InstrAddOperand(MIB, MO);
1882 static MachineInstr *FuseInst(MachineFunction &MF,
1883 unsigned Opcode, unsigned OpNo,
1884 SmallVector<MachineOperand,4> &MOs,
1885 MachineInstr *MI, const TargetInstrInfo &TII) {
1886 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
1887 MachineInstrBuilder MIB(NewMI);
1889 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1890 MachineOperand &MO = MI->getOperand(i);
1892 assert(MO.isRegister() && "Expected to fold into reg operand!");
1893 unsigned NumAddrOps = MOs.size();
1894 for (unsigned i = 0; i != NumAddrOps; ++i)
1895 MIB = X86InstrAddOperand(MIB, MOs[i]);
1896 if (NumAddrOps < 4) // FrameIndex only
1897 MIB.addImm(1).addReg(0).addImm(0);
1899 MIB = X86InstrAddOperand(MIB, MO);
1905 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1906 SmallVector<MachineOperand,4> &MOs,
1908 MachineFunction &MF = *MI->getParent()->getParent();
1909 MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
1911 unsigned NumAddrOps = MOs.size();
1912 for (unsigned i = 0; i != NumAddrOps; ++i)
1913 MIB = X86InstrAddOperand(MIB, MOs[i]);
1914 if (NumAddrOps < 4) // FrameIndex only
1915 MIB.addImm(1).addReg(0).addImm(0);
1916 return MIB.addImm(0);
1920 X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1921 MachineInstr *MI, unsigned i,
1922 SmallVector<MachineOperand,4> &MOs) const {
1923 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1924 bool isTwoAddrFold = false;
1925 unsigned NumOps = MI->getDesc().getNumOperands();
1926 bool isTwoAddr = NumOps > 1 &&
1927 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1929 MachineInstr *NewMI = NULL;
1930 // Folding a memory location into the two-address part of a two-address
1931 // instruction is different than folding it other places. It requires
1932 // replacing the *two* registers with the memory location.
1933 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1934 MI->getOperand(0).isRegister() &&
1935 MI->getOperand(1).isRegister() &&
1936 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1937 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1938 isTwoAddrFold = true;
1939 } else if (i == 0) { // If operand 0
1940 if (MI->getOpcode() == X86::MOV16r0)
1941 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
1942 else if (MI->getOpcode() == X86::MOV32r0)
1943 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
1944 else if (MI->getOpcode() == X86::MOV64r0)
1945 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
1946 else if (MI->getOpcode() == X86::MOV8r0)
1947 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
1951 OpcodeTablePtr = &RegOp2MemOpTable0;
1952 } else if (i == 1) {
1953 OpcodeTablePtr = &RegOp2MemOpTable1;
1954 } else if (i == 2) {
1955 OpcodeTablePtr = &RegOp2MemOpTable2;
1958 // If table selected...
1959 if (OpcodeTablePtr) {
1960 // Find the Opcode to fuse
1961 DenseMap<unsigned*, unsigned>::iterator I =
1962 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1963 if (I != OpcodeTablePtr->end()) {
1965 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
1967 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
1973 if (PrintFailedFusing)
1974 cerr << "We failed to fuse operand " << i << *MI;
1979 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1981 SmallVectorImpl<unsigned> &Ops,
1982 int FrameIndex) const {
1983 // Check switch flag
1984 if (NoFusing) return NULL;
1986 const MachineFrameInfo *MFI = MF.getFrameInfo();
1987 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
1988 // FIXME: Move alignment requirement into tables?
1989 if (Alignment < 16) {
1990 switch (MI->getOpcode()) {
1992 // Not always safe to fold movsd into these instructions since their load
1993 // folding variants expects the address to be 16 byte aligned.
1994 case X86::FsANDNPDrr:
1995 case X86::FsANDNPSrr:
1996 case X86::FsANDPDrr:
1997 case X86::FsANDPSrr:
2000 case X86::FsXORPDrr:
2001 case X86::FsXORPSrr:
2006 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2007 unsigned NewOpc = 0;
2008 switch (MI->getOpcode()) {
2009 default: return NULL;
2010 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2011 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2012 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2013 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2015 // Change to CMPXXri r, 0 first.
2016 MI->setDesc(get(NewOpc));
2017 MI->getOperand(1).ChangeToImmediate(0);
2018 } else if (Ops.size() != 1)
2021 SmallVector<MachineOperand,4> MOs;
2022 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2023 return foldMemoryOperand(MF, MI, Ops[0], MOs);
2026 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
2028 SmallVectorImpl<unsigned> &Ops,
2029 MachineInstr *LoadMI) const {
2030 // Check switch flag
2031 if (NoFusing) return NULL;
2033 unsigned Alignment = 0;
2034 for (alist<MachineMemOperand>::iterator i = LoadMI->memoperands_begin(),
2035 e = LoadMI->memoperands_end(); i != e; ++i) {
2036 const MachineMemOperand &MRO = *i;
2037 unsigned Align = MRO.getAlignment();
2038 if (Align > Alignment)
2042 // FIXME: Move alignment requirement into tables?
2043 if (Alignment < 16) {
2044 switch (MI->getOpcode()) {
2046 // Not always safe to fold movsd into these instructions since their load
2047 // folding variants expects the address to be 16 byte aligned.
2048 case X86::FsANDNPDrr:
2049 case X86::FsANDNPSrr:
2050 case X86::FsANDPDrr:
2051 case X86::FsANDPSrr:
2054 case X86::FsXORPDrr:
2055 case X86::FsXORPSrr:
2060 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2061 unsigned NewOpc = 0;
2062 switch (MI->getOpcode()) {
2063 default: return NULL;
2064 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2065 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2066 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2067 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2069 // Change to CMPXXri r, 0 first.
2070 MI->setDesc(get(NewOpc));
2071 MI->getOperand(1).ChangeToImmediate(0);
2072 } else if (Ops.size() != 1)
2075 SmallVector<MachineOperand,4> MOs;
2076 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2077 for (unsigned i = NumOps - 4; i != NumOps; ++i)
2078 MOs.push_back(LoadMI->getOperand(i));
2079 return foldMemoryOperand(MF, MI, Ops[0], MOs);
2083 bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
2084 SmallVectorImpl<unsigned> &Ops) const {
2085 // Check switch flag
2086 if (NoFusing) return 0;
2088 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2089 switch (MI->getOpcode()) {
2090 default: return false;
2099 if (Ops.size() != 1)
2102 unsigned OpNum = Ops[0];
2103 unsigned Opc = MI->getOpcode();
2104 unsigned NumOps = MI->getDesc().getNumOperands();
2105 bool isTwoAddr = NumOps > 1 &&
2106 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2108 // Folding a memory location into the two-address part of a two-address
2109 // instruction is different than folding it other places. It requires
2110 // replacing the *two* registers with the memory location.
2111 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2112 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2113 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2114 } else if (OpNum == 0) { // If operand 0
2123 OpcodeTablePtr = &RegOp2MemOpTable0;
2124 } else if (OpNum == 1) {
2125 OpcodeTablePtr = &RegOp2MemOpTable1;
2126 } else if (OpNum == 2) {
2127 OpcodeTablePtr = &RegOp2MemOpTable2;
2130 if (OpcodeTablePtr) {
2131 // Find the Opcode to fuse
2132 DenseMap<unsigned*, unsigned>::iterator I =
2133 OpcodeTablePtr->find((unsigned*)Opc);
2134 if (I != OpcodeTablePtr->end())
2140 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2141 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2142 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2143 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2144 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2145 if (I == MemOp2RegOpTable.end())
2147 unsigned Opc = I->second.first;
2148 unsigned Index = I->second.second & 0xf;
2149 bool FoldedLoad = I->second.second & (1 << 4);
2150 bool FoldedStore = I->second.second & (1 << 5);
2151 if (UnfoldLoad && !FoldedLoad)
2153 UnfoldLoad &= FoldedLoad;
2154 if (UnfoldStore && !FoldedStore)
2156 UnfoldStore &= FoldedStore;
2158 const TargetInstrDesc &TID = get(Opc);
2159 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2160 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2161 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2162 SmallVector<MachineOperand,4> AddrOps;
2163 SmallVector<MachineOperand,2> BeforeOps;
2164 SmallVector<MachineOperand,2> AfterOps;
2165 SmallVector<MachineOperand,4> ImpOps;
2166 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2167 MachineOperand &Op = MI->getOperand(i);
2168 if (i >= Index && i < Index+4)
2169 AddrOps.push_back(Op);
2170 else if (Op.isRegister() && Op.isImplicit())
2171 ImpOps.push_back(Op);
2173 BeforeOps.push_back(Op);
2175 AfterOps.push_back(Op);
2178 // Emit the load instruction.
2180 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2182 // Address operands cannot be marked isKill.
2183 for (unsigned i = 1; i != 5; ++i) {
2184 MachineOperand &MO = NewMIs[0]->getOperand(i);
2185 if (MO.isRegister())
2186 MO.setIsKill(false);
2191 // Emit the data processing instruction.
2192 MachineInstr *DataMI = MF.CreateMachineInstr(TID, true);
2193 MachineInstrBuilder MIB(DataMI);
2196 MIB.addReg(Reg, true);
2197 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2198 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
2201 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2202 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
2203 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2204 MachineOperand &MO = ImpOps[i];
2205 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
2207 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2208 unsigned NewOpc = 0;
2209 switch (DataMI->getOpcode()) {
2211 case X86::CMP64ri32:
2215 MachineOperand &MO0 = DataMI->getOperand(0);
2216 MachineOperand &MO1 = DataMI->getOperand(1);
2217 if (MO1.getImm() == 0) {
2218 switch (DataMI->getOpcode()) {
2220 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2221 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2222 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2223 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2225 DataMI->setDesc(get(NewOpc));
2226 MO1.ChangeToRegister(MO0.getReg(), false);
2230 NewMIs.push_back(DataMI);
2232 // Emit the store instruction.
2234 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2235 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2236 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2237 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2244 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2245 SmallVectorImpl<SDNode*> &NewNodes) const {
2246 if (!N->isTargetOpcode())
2249 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2250 MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode());
2251 if (I == MemOp2RegOpTable.end())
2253 unsigned Opc = I->second.first;
2254 unsigned Index = I->second.second & 0xf;
2255 bool FoldedLoad = I->second.second & (1 << 4);
2256 bool FoldedStore = I->second.second & (1 << 5);
2257 const TargetInstrDesc &TID = get(Opc);
2258 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2259 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2260 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2261 std::vector<SDOperand> AddrOps;
2262 std::vector<SDOperand> BeforeOps;
2263 std::vector<SDOperand> AfterOps;
2264 unsigned NumOps = N->getNumOperands();
2265 for (unsigned i = 0; i != NumOps-1; ++i) {
2266 SDOperand Op = N->getOperand(i);
2267 if (i >= Index && i < Index+4)
2268 AddrOps.push_back(Op);
2270 BeforeOps.push_back(Op);
2272 AfterOps.push_back(Op);
2274 SDOperand Chain = N->getOperand(NumOps-1);
2275 AddrOps.push_back(Chain);
2277 // Emit the load instruction.
2280 MVT VT = *RC->vt_begin();
2281 Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT,
2282 MVT::Other, &AddrOps[0], AddrOps.size());
2283 NewNodes.push_back(Load);
2286 // Emit the data processing instruction.
2287 std::vector<MVT> VTs;
2288 const TargetRegisterClass *DstRC = 0;
2289 if (TID.getNumDefs() > 0) {
2290 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2291 DstRC = DstTOI.isLookupPtrRegClass()
2292 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2293 VTs.push_back(*DstRC->vt_begin());
2295 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2296 MVT VT = N->getValueType(i);
2297 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2301 BeforeOps.push_back(SDOperand(Load, 0));
2302 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2303 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
2304 NewNodes.push_back(NewNode);
2306 // Emit the store instruction.
2309 AddrOps.push_back(SDOperand(NewNode, 0));
2310 AddrOps.push_back(Chain);
2311 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, RI.getStackAlignment()),
2312 MVT::Other, &AddrOps[0], AddrOps.size());
2313 NewNodes.push_back(Store);
2319 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2320 bool UnfoldLoad, bool UnfoldStore) const {
2321 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2322 MemOp2RegOpTable.find((unsigned*)Opc);
2323 if (I == MemOp2RegOpTable.end())
2325 bool FoldedLoad = I->second.second & (1 << 4);
2326 bool FoldedStore = I->second.second & (1 << 5);
2327 if (UnfoldLoad && !FoldedLoad)
2329 if (UnfoldStore && !FoldedStore)
2331 return I->second.first;
2334 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
2335 if (MBB.empty()) return false;
2337 switch (MBB.back().getOpcode()) {
2338 case X86::TCRETURNri:
2339 case X86::TCRETURNdi:
2340 case X86::RET: // Return.
2345 case X86::JMP: // Uncond branch.
2346 case X86::JMP32r: // Indirect branch.
2347 case X86::JMP64r: // Indirect branch (64-bit).
2348 case X86::JMP32m: // Indirect branch through mem.
2349 case X86::JMP64m: // Indirect branch through mem (64-bit).
2351 default: return false;
2356 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
2357 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2358 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
2362 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
2363 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
2364 if (Subtarget->is64Bit())
2365 return &X86::GR64RegClass;
2367 return &X86::GR32RegClass;
2370 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2371 switch (Desc->TSFlags & X86II::ImmMask) {
2372 case X86II::Imm8: return 1;
2373 case X86II::Imm16: return 2;
2374 case X86II::Imm32: return 4;
2375 case X86II::Imm64: return 8;
2376 default: assert(0 && "Immediate size not set!");
2381 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2382 /// e.g. r8, xmm8, etc.
2383 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2384 if (!MO.isRegister()) return false;
2385 switch (MO.getReg()) {
2387 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2388 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2389 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2390 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2391 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2392 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2393 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2394 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2395 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2396 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2403 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2404 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2405 /// size, and 3) use of X86-64 extended registers.
2406 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2408 const TargetInstrDesc &Desc = MI.getDesc();
2410 // Pseudo instructions do not need REX prefix byte.
2411 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2413 if (Desc.TSFlags & X86II::REX_W)
2416 unsigned NumOps = Desc.getNumOperands();
2418 bool isTwoAddr = NumOps > 1 &&
2419 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2421 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2422 unsigned i = isTwoAddr ? 1 : 0;
2423 for (unsigned e = NumOps; i != e; ++i) {
2424 const MachineOperand& MO = MI.getOperand(i);
2425 if (MO.isRegister()) {
2426 unsigned Reg = MO.getReg();
2427 if (isX86_64NonExtLowByteReg(Reg))
2432 switch (Desc.TSFlags & X86II::FormMask) {
2433 case X86II::MRMInitReg:
2434 if (isX86_64ExtendedReg(MI.getOperand(0)))
2435 REX |= (1 << 0) | (1 << 2);
2437 case X86II::MRMSrcReg: {
2438 if (isX86_64ExtendedReg(MI.getOperand(0)))
2440 i = isTwoAddr ? 2 : 1;
2441 for (unsigned e = NumOps; i != e; ++i) {
2442 const MachineOperand& MO = MI.getOperand(i);
2443 if (isX86_64ExtendedReg(MO))
2448 case X86II::MRMSrcMem: {
2449 if (isX86_64ExtendedReg(MI.getOperand(0)))
2452 i = isTwoAddr ? 2 : 1;
2453 for (; i != NumOps; ++i) {
2454 const MachineOperand& MO = MI.getOperand(i);
2455 if (MO.isRegister()) {
2456 if (isX86_64ExtendedReg(MO))
2463 case X86II::MRM0m: case X86II::MRM1m:
2464 case X86II::MRM2m: case X86II::MRM3m:
2465 case X86II::MRM4m: case X86II::MRM5m:
2466 case X86II::MRM6m: case X86II::MRM7m:
2467 case X86II::MRMDestMem: {
2468 unsigned e = isTwoAddr ? 5 : 4;
2469 i = isTwoAddr ? 1 : 0;
2470 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2473 for (; i != e; ++i) {
2474 const MachineOperand& MO = MI.getOperand(i);
2475 if (MO.isRegister()) {
2476 if (isX86_64ExtendedReg(MO))
2484 if (isX86_64ExtendedReg(MI.getOperand(0)))
2486 i = isTwoAddr ? 2 : 1;
2487 for (unsigned e = NumOps; i != e; ++i) {
2488 const MachineOperand& MO = MI.getOperand(i);
2489 if (isX86_64ExtendedReg(MO))
2499 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2500 /// relative block address instruction
2502 static unsigned sizePCRelativeBlockAddress() {
2506 /// sizeGlobalAddress - Give the size of the emission of this global address
2508 static unsigned sizeGlobalAddress(bool dword) {
2509 return dword ? 8 : 4;
2512 /// sizeConstPoolAddress - Give the size of the emission of this constant
2515 static unsigned sizeConstPoolAddress(bool dword) {
2516 return dword ? 8 : 4;
2519 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2522 static unsigned sizeExternalSymbolAddress(bool dword) {
2523 return dword ? 8 : 4;
2526 /// sizeJumpTableAddress - Give the size of the emission of this jump
2529 static unsigned sizeJumpTableAddress(bool dword) {
2530 return dword ? 8 : 4;
2533 static unsigned sizeConstant(unsigned Size) {
2537 static unsigned sizeRegModRMByte(){
2541 static unsigned sizeSIBByte(){
2545 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2546 unsigned FinalSize = 0;
2547 // If this is a simple integer displacement that doesn't require a relocation.
2549 FinalSize += sizeConstant(4);
2553 // Otherwise, this is something that requires a relocation.
2554 if (RelocOp->isGlobalAddress()) {
2555 FinalSize += sizeGlobalAddress(false);
2556 } else if (RelocOp->isConstantPoolIndex()) {
2557 FinalSize += sizeConstPoolAddress(false);
2558 } else if (RelocOp->isJumpTableIndex()) {
2559 FinalSize += sizeJumpTableAddress(false);
2561 assert(0 && "Unknown value to relocate!");
2566 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2567 bool IsPIC, bool Is64BitMode) {
2568 const MachineOperand &Op3 = MI.getOperand(Op+3);
2570 const MachineOperand *DispForReloc = 0;
2571 unsigned FinalSize = 0;
2573 // Figure out what sort of displacement we have to handle here.
2574 if (Op3.isGlobalAddress()) {
2575 DispForReloc = &Op3;
2576 } else if (Op3.isConstantPoolIndex()) {
2577 if (Is64BitMode || IsPIC) {
2578 DispForReloc = &Op3;
2582 } else if (Op3.isJumpTableIndex()) {
2583 if (Is64BitMode || IsPIC) {
2584 DispForReloc = &Op3;
2592 const MachineOperand &Base = MI.getOperand(Op);
2593 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2595 unsigned BaseReg = Base.getReg();
2597 // Is a SIB byte needed?
2598 if (IndexReg.getReg() == 0 &&
2599 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2600 if (BaseReg == 0) { // Just a displacement?
2601 // Emit special case [disp32] encoding
2603 FinalSize += getDisplacementFieldSize(DispForReloc);
2605 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2606 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2607 // Emit simple indirect register encoding... [EAX] f.e.
2609 // Be pessimistic and assume it's a disp32, not a disp8
2611 // Emit the most general non-SIB encoding: [REG+disp32]
2613 FinalSize += getDisplacementFieldSize(DispForReloc);
2617 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2618 assert(IndexReg.getReg() != X86::ESP &&
2619 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2621 bool ForceDisp32 = false;
2622 if (BaseReg == 0 || DispForReloc) {
2623 // Emit the normal disp32 encoding.
2630 FinalSize += sizeSIBByte();
2632 // Do we need to output a displacement?
2633 if (DispVal != 0 || ForceDisp32) {
2634 FinalSize += getDisplacementFieldSize(DispForReloc);
2641 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2642 const TargetInstrDesc *Desc,
2643 bool IsPIC, bool Is64BitMode) {
2645 unsigned Opcode = Desc->Opcode;
2646 unsigned FinalSize = 0;
2648 // Emit the lock opcode prefix as needed.
2649 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2651 // Emit the repeat opcode prefix as needed.
2652 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2654 // Emit the operand size opcode prefix as needed.
2655 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2657 // Emit the address size opcode prefix as needed.
2658 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2660 bool Need0FPrefix = false;
2661 switch (Desc->TSFlags & X86II::Op0Mask) {
2662 case X86II::TB: // Two-byte opcode prefix
2663 case X86II::T8: // 0F 38
2664 case X86II::TA: // 0F 3A
2665 Need0FPrefix = true;
2667 case X86II::REP: break; // already handled.
2668 case X86II::XS: // F3 0F
2670 Need0FPrefix = true;
2672 case X86II::XD: // F2 0F
2674 Need0FPrefix = true;
2676 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2677 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2679 break; // Two-byte opcode prefix
2680 default: assert(0 && "Invalid prefix!");
2681 case 0: break; // No prefix!
2686 unsigned REX = X86InstrInfo::determineREX(MI);
2691 // 0x0F escape code must be emitted just before the opcode.
2695 switch (Desc->TSFlags & X86II::Op0Mask) {
2696 case X86II::T8: // 0F 38
2699 case X86II::TA: // 0F 3A
2704 // If this is a two-address instruction, skip one of the register operands.
2705 unsigned NumOps = Desc->getNumOperands();
2707 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2710 switch (Desc->TSFlags & X86II::FormMask) {
2711 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
2713 // Remember the current PC offset, this is the PIC relocation
2718 case TargetInstrInfo::INLINEASM: {
2719 const MachineFunction *MF = MI.getParent()->getParent();
2720 const char *AsmStr = MI.getOperand(0).getSymbolName();
2721 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
2722 FinalSize += AI->getInlineAsmLength(AsmStr);
2725 case TargetInstrInfo::DBG_LABEL:
2726 case TargetInstrInfo::EH_LABEL:
2728 case TargetInstrInfo::IMPLICIT_DEF:
2729 case TargetInstrInfo::DECLARE:
2730 case X86::DWARF_LOC:
2731 case X86::FP_REG_KILL:
2733 case X86::MOVPC32r: {
2734 // This emits the "call" portion of this pseudo instruction.
2736 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2745 if (CurOp != NumOps) {
2746 const MachineOperand &MO = MI.getOperand(CurOp++);
2747 if (MO.isMachineBasicBlock()) {
2748 FinalSize += sizePCRelativeBlockAddress();
2749 } else if (MO.isGlobalAddress()) {
2750 FinalSize += sizeGlobalAddress(false);
2751 } else if (MO.isExternalSymbol()) {
2752 FinalSize += sizeExternalSymbolAddress(false);
2753 } else if (MO.isImmediate()) {
2754 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2756 assert(0 && "Unknown RawFrm operand!");
2761 case X86II::AddRegFrm:
2765 if (CurOp != NumOps) {
2766 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2767 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2768 if (MO1.isImmediate())
2769 FinalSize += sizeConstant(Size);
2772 if (Opcode == X86::MOV64ri)
2774 if (MO1.isGlobalAddress()) {
2775 FinalSize += sizeGlobalAddress(dword);
2776 } else if (MO1.isExternalSymbol())
2777 FinalSize += sizeExternalSymbolAddress(dword);
2778 else if (MO1.isConstantPoolIndex())
2779 FinalSize += sizeConstPoolAddress(dword);
2780 else if (MO1.isJumpTableIndex())
2781 FinalSize += sizeJumpTableAddress(dword);
2786 case X86II::MRMDestReg: {
2788 FinalSize += sizeRegModRMByte();
2790 if (CurOp != NumOps) {
2792 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2796 case X86II::MRMDestMem: {
2798 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2800 if (CurOp != NumOps) {
2802 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2807 case X86II::MRMSrcReg:
2809 FinalSize += sizeRegModRMByte();
2811 if (CurOp != NumOps) {
2813 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2817 case X86II::MRMSrcMem: {
2820 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
2822 if (CurOp != NumOps) {
2824 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2829 case X86II::MRM0r: case X86II::MRM1r:
2830 case X86II::MRM2r: case X86II::MRM3r:
2831 case X86II::MRM4r: case X86II::MRM5r:
2832 case X86II::MRM6r: case X86II::MRM7r:
2835 FinalSize += sizeRegModRMByte();
2837 if (CurOp != NumOps) {
2838 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2839 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2840 if (MO1.isImmediate())
2841 FinalSize += sizeConstant(Size);
2844 if (Opcode == X86::MOV64ri32)
2846 if (MO1.isGlobalAddress()) {
2847 FinalSize += sizeGlobalAddress(dword);
2848 } else if (MO1.isExternalSymbol())
2849 FinalSize += sizeExternalSymbolAddress(dword);
2850 else if (MO1.isConstantPoolIndex())
2851 FinalSize += sizeConstPoolAddress(dword);
2852 else if (MO1.isJumpTableIndex())
2853 FinalSize += sizeJumpTableAddress(dword);
2858 case X86II::MRM0m: case X86II::MRM1m:
2859 case X86II::MRM2m: case X86II::MRM3m:
2860 case X86II::MRM4m: case X86II::MRM5m:
2861 case X86II::MRM6m: case X86II::MRM7m: {
2864 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2867 if (CurOp != NumOps) {
2868 const MachineOperand &MO = MI.getOperand(CurOp++);
2869 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2870 if (MO.isImmediate())
2871 FinalSize += sizeConstant(Size);
2874 if (Opcode == X86::MOV64mi32)
2876 if (MO.isGlobalAddress()) {
2877 FinalSize += sizeGlobalAddress(dword);
2878 } else if (MO.isExternalSymbol())
2879 FinalSize += sizeExternalSymbolAddress(dword);
2880 else if (MO.isConstantPoolIndex())
2881 FinalSize += sizeConstPoolAddress(dword);
2882 else if (MO.isJumpTableIndex())
2883 FinalSize += sizeJumpTableAddress(dword);
2889 case X86II::MRMInitReg:
2891 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
2892 FinalSize += sizeRegModRMByte();
2897 if (!Desc->isVariadic() && CurOp != NumOps) {
2898 cerr << "Cannot determine size: ";
2909 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
2910 const TargetInstrDesc &Desc = MI->getDesc();
2911 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
2912 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
2913 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
2914 if (Desc.getOpcode() == X86::MOVPC32r) {
2915 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);