1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/SSARegMap.h"
26 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
27 : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
28 TM(tm), RI(tm, *this) {
31 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
33 unsigned& destReg) const {
34 MachineOpCode oc = MI.getOpcode();
35 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
36 oc == X86::MOV32rr || oc == X86::MOV64rr ||
37 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
38 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
39 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
40 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
41 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
42 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
43 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
44 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
45 assert(MI.getNumOperands() >= 2 &&
46 MI.getOperand(0).isRegister() &&
47 MI.getOperand(1).isRegister() &&
48 "invalid register-register move instruction");
49 sourceReg = MI.getOperand(1).getReg();
50 destReg = MI.getOperand(0).getReg();
56 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
57 int &FrameIndex) const {
58 switch (MI->getOpcode()) {
71 case X86::MMX_MOVD64rm:
72 case X86::MMX_MOVQ64rm:
73 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
74 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
75 MI->getOperand(2).getImmedValue() == 1 &&
76 MI->getOperand(3).getReg() == 0 &&
77 MI->getOperand(4).getImmedValue() == 0) {
78 FrameIndex = MI->getOperand(1).getFrameIndex();
79 return MI->getOperand(0).getReg();
86 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
87 int &FrameIndex) const {
88 switch (MI->getOpcode()) {
101 case X86::MMX_MOVD64mr:
102 case X86::MMX_MOVQ64mr:
103 case X86::MMX_MOVNTQmr:
104 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
105 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
106 MI->getOperand(1).getImmedValue() == 1 &&
107 MI->getOperand(2).getReg() == 0 &&
108 MI->getOperand(3).getImmedValue() == 0) {
109 FrameIndex = MI->getOperand(0).getFrameIndex();
110 return MI->getOperand(4).getReg();
118 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
119 switch (MI->getOpcode()) {
132 case X86::MMX_MOVD64rm:
133 case X86::MMX_MOVQ64rm:
134 // Loads from constant pools are trivially rematerializable.
135 return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
136 MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
137 MI->getOperand(1).getReg() == 0 &&
138 MI->getOperand(2).getImmedValue() == 1 &&
139 MI->getOperand(3).getReg() == 0;
141 // All other instructions marked M_REMATERIALIZABLE are always trivially
146 /// convertToThreeAddress - This method must be implemented by targets that
147 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
148 /// may be able to convert a two-address instruction into a true
149 /// three-address instruction on demand. This allows the X86 target (for
150 /// example) to convert ADD and SHL instructions into LEA instructions if they
151 /// would require register copies due to two-addressness.
153 /// This method returns a null pointer if the transformation cannot be
154 /// performed, otherwise it returns the new instruction.
157 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
158 MachineBasicBlock::iterator &MBBI,
159 LiveVariables &LV) const {
160 MachineInstr *MI = MBBI;
161 // All instructions input are two-addr instructions. Get the known operands.
162 unsigned Dest = MI->getOperand(0).getReg();
163 unsigned Src = MI->getOperand(1).getReg();
165 MachineInstr *NewMI = NULL;
166 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
167 // we have better subtarget support, enable the 16-bit LEA generation here.
168 bool DisableLEA16 = true;
170 switch (MI->getOpcode()) {
172 case X86::SHUFPSrri: {
173 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
174 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
176 unsigned A = MI->getOperand(0).getReg();
177 unsigned B = MI->getOperand(1).getReg();
178 unsigned C = MI->getOperand(2).getReg();
179 unsigned M = MI->getOperand(3).getImm();
180 if (B != C) return 0;
181 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
185 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
186 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
187 // the flags produced by a shift yet, so this is safe.
188 unsigned Dest = MI->getOperand(0).getReg();
189 unsigned Src = MI->getOperand(1).getReg();
190 unsigned ShAmt = MI->getOperand(2).getImm();
191 if (ShAmt == 0 || ShAmt >= 4) return 0;
193 NewMI = BuildMI(get(X86::LEA64r), Dest)
194 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
198 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
199 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
200 // the flags produced by a shift yet, so this is safe.
201 unsigned Dest = MI->getOperand(0).getReg();
202 unsigned Src = MI->getOperand(1).getReg();
203 unsigned ShAmt = MI->getOperand(2).getImm();
204 if (ShAmt == 0 || ShAmt >= 4) return 0;
206 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
207 X86::LEA64_32r : X86::LEA32r;
208 NewMI = BuildMI(get(Opc), Dest)
209 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
213 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
214 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
215 // the flags produced by a shift yet, so this is safe.
216 unsigned Dest = MI->getOperand(0).getReg();
217 unsigned Src = MI->getOperand(1).getReg();
218 unsigned ShAmt = MI->getOperand(2).getImm();
219 if (ShAmt == 0 || ShAmt >= 4) return 0;
222 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
223 SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
224 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
225 ? X86::LEA64_32r : X86::LEA32r;
226 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
227 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
230 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
231 Ins->copyKillDeadInfo(MI);
233 NewMI = BuildMI(get(Opc), leaOutReg)
234 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
237 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
238 Ext->copyKillDeadInfo(MI);
240 MFI->insert(MBBI, Ins); // Insert the insert_subreg
241 LV.instructionChanged(MI, NewMI); // Update live variables
242 LV.addVirtualRegisterKilled(leaInReg, NewMI);
243 MFI->insert(MBBI, NewMI); // Insert the new inst
244 LV.addVirtualRegisterKilled(leaOutReg, Ext);
245 MFI->insert(MBBI, Ext); // Insert the extract_subreg
248 NewMI = BuildMI(get(X86::LEA16r), Dest)
249 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
255 // FIXME: None of these instructions are promotable to LEAs without
256 // additional information. In particular, LEA doesn't set the flags that
257 // add and inc do. :(
259 switch (MI->getOpcode()) {
262 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
263 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1);
267 if (DisableLEA16) return 0;
268 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
269 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
273 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
274 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1);
278 if (DisableLEA16) return 0;
279 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
280 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
283 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
284 NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src,
285 MI->getOperand(2).getReg());
288 if (DisableLEA16) return 0;
289 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
290 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
291 MI->getOperand(2).getReg());
295 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
296 if (MI->getOperand(2).isImmediate())
297 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src,
298 MI->getOperand(2).getImmedValue());
302 if (DisableLEA16) return 0;
303 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
304 if (MI->getOperand(2).isImmediate())
305 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
306 MI->getOperand(2).getImmedValue());
309 if (DisableLEA16) return 0;
311 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
312 "Unknown shl instruction!");
313 unsigned ShAmt = MI->getOperand(2).getImmedValue();
314 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
316 AM.Scale = 1 << ShAmt;
318 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
319 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
325 NewMI->copyKillDeadInfo(MI);
326 LV.instructionChanged(MI, NewMI); // Update live variables
327 MFI->insert(MBBI, NewMI); // Insert the new inst
332 /// commuteInstruction - We have a few instructions that must be hacked on to
335 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
336 // FIXME: Can commute cmoves by changing the condition!
337 switch (MI->getOpcode()) {
338 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
339 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
340 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
341 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
342 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
343 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
346 switch (MI->getOpcode()) {
347 default: assert(0 && "Unreachable!");
348 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
349 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
350 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
351 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
352 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
353 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
355 unsigned Amt = MI->getOperand(3).getImmedValue();
356 unsigned A = MI->getOperand(0).getReg();
357 unsigned B = MI->getOperand(1).getReg();
358 unsigned C = MI->getOperand(2).getReg();
359 bool BisKill = MI->getOperand(1).isKill();
360 bool CisKill = MI->getOperand(2).isKill();
361 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
362 .addReg(B, false, false, BisKill).addImm(Size-Amt);
365 return TargetInstrInfo::commuteInstruction(MI);
369 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
371 default: return X86::COND_INVALID;
372 case X86::JE: return X86::COND_E;
373 case X86::JNE: return X86::COND_NE;
374 case X86::JL: return X86::COND_L;
375 case X86::JLE: return X86::COND_LE;
376 case X86::JG: return X86::COND_G;
377 case X86::JGE: return X86::COND_GE;
378 case X86::JB: return X86::COND_B;
379 case X86::JBE: return X86::COND_BE;
380 case X86::JA: return X86::COND_A;
381 case X86::JAE: return X86::COND_AE;
382 case X86::JS: return X86::COND_S;
383 case X86::JNS: return X86::COND_NS;
384 case X86::JP: return X86::COND_P;
385 case X86::JNP: return X86::COND_NP;
386 case X86::JO: return X86::COND_O;
387 case X86::JNO: return X86::COND_NO;
391 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
393 default: assert(0 && "Illegal condition code!");
394 case X86::COND_E: return X86::JE;
395 case X86::COND_NE: return X86::JNE;
396 case X86::COND_L: return X86::JL;
397 case X86::COND_LE: return X86::JLE;
398 case X86::COND_G: return X86::JG;
399 case X86::COND_GE: return X86::JGE;
400 case X86::COND_B: return X86::JB;
401 case X86::COND_BE: return X86::JBE;
402 case X86::COND_A: return X86::JA;
403 case X86::COND_AE: return X86::JAE;
404 case X86::COND_S: return X86::JS;
405 case X86::COND_NS: return X86::JNS;
406 case X86::COND_P: return X86::JP;
407 case X86::COND_NP: return X86::JNP;
408 case X86::COND_O: return X86::JO;
409 case X86::COND_NO: return X86::JNO;
413 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
414 /// e.g. turning COND_E to COND_NE.
415 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
417 default: assert(0 && "Illegal condition code!");
418 case X86::COND_E: return X86::COND_NE;
419 case X86::COND_NE: return X86::COND_E;
420 case X86::COND_L: return X86::COND_GE;
421 case X86::COND_LE: return X86::COND_G;
422 case X86::COND_G: return X86::COND_LE;
423 case X86::COND_GE: return X86::COND_L;
424 case X86::COND_B: return X86::COND_AE;
425 case X86::COND_BE: return X86::COND_A;
426 case X86::COND_A: return X86::COND_BE;
427 case X86::COND_AE: return X86::COND_B;
428 case X86::COND_S: return X86::COND_NS;
429 case X86::COND_NS: return X86::COND_S;
430 case X86::COND_P: return X86::COND_NP;
431 case X86::COND_NP: return X86::COND_P;
432 case X86::COND_O: return X86::COND_NO;
433 case X86::COND_NO: return X86::COND_O;
437 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
438 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
439 if (TID->Flags & M_TERMINATOR_FLAG) {
440 // Conditional branch is a special case.
441 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
443 if ((TID->Flags & M_PREDICABLE) == 0)
445 return !isPredicated(MI);
450 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
451 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
452 const X86InstrInfo &TII) {
453 if (MI->getOpcode() == X86::FP_REG_KILL)
455 return TII.isUnpredicatedTerminator(MI);
458 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
459 MachineBasicBlock *&TBB,
460 MachineBasicBlock *&FBB,
461 std::vector<MachineOperand> &Cond) const {
462 // If the block has no terminators, it just falls into the block after it.
463 MachineBasicBlock::iterator I = MBB.end();
464 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
467 // Get the last instruction in the block.
468 MachineInstr *LastInst = I;
470 // If there is only one terminator instruction, process it.
471 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
472 if (!isBranch(LastInst->getOpcode()))
475 // If the block ends with a branch there are 3 possibilities:
476 // it's an unconditional, conditional, or indirect branch.
478 if (LastInst->getOpcode() == X86::JMP) {
479 TBB = LastInst->getOperand(0).getMachineBasicBlock();
482 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
483 if (BranchCode == X86::COND_INVALID)
484 return true; // Can't handle indirect branch.
486 // Otherwise, block ends with fall-through condbranch.
487 TBB = LastInst->getOperand(0).getMachineBasicBlock();
488 Cond.push_back(MachineOperand::CreateImm(BranchCode));
492 // Get the instruction before it if it's a terminator.
493 MachineInstr *SecondLastInst = I;
495 // If there are three terminators, we don't know what sort of block this is.
496 if (SecondLastInst && I != MBB.begin() &&
497 isBrAnalysisUnpredicatedTerminator(--I, *this))
500 // If the block ends with X86::JMP and a conditional branch, handle it.
501 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
502 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
503 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
504 Cond.push_back(MachineOperand::CreateImm(BranchCode));
505 FBB = LastInst->getOperand(0).getMachineBasicBlock();
509 // If the block ends with two X86::JMPs, handle it. The second one is not
510 // executed, so remove it.
511 if (SecondLastInst->getOpcode() == X86::JMP &&
512 LastInst->getOpcode() == X86::JMP) {
513 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
515 I->eraseFromParent();
519 // Otherwise, can't handle this.
523 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
524 MachineBasicBlock::iterator I = MBB.end();
525 if (I == MBB.begin()) return 0;
527 if (I->getOpcode() != X86::JMP &&
528 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
531 // Remove the branch.
532 I->eraseFromParent();
536 if (I == MBB.begin()) return 1;
538 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
541 // Remove the branch.
542 I->eraseFromParent();
547 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
548 MachineBasicBlock *FBB,
549 const std::vector<MachineOperand> &Cond) const {
550 // Shouldn't be a fall through.
551 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
552 assert((Cond.size() == 1 || Cond.size() == 0) &&
553 "X86 branch conditions have one component!");
555 if (FBB == 0) { // One way branch.
557 // Unconditional branch?
558 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
560 // Conditional branch.
561 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
562 BuildMI(&MBB, get(Opc)).addMBB(TBB);
567 // Two-way Conditional branch.
568 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
569 BuildMI(&MBB, get(Opc)).addMBB(TBB);
570 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
574 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
575 if (MBB.empty()) return false;
577 switch (MBB.back().getOpcode()) {
578 case X86::RET: // Return.
583 case X86::JMP: // Uncond branch.
584 case X86::JMP32r: // Indirect branch.
585 case X86::JMP32m: // Indirect branch through mem.
587 default: return false;
592 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
593 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
594 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
598 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
599 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
600 if (Subtarget->is64Bit())
601 return &X86::GR64RegClass;
603 return &X86::GR32RegClass;