1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/MC/MCInst.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/MC/MCAsmInfo.h"
37 #define GET_INSTRINFO_CTOR
38 #include "X86GenInstrInfo.inc"
43 NoFusing("disable-spill-fusing",
44 cl::desc("Disable fusing of spill code into instructions"));
46 PrintFailedFusing("print-failed-fuse-candidates",
47 cl::desc("Print instructions that the allocator wants to"
48 " fuse, but the X86 backend currently can't"),
51 ReMatPICStubLoad("remat-pic-stub-load",
52 cl::desc("Re-materialize load from stub in PIC mode"),
53 cl::init(false), cl::Hidden);
56 // Select which memory operand is being unfolded.
57 // (stored in bits 0 - 7)
63 // Minimum alignment required for load/store.
64 // Used for RegOp->MemOp conversion.
65 // (stored in bits 8 - 15)
67 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
68 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
69 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
70 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
72 // Do not insert the reverse map (MemOp -> RegOp) into the table.
73 // This may be needed because there is a many -> one mapping.
74 TB_NO_REVERSE = 1 << 16,
76 // Do not insert the forward map (RegOp -> MemOp) into the table.
77 // This is needed for Native Client, which prohibits branch
78 // instructions from using a memory operand.
79 TB_NO_FORWARD = 1 << 17,
81 TB_FOLDED_LOAD = 1 << 18,
82 TB_FOLDED_STORE = 1 << 19
85 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
86 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
87 ? X86::ADJCALLSTACKDOWN64
88 : X86::ADJCALLSTACKDOWN32),
89 (tm.getSubtarget<X86Subtarget>().is64Bit()
90 ? X86::ADJCALLSTACKUP64
91 : X86::ADJCALLSTACKUP32)),
92 TM(tm), RI(tm, *this) {
94 static const unsigned OpTbl2Addr[][3] = {
95 { X86::ADC32ri, X86::ADC32mi, 0 },
96 { X86::ADC32ri8, X86::ADC32mi8, 0 },
97 { X86::ADC32rr, X86::ADC32mr, 0 },
98 { X86::ADC64ri32, X86::ADC64mi32, 0 },
99 { X86::ADC64ri8, X86::ADC64mi8, 0 },
100 { X86::ADC64rr, X86::ADC64mr, 0 },
101 { X86::ADD16ri, X86::ADD16mi, 0 },
102 { X86::ADD16ri8, X86::ADD16mi8, 0 },
103 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
104 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
105 { X86::ADD16rr, X86::ADD16mr, 0 },
106 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
107 { X86::ADD32ri, X86::ADD32mi, 0 },
108 { X86::ADD32ri8, X86::ADD32mi8, 0 },
109 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
110 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
111 { X86::ADD32rr, X86::ADD32mr, 0 },
112 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
113 { X86::ADD64ri32, X86::ADD64mi32, 0 },
114 { X86::ADD64ri8, X86::ADD64mi8, 0 },
115 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
116 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
117 { X86::ADD64rr, X86::ADD64mr, 0 },
118 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
119 { X86::ADD8ri, X86::ADD8mi, 0 },
120 { X86::ADD8rr, X86::ADD8mr, 0 },
121 { X86::AND16ri, X86::AND16mi, 0 },
122 { X86::AND16ri8, X86::AND16mi8, 0 },
123 { X86::AND16rr, X86::AND16mr, 0 },
124 { X86::AND32ri, X86::AND32mi, 0 },
125 { X86::AND32ri8, X86::AND32mi8, 0 },
126 { X86::AND32rr, X86::AND32mr, 0 },
127 { X86::AND64ri32, X86::AND64mi32, 0 },
128 { X86::AND64ri8, X86::AND64mi8, 0 },
129 { X86::AND64rr, X86::AND64mr, 0 },
130 { X86::AND8ri, X86::AND8mi, 0 },
131 { X86::AND8rr, X86::AND8mr, 0 },
132 { X86::DEC16r, X86::DEC16m, 0 },
133 { X86::DEC32r, X86::DEC32m, 0 },
134 { X86::DEC64_16r, X86::DEC64_16m, 0 },
135 { X86::DEC64_32r, X86::DEC64_32m, 0 },
136 { X86::DEC64r, X86::DEC64m, 0 },
137 { X86::DEC8r, X86::DEC8m, 0 },
138 { X86::INC16r, X86::INC16m, 0 },
139 { X86::INC32r, X86::INC32m, 0 },
140 { X86::INC64_16r, X86::INC64_16m, 0 },
141 { X86::INC64_32r, X86::INC64_32m, 0 },
142 { X86::INC64r, X86::INC64m, 0 },
143 { X86::INC8r, X86::INC8m, 0 },
144 { X86::NEG16r, X86::NEG16m, 0 },
145 { X86::NEG32r, X86::NEG32m, 0 },
146 { X86::NEG64r, X86::NEG64m, 0 },
147 { X86::NEG8r, X86::NEG8m, 0 },
148 { X86::NOT16r, X86::NOT16m, 0 },
149 { X86::NOT32r, X86::NOT32m, 0 },
150 { X86::NOT64r, X86::NOT64m, 0 },
151 { X86::NOT8r, X86::NOT8m, 0 },
152 { X86::OR16ri, X86::OR16mi, 0 },
153 { X86::OR16ri8, X86::OR16mi8, 0 },
154 { X86::OR16rr, X86::OR16mr, 0 },
155 { X86::OR32ri, X86::OR32mi, 0 },
156 { X86::OR32ri8, X86::OR32mi8, 0 },
157 { X86::OR32rr, X86::OR32mr, 0 },
158 { X86::OR64ri32, X86::OR64mi32, 0 },
159 { X86::OR64ri8, X86::OR64mi8, 0 },
160 { X86::OR64rr, X86::OR64mr, 0 },
161 { X86::OR8ri, X86::OR8mi, 0 },
162 { X86::OR8rr, X86::OR8mr, 0 },
163 { X86::ROL16r1, X86::ROL16m1, 0 },
164 { X86::ROL16rCL, X86::ROL16mCL, 0 },
165 { X86::ROL16ri, X86::ROL16mi, 0 },
166 { X86::ROL32r1, X86::ROL32m1, 0 },
167 { X86::ROL32rCL, X86::ROL32mCL, 0 },
168 { X86::ROL32ri, X86::ROL32mi, 0 },
169 { X86::ROL64r1, X86::ROL64m1, 0 },
170 { X86::ROL64rCL, X86::ROL64mCL, 0 },
171 { X86::ROL64ri, X86::ROL64mi, 0 },
172 { X86::ROL8r1, X86::ROL8m1, 0 },
173 { X86::ROL8rCL, X86::ROL8mCL, 0 },
174 { X86::ROL8ri, X86::ROL8mi, 0 },
175 { X86::ROR16r1, X86::ROR16m1, 0 },
176 { X86::ROR16rCL, X86::ROR16mCL, 0 },
177 { X86::ROR16ri, X86::ROR16mi, 0 },
178 { X86::ROR32r1, X86::ROR32m1, 0 },
179 { X86::ROR32rCL, X86::ROR32mCL, 0 },
180 { X86::ROR32ri, X86::ROR32mi, 0 },
181 { X86::ROR64r1, X86::ROR64m1, 0 },
182 { X86::ROR64rCL, X86::ROR64mCL, 0 },
183 { X86::ROR64ri, X86::ROR64mi, 0 },
184 { X86::ROR8r1, X86::ROR8m1, 0 },
185 { X86::ROR8rCL, X86::ROR8mCL, 0 },
186 { X86::ROR8ri, X86::ROR8mi, 0 },
187 { X86::SAR16r1, X86::SAR16m1, 0 },
188 { X86::SAR16rCL, X86::SAR16mCL, 0 },
189 { X86::SAR16ri, X86::SAR16mi, 0 },
190 { X86::SAR32r1, X86::SAR32m1, 0 },
191 { X86::SAR32rCL, X86::SAR32mCL, 0 },
192 { X86::SAR32ri, X86::SAR32mi, 0 },
193 { X86::SAR64r1, X86::SAR64m1, 0 },
194 { X86::SAR64rCL, X86::SAR64mCL, 0 },
195 { X86::SAR64ri, X86::SAR64mi, 0 },
196 { X86::SAR8r1, X86::SAR8m1, 0 },
197 { X86::SAR8rCL, X86::SAR8mCL, 0 },
198 { X86::SAR8ri, X86::SAR8mi, 0 },
199 { X86::SBB32ri, X86::SBB32mi, 0 },
200 { X86::SBB32ri8, X86::SBB32mi8, 0 },
201 { X86::SBB32rr, X86::SBB32mr, 0 },
202 { X86::SBB64ri32, X86::SBB64mi32, 0 },
203 { X86::SBB64ri8, X86::SBB64mi8, 0 },
204 { X86::SBB64rr, X86::SBB64mr, 0 },
205 { X86::SHL16rCL, X86::SHL16mCL, 0 },
206 { X86::SHL16ri, X86::SHL16mi, 0 },
207 { X86::SHL32rCL, X86::SHL32mCL, 0 },
208 { X86::SHL32ri, X86::SHL32mi, 0 },
209 { X86::SHL64rCL, X86::SHL64mCL, 0 },
210 { X86::SHL64ri, X86::SHL64mi, 0 },
211 { X86::SHL8rCL, X86::SHL8mCL, 0 },
212 { X86::SHL8ri, X86::SHL8mi, 0 },
213 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
214 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
215 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
216 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
217 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
218 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
219 { X86::SHR16r1, X86::SHR16m1, 0 },
220 { X86::SHR16rCL, X86::SHR16mCL, 0 },
221 { X86::SHR16ri, X86::SHR16mi, 0 },
222 { X86::SHR32r1, X86::SHR32m1, 0 },
223 { X86::SHR32rCL, X86::SHR32mCL, 0 },
224 { X86::SHR32ri, X86::SHR32mi, 0 },
225 { X86::SHR64r1, X86::SHR64m1, 0 },
226 { X86::SHR64rCL, X86::SHR64mCL, 0 },
227 { X86::SHR64ri, X86::SHR64mi, 0 },
228 { X86::SHR8r1, X86::SHR8m1, 0 },
229 { X86::SHR8rCL, X86::SHR8mCL, 0 },
230 { X86::SHR8ri, X86::SHR8mi, 0 },
231 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
232 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
233 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
234 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
235 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
236 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
237 { X86::SUB16ri, X86::SUB16mi, 0 },
238 { X86::SUB16ri8, X86::SUB16mi8, 0 },
239 { X86::SUB16rr, X86::SUB16mr, 0 },
240 { X86::SUB32ri, X86::SUB32mi, 0 },
241 { X86::SUB32ri8, X86::SUB32mi8, 0 },
242 { X86::SUB32rr, X86::SUB32mr, 0 },
243 { X86::SUB64ri32, X86::SUB64mi32, 0 },
244 { X86::SUB64ri8, X86::SUB64mi8, 0 },
245 { X86::SUB64rr, X86::SUB64mr, 0 },
246 { X86::SUB8ri, X86::SUB8mi, 0 },
247 { X86::SUB8rr, X86::SUB8mr, 0 },
248 { X86::XOR16ri, X86::XOR16mi, 0 },
249 { X86::XOR16ri8, X86::XOR16mi8, 0 },
250 { X86::XOR16rr, X86::XOR16mr, 0 },
251 { X86::XOR32ri, X86::XOR32mi, 0 },
252 { X86::XOR32ri8, X86::XOR32mi8, 0 },
253 { X86::XOR32rr, X86::XOR32mr, 0 },
254 { X86::XOR64ri32, X86::XOR64mi32, 0 },
255 { X86::XOR64ri8, X86::XOR64mi8, 0 },
256 { X86::XOR64rr, X86::XOR64mr, 0 },
257 { X86::XOR8ri, X86::XOR8mi, 0 },
258 { X86::XOR8rr, X86::XOR8mr, 0 }
261 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
262 unsigned RegOp = OpTbl2Addr[i][0];
263 unsigned MemOp = OpTbl2Addr[i][1];
264 unsigned Flags = OpTbl2Addr[i][2];
265 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
267 // Index 0, folded load and store, no alignment requirement.
268 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
271 static const unsigned OpTbl0[][3] = {
272 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
273 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
274 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
275 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
276 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
277 { X86::WINCALL64r, X86::WINCALL64m, TB_FOLDED_LOAD },
278 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
279 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
280 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
281 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
282 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
283 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
284 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
285 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
286 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
287 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
288 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
289 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
290 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
291 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
292 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
293 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
294 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
295 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
296 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
297 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
298 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
299 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
300 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
301 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
302 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
303 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
304 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
305 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
306 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
307 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
308 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
309 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
310 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
311 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
312 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
313 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
314 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
315 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
316 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
317 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
318 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
319 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
320 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
321 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
322 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
323 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
324 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
325 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
326 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
327 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
328 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
329 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
330 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
331 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
332 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
333 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
334 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
335 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
336 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
337 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
338 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
339 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
340 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
341 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
342 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
343 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
344 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
345 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
346 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
347 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
348 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
349 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
350 // AVX 128-bit versions of foldable instructions
351 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
352 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
353 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
354 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
355 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
356 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
357 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
358 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
359 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
360 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
361 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
362 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
363 // AVX 256-bit foldable instructions
364 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
365 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
366 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
367 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
368 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
371 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
372 unsigned RegOp = OpTbl0[i][0];
373 unsigned MemOp = OpTbl0[i][1];
374 unsigned Flags = OpTbl0[i][2];
375 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
376 RegOp, MemOp, TB_INDEX_0 | Flags);
379 static const unsigned OpTbl1[][3] = {
380 { X86::CMP16rr, X86::CMP16rm, 0 },
381 { X86::CMP32rr, X86::CMP32rm, 0 },
382 { X86::CMP64rr, X86::CMP64rm, 0 },
383 { X86::CMP8rr, X86::CMP8rm, 0 },
384 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
385 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
386 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
387 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
388 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
389 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
390 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
391 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
392 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
393 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
394 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
395 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
396 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
397 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
398 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
399 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
400 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
401 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
402 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
403 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
404 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
405 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
406 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
407 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
408 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
409 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
410 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
411 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
412 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
413 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
414 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
415 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
416 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
417 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
418 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
419 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
420 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
421 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
422 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
423 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
424 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
425 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
426 { X86::MOV16rr, X86::MOV16rm, 0 },
427 { X86::MOV32rr, X86::MOV32rm, 0 },
428 { X86::MOV64rr, X86::MOV64rm, 0 },
429 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
430 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
431 { X86::MOV8rr, X86::MOV8rm, 0 },
432 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
433 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
434 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
435 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
436 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
437 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
438 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
439 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
440 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
441 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
442 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
443 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
444 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
445 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
446 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
447 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
448 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
449 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
450 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
451 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
452 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
453 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
454 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
455 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
456 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
457 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
458 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
459 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
460 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
461 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
462 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
463 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
464 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
465 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
466 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
467 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
468 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
469 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
470 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
471 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
472 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
473 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
474 { X86::SQRTSDr, X86::SQRTSDm, 0 },
475 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
476 { X86::SQRTSSr, X86::SQRTSSm, 0 },
477 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
478 { X86::TEST16rr, X86::TEST16rm, 0 },
479 { X86::TEST32rr, X86::TEST32rm, 0 },
480 { X86::TEST64rr, X86::TEST64rm, 0 },
481 { X86::TEST8rr, X86::TEST8rm, 0 },
482 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
483 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
484 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
485 // AVX 128-bit versions of foldable instructions
486 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
487 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
488 { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm, TB_ALIGN_16 },
489 { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm, TB_ALIGN_16 },
490 { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
491 { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
492 { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
493 { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
494 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
495 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
496 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
497 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
498 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
499 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
500 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
501 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
502 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
503 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
504 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
505 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
506 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
507 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
508 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
509 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
510 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
511 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
512 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
513 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 },
514 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 },
515 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 },
516 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
517 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
518 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
519 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
520 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
521 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
522 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
523 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
524 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
525 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
526 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
527 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
528 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
529 // AVX 256-bit foldable instructions
530 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
531 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
532 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_16 },
533 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
534 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
535 // AVX2 foldable instructions
536 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_16 },
537 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_16 },
538 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_16 },
539 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_16 },
540 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_16 },
541 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_16 }
544 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
545 unsigned RegOp = OpTbl1[i][0];
546 unsigned MemOp = OpTbl1[i][1];
547 unsigned Flags = OpTbl1[i][2];
548 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
550 // Index 1, folded load
551 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
554 static const unsigned OpTbl2[][3] = {
555 { X86::ADC32rr, X86::ADC32rm, 0 },
556 { X86::ADC64rr, X86::ADC64rm, 0 },
557 { X86::ADD16rr, X86::ADD16rm, 0 },
558 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
559 { X86::ADD32rr, X86::ADD32rm, 0 },
560 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
561 { X86::ADD64rr, X86::ADD64rm, 0 },
562 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
563 { X86::ADD8rr, X86::ADD8rm, 0 },
564 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
565 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
566 { X86::ADDSDrr, X86::ADDSDrm, 0 },
567 { X86::ADDSSrr, X86::ADDSSrm, 0 },
568 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
569 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
570 { X86::AND16rr, X86::AND16rm, 0 },
571 { X86::AND32rr, X86::AND32rm, 0 },
572 { X86::AND64rr, X86::AND64rm, 0 },
573 { X86::AND8rr, X86::AND8rm, 0 },
574 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
575 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
576 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
577 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
578 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
579 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
580 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
581 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
582 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
583 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
584 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
585 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
586 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
587 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
588 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
589 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
590 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
591 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
592 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
593 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
594 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
595 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
596 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
597 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
598 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
599 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
600 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
601 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
602 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
603 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
604 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
605 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
606 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
607 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
608 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
609 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
610 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
611 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
612 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
613 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
614 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
615 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
616 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
617 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
618 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
619 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
620 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
621 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
622 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
623 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
624 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
625 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
626 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
627 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
628 { X86::CMPSDrr, X86::CMPSDrm, 0 },
629 { X86::CMPSSrr, X86::CMPSSrm, 0 },
630 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
631 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
632 { X86::DIVSDrr, X86::DIVSDrm, 0 },
633 { X86::DIVSSrr, X86::DIVSSrm, 0 },
634 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
635 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
636 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
637 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
638 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
639 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
640 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
641 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
642 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
643 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
644 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
645 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
646 { X86::IMUL16rr, X86::IMUL16rm, 0 },
647 { X86::IMUL32rr, X86::IMUL32rm, 0 },
648 { X86::IMUL64rr, X86::IMUL64rm, 0 },
649 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
650 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
651 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
652 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
653 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
654 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
655 { X86::MAXSDrr, X86::MAXSDrm, 0 },
656 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
657 { X86::MAXSSrr, X86::MAXSSrm, 0 },
658 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
659 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
660 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
661 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
662 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
663 { X86::MINSDrr, X86::MINSDrm, 0 },
664 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
665 { X86::MINSSrr, X86::MINSSrm, 0 },
666 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
667 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
668 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
669 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
670 { X86::MULSDrr, X86::MULSDrm, 0 },
671 { X86::MULSSrr, X86::MULSSrm, 0 },
672 { X86::OR16rr, X86::OR16rm, 0 },
673 { X86::OR32rr, X86::OR32rm, 0 },
674 { X86::OR64rr, X86::OR64rm, 0 },
675 { X86::OR8rr, X86::OR8rm, 0 },
676 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
677 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
678 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
679 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
680 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
681 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
682 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
683 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
684 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
685 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
686 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
687 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
688 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
689 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
690 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
691 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
692 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
693 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
694 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
695 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
696 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
697 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
698 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
699 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
700 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
701 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
702 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
703 { X86::PHADDDrr128, X86::PHADDDrm128, TB_ALIGN_16 },
704 { X86::PHADDWrr128, X86::PHADDWrm128, TB_ALIGN_16 },
705 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
706 { X86::PHSUBDrr128, X86::PHSUBDrm128, TB_ALIGN_16 },
707 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
708 { X86::PHSUBWrr128, X86::PHSUBWrm128, TB_ALIGN_16 },
709 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
710 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
711 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
712 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
713 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
714 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
715 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
716 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
717 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
718 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
719 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
720 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
721 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
722 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
723 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
724 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
725 { X86::PSHUFBrr128, X86::PSHUFBrm128, TB_ALIGN_16 },
726 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
727 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
728 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
729 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
730 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
731 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
732 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
733 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
734 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
735 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
736 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
737 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
738 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
739 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
740 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
741 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
742 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
743 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
744 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
745 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
746 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
747 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
748 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
749 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
750 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
751 { X86::SBB32rr, X86::SBB32rm, 0 },
752 { X86::SBB64rr, X86::SBB64rm, 0 },
753 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
754 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
755 { X86::SUB16rr, X86::SUB16rm, 0 },
756 { X86::SUB32rr, X86::SUB32rm, 0 },
757 { X86::SUB64rr, X86::SUB64rm, 0 },
758 { X86::SUB8rr, X86::SUB8rm, 0 },
759 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
760 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
761 { X86::SUBSDrr, X86::SUBSDrm, 0 },
762 { X86::SUBSSrr, X86::SUBSSrm, 0 },
763 // FIXME: TEST*rr -> swapped operand of TEST*mr.
764 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
765 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
766 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
767 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
768 { X86::XOR16rr, X86::XOR16rm, 0 },
769 { X86::XOR32rr, X86::XOR32rm, 0 },
770 { X86::XOR64rr, X86::XOR64rm, 0 },
771 { X86::XOR8rr, X86::XOR8rm, 0 },
772 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
773 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
774 // AVX 128-bit versions of foldable instructions
775 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
776 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
777 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
778 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
779 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
780 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
781 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
782 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
783 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
784 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
785 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
786 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
787 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
788 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
789 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
790 { X86::Int_VCVTTSD2SIrr, X86::Int_VCVTTSD2SIrm, 0 },
791 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
792 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
793 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
794 { X86::Int_VCVTTSS2SIrr, X86::Int_VCVTTSS2SIrm, 0 },
795 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
796 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
797 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, TB_ALIGN_16 },
798 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
799 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
800 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
801 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
802 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
803 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
804 { X86::VADDSDrr, X86::VADDSDrm, 0 },
805 { X86::VADDSSrr, X86::VADDSSrm, 0 },
806 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
807 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
808 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
809 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
810 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
811 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
812 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
813 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
814 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
815 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
816 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
817 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
818 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
819 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
820 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
821 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
822 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
823 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
824 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
825 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
826 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
827 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
828 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
829 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
830 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
831 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
832 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
833 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
834 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
835 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
836 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
837 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
838 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
839 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
840 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
841 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
842 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
843 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
844 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
845 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
846 { X86::VMINSDrr, X86::VMINSDrm, 0 },
847 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
848 { X86::VMINSSrr, X86::VMINSSrm, 0 },
849 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
850 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 },
851 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
852 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
853 { X86::VMULSDrr, X86::VMULSDrm, 0 },
854 { X86::VMULSSrr, X86::VMULSSrm, 0 },
855 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
856 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
857 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
858 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
859 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 },
860 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
861 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
862 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
863 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
864 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
865 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
866 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 },
867 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 },
868 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
869 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 },
870 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
871 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
872 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 },
873 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 },
874 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
875 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
876 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 },
877 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
878 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
879 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
880 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 },
881 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
882 { X86::VPHADDDrr128, X86::VPHADDDrm128, TB_ALIGN_16 },
883 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 },
884 { X86::VPHADDWrr128, X86::VPHADDWrm128, TB_ALIGN_16 },
885 { X86::VPHSUBDrr128, X86::VPHSUBDrm128, TB_ALIGN_16 },
886 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 },
887 { X86::VPHSUBWrr128, X86::VPHSUBWrm128, TB_ALIGN_16 },
888 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
889 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 },
890 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
891 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
892 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
893 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
894 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
895 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
896 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 },
897 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
898 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
899 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
900 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
901 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
902 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
903 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
904 { X86::VPSHUFBrr128, X86::VPSHUFBrm128, TB_ALIGN_16 },
905 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, TB_ALIGN_16 },
906 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, TB_ALIGN_16 },
907 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, TB_ALIGN_16 },
908 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
909 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
910 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
911 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
912 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
913 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
914 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
915 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
916 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
917 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
918 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
919 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
920 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
921 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
922 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
923 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
924 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
925 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
926 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
927 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
928 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
929 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
930 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
931 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
932 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
933 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
934 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
935 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
936 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
937 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
938 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
939 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
940 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
941 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 },
942 // AVX2 foldable instructions
943 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_16 },
944 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_16 },
945 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_16 },
946 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_16 },
947 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_16 },
948 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_16 },
949 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_16 },
950 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_16 },
951 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_16 },
952 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_16 },
953 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_16 },
954 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_16 },
955 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_16 },
956 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_16 },
957 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_16 },
958 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_16 },
959 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_16 },
960 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_16 },
961 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_16 },
962 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_16 },
963 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_16 },
964 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_16 },
965 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_16 },
966 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_16 },
967 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_16 },
968 { X86::VPHADDDrr256, X86::VPHADDDrm256, TB_ALIGN_16 },
969 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_16 },
970 { X86::VPHADDWrr256, X86::VPHADDWrm256, TB_ALIGN_16 },
971 { X86::VPHSUBDrr256, X86::VPHSUBDrm256, TB_ALIGN_16 },
972 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_16 },
973 { X86::VPHSUBWrr256, X86::VPHSUBWrm256, TB_ALIGN_16 },
974 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_16 },
975 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_16 },
976 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_16 },
977 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_16 },
978 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_16 },
979 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_16 },
980 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_16 },
981 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_16 },
982 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_16 },
983 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_16 },
984 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_16 },
985 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_16 },
986 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_16 },
987 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_16 },
988 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_16 },
989 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_16 },
990 { X86::VPSHUFBrr256, X86::VPSHUFBrm256, TB_ALIGN_16 },
991 { X86::VPSIGNBrr256, X86::VPSIGNBrm256, TB_ALIGN_16 },
992 { X86::VPSIGNWrr256, X86::VPSIGNWrm256, TB_ALIGN_16 },
993 { X86::VPSIGNDrr256, X86::VPSIGNDrm256, TB_ALIGN_16 },
994 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 },
995 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 },
996 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 },
997 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 },
998 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_16 },
999 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 },
1000 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_16 },
1001 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 },
1002 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 },
1003 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 },
1004 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_16 },
1005 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 },
1006 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 },
1007 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 },
1008 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 },
1009 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_16 },
1010 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 },
1011 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_16 },
1012 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_16 },
1013 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_16 },
1014 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_16 },
1015 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_16 },
1016 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_16 },
1017 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_16 },
1018 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_16 },
1019 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 },
1020 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_16 },
1021 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_16 },
1022 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_16 },
1023 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_16 },
1024 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_16 },
1025 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_16 },
1026 // FIXME: add AVX 256-bit foldable instructions
1029 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1030 unsigned RegOp = OpTbl2[i][0];
1031 unsigned MemOp = OpTbl2[i][1];
1032 unsigned Flags = OpTbl2[i][2];
1033 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1035 // Index 2, folded load
1036 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1041 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1042 MemOp2RegOpTableType &M2RTable,
1043 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1044 if ((Flags & TB_NO_FORWARD) == 0) {
1045 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1046 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1048 if ((Flags & TB_NO_REVERSE) == 0) {
1049 assert(!M2RTable.count(MemOp) &&
1050 "Duplicated entries in unfolding maps?");
1051 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1056 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1057 unsigned &SrcReg, unsigned &DstReg,
1058 unsigned &SubIdx) const {
1059 switch (MI.getOpcode()) {
1061 case X86::MOVSX16rr8:
1062 case X86::MOVZX16rr8:
1063 case X86::MOVSX32rr8:
1064 case X86::MOVZX32rr8:
1065 case X86::MOVSX64rr8:
1066 case X86::MOVZX64rr8:
1067 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1068 // It's not always legal to reference the low 8-bit of the larger
1069 // register in 32-bit mode.
1071 case X86::MOVSX32rr16:
1072 case X86::MOVZX32rr16:
1073 case X86::MOVSX64rr16:
1074 case X86::MOVZX64rr16:
1075 case X86::MOVSX64rr32:
1076 case X86::MOVZX64rr32: {
1077 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1080 SrcReg = MI.getOperand(1).getReg();
1081 DstReg = MI.getOperand(0).getReg();
1082 switch (MI.getOpcode()) {
1084 llvm_unreachable(0);
1086 case X86::MOVSX16rr8:
1087 case X86::MOVZX16rr8:
1088 case X86::MOVSX32rr8:
1089 case X86::MOVZX32rr8:
1090 case X86::MOVSX64rr8:
1091 case X86::MOVZX64rr8:
1092 SubIdx = X86::sub_8bit;
1094 case X86::MOVSX32rr16:
1095 case X86::MOVZX32rr16:
1096 case X86::MOVSX64rr16:
1097 case X86::MOVZX64rr16:
1098 SubIdx = X86::sub_16bit;
1100 case X86::MOVSX64rr32:
1101 case X86::MOVZX64rr32:
1102 SubIdx = X86::sub_32bit;
1111 /// isFrameOperand - Return true and the FrameIndex if the specified
1112 /// operand and follow operands form a reference to the stack frame.
1113 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1114 int &FrameIndex) const {
1115 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1116 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1117 MI->getOperand(Op+1).getImm() == 1 &&
1118 MI->getOperand(Op+2).getReg() == 0 &&
1119 MI->getOperand(Op+3).getImm() == 0) {
1120 FrameIndex = MI->getOperand(Op).getIndex();
1126 static bool isFrameLoadOpcode(int Opcode) {
1141 case X86::VMOVAPSrm:
1142 case X86::VMOVAPDrm:
1143 case X86::VMOVDQArm:
1144 case X86::VMOVAPSYrm:
1145 case X86::VMOVAPDYrm:
1146 case X86::VMOVDQAYrm:
1147 case X86::MMX_MOVD64rm:
1148 case X86::MMX_MOVQ64rm:
1155 static bool isFrameStoreOpcode(int Opcode) {
1162 case X86::ST_FpP64m:
1170 case X86::VMOVAPSmr:
1171 case X86::VMOVAPDmr:
1172 case X86::VMOVDQAmr:
1173 case X86::VMOVAPSYmr:
1174 case X86::VMOVAPDYmr:
1175 case X86::VMOVDQAYmr:
1176 case X86::MMX_MOVD64mr:
1177 case X86::MMX_MOVQ64mr:
1178 case X86::MMX_MOVNTQmr:
1184 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1185 int &FrameIndex) const {
1186 if (isFrameLoadOpcode(MI->getOpcode()))
1187 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1188 return MI->getOperand(0).getReg();
1192 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1193 int &FrameIndex) const {
1194 if (isFrameLoadOpcode(MI->getOpcode())) {
1196 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1198 // Check for post-frame index elimination operations
1199 const MachineMemOperand *Dummy;
1200 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1205 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1206 int &FrameIndex) const {
1207 if (isFrameStoreOpcode(MI->getOpcode()))
1208 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1209 isFrameOperand(MI, 0, FrameIndex))
1210 return MI->getOperand(X86::AddrNumOperands).getReg();
1214 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1215 int &FrameIndex) const {
1216 if (isFrameStoreOpcode(MI->getOpcode())) {
1218 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1220 // Check for post-frame index elimination operations
1221 const MachineMemOperand *Dummy;
1222 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1227 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1229 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1230 bool isPICBase = false;
1231 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1232 E = MRI.def_end(); I != E; ++I) {
1233 MachineInstr *DefMI = I.getOperand().getParent();
1234 if (DefMI->getOpcode() != X86::MOVPC32r)
1236 assert(!isPICBase && "More than one PIC base?");
1243 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1244 AliasAnalysis *AA) const {
1245 switch (MI->getOpcode()) {
1260 case X86::VMOVAPSrm:
1261 case X86::VMOVUPSrm:
1262 case X86::VMOVAPDrm:
1263 case X86::VMOVDQArm:
1264 case X86::VMOVAPSYrm:
1265 case X86::VMOVUPSYrm:
1266 case X86::VMOVAPDYrm:
1267 case X86::VMOVDQAYrm:
1268 case X86::MMX_MOVD64rm:
1269 case X86::MMX_MOVQ64rm:
1270 case X86::FsVMOVAPSrm:
1271 case X86::FsVMOVAPDrm:
1272 case X86::FsMOVAPSrm:
1273 case X86::FsMOVAPDrm: {
1274 // Loads from constant pools are trivially rematerializable.
1275 if (MI->getOperand(1).isReg() &&
1276 MI->getOperand(2).isImm() &&
1277 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1278 MI->isInvariantLoad(AA)) {
1279 unsigned BaseReg = MI->getOperand(1).getReg();
1280 if (BaseReg == 0 || BaseReg == X86::RIP)
1282 // Allow re-materialization of PIC load.
1283 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1285 const MachineFunction &MF = *MI->getParent()->getParent();
1286 const MachineRegisterInfo &MRI = MF.getRegInfo();
1287 bool isPICBase = false;
1288 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1289 E = MRI.def_end(); I != E; ++I) {
1290 MachineInstr *DefMI = I.getOperand().getParent();
1291 if (DefMI->getOpcode() != X86::MOVPC32r)
1293 assert(!isPICBase && "More than one PIC base?");
1303 if (MI->getOperand(2).isImm() &&
1304 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1305 !MI->getOperand(4).isReg()) {
1306 // lea fi#, lea GV, etc. are all rematerializable.
1307 if (!MI->getOperand(1).isReg())
1309 unsigned BaseReg = MI->getOperand(1).getReg();
1312 // Allow re-materialization of lea PICBase + x.
1313 const MachineFunction &MF = *MI->getParent()->getParent();
1314 const MachineRegisterInfo &MRI = MF.getRegInfo();
1315 return regIsPICBase(BaseReg, MRI);
1321 // All other instructions marked M_REMATERIALIZABLE are always trivially
1322 // rematerializable.
1326 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1327 /// would clobber the EFLAGS condition register. Note the result may be
1328 /// conservative. If it cannot definitely determine the safety after visiting
1329 /// a few instructions in each direction it assumes it's not safe.
1330 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1331 MachineBasicBlock::iterator I) {
1332 MachineBasicBlock::iterator E = MBB.end();
1334 // For compile time consideration, if we are not able to determine the
1335 // safety after visiting 4 instructions in each direction, we will assume
1337 MachineBasicBlock::iterator Iter = I;
1338 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1339 bool SeenDef = false;
1340 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1341 MachineOperand &MO = Iter->getOperand(j);
1344 if (MO.getReg() == X86::EFLAGS) {
1352 // This instruction defines EFLAGS, no need to look any further.
1355 // Skip over DBG_VALUE.
1356 while (Iter != E && Iter->isDebugValue())
1360 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1363 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1364 SE = MBB.succ_end(); SI != SE; ++SI)
1365 if ((*SI)->isLiveIn(X86::EFLAGS))
1370 MachineBasicBlock::iterator B = MBB.begin();
1372 for (unsigned i = 0; i < 4; ++i) {
1373 // If we make it to the beginning of the block, it's safe to clobber
1374 // EFLAGS iff EFLAGS is not live-in.
1376 return !MBB.isLiveIn(X86::EFLAGS);
1379 // Skip over DBG_VALUE.
1380 while (Iter != B && Iter->isDebugValue())
1383 bool SawKill = false;
1384 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1385 MachineOperand &MO = Iter->getOperand(j);
1386 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1387 if (MO.isDef()) return MO.isDead();
1388 if (MO.isKill()) SawKill = true;
1393 // This instruction kills EFLAGS and doesn't redefine it, so
1394 // there's no need to look further.
1398 // Conservative answer.
1402 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1403 MachineBasicBlock::iterator I,
1404 unsigned DestReg, unsigned SubIdx,
1405 const MachineInstr *Orig,
1406 const TargetRegisterInfo &TRI) const {
1407 DebugLoc DL = Orig->getDebugLoc();
1409 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1410 // Re-materialize them as movri instructions to avoid side effects.
1412 unsigned Opc = Orig->getOpcode();
1418 case X86::MOV64r0: {
1419 if (!isSafeToClobberEFLAGS(MBB, I)) {
1422 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1423 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1424 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1425 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1434 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1437 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1440 MachineInstr *NewMI = prior(I);
1441 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1444 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1445 /// is not marked dead.
1446 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1447 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1448 MachineOperand &MO = MI->getOperand(i);
1449 if (MO.isReg() && MO.isDef() &&
1450 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1457 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1458 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1459 /// to a 32-bit superregister and then truncating back down to a 16-bit
1462 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1463 MachineFunction::iterator &MFI,
1464 MachineBasicBlock::iterator &MBBI,
1465 LiveVariables *LV) const {
1466 MachineInstr *MI = MBBI;
1467 unsigned Dest = MI->getOperand(0).getReg();
1468 unsigned Src = MI->getOperand(1).getReg();
1469 bool isDead = MI->getOperand(0).isDead();
1470 bool isKill = MI->getOperand(1).isKill();
1472 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1473 ? X86::LEA64_32r : X86::LEA32r;
1474 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1475 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1476 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1478 // Build and insert into an implicit UNDEF value. This is OK because
1479 // well be shifting and then extracting the lower 16-bits.
1480 // This has the potential to cause partial register stall. e.g.
1481 // movw (%rbp,%rcx,2), %dx
1482 // leal -65(%rdx), %esi
1483 // But testing has shown this *does* help performance in 64-bit mode (at
1484 // least on modern x86 machines).
1485 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1486 MachineInstr *InsMI =
1487 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1488 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1489 .addReg(Src, getKillRegState(isKill));
1491 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1492 get(Opc), leaOutReg);
1495 llvm_unreachable(0);
1497 case X86::SHL16ri: {
1498 unsigned ShAmt = MI->getOperand(2).getImm();
1499 MIB.addReg(0).addImm(1 << ShAmt)
1500 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1504 case X86::INC64_16r:
1505 addRegOffset(MIB, leaInReg, true, 1);
1508 case X86::DEC64_16r:
1509 addRegOffset(MIB, leaInReg, true, -1);
1513 case X86::ADD16ri_DB:
1514 case X86::ADD16ri8_DB:
1515 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1518 case X86::ADD16rr_DB: {
1519 unsigned Src2 = MI->getOperand(2).getReg();
1520 bool isKill2 = MI->getOperand(2).isKill();
1521 unsigned leaInReg2 = 0;
1522 MachineInstr *InsMI2 = 0;
1524 // ADD16rr %reg1028<kill>, %reg1028
1525 // just a single insert_subreg.
1526 addRegReg(MIB, leaInReg, true, leaInReg, false);
1528 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1529 // Build and insert into an implicit UNDEF value. This is OK because
1530 // well be shifting and then extracting the lower 16-bits.
1531 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1533 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1534 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1535 .addReg(Src2, getKillRegState(isKill2));
1536 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1538 if (LV && isKill2 && InsMI2)
1539 LV->replaceKillInstruction(Src2, MI, InsMI2);
1544 MachineInstr *NewMI = MIB;
1545 MachineInstr *ExtMI =
1546 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1547 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1548 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1551 // Update live variables
1552 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1553 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1555 LV->replaceKillInstruction(Src, MI, InsMI);
1557 LV->replaceKillInstruction(Dest, MI, ExtMI);
1563 /// convertToThreeAddress - This method must be implemented by targets that
1564 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1565 /// may be able to convert a two-address instruction into a true
1566 /// three-address instruction on demand. This allows the X86 target (for
1567 /// example) to convert ADD and SHL instructions into LEA instructions if they
1568 /// would require register copies due to two-addressness.
1570 /// This method returns a null pointer if the transformation cannot be
1571 /// performed, otherwise it returns the new instruction.
1574 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1575 MachineBasicBlock::iterator &MBBI,
1576 LiveVariables *LV) const {
1577 MachineInstr *MI = MBBI;
1578 MachineFunction &MF = *MI->getParent()->getParent();
1579 // All instructions input are two-addr instructions. Get the known operands.
1580 unsigned Dest = MI->getOperand(0).getReg();
1581 unsigned Src = MI->getOperand(1).getReg();
1582 bool isDead = MI->getOperand(0).isDead();
1583 bool isKill = MI->getOperand(1).isKill();
1585 MachineInstr *NewMI = NULL;
1586 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1587 // we have better subtarget support, enable the 16-bit LEA generation here.
1588 // 16-bit LEA is also slow on Core2.
1589 bool DisableLEA16 = true;
1590 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1592 unsigned MIOpc = MI->getOpcode();
1594 case X86::SHUFPSrri: {
1595 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1596 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1598 unsigned B = MI->getOperand(1).getReg();
1599 unsigned C = MI->getOperand(2).getReg();
1600 if (B != C) return 0;
1601 unsigned A = MI->getOperand(0).getReg();
1602 unsigned M = MI->getOperand(3).getImm();
1603 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1604 .addReg(A, RegState::Define | getDeadRegState(isDead))
1605 .addReg(B, getKillRegState(isKill)).addImm(M);
1608 case X86::SHUFPDrri: {
1609 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1610 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1612 unsigned B = MI->getOperand(1).getReg();
1613 unsigned C = MI->getOperand(2).getReg();
1614 if (B != C) return 0;
1615 unsigned A = MI->getOperand(0).getReg();
1616 unsigned M = MI->getOperand(3).getImm();
1618 // Convert to PSHUFD mask.
1619 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1621 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1622 .addReg(A, RegState::Define | getDeadRegState(isDead))
1623 .addReg(B, getKillRegState(isKill)).addImm(M);
1626 case X86::SHL64ri: {
1627 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1628 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1629 // the flags produced by a shift yet, so this is safe.
1630 unsigned ShAmt = MI->getOperand(2).getImm();
1631 if (ShAmt == 0 || ShAmt >= 4) return 0;
1633 // LEA can't handle RSP.
1634 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1635 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1638 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1639 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1640 .addReg(0).addImm(1 << ShAmt)
1641 .addReg(Src, getKillRegState(isKill))
1642 .addImm(0).addReg(0);
1645 case X86::SHL32ri: {
1646 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1647 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1648 // the flags produced by a shift yet, so this is safe.
1649 unsigned ShAmt = MI->getOperand(2).getImm();
1650 if (ShAmt == 0 || ShAmt >= 4) return 0;
1652 // LEA can't handle ESP.
1653 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1654 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1657 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1658 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1659 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1660 .addReg(0).addImm(1 << ShAmt)
1661 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1664 case X86::SHL16ri: {
1665 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1666 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1667 // the flags produced by a shift yet, so this is safe.
1668 unsigned ShAmt = MI->getOperand(2).getImm();
1669 if (ShAmt == 0 || ShAmt >= 4) return 0;
1672 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1673 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1674 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1675 .addReg(0).addImm(1 << ShAmt)
1676 .addReg(Src, getKillRegState(isKill))
1677 .addImm(0).addReg(0);
1681 // The following opcodes also sets the condition code register(s). Only
1682 // convert them to equivalent lea if the condition code register def's
1684 if (hasLiveCondCodeDef(MI))
1691 case X86::INC64_32r: {
1692 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1693 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1694 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1696 // LEA can't handle RSP.
1697 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1698 !MF.getRegInfo().constrainRegClass(Src,
1699 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1700 X86::GR32_NOSPRegisterClass))
1703 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1704 .addReg(Dest, RegState::Define |
1705 getDeadRegState(isDead)),
1710 case X86::INC64_16r:
1712 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1713 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1714 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1715 .addReg(Dest, RegState::Define |
1716 getDeadRegState(isDead)),
1721 case X86::DEC64_32r: {
1722 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1723 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1724 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1725 // LEA can't handle RSP.
1726 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1727 !MF.getRegInfo().constrainRegClass(Src,
1728 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1729 X86::GR32_NOSPRegisterClass))
1732 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1733 .addReg(Dest, RegState::Define |
1734 getDeadRegState(isDead)),
1739 case X86::DEC64_16r:
1741 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1742 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1743 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1744 .addReg(Dest, RegState::Define |
1745 getDeadRegState(isDead)),
1749 case X86::ADD64rr_DB:
1751 case X86::ADD32rr_DB: {
1752 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1754 TargetRegisterClass *RC;
1755 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1757 RC = X86::GR64_NOSPRegisterClass;
1759 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1760 RC = X86::GR32_NOSPRegisterClass;
1764 unsigned Src2 = MI->getOperand(2).getReg();
1765 bool isKill2 = MI->getOperand(2).isKill();
1767 // LEA can't handle RSP.
1768 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1769 !MF.getRegInfo().constrainRegClass(Src2, RC))
1772 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1773 .addReg(Dest, RegState::Define |
1774 getDeadRegState(isDead)),
1775 Src, isKill, Src2, isKill2);
1777 LV->replaceKillInstruction(Src2, MI, NewMI);
1781 case X86::ADD16rr_DB: {
1783 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1784 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1785 unsigned Src2 = MI->getOperand(2).getReg();
1786 bool isKill2 = MI->getOperand(2).isKill();
1787 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1788 .addReg(Dest, RegState::Define |
1789 getDeadRegState(isDead)),
1790 Src, isKill, Src2, isKill2);
1792 LV->replaceKillInstruction(Src2, MI, NewMI);
1795 case X86::ADD64ri32:
1797 case X86::ADD64ri32_DB:
1798 case X86::ADD64ri8_DB:
1799 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1800 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1801 .addReg(Dest, RegState::Define |
1802 getDeadRegState(isDead)),
1803 Src, isKill, MI->getOperand(2).getImm());
1807 case X86::ADD32ri_DB:
1808 case X86::ADD32ri8_DB: {
1809 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1810 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1811 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1812 .addReg(Dest, RegState::Define |
1813 getDeadRegState(isDead)),
1814 Src, isKill, MI->getOperand(2).getImm());
1819 case X86::ADD16ri_DB:
1820 case X86::ADD16ri8_DB:
1822 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1823 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1824 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1825 .addReg(Dest, RegState::Define |
1826 getDeadRegState(isDead)),
1827 Src, isKill, MI->getOperand(2).getImm());
1833 if (!NewMI) return 0;
1835 if (LV) { // Update live variables
1837 LV->replaceKillInstruction(Src, MI, NewMI);
1839 LV->replaceKillInstruction(Dest, MI, NewMI);
1842 MFI->insert(MBBI, NewMI); // Insert the new inst
1846 /// commuteInstruction - We have a few instructions that must be hacked on to
1850 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1851 switch (MI->getOpcode()) {
1852 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1853 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1854 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1855 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1856 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1857 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1860 switch (MI->getOpcode()) {
1861 default: llvm_unreachable("Unreachable!");
1862 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1863 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1864 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1865 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1866 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1867 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1869 unsigned Amt = MI->getOperand(3).getImm();
1871 MachineFunction &MF = *MI->getParent()->getParent();
1872 MI = MF.CloneMachineInstr(MI);
1875 MI->setDesc(get(Opc));
1876 MI->getOperand(3).setImm(Size-Amt);
1877 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1879 case X86::CMOVB16rr:
1880 case X86::CMOVB32rr:
1881 case X86::CMOVB64rr:
1882 case X86::CMOVAE16rr:
1883 case X86::CMOVAE32rr:
1884 case X86::CMOVAE64rr:
1885 case X86::CMOVE16rr:
1886 case X86::CMOVE32rr:
1887 case X86::CMOVE64rr:
1888 case X86::CMOVNE16rr:
1889 case X86::CMOVNE32rr:
1890 case X86::CMOVNE64rr:
1891 case X86::CMOVBE16rr:
1892 case X86::CMOVBE32rr:
1893 case X86::CMOVBE64rr:
1894 case X86::CMOVA16rr:
1895 case X86::CMOVA32rr:
1896 case X86::CMOVA64rr:
1897 case X86::CMOVL16rr:
1898 case X86::CMOVL32rr:
1899 case X86::CMOVL64rr:
1900 case X86::CMOVGE16rr:
1901 case X86::CMOVGE32rr:
1902 case X86::CMOVGE64rr:
1903 case X86::CMOVLE16rr:
1904 case X86::CMOVLE32rr:
1905 case X86::CMOVLE64rr:
1906 case X86::CMOVG16rr:
1907 case X86::CMOVG32rr:
1908 case X86::CMOVG64rr:
1909 case X86::CMOVS16rr:
1910 case X86::CMOVS32rr:
1911 case X86::CMOVS64rr:
1912 case X86::CMOVNS16rr:
1913 case X86::CMOVNS32rr:
1914 case X86::CMOVNS64rr:
1915 case X86::CMOVP16rr:
1916 case X86::CMOVP32rr:
1917 case X86::CMOVP64rr:
1918 case X86::CMOVNP16rr:
1919 case X86::CMOVNP32rr:
1920 case X86::CMOVNP64rr:
1921 case X86::CMOVO16rr:
1922 case X86::CMOVO32rr:
1923 case X86::CMOVO64rr:
1924 case X86::CMOVNO16rr:
1925 case X86::CMOVNO32rr:
1926 case X86::CMOVNO64rr: {
1928 switch (MI->getOpcode()) {
1930 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1931 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1932 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1933 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1934 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1935 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1936 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1937 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1938 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1939 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1940 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1941 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1942 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1943 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1944 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1945 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1946 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1947 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1948 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1949 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1950 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1951 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1952 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1953 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1954 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1955 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1956 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1957 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1958 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1959 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1960 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1961 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1962 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1963 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1964 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1965 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1966 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1967 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1968 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1969 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1970 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1971 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1972 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1973 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1974 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1975 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1976 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1977 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1980 MachineFunction &MF = *MI->getParent()->getParent();
1981 MI = MF.CloneMachineInstr(MI);
1984 MI->setDesc(get(Opc));
1985 // Fallthrough intended.
1988 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1992 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1994 default: return X86::COND_INVALID;
1995 case X86::JE_4: return X86::COND_E;
1996 case X86::JNE_4: return X86::COND_NE;
1997 case X86::JL_4: return X86::COND_L;
1998 case X86::JLE_4: return X86::COND_LE;
1999 case X86::JG_4: return X86::COND_G;
2000 case X86::JGE_4: return X86::COND_GE;
2001 case X86::JB_4: return X86::COND_B;
2002 case X86::JBE_4: return X86::COND_BE;
2003 case X86::JA_4: return X86::COND_A;
2004 case X86::JAE_4: return X86::COND_AE;
2005 case X86::JS_4: return X86::COND_S;
2006 case X86::JNS_4: return X86::COND_NS;
2007 case X86::JP_4: return X86::COND_P;
2008 case X86::JNP_4: return X86::COND_NP;
2009 case X86::JO_4: return X86::COND_O;
2010 case X86::JNO_4: return X86::COND_NO;
2014 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2016 default: llvm_unreachable("Illegal condition code!");
2017 case X86::COND_E: return X86::JE_4;
2018 case X86::COND_NE: return X86::JNE_4;
2019 case X86::COND_L: return X86::JL_4;
2020 case X86::COND_LE: return X86::JLE_4;
2021 case X86::COND_G: return X86::JG_4;
2022 case X86::COND_GE: return X86::JGE_4;
2023 case X86::COND_B: return X86::JB_4;
2024 case X86::COND_BE: return X86::JBE_4;
2025 case X86::COND_A: return X86::JA_4;
2026 case X86::COND_AE: return X86::JAE_4;
2027 case X86::COND_S: return X86::JS_4;
2028 case X86::COND_NS: return X86::JNS_4;
2029 case X86::COND_P: return X86::JP_4;
2030 case X86::COND_NP: return X86::JNP_4;
2031 case X86::COND_O: return X86::JO_4;
2032 case X86::COND_NO: return X86::JNO_4;
2036 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2037 /// e.g. turning COND_E to COND_NE.
2038 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2040 default: llvm_unreachable("Illegal condition code!");
2041 case X86::COND_E: return X86::COND_NE;
2042 case X86::COND_NE: return X86::COND_E;
2043 case X86::COND_L: return X86::COND_GE;
2044 case X86::COND_LE: return X86::COND_G;
2045 case X86::COND_G: return X86::COND_LE;
2046 case X86::COND_GE: return X86::COND_L;
2047 case X86::COND_B: return X86::COND_AE;
2048 case X86::COND_BE: return X86::COND_A;
2049 case X86::COND_A: return X86::COND_BE;
2050 case X86::COND_AE: return X86::COND_B;
2051 case X86::COND_S: return X86::COND_NS;
2052 case X86::COND_NS: return X86::COND_S;
2053 case X86::COND_P: return X86::COND_NP;
2054 case X86::COND_NP: return X86::COND_P;
2055 case X86::COND_O: return X86::COND_NO;
2056 case X86::COND_NO: return X86::COND_O;
2060 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2061 if (!MI->isTerminator()) return false;
2063 // Conditional branch is a special case.
2064 if (MI->isBranch() && !MI->isBarrier())
2066 if (!MI->isPredicable())
2068 return !isPredicated(MI);
2071 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2072 MachineBasicBlock *&TBB,
2073 MachineBasicBlock *&FBB,
2074 SmallVectorImpl<MachineOperand> &Cond,
2075 bool AllowModify) const {
2076 // Start from the bottom of the block and work up, examining the
2077 // terminator instructions.
2078 MachineBasicBlock::iterator I = MBB.end();
2079 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2080 while (I != MBB.begin()) {
2082 if (I->isDebugValue())
2085 // Working from the bottom, when we see a non-terminator instruction, we're
2087 if (!isUnpredicatedTerminator(I))
2090 // A terminator that isn't a branch can't easily be handled by this
2095 // Handle unconditional branches.
2096 if (I->getOpcode() == X86::JMP_4) {
2100 TBB = I->getOperand(0).getMBB();
2104 // If the block has any instructions after a JMP, delete them.
2105 while (llvm::next(I) != MBB.end())
2106 llvm::next(I)->eraseFromParent();
2111 // Delete the JMP if it's equivalent to a fall-through.
2112 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2114 I->eraseFromParent();
2116 UnCondBrIter = MBB.end();
2120 // TBB is used to indicate the unconditional destination.
2121 TBB = I->getOperand(0).getMBB();
2125 // Handle conditional branches.
2126 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2127 if (BranchCode == X86::COND_INVALID)
2128 return true; // Can't handle indirect branch.
2130 // Working from the bottom, handle the first conditional branch.
2132 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2133 if (AllowModify && UnCondBrIter != MBB.end() &&
2134 MBB.isLayoutSuccessor(TargetBB)) {
2135 // If we can modify the code and it ends in something like:
2143 // Then we can change this to:
2150 // Which is a bit more efficient.
2151 // We conditionally jump to the fall-through block.
2152 BranchCode = GetOppositeBranchCondition(BranchCode);
2153 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2154 MachineBasicBlock::iterator OldInst = I;
2156 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2157 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2158 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2161 OldInst->eraseFromParent();
2162 UnCondBrIter->eraseFromParent();
2164 // Restart the analysis.
2165 UnCondBrIter = MBB.end();
2171 TBB = I->getOperand(0).getMBB();
2172 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2176 // Handle subsequent conditional branches. Only handle the case where all
2177 // conditional branches branch to the same destination and their condition
2178 // opcodes fit one of the special multi-branch idioms.
2179 assert(Cond.size() == 1);
2182 // Only handle the case where all conditional branches branch to the same
2184 if (TBB != I->getOperand(0).getMBB())
2187 // If the conditions are the same, we can leave them alone.
2188 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2189 if (OldBranchCode == BranchCode)
2192 // If they differ, see if they fit one of the known patterns. Theoretically,
2193 // we could handle more patterns here, but we shouldn't expect to see them
2194 // if instruction selection has done a reasonable job.
2195 if ((OldBranchCode == X86::COND_NP &&
2196 BranchCode == X86::COND_E) ||
2197 (OldBranchCode == X86::COND_E &&
2198 BranchCode == X86::COND_NP))
2199 BranchCode = X86::COND_NP_OR_E;
2200 else if ((OldBranchCode == X86::COND_P &&
2201 BranchCode == X86::COND_NE) ||
2202 (OldBranchCode == X86::COND_NE &&
2203 BranchCode == X86::COND_P))
2204 BranchCode = X86::COND_NE_OR_P;
2208 // Update the MachineOperand.
2209 Cond[0].setImm(BranchCode);
2215 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2216 MachineBasicBlock::iterator I = MBB.end();
2219 while (I != MBB.begin()) {
2221 if (I->isDebugValue())
2223 if (I->getOpcode() != X86::JMP_4 &&
2224 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2226 // Remove the branch.
2227 I->eraseFromParent();
2236 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2237 MachineBasicBlock *FBB,
2238 const SmallVectorImpl<MachineOperand> &Cond,
2239 DebugLoc DL) const {
2240 // Shouldn't be a fall through.
2241 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2242 assert((Cond.size() == 1 || Cond.size() == 0) &&
2243 "X86 branch conditions have one component!");
2246 // Unconditional branch?
2247 assert(!FBB && "Unconditional branch with multiple successors!");
2248 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2252 // Conditional branch.
2254 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2256 case X86::COND_NP_OR_E:
2257 // Synthesize NP_OR_E with two branches.
2258 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2260 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2263 case X86::COND_NE_OR_P:
2264 // Synthesize NE_OR_P with two branches.
2265 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2267 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2271 unsigned Opc = GetCondBranchFromCond(CC);
2272 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2277 // Two-way Conditional branch. Insert the second branch.
2278 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2284 /// isHReg - Test if the given register is a physical h register.
2285 static bool isHReg(unsigned Reg) {
2286 return X86::GR8_ABCD_HRegClass.contains(Reg);
2289 // Try and copy between VR128/VR64 and GR64 registers.
2290 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2292 // SrcReg(VR128) -> DestReg(GR64)
2293 // SrcReg(VR64) -> DestReg(GR64)
2294 // SrcReg(GR64) -> DestReg(VR128)
2295 // SrcReg(GR64) -> DestReg(VR64)
2297 if (X86::GR64RegClass.contains(DestReg)) {
2298 if (X86::VR128RegClass.contains(SrcReg)) {
2299 // Copy from a VR128 register to a GR64 register.
2300 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2301 } else if (X86::VR64RegClass.contains(SrcReg)) {
2302 // Copy from a VR64 register to a GR64 register.
2303 return X86::MOVSDto64rr;
2305 } else if (X86::GR64RegClass.contains(SrcReg)) {
2306 // Copy from a GR64 register to a VR128 register.
2307 if (X86::VR128RegClass.contains(DestReg))
2308 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2309 // Copy from a GR64 register to a VR64 register.
2310 else if (X86::VR64RegClass.contains(DestReg))
2311 return X86::MOV64toSDrr;
2314 // SrcReg(FR32) -> DestReg(GR32)
2315 // SrcReg(GR32) -> DestReg(FR32)
2317 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2318 // Copy from a FR32 register to a GR32 register.
2319 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2321 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2322 // Copy from a GR32 register to a FR32 register.
2323 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2328 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2329 MachineBasicBlock::iterator MI, DebugLoc DL,
2330 unsigned DestReg, unsigned SrcReg,
2331 bool KillSrc) const {
2332 // First deal with the normal symmetric copies.
2333 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2335 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2337 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2339 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2341 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2342 // Copying to or from a physical H register on x86-64 requires a NOREX
2343 // move. Otherwise use a normal move.
2344 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2345 TM.getSubtarget<X86Subtarget>().is64Bit()) {
2346 Opc = X86::MOV8rr_NOREX;
2347 // Both operands must be encodable without an REX prefix.
2348 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2349 "8-bit H register can not be copied outside GR8_NOREX");
2352 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2353 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2354 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2355 Opc = X86::VMOVAPSYrr;
2356 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2357 Opc = X86::MMX_MOVQ64rr;
2359 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2362 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2363 .addReg(SrcReg, getKillRegState(KillSrc));
2367 // Moving EFLAGS to / from another register requires a push and a pop.
2368 if (SrcReg == X86::EFLAGS) {
2369 if (X86::GR64RegClass.contains(DestReg)) {
2370 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2371 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2373 } else if (X86::GR32RegClass.contains(DestReg)) {
2374 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2375 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2379 if (DestReg == X86::EFLAGS) {
2380 if (X86::GR64RegClass.contains(SrcReg)) {
2381 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2382 .addReg(SrcReg, getKillRegState(KillSrc));
2383 BuildMI(MBB, MI, DL, get(X86::POPF64));
2385 } else if (X86::GR32RegClass.contains(SrcReg)) {
2386 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2387 .addReg(SrcReg, getKillRegState(KillSrc));
2388 BuildMI(MBB, MI, DL, get(X86::POPF32));
2393 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2394 << " to " << RI.getName(DestReg) << '\n');
2395 llvm_unreachable("Cannot emit physreg copy instruction");
2398 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2399 const TargetRegisterClass *RC,
2400 bool isStackAligned,
2401 const TargetMachine &TM,
2403 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2404 switch (RC->getSize()) {
2406 llvm_unreachable("Unknown spill size");
2408 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2409 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2410 // Copying to or from a physical H register on x86-64 requires a NOREX
2411 // move. Otherwise use a normal move.
2412 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2413 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2414 return load ? X86::MOV8rm : X86::MOV8mr;
2416 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2417 return load ? X86::MOV16rm : X86::MOV16mr;
2419 if (X86::GR32RegClass.hasSubClassEq(RC))
2420 return load ? X86::MOV32rm : X86::MOV32mr;
2421 if (X86::FR32RegClass.hasSubClassEq(RC))
2423 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2424 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2425 if (X86::RFP32RegClass.hasSubClassEq(RC))
2426 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2427 llvm_unreachable("Unknown 4-byte regclass");
2429 if (X86::GR64RegClass.hasSubClassEq(RC))
2430 return load ? X86::MOV64rm : X86::MOV64mr;
2431 if (X86::FR64RegClass.hasSubClassEq(RC))
2433 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2434 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2435 if (X86::VR64RegClass.hasSubClassEq(RC))
2436 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2437 if (X86::RFP64RegClass.hasSubClassEq(RC))
2438 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2439 llvm_unreachable("Unknown 8-byte regclass");
2441 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2442 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2444 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2445 // If stack is realigned we can use aligned stores.
2448 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2449 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2452 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2453 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2456 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2457 // If stack is realigned we can use aligned stores.
2459 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2461 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2465 static unsigned getStoreRegOpcode(unsigned SrcReg,
2466 const TargetRegisterClass *RC,
2467 bool isStackAligned,
2468 TargetMachine &TM) {
2469 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2473 static unsigned getLoadRegOpcode(unsigned DestReg,
2474 const TargetRegisterClass *RC,
2475 bool isStackAligned,
2476 const TargetMachine &TM) {
2477 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2480 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2481 MachineBasicBlock::iterator MI,
2482 unsigned SrcReg, bool isKill, int FrameIdx,
2483 const TargetRegisterClass *RC,
2484 const TargetRegisterInfo *TRI) const {
2485 const MachineFunction &MF = *MBB.getParent();
2486 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2487 "Stack slot too small for store");
2488 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2489 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2490 RI.canRealignStack(MF);
2491 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2492 DebugLoc DL = MBB.findDebugLoc(MI);
2493 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2494 .addReg(SrcReg, getKillRegState(isKill));
2497 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2499 SmallVectorImpl<MachineOperand> &Addr,
2500 const TargetRegisterClass *RC,
2501 MachineInstr::mmo_iterator MMOBegin,
2502 MachineInstr::mmo_iterator MMOEnd,
2503 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2504 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2505 bool isAligned = MMOBegin != MMOEnd &&
2506 (*MMOBegin)->getAlignment() >= Alignment;
2507 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2509 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2510 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2511 MIB.addOperand(Addr[i]);
2512 MIB.addReg(SrcReg, getKillRegState(isKill));
2513 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2514 NewMIs.push_back(MIB);
2518 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2519 MachineBasicBlock::iterator MI,
2520 unsigned DestReg, int FrameIdx,
2521 const TargetRegisterClass *RC,
2522 const TargetRegisterInfo *TRI) const {
2523 const MachineFunction &MF = *MBB.getParent();
2524 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2525 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2526 RI.canRealignStack(MF);
2527 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2528 DebugLoc DL = MBB.findDebugLoc(MI);
2529 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2532 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2533 SmallVectorImpl<MachineOperand> &Addr,
2534 const TargetRegisterClass *RC,
2535 MachineInstr::mmo_iterator MMOBegin,
2536 MachineInstr::mmo_iterator MMOEnd,
2537 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2538 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2539 bool isAligned = MMOBegin != MMOEnd &&
2540 (*MMOBegin)->getAlignment() >= Alignment;
2541 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2543 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2544 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2545 MIB.addOperand(Addr[i]);
2546 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2547 NewMIs.push_back(MIB);
2550 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2551 /// instruction with two undef reads of the register being defined. This is
2552 /// used for mapping:
2555 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2557 static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2558 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2559 unsigned Reg = MI->getOperand(0).getReg();
2562 // MachineInstr::addOperand() will insert explicit operands before any
2563 // implicit operands.
2564 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2565 .addReg(Reg, RegState::Undef);
2566 // But we don't trust that.
2567 assert(MI->getOperand(1).getReg() == Reg &&
2568 MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2572 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2573 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2574 switch (MI->getOpcode()) {
2578 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
2579 case X86::TEST8ri_NOREX:
2580 MI->setDesc(get(X86::TEST8ri));
2587 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2588 int FrameIx, uint64_t Offset,
2589 const MDNode *MDPtr,
2590 DebugLoc DL) const {
2592 AM.BaseType = X86AddressMode::FrameIndexBase;
2593 AM.Base.FrameIndex = FrameIx;
2594 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2595 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2599 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2600 const SmallVectorImpl<MachineOperand> &MOs,
2602 const TargetInstrInfo &TII) {
2603 // Create the base instruction with the memory operand as the first part.
2604 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2605 MI->getDebugLoc(), true);
2606 MachineInstrBuilder MIB(NewMI);
2607 unsigned NumAddrOps = MOs.size();
2608 for (unsigned i = 0; i != NumAddrOps; ++i)
2609 MIB.addOperand(MOs[i]);
2610 if (NumAddrOps < 4) // FrameIndex only
2613 // Loop over the rest of the ri operands, converting them over.
2614 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2615 for (unsigned i = 0; i != NumOps; ++i) {
2616 MachineOperand &MO = MI->getOperand(i+2);
2619 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2620 MachineOperand &MO = MI->getOperand(i);
2626 static MachineInstr *FuseInst(MachineFunction &MF,
2627 unsigned Opcode, unsigned OpNo,
2628 const SmallVectorImpl<MachineOperand> &MOs,
2629 MachineInstr *MI, const TargetInstrInfo &TII) {
2630 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2631 MI->getDebugLoc(), true);
2632 MachineInstrBuilder MIB(NewMI);
2634 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2635 MachineOperand &MO = MI->getOperand(i);
2637 assert(MO.isReg() && "Expected to fold into reg operand!");
2638 unsigned NumAddrOps = MOs.size();
2639 for (unsigned i = 0; i != NumAddrOps; ++i)
2640 MIB.addOperand(MOs[i]);
2641 if (NumAddrOps < 4) // FrameIndex only
2650 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2651 const SmallVectorImpl<MachineOperand> &MOs,
2653 MachineFunction &MF = *MI->getParent()->getParent();
2654 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2656 unsigned NumAddrOps = MOs.size();
2657 for (unsigned i = 0; i != NumAddrOps; ++i)
2658 MIB.addOperand(MOs[i]);
2659 if (NumAddrOps < 4) // FrameIndex only
2661 return MIB.addImm(0);
2665 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2666 MachineInstr *MI, unsigned i,
2667 const SmallVectorImpl<MachineOperand> &MOs,
2668 unsigned Size, unsigned Align) const {
2669 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2670 bool isTwoAddrFold = false;
2671 unsigned NumOps = MI->getDesc().getNumOperands();
2672 bool isTwoAddr = NumOps > 1 &&
2673 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2675 // FIXME: AsmPrinter doesn't know how to handle
2676 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2677 if (MI->getOpcode() == X86::ADD32ri &&
2678 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2681 MachineInstr *NewMI = NULL;
2682 // Folding a memory location into the two-address part of a two-address
2683 // instruction is different than folding it other places. It requires
2684 // replacing the *two* registers with the memory location.
2685 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2686 MI->getOperand(0).isReg() &&
2687 MI->getOperand(1).isReg() &&
2688 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2689 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2690 isTwoAddrFold = true;
2691 } else if (i == 0) { // If operand 0
2692 if (MI->getOpcode() == X86::MOV64r0)
2693 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2694 else if (MI->getOpcode() == X86::MOV32r0)
2695 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2696 else if (MI->getOpcode() == X86::MOV16r0)
2697 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2698 else if (MI->getOpcode() == X86::MOV8r0)
2699 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2703 OpcodeTablePtr = &RegOp2MemOpTable0;
2704 } else if (i == 1) {
2705 OpcodeTablePtr = &RegOp2MemOpTable1;
2706 } else if (i == 2) {
2707 OpcodeTablePtr = &RegOp2MemOpTable2;
2710 // If table selected...
2711 if (OpcodeTablePtr) {
2712 // Find the Opcode to fuse
2713 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2714 OpcodeTablePtr->find(MI->getOpcode());
2715 if (I != OpcodeTablePtr->end()) {
2716 unsigned Opcode = I->second.first;
2717 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2718 if (Align < MinAlign)
2720 bool NarrowToMOV32rm = false;
2722 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2723 if (Size < RCSize) {
2724 // Check if it's safe to fold the load. If the size of the object is
2725 // narrower than the load width, then it's not.
2726 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2728 // If this is a 64-bit load, but the spill slot is 32, then we can do
2729 // a 32-bit load which is implicitly zero-extended. This likely is due
2730 // to liveintervalanalysis remat'ing a load from stack slot.
2731 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2733 Opcode = X86::MOV32rm;
2734 NarrowToMOV32rm = true;
2739 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2741 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2743 if (NarrowToMOV32rm) {
2744 // If this is the special case where we use a MOV32rm to load a 32-bit
2745 // value and zero-extend the top bits. Change the destination register
2747 unsigned DstReg = NewMI->getOperand(0).getReg();
2748 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2749 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2752 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2759 if (PrintFailedFusing && !MI->isCopy())
2760 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2764 /// hasPartialRegUpdate - Return true for all instructions that only update
2765 /// the first 32 or 64-bits of the destination register and leave the rest
2766 /// unmodified. This can be used to avoid folding loads if the instructions
2767 /// only update part of the destination register, and the non-updated part is
2768 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
2769 /// instructions breaks the partial register dependency and it can improve
2770 /// performance. e.g.:
2772 /// movss (%rdi), %xmm0
2773 /// cvtss2sd %xmm0, %xmm0
2776 /// cvtss2sd (%rdi), %xmm0
2778 /// FIXME: This should be turned into a TSFlags.
2780 static bool hasPartialRegUpdate(unsigned Opcode) {
2782 case X86::CVTSI2SSrr:
2783 case X86::CVTSI2SS64rr:
2784 case X86::CVTSI2SDrr:
2785 case X86::CVTSI2SD64rr:
2786 case X86::CVTSD2SSrr:
2787 case X86::Int_CVTSD2SSrr:
2788 case X86::CVTSS2SDrr:
2789 case X86::Int_CVTSS2SDrr:
2791 case X86::RCPSSr_Int:
2793 case X86::ROUNDSDr_Int:
2795 case X86::ROUNDSSr_Int:
2797 case X86::RSQRTSSr_Int:
2799 case X86::SQRTSSr_Int:
2800 // AVX encoded versions
2801 case X86::VCVTSD2SSrr:
2802 case X86::Int_VCVTSD2SSrr:
2803 case X86::VCVTSS2SDrr:
2804 case X86::Int_VCVTSS2SDrr:
2806 case X86::VROUNDSDr:
2807 case X86::VROUNDSDr_Int:
2808 case X86::VROUNDSSr:
2809 case X86::VROUNDSSr_Int:
2810 case X86::VRSQRTSSr:
2818 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
2819 /// instructions we would like before a partial register update.
2820 unsigned X86InstrInfo::
2821 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
2822 const TargetRegisterInfo *TRI) const {
2823 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
2826 // If MI is marked as reading Reg, the partial register update is wanted.
2827 const MachineOperand &MO = MI->getOperand(0);
2828 unsigned Reg = MO.getReg();
2829 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2830 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
2833 if (MI->readsRegister(Reg, TRI))
2837 // If any of the preceding 16 instructions are reading Reg, insert a
2838 // dependency breaking instruction. The magic number is based on a few
2839 // Nehalem experiments.
2844 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
2845 const TargetRegisterInfo *TRI) const {
2846 unsigned Reg = MI->getOperand(OpNum).getReg();
2847 if (X86::VR128RegClass.contains(Reg)) {
2848 // These instructions are all floating point domain, so xorps is the best
2850 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2851 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
2852 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
2853 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
2854 } else if (X86::VR256RegClass.contains(Reg)) {
2855 // Use vxorps to clear the full ymm register.
2856 // It wants to read and write the xmm sub-register.
2857 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
2858 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
2859 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
2860 .addReg(Reg, RegState::ImplicitDefine);
2863 MI->addRegisterKilled(Reg, TRI, true);
2866 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2868 const SmallVectorImpl<unsigned> &Ops,
2869 int FrameIndex) const {
2870 // Check switch flag
2871 if (NoFusing) return NULL;
2873 // Unless optimizing for size, don't fold to avoid partial
2874 // register update stalls
2875 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2876 hasPartialRegUpdate(MI->getOpcode()))
2879 const MachineFrameInfo *MFI = MF.getFrameInfo();
2880 unsigned Size = MFI->getObjectSize(FrameIndex);
2881 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2882 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2883 unsigned NewOpc = 0;
2884 unsigned RCSize = 0;
2885 switch (MI->getOpcode()) {
2886 default: return NULL;
2887 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2888 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2889 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2890 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2892 // Check if it's safe to fold the load. If the size of the object is
2893 // narrower than the load width, then it's not.
2896 // Change to CMPXXri r, 0 first.
2897 MI->setDesc(get(NewOpc));
2898 MI->getOperand(1).ChangeToImmediate(0);
2899 } else if (Ops.size() != 1)
2902 SmallVector<MachineOperand,4> MOs;
2903 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2904 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2907 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2909 const SmallVectorImpl<unsigned> &Ops,
2910 MachineInstr *LoadMI) const {
2911 // Check switch flag
2912 if (NoFusing) return NULL;
2914 // Unless optimizing for size, don't fold to avoid partial
2915 // register update stalls
2916 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2917 hasPartialRegUpdate(MI->getOpcode()))
2920 // Determine the alignment of the load.
2921 unsigned Alignment = 0;
2922 if (LoadMI->hasOneMemOperand())
2923 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2925 switch (LoadMI->getOpcode()) {
2926 case X86::AVX_SET0PSY:
2927 case X86::AVX_SET0PDY:
2928 case X86::AVX2_SETALLONES:
2929 case X86::AVX2_SET0:
2933 case X86::V_SETALLONES:
2934 case X86::AVX_SETALLONES:
2946 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2947 unsigned NewOpc = 0;
2948 switch (MI->getOpcode()) {
2949 default: return NULL;
2950 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2951 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2952 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2953 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2955 // Change to CMPXXri r, 0 first.
2956 MI->setDesc(get(NewOpc));
2957 MI->getOperand(1).ChangeToImmediate(0);
2958 } else if (Ops.size() != 1)
2961 // Make sure the subregisters match.
2962 // Otherwise we risk changing the size of the load.
2963 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2966 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2967 switch (LoadMI->getOpcode()) {
2969 case X86::V_SETALLONES:
2970 case X86::AVX_SET0PSY:
2971 case X86::AVX_SET0PDY:
2972 case X86::AVX_SETALLONES:
2973 case X86::AVX2_SETALLONES:
2974 case X86::AVX2_SET0:
2976 case X86::FsFLD0SS: {
2977 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2978 // Create a constant-pool entry and operands to load from it.
2980 // Medium and large mode can't fold loads this way.
2981 if (TM.getCodeModel() != CodeModel::Small &&
2982 TM.getCodeModel() != CodeModel::Kernel)
2985 // x86-32 PIC requires a PIC base register for constant pools.
2986 unsigned PICBase = 0;
2987 if (TM.getRelocationModel() == Reloc::PIC_) {
2988 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2991 // FIXME: PICBase = getGlobalBaseReg(&MF);
2992 // This doesn't work for several reasons.
2993 // 1. GlobalBaseReg may have been spilled.
2994 // 2. It may not be live at MI.
2998 // Create a constant-pool entry.
2999 MachineConstantPool &MCP = *MF.getConstantPool();
3001 unsigned Opc = LoadMI->getOpcode();
3002 if (Opc == X86::FsFLD0SS)
3003 Ty = Type::getFloatTy(MF.getFunction()->getContext());
3004 else if (Opc == X86::FsFLD0SD)
3005 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
3006 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
3007 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
3008 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0)
3009 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
3011 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
3013 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
3014 Opc == X86::AVX2_SETALLONES);
3015 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3016 Constant::getNullValue(Ty);
3017 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
3019 // Create operands to load from the constant pool entry.
3020 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3021 MOs.push_back(MachineOperand::CreateImm(1));
3022 MOs.push_back(MachineOperand::CreateReg(0, false));
3023 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
3024 MOs.push_back(MachineOperand::CreateReg(0, false));
3028 // Folding a normal load. Just copy the load's address operands.
3029 unsigned NumOps = LoadMI->getDesc().getNumOperands();
3030 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
3031 MOs.push_back(LoadMI->getOperand(i));
3035 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
3039 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3040 const SmallVectorImpl<unsigned> &Ops) const {
3041 // Check switch flag
3042 if (NoFusing) return 0;
3044 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3045 switch (MI->getOpcode()) {
3046 default: return false;
3053 // FIXME: AsmPrinter doesn't know how to handle
3054 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3055 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3061 if (Ops.size() != 1)
3064 unsigned OpNum = Ops[0];
3065 unsigned Opc = MI->getOpcode();
3066 unsigned NumOps = MI->getDesc().getNumOperands();
3067 bool isTwoAddr = NumOps > 1 &&
3068 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3070 // Folding a memory location into the two-address part of a two-address
3071 // instruction is different than folding it other places. It requires
3072 // replacing the *two* registers with the memory location.
3073 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3074 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3075 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3076 } else if (OpNum == 0) { // If operand 0
3081 case X86::MOV64r0: return true;
3084 OpcodeTablePtr = &RegOp2MemOpTable0;
3085 } else if (OpNum == 1) {
3086 OpcodeTablePtr = &RegOp2MemOpTable1;
3087 } else if (OpNum == 2) {
3088 OpcodeTablePtr = &RegOp2MemOpTable2;
3091 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3093 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
3096 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3097 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
3098 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3099 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3100 MemOp2RegOpTable.find(MI->getOpcode());
3101 if (I == MemOp2RegOpTable.end())
3103 unsigned Opc = I->second.first;
3104 unsigned Index = I->second.second & TB_INDEX_MASK;
3105 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3106 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3107 if (UnfoldLoad && !FoldedLoad)
3109 UnfoldLoad &= FoldedLoad;
3110 if (UnfoldStore && !FoldedStore)
3112 UnfoldStore &= FoldedStore;
3114 const MCInstrDesc &MCID = get(Opc);
3115 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3116 if (!MI->hasOneMemOperand() &&
3117 RC == &X86::VR128RegClass &&
3118 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3119 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3120 // conservatively assume the address is unaligned. That's bad for
3123 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
3124 SmallVector<MachineOperand,2> BeforeOps;
3125 SmallVector<MachineOperand,2> AfterOps;
3126 SmallVector<MachineOperand,4> ImpOps;
3127 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3128 MachineOperand &Op = MI->getOperand(i);
3129 if (i >= Index && i < Index + X86::AddrNumOperands)
3130 AddrOps.push_back(Op);
3131 else if (Op.isReg() && Op.isImplicit())
3132 ImpOps.push_back(Op);
3134 BeforeOps.push_back(Op);
3136 AfterOps.push_back(Op);
3139 // Emit the load instruction.
3141 std::pair<MachineInstr::mmo_iterator,
3142 MachineInstr::mmo_iterator> MMOs =
3143 MF.extractLoadMemRefs(MI->memoperands_begin(),
3144 MI->memoperands_end());
3145 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3147 // Address operands cannot be marked isKill.
3148 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
3149 MachineOperand &MO = NewMIs[0]->getOperand(i);
3151 MO.setIsKill(false);
3156 // Emit the data processing instruction.
3157 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
3158 MachineInstrBuilder MIB(DataMI);
3161 MIB.addReg(Reg, RegState::Define);
3162 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
3163 MIB.addOperand(BeforeOps[i]);
3166 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
3167 MIB.addOperand(AfterOps[i]);
3168 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3169 MachineOperand &MO = ImpOps[i];
3170 MIB.addReg(MO.getReg(),
3171 getDefRegState(MO.isDef()) |
3172 RegState::Implicit |
3173 getKillRegState(MO.isKill()) |
3174 getDeadRegState(MO.isDead()) |
3175 getUndefRegState(MO.isUndef()));
3177 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3178 unsigned NewOpc = 0;
3179 switch (DataMI->getOpcode()) {
3181 case X86::CMP64ri32:
3188 MachineOperand &MO0 = DataMI->getOperand(0);
3189 MachineOperand &MO1 = DataMI->getOperand(1);
3190 if (MO1.getImm() == 0) {
3191 switch (DataMI->getOpcode()) {
3194 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
3196 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
3198 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
3199 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
3201 DataMI->setDesc(get(NewOpc));
3202 MO1.ChangeToRegister(MO0.getReg(), false);
3206 NewMIs.push_back(DataMI);
3208 // Emit the store instruction.
3210 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
3211 std::pair<MachineInstr::mmo_iterator,
3212 MachineInstr::mmo_iterator> MMOs =
3213 MF.extractStoreMemRefs(MI->memoperands_begin(),
3214 MI->memoperands_end());
3215 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3222 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3223 SmallVectorImpl<SDNode*> &NewNodes) const {
3224 if (!N->isMachineOpcode())
3227 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3228 MemOp2RegOpTable.find(N->getMachineOpcode());
3229 if (I == MemOp2RegOpTable.end())
3231 unsigned Opc = I->second.first;
3232 unsigned Index = I->second.second & TB_INDEX_MASK;
3233 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3234 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3235 const MCInstrDesc &MCID = get(Opc);
3236 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3237 unsigned NumDefs = MCID.NumDefs;
3238 std::vector<SDValue> AddrOps;
3239 std::vector<SDValue> BeforeOps;
3240 std::vector<SDValue> AfterOps;
3241 DebugLoc dl = N->getDebugLoc();
3242 unsigned NumOps = N->getNumOperands();
3243 for (unsigned i = 0; i != NumOps-1; ++i) {
3244 SDValue Op = N->getOperand(i);
3245 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3246 AddrOps.push_back(Op);
3247 else if (i < Index-NumDefs)
3248 BeforeOps.push_back(Op);
3249 else if (i > Index-NumDefs)
3250 AfterOps.push_back(Op);
3252 SDValue Chain = N->getOperand(NumOps-1);
3253 AddrOps.push_back(Chain);
3255 // Emit the load instruction.
3257 MachineFunction &MF = DAG.getMachineFunction();
3259 EVT VT = *RC->vt_begin();
3260 std::pair<MachineInstr::mmo_iterator,
3261 MachineInstr::mmo_iterator> MMOs =
3262 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3263 cast<MachineSDNode>(N)->memoperands_end());
3264 if (!(*MMOs.first) &&
3265 RC == &X86::VR128RegClass &&
3266 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3267 // Do not introduce a slow unaligned load.
3269 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3270 bool isAligned = (*MMOs.first) &&
3271 (*MMOs.first)->getAlignment() >= Alignment;
3272 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3273 VT, MVT::Other, &AddrOps[0], AddrOps.size());
3274 NewNodes.push_back(Load);
3276 // Preserve memory reference information.
3277 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3280 // Emit the data processing instruction.
3281 std::vector<EVT> VTs;
3282 const TargetRegisterClass *DstRC = 0;
3283 if (MCID.getNumDefs() > 0) {
3284 DstRC = getRegClass(MCID, 0, &RI);
3285 VTs.push_back(*DstRC->vt_begin());
3287 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3288 EVT VT = N->getValueType(i);
3289 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3293 BeforeOps.push_back(SDValue(Load, 0));
3294 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3295 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3297 NewNodes.push_back(NewNode);
3299 // Emit the store instruction.
3302 AddrOps.push_back(SDValue(NewNode, 0));
3303 AddrOps.push_back(Chain);
3304 std::pair<MachineInstr::mmo_iterator,
3305 MachineInstr::mmo_iterator> MMOs =
3306 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3307 cast<MachineSDNode>(N)->memoperands_end());
3308 if (!(*MMOs.first) &&
3309 RC == &X86::VR128RegClass &&
3310 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3311 // Do not introduce a slow unaligned store.
3313 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3314 bool isAligned = (*MMOs.first) &&
3315 (*MMOs.first)->getAlignment() >= Alignment;
3316 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3319 &AddrOps[0], AddrOps.size());
3320 NewNodes.push_back(Store);
3322 // Preserve memory reference information.
3323 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3329 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3330 bool UnfoldLoad, bool UnfoldStore,
3331 unsigned *LoadRegIndex) const {
3332 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3333 MemOp2RegOpTable.find(Opc);
3334 if (I == MemOp2RegOpTable.end())
3336 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3337 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3338 if (UnfoldLoad && !FoldedLoad)
3340 if (UnfoldStore && !FoldedStore)
3343 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3344 return I->second.first;
3348 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3349 int64_t &Offset1, int64_t &Offset2) const {
3350 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3352 unsigned Opc1 = Load1->getMachineOpcode();
3353 unsigned Opc2 = Load2->getMachineOpcode();
3355 default: return false;
3365 case X86::MMX_MOVD64rm:
3366 case X86::MMX_MOVQ64rm:
3367 case X86::FsMOVAPSrm:
3368 case X86::FsMOVAPDrm:
3374 // AVX load instructions
3377 case X86::FsVMOVAPSrm:
3378 case X86::FsVMOVAPDrm:
3379 case X86::VMOVAPSrm:
3380 case X86::VMOVUPSrm:
3381 case X86::VMOVAPDrm:
3382 case X86::VMOVDQArm:
3383 case X86::VMOVDQUrm:
3384 case X86::VMOVAPSYrm:
3385 case X86::VMOVUPSYrm:
3386 case X86::VMOVAPDYrm:
3387 case X86::VMOVDQAYrm:
3388 case X86::VMOVDQUYrm:
3392 default: return false;
3402 case X86::MMX_MOVD64rm:
3403 case X86::MMX_MOVQ64rm:
3404 case X86::FsMOVAPSrm:
3405 case X86::FsMOVAPDrm:
3411 // AVX load instructions
3414 case X86::FsVMOVAPSrm:
3415 case X86::FsVMOVAPDrm:
3416 case X86::VMOVAPSrm:
3417 case X86::VMOVUPSrm:
3418 case X86::VMOVAPDrm:
3419 case X86::VMOVDQArm:
3420 case X86::VMOVDQUrm:
3421 case X86::VMOVAPSYrm:
3422 case X86::VMOVUPSYrm:
3423 case X86::VMOVAPDYrm:
3424 case X86::VMOVDQAYrm:
3425 case X86::VMOVDQUYrm:
3429 // Check if chain operands and base addresses match.
3430 if (Load1->getOperand(0) != Load2->getOperand(0) ||
3431 Load1->getOperand(5) != Load2->getOperand(5))
3433 // Segment operands should match as well.
3434 if (Load1->getOperand(4) != Load2->getOperand(4))
3436 // Scale should be 1, Index should be Reg0.
3437 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3438 Load1->getOperand(2) == Load2->getOperand(2)) {
3439 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3442 // Now let's examine the displacements.
3443 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3444 isa<ConstantSDNode>(Load2->getOperand(3))) {
3445 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3446 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3453 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3454 int64_t Offset1, int64_t Offset2,
3455 unsigned NumLoads) const {
3456 assert(Offset2 > Offset1);
3457 if ((Offset2 - Offset1) / 8 > 64)
3460 unsigned Opc1 = Load1->getMachineOpcode();
3461 unsigned Opc2 = Load2->getMachineOpcode();
3463 return false; // FIXME: overly conservative?
3470 case X86::MMX_MOVD64rm:
3471 case X86::MMX_MOVQ64rm:
3475 EVT VT = Load1->getValueType(0);
3476 switch (VT.getSimpleVT().SimpleTy) {
3478 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3479 // have 16 of them to play with.
3480 if (TM.getSubtargetImpl()->is64Bit()) {
3483 } else if (NumLoads) {
3503 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3504 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3505 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3506 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3508 Cond[0].setImm(GetOppositeBranchCondition(CC));
3513 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3514 // FIXME: Return false for x87 stack register classes for now. We can't
3515 // allow any loads of these registers before FpGet_ST0_80.
3516 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3517 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3520 /// getGlobalBaseReg - Return a virtual register initialized with the
3521 /// the global base register value. Output instructions required to
3522 /// initialize the register in the function entry block, if necessary.
3524 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3526 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3527 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3528 "X86-64 PIC uses RIP relative addressing");
3530 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3531 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3532 if (GlobalBaseReg != 0)
3533 return GlobalBaseReg;
3535 // Create the register. The code to initialize it is inserted
3536 // later, by the CGBR pass (below).
3537 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3538 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3539 X86FI->setGlobalBaseReg(GlobalBaseReg);
3540 return GlobalBaseReg;
3543 // These are the replaceable SSE instructions. Some of these have Int variants
3544 // that we don't include here. We don't want to replace instructions selected
3546 static const unsigned ReplaceableInstrs[][3] = {
3547 //PackedSingle PackedDouble PackedInt
3548 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3549 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3550 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3551 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3552 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3553 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3554 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3555 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3556 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3557 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3558 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3559 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3560 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3561 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3562 // AVX 128-bit support
3563 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3564 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3565 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3566 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3567 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3568 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3569 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3570 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3571 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3572 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3573 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3574 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3575 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3576 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3577 // AVX 256-bit support
3578 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
3579 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
3580 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
3581 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
3582 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
3583 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
3586 static const unsigned ReplaceableInstrsAVX2[][3] = {
3587 //PackedSingle PackedDouble PackedInt
3588 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
3589 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
3590 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
3591 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
3592 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
3593 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
3594 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
3595 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
3596 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3597 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3598 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
3599 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
3600 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
3601 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }
3604 // FIXME: Some shuffle and unpack instructions have equivalents in different
3605 // domains, but they require a bit more work than just switching opcodes.
3607 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3608 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3609 if (ReplaceableInstrs[i][domain-1] == opcode)
3610 return ReplaceableInstrs[i];
3614 static const unsigned *lookupAVX2(unsigned opcode, unsigned domain) {
3615 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
3616 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
3617 return ReplaceableInstrsAVX2[i];
3621 std::pair<uint16_t, uint16_t>
3622 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3623 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3624 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
3625 uint16_t validDomains = 0;
3626 if (domain && lookup(MI->getOpcode(), domain))
3628 else if (domain && lookupAVX2(MI->getOpcode(), domain))
3629 validDomains = hasAVX2 ? 0xe : 0x6;
3630 return std::make_pair(domain, validDomains);
3633 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3634 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3635 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3636 assert(dom && "Not an SSE instruction");
3637 const unsigned *table = lookup(MI->getOpcode(), dom);
3638 if (!table) { // try the other table
3639 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
3640 "256-bit vector operations only available in AVX2");
3641 table = lookupAVX2(MI->getOpcode(), dom);
3643 assert(table && "Cannot change domain");
3644 MI->setDesc(get(table[Domain-1]));
3647 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3648 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3649 NopInst.setOpcode(X86::NOOP);
3652 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3654 default: return false;
3656 case X86::DIVSDrm_Int:
3658 case X86::DIVSDrr_Int:
3660 case X86::DIVSSrm_Int:
3662 case X86::DIVSSrr_Int:
3664 case X86::SQRTPDm_Int:
3666 case X86::SQRTPDr_Int:
3668 case X86::SQRTPSm_Int:
3670 case X86::SQRTPSr_Int:
3672 case X86::SQRTSDm_Int:
3674 case X86::SQRTSDr_Int:
3676 case X86::SQRTSSm_Int:
3678 case X86::SQRTSSr_Int:
3679 // AVX instructions with high latency
3681 case X86::VDIVSDrm_Int:
3683 case X86::VDIVSDrr_Int:
3685 case X86::VDIVSSrm_Int:
3687 case X86::VDIVSSrr_Int:
3689 case X86::VSQRTPDm_Int:
3691 case X86::VSQRTPDr_Int:
3693 case X86::VSQRTPSm_Int:
3695 case X86::VSQRTPSr_Int:
3697 case X86::VSQRTSDm_Int:
3700 case X86::VSQRTSSm_Int:
3707 hasHighOperandLatency(const InstrItineraryData *ItinData,
3708 const MachineRegisterInfo *MRI,
3709 const MachineInstr *DefMI, unsigned DefIdx,
3710 const MachineInstr *UseMI, unsigned UseIdx) const {
3711 return isHighLatencyDef(DefMI->getOpcode());
3715 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3716 /// global base register for x86-32.
3717 struct CGBR : public MachineFunctionPass {
3719 CGBR() : MachineFunctionPass(ID) {}
3721 virtual bool runOnMachineFunction(MachineFunction &MF) {
3722 const X86TargetMachine *TM =
3723 static_cast<const X86TargetMachine *>(&MF.getTarget());
3725 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3726 "X86-64 PIC uses RIP relative addressing");
3728 // Only emit a global base reg in PIC mode.
3729 if (TM->getRelocationModel() != Reloc::PIC_)
3732 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3733 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3735 // If we didn't need a GlobalBaseReg, don't insert code.
3736 if (GlobalBaseReg == 0)
3739 // Insert the set of GlobalBaseReg into the first MBB of the function
3740 MachineBasicBlock &FirstMBB = MF.front();
3741 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3742 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3743 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3744 const X86InstrInfo *TII = TM->getInstrInfo();
3747 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3748 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3752 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3753 // only used in JIT code emission as displacement to pc.
3754 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3756 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3757 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3758 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3759 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3760 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3761 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3762 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3768 virtual const char *getPassName() const {
3769 return "X86 PIC Global Base Reg Initialization";
3772 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3773 AU.setPreservesCFG();
3774 MachineFunctionPass::getAnalysisUsage(AU);
3781 llvm::createGlobalBaseRegPass() { return new CGBR(); }