1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/Target/TargetOptions.h"
29 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
30 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
31 TM(tm), RI(tm, *this) {
34 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
36 unsigned& destReg) const {
37 MachineOpCode oc = MI.getOpcode();
38 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
39 oc == X86::MOV32rr || oc == X86::MOV64rr ||
40 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
41 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
42 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
43 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
44 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
45 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
46 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
47 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
48 assert(MI.getNumOperands() >= 2 &&
49 MI.getOperand(0).isRegister() &&
50 MI.getOperand(1).isRegister() &&
51 "invalid register-register move instruction");
52 sourceReg = MI.getOperand(1).getReg();
53 destReg = MI.getOperand(0).getReg();
59 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
60 int &FrameIndex) const {
61 switch (MI->getOpcode()) {
74 case X86::MMX_MOVD64rm:
75 case X86::MMX_MOVQ64rm:
76 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
77 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
78 MI->getOperand(2).getImm() == 1 &&
79 MI->getOperand(3).getReg() == 0 &&
80 MI->getOperand(4).getImm() == 0) {
81 FrameIndex = MI->getOperand(1).getIndex();
82 return MI->getOperand(0).getReg();
89 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
90 int &FrameIndex) const {
91 switch (MI->getOpcode()) {
104 case X86::MMX_MOVD64mr:
105 case X86::MMX_MOVQ64mr:
106 case X86::MMX_MOVNTQmr:
107 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
108 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
109 MI->getOperand(1).getImm() == 1 &&
110 MI->getOperand(2).getReg() == 0 &&
111 MI->getOperand(3).getImm() == 0) {
112 FrameIndex = MI->getOperand(0).getIndex();
113 return MI->getOperand(4).getReg();
121 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
122 switch (MI->getOpcode()) {
135 case X86::MMX_MOVD64rm:
136 case X86::MMX_MOVQ64rm:
137 // Loads from constant pools are trivially rematerializable.
138 if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
139 MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
140 MI->getOperand(1).getReg() == 0 &&
141 MI->getOperand(2).getImm() == 1 &&
142 MI->getOperand(3).getReg() == 0)
145 // If this is a load from a fixed argument slot, we know the value is
146 // invariant across the whole function, because we don't redefine argument
149 // FIXME: This is disabled due to a remat bug. rdar://5671644
150 MachineFunction *MF = MI->getParent()->getParent();
151 if (MI->getOperand(1).isFI() &&
152 MF->getFrameInfo()->isFixedObjectIndex(MI->getOperand(1).getIndex()))
158 // All other instructions marked M_REMATERIALIZABLE are always trivially
163 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
164 /// method is called to determine if the specific instance of this instruction
165 /// has side effects. This is useful in cases of instructions, like loads, which
166 /// generally always have side effects. A load from a constant pool doesn't have
167 /// side effects, though. So we need to differentiate it from the general case.
168 bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
169 switch (MI->getOpcode()) {
172 if (MI->getOperand(1).isRegister()) {
173 unsigned Reg = MI->getOperand(1).getReg();
174 const X86Subtarget &ST = TM.getSubtarget<X86Subtarget>();
176 // Loads from global addresses which aren't redefined in the function are
178 if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
179 MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
180 MI->getOperand(4).isGlobal() &&
181 ST.GVRequiresExtraLoad(MI->getOperand(4).getGlobal(), TM, false) &&
182 MI->getOperand(2).getImm() == 1 &&
183 MI->getOperand(3).getReg() == 0)
197 case X86::MMX_MOVD64rm:
198 case X86::MMX_MOVQ64rm:
199 // Loads from constant pools are trivially rematerializable.
200 if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
201 MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
202 MI->getOperand(1).getReg() == 0 &&
203 MI->getOperand(2).getImm() == 1 &&
204 MI->getOperand(3).getReg() == 0)
207 // If this is a load from a fixed argument slot, we know the value is
208 // invariant across the whole function, because we don't redefine argument
210 MachineFunction *MF = MI->getParent()->getParent();
211 if (MI->getOperand(1).isFI() &&
212 MF->getFrameInfo()->isFixedObjectIndex(MI->getOperand(1).getIndex()))
218 // All other instances of these instructions are presumed to have side
223 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
224 /// is not marked dead.
225 static bool hasLiveCondCodeDef(MachineInstr *MI) {
226 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
227 MachineOperand &MO = MI->getOperand(i);
228 if (MO.isRegister() && MO.isDef() &&
229 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
236 /// convertToThreeAddress - This method must be implemented by targets that
237 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
238 /// may be able to convert a two-address instruction into a true
239 /// three-address instruction on demand. This allows the X86 target (for
240 /// example) to convert ADD and SHL instructions into LEA instructions if they
241 /// would require register copies due to two-addressness.
243 /// This method returns a null pointer if the transformation cannot be
244 /// performed, otherwise it returns the new instruction.
247 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
248 MachineBasicBlock::iterator &MBBI,
249 LiveVariables &LV) const {
250 MachineInstr *MI = MBBI;
251 // All instructions input are two-addr instructions. Get the known operands.
252 unsigned Dest = MI->getOperand(0).getReg();
253 unsigned Src = MI->getOperand(1).getReg();
255 MachineInstr *NewMI = NULL;
256 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
257 // we have better subtarget support, enable the 16-bit LEA generation here.
258 bool DisableLEA16 = true;
260 unsigned MIOpc = MI->getOpcode();
262 case X86::SHUFPSrri: {
263 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
264 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
266 unsigned A = MI->getOperand(0).getReg();
267 unsigned B = MI->getOperand(1).getReg();
268 unsigned C = MI->getOperand(2).getReg();
269 unsigned M = MI->getOperand(3).getImm();
270 if (B != C) return 0;
271 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
275 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
276 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
277 // the flags produced by a shift yet, so this is safe.
278 unsigned Dest = MI->getOperand(0).getReg();
279 unsigned Src = MI->getOperand(1).getReg();
280 unsigned ShAmt = MI->getOperand(2).getImm();
281 if (ShAmt == 0 || ShAmt >= 4) return 0;
283 NewMI = BuildMI(get(X86::LEA64r), Dest)
284 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
288 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
289 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
290 // the flags produced by a shift yet, so this is safe.
291 unsigned Dest = MI->getOperand(0).getReg();
292 unsigned Src = MI->getOperand(1).getReg();
293 unsigned ShAmt = MI->getOperand(2).getImm();
294 if (ShAmt == 0 || ShAmt >= 4) return 0;
296 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
297 X86::LEA64_32r : X86::LEA32r;
298 NewMI = BuildMI(get(Opc), Dest)
299 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
303 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
304 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
305 // the flags produced by a shift yet, so this is safe.
306 unsigned Dest = MI->getOperand(0).getReg();
307 unsigned Src = MI->getOperand(1).getReg();
308 unsigned ShAmt = MI->getOperand(2).getImm();
309 if (ShAmt == 0 || ShAmt >= 4) return 0;
312 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
313 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
314 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
315 ? X86::LEA64_32r : X86::LEA32r;
316 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
317 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
320 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
321 Ins->copyKillDeadInfo(MI);
323 NewMI = BuildMI(get(Opc), leaOutReg)
324 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
327 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
328 Ext->copyKillDeadInfo(MI);
330 MFI->insert(MBBI, Ins); // Insert the insert_subreg
331 LV.instructionChanged(MI, NewMI); // Update live variables
332 LV.addVirtualRegisterKilled(leaInReg, NewMI);
333 MFI->insert(MBBI, NewMI); // Insert the new inst
334 LV.addVirtualRegisterKilled(leaOutReg, Ext);
335 MFI->insert(MBBI, Ext); // Insert the extract_subreg
338 NewMI = BuildMI(get(X86::LEA16r), Dest)
339 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
344 // The following opcodes also sets the condition code register(s). Only
345 // convert them to equivalent lea if the condition code register def's
347 if (hasLiveCondCodeDef(MI))
350 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
355 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
356 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
357 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
358 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
363 if (DisableLEA16) return 0;
364 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
365 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
369 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
370 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
371 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
372 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
377 if (DisableLEA16) return 0;
378 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
379 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
383 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
384 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
385 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
386 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
387 MI->getOperand(2).getReg());
391 if (DisableLEA16) return 0;
392 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
393 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
394 MI->getOperand(2).getReg());
398 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
399 if (MI->getOperand(2).isImmediate())
400 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
401 MI->getOperand(2).getImm());
405 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
406 if (MI->getOperand(2).isImmediate()) {
407 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
408 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
409 MI->getOperand(2).getImm());
414 if (DisableLEA16) return 0;
415 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
416 if (MI->getOperand(2).isImmediate())
417 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
418 MI->getOperand(2).getImm());
421 if (DisableLEA16) return 0;
424 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
425 "Unknown shl instruction!");
426 unsigned ShAmt = MI->getOperand(2).getImm();
427 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
429 AM.Scale = 1 << ShAmt;
431 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
432 : (MIOpc == X86::SHL32ri
433 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
434 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
442 NewMI->copyKillDeadInfo(MI);
443 LV.instructionChanged(MI, NewMI); // Update live variables
444 MFI->insert(MBBI, NewMI); // Insert the new inst
448 /// commuteInstruction - We have a few instructions that must be hacked on to
451 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
452 switch (MI->getOpcode()) {
453 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
454 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
455 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
456 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
457 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
458 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
461 switch (MI->getOpcode()) {
462 default: assert(0 && "Unreachable!");
463 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
464 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
465 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
466 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
467 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
468 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
470 unsigned Amt = MI->getOperand(3).getImm();
471 unsigned A = MI->getOperand(0).getReg();
472 unsigned B = MI->getOperand(1).getReg();
473 unsigned C = MI->getOperand(2).getReg();
474 bool BisKill = MI->getOperand(1).isKill();
475 bool CisKill = MI->getOperand(2).isKill();
476 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
477 .addReg(B, false, false, BisKill).addImm(Size-Amt);
482 case X86::CMOVAE16rr:
483 case X86::CMOVAE32rr:
484 case X86::CMOVAE64rr:
488 case X86::CMOVNE16rr:
489 case X86::CMOVNE32rr:
490 case X86::CMOVNE64rr:
491 case X86::CMOVBE16rr:
492 case X86::CMOVBE32rr:
493 case X86::CMOVBE64rr:
500 case X86::CMOVGE16rr:
501 case X86::CMOVGE32rr:
502 case X86::CMOVGE64rr:
503 case X86::CMOVLE16rr:
504 case X86::CMOVLE32rr:
505 case X86::CMOVLE64rr:
512 case X86::CMOVNS16rr:
513 case X86::CMOVNS32rr:
514 case X86::CMOVNS64rr:
518 case X86::CMOVNP16rr:
519 case X86::CMOVNP32rr:
520 case X86::CMOVNP64rr: {
522 switch (MI->getOpcode()) {
524 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
525 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
526 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
527 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
528 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
529 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
530 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
531 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
532 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
533 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
534 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
535 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
536 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
537 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
538 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
539 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
540 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
541 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
542 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
543 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
544 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
545 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
546 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
547 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
548 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
549 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
550 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
551 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
552 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
553 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
554 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
555 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
556 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
557 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
558 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
559 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
560 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
561 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
562 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
563 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
564 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
565 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
568 MI->setInstrDescriptor(get(Opc));
569 // Fallthrough intended.
572 return TargetInstrInfoImpl::commuteInstruction(MI);
576 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
578 default: return X86::COND_INVALID;
579 case X86::JE: return X86::COND_E;
580 case X86::JNE: return X86::COND_NE;
581 case X86::JL: return X86::COND_L;
582 case X86::JLE: return X86::COND_LE;
583 case X86::JG: return X86::COND_G;
584 case X86::JGE: return X86::COND_GE;
585 case X86::JB: return X86::COND_B;
586 case X86::JBE: return X86::COND_BE;
587 case X86::JA: return X86::COND_A;
588 case X86::JAE: return X86::COND_AE;
589 case X86::JS: return X86::COND_S;
590 case X86::JNS: return X86::COND_NS;
591 case X86::JP: return X86::COND_P;
592 case X86::JNP: return X86::COND_NP;
593 case X86::JO: return X86::COND_O;
594 case X86::JNO: return X86::COND_NO;
598 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
600 default: assert(0 && "Illegal condition code!");
601 case X86::COND_E: return X86::JE;
602 case X86::COND_NE: return X86::JNE;
603 case X86::COND_L: return X86::JL;
604 case X86::COND_LE: return X86::JLE;
605 case X86::COND_G: return X86::JG;
606 case X86::COND_GE: return X86::JGE;
607 case X86::COND_B: return X86::JB;
608 case X86::COND_BE: return X86::JBE;
609 case X86::COND_A: return X86::JA;
610 case X86::COND_AE: return X86::JAE;
611 case X86::COND_S: return X86::JS;
612 case X86::COND_NS: return X86::JNS;
613 case X86::COND_P: return X86::JP;
614 case X86::COND_NP: return X86::JNP;
615 case X86::COND_O: return X86::JO;
616 case X86::COND_NO: return X86::JNO;
620 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
621 /// e.g. turning COND_E to COND_NE.
622 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
624 default: assert(0 && "Illegal condition code!");
625 case X86::COND_E: return X86::COND_NE;
626 case X86::COND_NE: return X86::COND_E;
627 case X86::COND_L: return X86::COND_GE;
628 case X86::COND_LE: return X86::COND_G;
629 case X86::COND_G: return X86::COND_LE;
630 case X86::COND_GE: return X86::COND_L;
631 case X86::COND_B: return X86::COND_AE;
632 case X86::COND_BE: return X86::COND_A;
633 case X86::COND_A: return X86::COND_BE;
634 case X86::COND_AE: return X86::COND_B;
635 case X86::COND_S: return X86::COND_NS;
636 case X86::COND_NS: return X86::COND_S;
637 case X86::COND_P: return X86::COND_NP;
638 case X86::COND_NP: return X86::COND_P;
639 case X86::COND_O: return X86::COND_NO;
640 case X86::COND_NO: return X86::COND_O;
644 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
645 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
646 if (TID->Flags & M_TERMINATOR_FLAG) {
647 // Conditional branch is a special case.
648 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
650 if ((TID->Flags & M_PREDICABLE) == 0)
652 return !isPredicated(MI);
657 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
658 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
659 const X86InstrInfo &TII) {
660 if (MI->getOpcode() == X86::FP_REG_KILL)
662 return TII.isUnpredicatedTerminator(MI);
665 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
666 MachineBasicBlock *&TBB,
667 MachineBasicBlock *&FBB,
668 std::vector<MachineOperand> &Cond) const {
669 // If the block has no terminators, it just falls into the block after it.
670 MachineBasicBlock::iterator I = MBB.end();
671 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
674 // Get the last instruction in the block.
675 MachineInstr *LastInst = I;
677 // If there is only one terminator instruction, process it.
678 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
679 if (!isBranch(LastInst->getOpcode()))
682 // If the block ends with a branch there are 3 possibilities:
683 // it's an unconditional, conditional, or indirect branch.
685 if (LastInst->getOpcode() == X86::JMP) {
686 TBB = LastInst->getOperand(0).getMBB();
689 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
690 if (BranchCode == X86::COND_INVALID)
691 return true; // Can't handle indirect branch.
693 // Otherwise, block ends with fall-through condbranch.
694 TBB = LastInst->getOperand(0).getMBB();
695 Cond.push_back(MachineOperand::CreateImm(BranchCode));
699 // Get the instruction before it if it's a terminator.
700 MachineInstr *SecondLastInst = I;
702 // If there are three terminators, we don't know what sort of block this is.
703 if (SecondLastInst && I != MBB.begin() &&
704 isBrAnalysisUnpredicatedTerminator(--I, *this))
707 // If the block ends with X86::JMP and a conditional branch, handle it.
708 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
709 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
710 TBB = SecondLastInst->getOperand(0).getMBB();
711 Cond.push_back(MachineOperand::CreateImm(BranchCode));
712 FBB = LastInst->getOperand(0).getMBB();
716 // If the block ends with two X86::JMPs, handle it. The second one is not
717 // executed, so remove it.
718 if (SecondLastInst->getOpcode() == X86::JMP &&
719 LastInst->getOpcode() == X86::JMP) {
720 TBB = SecondLastInst->getOperand(0).getMBB();
722 I->eraseFromParent();
726 // Otherwise, can't handle this.
730 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
731 MachineBasicBlock::iterator I = MBB.end();
732 if (I == MBB.begin()) return 0;
734 if (I->getOpcode() != X86::JMP &&
735 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
738 // Remove the branch.
739 I->eraseFromParent();
743 if (I == MBB.begin()) return 1;
745 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
748 // Remove the branch.
749 I->eraseFromParent();
753 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
754 MachineOperand &MO) {
756 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
757 false, false, MO.getSubReg());
758 else if (MO.isImmediate())
759 MIB = MIB.addImm(MO.getImm());
760 else if (MO.isFrameIndex())
761 MIB = MIB.addFrameIndex(MO.getIndex());
762 else if (MO.isGlobalAddress())
763 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
764 else if (MO.isConstantPoolIndex())
765 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
766 else if (MO.isJumpTableIndex())
767 MIB = MIB.addJumpTableIndex(MO.getIndex());
768 else if (MO.isExternalSymbol())
769 MIB = MIB.addExternalSymbol(MO.getSymbolName());
771 assert(0 && "Unknown operand for X86InstrAddOperand!");
777 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
778 MachineBasicBlock *FBB,
779 const std::vector<MachineOperand> &Cond) const {
780 // Shouldn't be a fall through.
781 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
782 assert((Cond.size() == 1 || Cond.size() == 0) &&
783 "X86 branch conditions have one component!");
785 if (FBB == 0) { // One way branch.
787 // Unconditional branch?
788 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
790 // Conditional branch.
791 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
792 BuildMI(&MBB, get(Opc)).addMBB(TBB);
797 // Two-way Conditional branch.
798 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
799 BuildMI(&MBB, get(Opc)).addMBB(TBB);
800 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
804 void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
805 MachineBasicBlock::iterator MI,
806 unsigned DestReg, unsigned SrcReg,
807 const TargetRegisterClass *DestRC,
808 const TargetRegisterClass *SrcRC) const {
809 if (DestRC != SrcRC) {
810 // Moving EFLAGS to / from another register requires a push and a pop.
811 if (SrcRC == &X86::CCRRegClass) {
812 assert(SrcReg == X86::EFLAGS);
813 if (DestRC == &X86::GR64RegClass) {
814 BuildMI(MBB, MI, get(X86::PUSHFQ));
815 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
817 } else if (DestRC == &X86::GR32RegClass) {
818 BuildMI(MBB, MI, get(X86::PUSHFD));
819 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
822 } else if (DestRC == &X86::CCRRegClass) {
823 assert(DestReg == X86::EFLAGS);
824 if (SrcRC == &X86::GR64RegClass) {
825 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
826 BuildMI(MBB, MI, get(X86::POPFQ));
828 } else if (SrcRC == &X86::GR32RegClass) {
829 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
830 BuildMI(MBB, MI, get(X86::POPFD));
834 cerr << "Not yet supported!";
839 if (DestRC == &X86::GR64RegClass) {
841 } else if (DestRC == &X86::GR32RegClass) {
843 } else if (DestRC == &X86::GR16RegClass) {
845 } else if (DestRC == &X86::GR8RegClass) {
847 } else if (DestRC == &X86::GR32_RegClass) {
849 } else if (DestRC == &X86::GR16_RegClass) {
851 } else if (DestRC == &X86::RFP32RegClass) {
852 Opc = X86::MOV_Fp3232;
853 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
854 Opc = X86::MOV_Fp6464;
855 } else if (DestRC == &X86::RFP80RegClass) {
856 Opc = X86::MOV_Fp8080;
857 } else if (DestRC == &X86::FR32RegClass) {
858 Opc = X86::FsMOVAPSrr;
859 } else if (DestRC == &X86::FR64RegClass) {
860 Opc = X86::FsMOVAPDrr;
861 } else if (DestRC == &X86::VR128RegClass) {
863 } else if (DestRC == &X86::VR64RegClass) {
864 Opc = X86::MMX_MOVQ64rr;
866 assert(0 && "Unknown regclass");
869 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
872 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
873 unsigned StackAlign) {
875 if (RC == &X86::GR64RegClass) {
877 } else if (RC == &X86::GR32RegClass) {
879 } else if (RC == &X86::GR16RegClass) {
881 } else if (RC == &X86::GR8RegClass) {
883 } else if (RC == &X86::GR32_RegClass) {
885 } else if (RC == &X86::GR16_RegClass) {
887 } else if (RC == &X86::RFP80RegClass) {
888 Opc = X86::ST_FpP80m; // pops
889 } else if (RC == &X86::RFP64RegClass) {
891 } else if (RC == &X86::RFP32RegClass) {
893 } else if (RC == &X86::FR32RegClass) {
895 } else if (RC == &X86::FR64RegClass) {
897 } else if (RC == &X86::VR128RegClass) {
898 // FIXME: Use movaps once we are capable of selectively
899 // aligning functions that spill SSE registers on 16-byte boundaries.
900 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
901 } else if (RC == &X86::VR64RegClass) {
902 Opc = X86::MMX_MOVQ64mr;
904 assert(0 && "Unknown regclass");
911 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
912 MachineBasicBlock::iterator MI,
913 unsigned SrcReg, bool isKill, int FrameIdx,
914 const TargetRegisterClass *RC) const {
915 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
916 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
917 .addReg(SrcReg, false, false, isKill);
920 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
922 SmallVectorImpl<MachineOperand> &Addr,
923 const TargetRegisterClass *RC,
924 SmallVectorImpl<MachineInstr*> &NewMIs) const {
925 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
926 MachineInstrBuilder MIB = BuildMI(get(Opc));
927 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
928 MIB = X86InstrAddOperand(MIB, Addr[i]);
929 MIB.addReg(SrcReg, false, false, isKill);
930 NewMIs.push_back(MIB);
933 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
934 unsigned StackAlign) {
936 if (RC == &X86::GR64RegClass) {
938 } else if (RC == &X86::GR32RegClass) {
940 } else if (RC == &X86::GR16RegClass) {
942 } else if (RC == &X86::GR8RegClass) {
944 } else if (RC == &X86::GR32_RegClass) {
946 } else if (RC == &X86::GR16_RegClass) {
948 } else if (RC == &X86::RFP80RegClass) {
950 } else if (RC == &X86::RFP64RegClass) {
952 } else if (RC == &X86::RFP32RegClass) {
954 } else if (RC == &X86::FR32RegClass) {
956 } else if (RC == &X86::FR64RegClass) {
958 } else if (RC == &X86::VR128RegClass) {
959 // FIXME: Use movaps once we are capable of selectively
960 // aligning functions that spill SSE registers on 16-byte boundaries.
961 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
962 } else if (RC == &X86::VR64RegClass) {
963 Opc = X86::MMX_MOVQ64rm;
965 assert(0 && "Unknown regclass");
972 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
973 MachineBasicBlock::iterator MI,
974 unsigned DestReg, int FrameIdx,
975 const TargetRegisterClass *RC) const{
976 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
977 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
980 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
981 SmallVectorImpl<MachineOperand> &Addr,
982 const TargetRegisterClass *RC,
983 SmallVectorImpl<MachineInstr*> &NewMIs) const {
984 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
985 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
986 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
987 MIB = X86InstrAddOperand(MIB, Addr[i]);
988 NewMIs.push_back(MIB);
991 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
992 MachineBasicBlock::iterator MI,
993 const std::vector<CalleeSavedInfo> &CSI) const {
997 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
998 unsigned SlotSize = is64Bit ? 8 : 4;
1000 MachineFunction &MF = *MBB.getParent();
1001 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1002 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1004 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1005 for (unsigned i = CSI.size(); i != 0; --i) {
1006 unsigned Reg = CSI[i-1].getReg();
1007 // Add the callee-saved register as live-in. It's killed at the spill.
1009 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1014 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1015 MachineBasicBlock::iterator MI,
1016 const std::vector<CalleeSavedInfo> &CSI) const {
1020 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1022 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1023 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1024 unsigned Reg = CSI[i].getReg();
1025 BuildMI(MBB, MI, get(Opc), Reg);
1030 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
1031 if (MBB.empty()) return false;
1033 switch (MBB.back().getOpcode()) {
1034 case X86::TCRETURNri:
1035 case X86::TCRETURNdi:
1036 case X86::RET: // Return.
1041 case X86::JMP: // Uncond branch.
1042 case X86::JMP32r: // Indirect branch.
1043 case X86::JMP64r: // Indirect branch (64-bit).
1044 case X86::JMP32m: // Indirect branch through mem.
1045 case X86::JMP64m: // Indirect branch through mem (64-bit).
1047 default: return false;
1052 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
1053 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
1054 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
1058 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
1059 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
1060 if (Subtarget->is64Bit())
1061 return &X86::GR64RegClass;
1063 return &X86::GR32RegClass;