1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/MC/MCAsmInfo.h"
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
50 ReMatPICStubLoad("remat-pic-stub-load",
51 cl::desc("Re-materialize load from stub in PIC mode"),
52 cl::init(false), cl::Hidden);
54 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
56 TM(tm), RI(tm, *this) {
57 SmallVector<unsigned,16> AmbEntries;
58 static const unsigned OpTbl2Addr[][2] = {
59 { X86::ADC32ri, X86::ADC32mi },
60 { X86::ADC32ri8, X86::ADC32mi8 },
61 { X86::ADC32rr, X86::ADC32mr },
62 { X86::ADC64ri32, X86::ADC64mi32 },
63 { X86::ADC64ri8, X86::ADC64mi8 },
64 { X86::ADC64rr, X86::ADC64mr },
65 { X86::ADD16ri, X86::ADD16mi },
66 { X86::ADD16ri8, X86::ADD16mi8 },
67 { X86::ADD16rr, X86::ADD16mr },
68 { X86::ADD32ri, X86::ADD32mi },
69 { X86::ADD32ri8, X86::ADD32mi8 },
70 { X86::ADD32rr, X86::ADD32mr },
71 { X86::ADD64ri32, X86::ADD64mi32 },
72 { X86::ADD64ri8, X86::ADD64mi8 },
73 { X86::ADD64rr, X86::ADD64mr },
74 { X86::ADD8ri, X86::ADD8mi },
75 { X86::ADD8rr, X86::ADD8mr },
76 { X86::AND16ri, X86::AND16mi },
77 { X86::AND16ri8, X86::AND16mi8 },
78 { X86::AND16rr, X86::AND16mr },
79 { X86::AND32ri, X86::AND32mi },
80 { X86::AND32ri8, X86::AND32mi8 },
81 { X86::AND32rr, X86::AND32mr },
82 { X86::AND64ri32, X86::AND64mi32 },
83 { X86::AND64ri8, X86::AND64mi8 },
84 { X86::AND64rr, X86::AND64mr },
85 { X86::AND8ri, X86::AND8mi },
86 { X86::AND8rr, X86::AND8mr },
87 { X86::DEC16r, X86::DEC16m },
88 { X86::DEC32r, X86::DEC32m },
89 { X86::DEC64_16r, X86::DEC64_16m },
90 { X86::DEC64_32r, X86::DEC64_32m },
91 { X86::DEC64r, X86::DEC64m },
92 { X86::DEC8r, X86::DEC8m },
93 { X86::INC16r, X86::INC16m },
94 { X86::INC32r, X86::INC32m },
95 { X86::INC64_16r, X86::INC64_16m },
96 { X86::INC64_32r, X86::INC64_32m },
97 { X86::INC64r, X86::INC64m },
98 { X86::INC8r, X86::INC8m },
99 { X86::NEG16r, X86::NEG16m },
100 { X86::NEG32r, X86::NEG32m },
101 { X86::NEG64r, X86::NEG64m },
102 { X86::NEG8r, X86::NEG8m },
103 { X86::NOT16r, X86::NOT16m },
104 { X86::NOT32r, X86::NOT32m },
105 { X86::NOT64r, X86::NOT64m },
106 { X86::NOT8r, X86::NOT8m },
107 { X86::OR16ri, X86::OR16mi },
108 { X86::OR16ri8, X86::OR16mi8 },
109 { X86::OR16rr, X86::OR16mr },
110 { X86::OR32ri, X86::OR32mi },
111 { X86::OR32ri8, X86::OR32mi8 },
112 { X86::OR32rr, X86::OR32mr },
113 { X86::OR64ri32, X86::OR64mi32 },
114 { X86::OR64ri8, X86::OR64mi8 },
115 { X86::OR64rr, X86::OR64mr },
116 { X86::OR8ri, X86::OR8mi },
117 { X86::OR8rr, X86::OR8mr },
118 { X86::ROL16r1, X86::ROL16m1 },
119 { X86::ROL16rCL, X86::ROL16mCL },
120 { X86::ROL16ri, X86::ROL16mi },
121 { X86::ROL32r1, X86::ROL32m1 },
122 { X86::ROL32rCL, X86::ROL32mCL },
123 { X86::ROL32ri, X86::ROL32mi },
124 { X86::ROL64r1, X86::ROL64m1 },
125 { X86::ROL64rCL, X86::ROL64mCL },
126 { X86::ROL64ri, X86::ROL64mi },
127 { X86::ROL8r1, X86::ROL8m1 },
128 { X86::ROL8rCL, X86::ROL8mCL },
129 { X86::ROL8ri, X86::ROL8mi },
130 { X86::ROR16r1, X86::ROR16m1 },
131 { X86::ROR16rCL, X86::ROR16mCL },
132 { X86::ROR16ri, X86::ROR16mi },
133 { X86::ROR32r1, X86::ROR32m1 },
134 { X86::ROR32rCL, X86::ROR32mCL },
135 { X86::ROR32ri, X86::ROR32mi },
136 { X86::ROR64r1, X86::ROR64m1 },
137 { X86::ROR64rCL, X86::ROR64mCL },
138 { X86::ROR64ri, X86::ROR64mi },
139 { X86::ROR8r1, X86::ROR8m1 },
140 { X86::ROR8rCL, X86::ROR8mCL },
141 { X86::ROR8ri, X86::ROR8mi },
142 { X86::SAR16r1, X86::SAR16m1 },
143 { X86::SAR16rCL, X86::SAR16mCL },
144 { X86::SAR16ri, X86::SAR16mi },
145 { X86::SAR32r1, X86::SAR32m1 },
146 { X86::SAR32rCL, X86::SAR32mCL },
147 { X86::SAR32ri, X86::SAR32mi },
148 { X86::SAR64r1, X86::SAR64m1 },
149 { X86::SAR64rCL, X86::SAR64mCL },
150 { X86::SAR64ri, X86::SAR64mi },
151 { X86::SAR8r1, X86::SAR8m1 },
152 { X86::SAR8rCL, X86::SAR8mCL },
153 { X86::SAR8ri, X86::SAR8mi },
154 { X86::SBB32ri, X86::SBB32mi },
155 { X86::SBB32ri8, X86::SBB32mi8 },
156 { X86::SBB32rr, X86::SBB32mr },
157 { X86::SBB64ri32, X86::SBB64mi32 },
158 { X86::SBB64ri8, X86::SBB64mi8 },
159 { X86::SBB64rr, X86::SBB64mr },
160 { X86::SHL16rCL, X86::SHL16mCL },
161 { X86::SHL16ri, X86::SHL16mi },
162 { X86::SHL32rCL, X86::SHL32mCL },
163 { X86::SHL32ri, X86::SHL32mi },
164 { X86::SHL64rCL, X86::SHL64mCL },
165 { X86::SHL64ri, X86::SHL64mi },
166 { X86::SHL8rCL, X86::SHL8mCL },
167 { X86::SHL8ri, X86::SHL8mi },
168 { X86::SHLD16rrCL, X86::SHLD16mrCL },
169 { X86::SHLD16rri8, X86::SHLD16mri8 },
170 { X86::SHLD32rrCL, X86::SHLD32mrCL },
171 { X86::SHLD32rri8, X86::SHLD32mri8 },
172 { X86::SHLD64rrCL, X86::SHLD64mrCL },
173 { X86::SHLD64rri8, X86::SHLD64mri8 },
174 { X86::SHR16r1, X86::SHR16m1 },
175 { X86::SHR16rCL, X86::SHR16mCL },
176 { X86::SHR16ri, X86::SHR16mi },
177 { X86::SHR32r1, X86::SHR32m1 },
178 { X86::SHR32rCL, X86::SHR32mCL },
179 { X86::SHR32ri, X86::SHR32mi },
180 { X86::SHR64r1, X86::SHR64m1 },
181 { X86::SHR64rCL, X86::SHR64mCL },
182 { X86::SHR64ri, X86::SHR64mi },
183 { X86::SHR8r1, X86::SHR8m1 },
184 { X86::SHR8rCL, X86::SHR8mCL },
185 { X86::SHR8ri, X86::SHR8mi },
186 { X86::SHRD16rrCL, X86::SHRD16mrCL },
187 { X86::SHRD16rri8, X86::SHRD16mri8 },
188 { X86::SHRD32rrCL, X86::SHRD32mrCL },
189 { X86::SHRD32rri8, X86::SHRD32mri8 },
190 { X86::SHRD64rrCL, X86::SHRD64mrCL },
191 { X86::SHRD64rri8, X86::SHRD64mri8 },
192 { X86::SUB16ri, X86::SUB16mi },
193 { X86::SUB16ri8, X86::SUB16mi8 },
194 { X86::SUB16rr, X86::SUB16mr },
195 { X86::SUB32ri, X86::SUB32mi },
196 { X86::SUB32ri8, X86::SUB32mi8 },
197 { X86::SUB32rr, X86::SUB32mr },
198 { X86::SUB64ri32, X86::SUB64mi32 },
199 { X86::SUB64ri8, X86::SUB64mi8 },
200 { X86::SUB64rr, X86::SUB64mr },
201 { X86::SUB8ri, X86::SUB8mi },
202 { X86::SUB8rr, X86::SUB8mr },
203 { X86::XOR16ri, X86::XOR16mi },
204 { X86::XOR16ri8, X86::XOR16mi8 },
205 { X86::XOR16rr, X86::XOR16mr },
206 { X86::XOR32ri, X86::XOR32mi },
207 { X86::XOR32ri8, X86::XOR32mi8 },
208 { X86::XOR32rr, X86::XOR32mr },
209 { X86::XOR64ri32, X86::XOR64mi32 },
210 { X86::XOR64ri8, X86::XOR64mi8 },
211 { X86::XOR64rr, X86::XOR64mr },
212 { X86::XOR8ri, X86::XOR8mi },
213 { X86::XOR8rr, X86::XOR8mr }
216 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
217 unsigned RegOp = OpTbl2Addr[i][0];
218 unsigned MemOp = OpTbl2Addr[i][1];
219 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
220 std::make_pair(MemOp,0))).second)
221 assert(false && "Duplicated entries?");
222 // Index 0, folded load and store, no alignment requirement.
223 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
224 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
225 std::make_pair(RegOp,
227 AmbEntries.push_back(MemOp);
230 // If the third value is 1, then it's folding either a load or a store.
231 static const unsigned OpTbl0[][4] = {
232 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
233 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
234 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
235 { X86::CALL32r, X86::CALL32m, 1, 0 },
236 { X86::CALL64r, X86::CALL64m, 1, 0 },
237 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
238 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
239 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
240 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
241 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
242 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
243 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
244 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
245 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
246 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
247 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
248 { X86::DIV16r, X86::DIV16m, 1, 0 },
249 { X86::DIV32r, X86::DIV32m, 1, 0 },
250 { X86::DIV64r, X86::DIV64m, 1, 0 },
251 { X86::DIV8r, X86::DIV8m, 1, 0 },
252 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
253 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
254 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
255 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
256 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
257 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
258 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
259 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
260 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
261 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
262 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
263 { X86::JMP32r, X86::JMP32m, 1, 0 },
264 { X86::JMP64r, X86::JMP64m, 1, 0 },
265 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
266 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
267 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
268 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
269 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
270 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
271 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
272 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
273 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
274 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
275 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
276 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
277 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
278 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
279 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 },
280 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 },
281 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
282 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
283 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 },
284 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
285 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
286 { X86::MUL16r, X86::MUL16m, 1, 0 },
287 { X86::MUL32r, X86::MUL32m, 1, 0 },
288 { X86::MUL64r, X86::MUL64m, 1, 0 },
289 { X86::MUL8r, X86::MUL8m, 1, 0 },
290 { X86::SETAEr, X86::SETAEm, 0, 0 },
291 { X86::SETAr, X86::SETAm, 0, 0 },
292 { X86::SETBEr, X86::SETBEm, 0, 0 },
293 { X86::SETBr, X86::SETBm, 0, 0 },
294 { X86::SETEr, X86::SETEm, 0, 0 },
295 { X86::SETGEr, X86::SETGEm, 0, 0 },
296 { X86::SETGr, X86::SETGm, 0, 0 },
297 { X86::SETLEr, X86::SETLEm, 0, 0 },
298 { X86::SETLr, X86::SETLm, 0, 0 },
299 { X86::SETNEr, X86::SETNEm, 0, 0 },
300 { X86::SETNOr, X86::SETNOm, 0, 0 },
301 { X86::SETNPr, X86::SETNPm, 0, 0 },
302 { X86::SETNSr, X86::SETNSm, 0, 0 },
303 { X86::SETOr, X86::SETOm, 0, 0 },
304 { X86::SETPr, X86::SETPm, 0, 0 },
305 { X86::SETSr, X86::SETSm, 0, 0 },
306 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
307 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
308 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
309 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
310 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
314 unsigned RegOp = OpTbl0[i][0];
315 unsigned MemOp = OpTbl0[i][1];
316 unsigned Align = OpTbl0[i][3];
317 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
318 std::make_pair(MemOp,Align))).second)
319 assert(false && "Duplicated entries?");
320 unsigned FoldedLoad = OpTbl0[i][2];
321 // Index 0, folded load or store.
322 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
323 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
324 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
325 std::make_pair(RegOp, AuxInfo))).second)
326 AmbEntries.push_back(MemOp);
329 static const unsigned OpTbl1[][3] = {
330 { X86::CMP16rr, X86::CMP16rm, 0 },
331 { X86::CMP32rr, X86::CMP32rm, 0 },
332 { X86::CMP64rr, X86::CMP64rm, 0 },
333 { X86::CMP8rr, X86::CMP8rm, 0 },
334 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
335 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
336 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
337 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
338 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
339 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
340 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
341 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
342 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
343 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
344 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
345 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
346 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
347 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
348 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
349 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
350 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
351 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
352 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
353 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
354 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
355 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
356 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
357 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
358 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
359 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
360 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
361 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
362 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
363 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
364 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
365 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
366 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
367 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
368 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
369 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
370 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
371 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
372 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
373 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
374 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
375 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
376 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
377 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
378 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
379 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
380 { X86::MOV16rr, X86::MOV16rm, 0 },
381 { X86::MOV32rr, X86::MOV32rm, 0 },
382 { X86::MOV64rr, X86::MOV64rm, 0 },
383 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
384 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
385 { X86::MOV8rr, X86::MOV8rm, 0 },
386 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
387 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
388 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
389 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
390 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
391 { X86::MOVDQArr, X86::MOVDQArm, 16 },
392 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 },
393 { X86::MOVSDrr, X86::MOVSDrm, 0 },
394 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
395 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
396 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 },
397 { X86::MOVSSrr, X86::MOVSSrm, 0 },
398 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
399 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
400 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
401 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
402 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
403 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
404 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
405 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
406 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
407 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
408 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
409 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
410 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
411 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
412 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
413 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
414 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
415 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
416 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
417 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
418 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
419 { X86::RCPPSr, X86::RCPPSm, 16 },
420 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
421 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
422 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
423 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
424 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
425 { X86::SQRTPDr, X86::SQRTPDm, 16 },
426 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
427 { X86::SQRTPSr, X86::SQRTPSm, 16 },
428 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
429 { X86::SQRTSDr, X86::SQRTSDm, 0 },
430 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
431 { X86::SQRTSSr, X86::SQRTSSm, 0 },
432 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
433 { X86::TEST16rr, X86::TEST16rm, 0 },
434 { X86::TEST32rr, X86::TEST32rm, 0 },
435 { X86::TEST64rr, X86::TEST64rm, 0 },
436 { X86::TEST8rr, X86::TEST8rm, 0 },
437 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
438 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
439 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
442 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
443 unsigned RegOp = OpTbl1[i][0];
444 unsigned MemOp = OpTbl1[i][1];
445 unsigned Align = OpTbl1[i][2];
446 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
447 std::make_pair(MemOp,Align))).second)
448 assert(false && "Duplicated entries?");
449 // Index 1, folded load
450 unsigned AuxInfo = 1 | (1 << 4);
451 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
452 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
453 std::make_pair(RegOp, AuxInfo))).second)
454 AmbEntries.push_back(MemOp);
457 static const unsigned OpTbl2[][3] = {
458 { X86::ADC32rr, X86::ADC32rm, 0 },
459 { X86::ADC64rr, X86::ADC64rm, 0 },
460 { X86::ADD16rr, X86::ADD16rm, 0 },
461 { X86::ADD32rr, X86::ADD32rm, 0 },
462 { X86::ADD64rr, X86::ADD64rm, 0 },
463 { X86::ADD8rr, X86::ADD8rm, 0 },
464 { X86::ADDPDrr, X86::ADDPDrm, 16 },
465 { X86::ADDPSrr, X86::ADDPSrm, 16 },
466 { X86::ADDSDrr, X86::ADDSDrm, 0 },
467 { X86::ADDSSrr, X86::ADDSSrm, 0 },
468 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
469 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
470 { X86::AND16rr, X86::AND16rm, 0 },
471 { X86::AND32rr, X86::AND32rm, 0 },
472 { X86::AND64rr, X86::AND64rm, 0 },
473 { X86::AND8rr, X86::AND8rm, 0 },
474 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
475 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
476 { X86::ANDPDrr, X86::ANDPDrm, 16 },
477 { X86::ANDPSrr, X86::ANDPSrm, 16 },
478 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
479 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
480 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
481 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
482 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
483 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
484 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
485 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
486 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
487 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
488 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
489 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
490 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
491 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
492 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
493 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
494 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
495 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
496 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
497 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
498 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
499 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
500 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
501 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
502 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
503 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
504 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
505 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
506 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
507 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
508 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
509 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
510 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
511 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
512 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
513 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
514 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
515 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
516 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
517 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
518 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
519 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
520 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
521 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
522 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
523 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
524 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
525 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
526 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
527 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
528 { X86::CMPSDrr, X86::CMPSDrm, 0 },
529 { X86::CMPSSrr, X86::CMPSSrm, 0 },
530 { X86::DIVPDrr, X86::DIVPDrm, 16 },
531 { X86::DIVPSrr, X86::DIVPSrm, 16 },
532 { X86::DIVSDrr, X86::DIVSDrm, 0 },
533 { X86::DIVSSrr, X86::DIVSSrm, 0 },
534 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
535 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
536 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
537 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
538 { X86::FsORPDrr, X86::FsORPDrm, 16 },
539 { X86::FsORPSrr, X86::FsORPSrm, 16 },
540 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
541 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
542 { X86::HADDPDrr, X86::HADDPDrm, 16 },
543 { X86::HADDPSrr, X86::HADDPSrm, 16 },
544 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
545 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
546 { X86::IMUL16rr, X86::IMUL16rm, 0 },
547 { X86::IMUL32rr, X86::IMUL32rm, 0 },
548 { X86::IMUL64rr, X86::IMUL64rm, 0 },
549 { X86::MAXPDrr, X86::MAXPDrm, 16 },
550 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
551 { X86::MAXPSrr, X86::MAXPSrm, 16 },
552 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
553 { X86::MAXSDrr, X86::MAXSDrm, 0 },
554 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
555 { X86::MAXSSrr, X86::MAXSSrm, 0 },
556 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
557 { X86::MINPDrr, X86::MINPDrm, 16 },
558 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
559 { X86::MINPSrr, X86::MINPSrm, 16 },
560 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
561 { X86::MINSDrr, X86::MINSDrm, 0 },
562 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
563 { X86::MINSSrr, X86::MINSSrm, 0 },
564 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
565 { X86::MULPDrr, X86::MULPDrm, 16 },
566 { X86::MULPSrr, X86::MULPSrm, 16 },
567 { X86::MULSDrr, X86::MULSDrm, 0 },
568 { X86::MULSSrr, X86::MULSSrm, 0 },
569 { X86::OR16rr, X86::OR16rm, 0 },
570 { X86::OR32rr, X86::OR32rm, 0 },
571 { X86::OR64rr, X86::OR64rm, 0 },
572 { X86::OR8rr, X86::OR8rm, 0 },
573 { X86::ORPDrr, X86::ORPDrm, 16 },
574 { X86::ORPSrr, X86::ORPSrm, 16 },
575 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
576 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
577 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
578 { X86::PADDBrr, X86::PADDBrm, 16 },
579 { X86::PADDDrr, X86::PADDDrm, 16 },
580 { X86::PADDQrr, X86::PADDQrm, 16 },
581 { X86::PADDSBrr, X86::PADDSBrm, 16 },
582 { X86::PADDSWrr, X86::PADDSWrm, 16 },
583 { X86::PADDWrr, X86::PADDWrm, 16 },
584 { X86::PANDNrr, X86::PANDNrm, 16 },
585 { X86::PANDrr, X86::PANDrm, 16 },
586 { X86::PAVGBrr, X86::PAVGBrm, 16 },
587 { X86::PAVGWrr, X86::PAVGWrm, 16 },
588 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
589 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
590 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
591 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
592 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
593 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
594 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
595 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
596 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
597 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
598 { X86::PMINSWrr, X86::PMINSWrm, 16 },
599 { X86::PMINUBrr, X86::PMINUBrm, 16 },
600 { X86::PMULDQrr, X86::PMULDQrm, 16 },
601 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
602 { X86::PMULHWrr, X86::PMULHWrm, 16 },
603 { X86::PMULLDrr, X86::PMULLDrm, 16 },
604 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
605 { X86::PMULLWrr, X86::PMULLWrm, 16 },
606 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
607 { X86::PORrr, X86::PORrm, 16 },
608 { X86::PSADBWrr, X86::PSADBWrm, 16 },
609 { X86::PSLLDrr, X86::PSLLDrm, 16 },
610 { X86::PSLLQrr, X86::PSLLQrm, 16 },
611 { X86::PSLLWrr, X86::PSLLWrm, 16 },
612 { X86::PSRADrr, X86::PSRADrm, 16 },
613 { X86::PSRAWrr, X86::PSRAWrm, 16 },
614 { X86::PSRLDrr, X86::PSRLDrm, 16 },
615 { X86::PSRLQrr, X86::PSRLQrm, 16 },
616 { X86::PSRLWrr, X86::PSRLWrm, 16 },
617 { X86::PSUBBrr, X86::PSUBBrm, 16 },
618 { X86::PSUBDrr, X86::PSUBDrm, 16 },
619 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
620 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
621 { X86::PSUBWrr, X86::PSUBWrm, 16 },
622 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
623 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
624 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
625 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
626 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
627 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
628 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
629 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
630 { X86::PXORrr, X86::PXORrm, 16 },
631 { X86::SBB32rr, X86::SBB32rm, 0 },
632 { X86::SBB64rr, X86::SBB64rm, 0 },
633 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
634 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
635 { X86::SUB16rr, X86::SUB16rm, 0 },
636 { X86::SUB32rr, X86::SUB32rm, 0 },
637 { X86::SUB64rr, X86::SUB64rm, 0 },
638 { X86::SUB8rr, X86::SUB8rm, 0 },
639 { X86::SUBPDrr, X86::SUBPDrm, 16 },
640 { X86::SUBPSrr, X86::SUBPSrm, 16 },
641 { X86::SUBSDrr, X86::SUBSDrm, 0 },
642 { X86::SUBSSrr, X86::SUBSSrm, 0 },
643 // FIXME: TEST*rr -> swapped operand of TEST*mr.
644 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
645 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
646 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
647 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
648 { X86::XOR16rr, X86::XOR16rm, 0 },
649 { X86::XOR32rr, X86::XOR32rm, 0 },
650 { X86::XOR64rr, X86::XOR64rm, 0 },
651 { X86::XOR8rr, X86::XOR8rm, 0 },
652 { X86::XORPDrr, X86::XORPDrm, 16 },
653 { X86::XORPSrr, X86::XORPSrm, 16 }
656 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
657 unsigned RegOp = OpTbl2[i][0];
658 unsigned MemOp = OpTbl2[i][1];
659 unsigned Align = OpTbl2[i][2];
660 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
661 std::make_pair(MemOp,Align))).second)
662 assert(false && "Duplicated entries?");
663 // Index 2, folded load
664 unsigned AuxInfo = 2 | (1 << 4);
665 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
666 std::make_pair(RegOp, AuxInfo))).second)
667 AmbEntries.push_back(MemOp);
670 // Remove ambiguous entries.
671 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
674 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
675 unsigned &SrcReg, unsigned &DstReg,
676 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
677 switch (MI.getOpcode()) {
681 case X86::MOV8rr_NOREX:
688 // FP Stack register class copies
689 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
690 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
691 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
693 case X86::FsMOVAPSrr:
694 case X86::FsMOVAPDrr:
698 case X86::MOVSS2PSrr:
699 case X86::MOVSD2PDrr:
700 case X86::MOVPS2SSrr:
701 case X86::MOVPD2SDrr:
702 case X86::MMX_MOVQ64rr:
703 assert(MI.getNumOperands() >= 2 &&
704 MI.getOperand(0).isReg() &&
705 MI.getOperand(1).isReg() &&
706 "invalid register-register move instruction");
707 SrcReg = MI.getOperand(1).getReg();
708 DstReg = MI.getOperand(0).getReg();
709 SrcSubIdx = MI.getOperand(1).getSubReg();
710 DstSubIdx = MI.getOperand(0).getSubReg();
716 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
717 unsigned &SrcReg, unsigned &DstReg,
718 unsigned &SubIdx) const {
719 switch (MI.getOpcode()) {
721 case X86::MOVSX16rr8:
722 case X86::MOVZX16rr8:
723 case X86::MOVSX32rr8:
724 case X86::MOVZX32rr8:
725 case X86::MOVSX64rr8:
726 case X86::MOVZX64rr8:
727 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
728 // It's not always legal to reference the low 8-bit of the larger
729 // register in 32-bit mode.
731 case X86::MOVSX32rr16:
732 case X86::MOVZX32rr16:
733 case X86::MOVSX64rr16:
734 case X86::MOVZX64rr16:
735 case X86::MOVSX64rr32:
736 case X86::MOVZX64rr32: {
737 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
740 SrcReg = MI.getOperand(1).getReg();
741 DstReg = MI.getOperand(0).getReg();
742 switch (MI.getOpcode()) {
746 case X86::MOVSX16rr8:
747 case X86::MOVZX16rr8:
748 case X86::MOVSX32rr8:
749 case X86::MOVZX32rr8:
750 case X86::MOVSX64rr8:
751 case X86::MOVZX64rr8:
754 case X86::MOVSX32rr16:
755 case X86::MOVZX32rr16:
756 case X86::MOVSX64rr16:
757 case X86::MOVZX64rr16:
760 case X86::MOVSX64rr32:
761 case X86::MOVZX64rr32:
771 /// isFrameOperand - Return true and the FrameIndex if the specified
772 /// operand and follow operands form a reference to the stack frame.
773 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
774 int &FrameIndex) const {
775 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
776 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
777 MI->getOperand(Op+1).getImm() == 1 &&
778 MI->getOperand(Op+2).getReg() == 0 &&
779 MI->getOperand(Op+3).getImm() == 0) {
780 FrameIndex = MI->getOperand(Op).getIndex();
786 static bool isFrameLoadOpcode(int Opcode) {
799 case X86::MMX_MOVD64rm:
800 case X86::MMX_MOVQ64rm:
807 static bool isFrameStoreOpcode(int Opcode) {
820 case X86::MMX_MOVD64mr:
821 case X86::MMX_MOVQ64mr:
822 case X86::MMX_MOVNTQmr:
828 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
829 int &FrameIndex) const {
830 if (isFrameLoadOpcode(MI->getOpcode()))
831 if (isFrameOperand(MI, 1, FrameIndex))
832 return MI->getOperand(0).getReg();
836 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
837 int &FrameIndex) const {
838 if (isFrameLoadOpcode(MI->getOpcode())) {
840 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
842 // Check for post-frame index elimination operations
843 const MachineMemOperand *Dummy;
844 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
849 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
850 const MachineMemOperand *&MMO,
851 int &FrameIndex) const {
852 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
853 oe = MI->memoperands_end();
856 if ((*o)->isLoad() && (*o)->getValue())
857 if (const FixedStackPseudoSourceValue *Value =
858 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
859 FrameIndex = Value->getFrameIndex();
867 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
868 int &FrameIndex) const {
869 if (isFrameStoreOpcode(MI->getOpcode()))
870 if (isFrameOperand(MI, 0, FrameIndex))
871 return MI->getOperand(X86AddrNumOperands).getReg();
875 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
876 int &FrameIndex) const {
877 if (isFrameStoreOpcode(MI->getOpcode())) {
879 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
881 // Check for post-frame index elimination operations
882 const MachineMemOperand *Dummy;
883 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
888 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
889 const MachineMemOperand *&MMO,
890 int &FrameIndex) const {
891 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
892 oe = MI->memoperands_end();
895 if ((*o)->isStore() && (*o)->getValue())
896 if (const FixedStackPseudoSourceValue *Value =
897 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
898 FrameIndex = Value->getFrameIndex();
906 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
908 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
909 bool isPICBase = false;
910 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
911 E = MRI.def_end(); I != E; ++I) {
912 MachineInstr *DefMI = I.getOperand().getParent();
913 if (DefMI->getOpcode() != X86::MOVPC32r)
915 assert(!isPICBase && "More than one PIC base?");
922 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
923 AliasAnalysis *AA) const {
924 switch (MI->getOpcode()) {
935 case X86::MOVUPSrm_Int:
938 case X86::MMX_MOVD64rm:
939 case X86::MMX_MOVQ64rm:
940 case X86::FsMOVAPSrm:
941 case X86::FsMOVAPDrm: {
942 // Loads from constant pools are trivially rematerializable.
943 if (MI->getOperand(1).isReg() &&
944 MI->getOperand(2).isImm() &&
945 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
946 MI->isInvariantLoad(AA)) {
947 unsigned BaseReg = MI->getOperand(1).getReg();
948 if (BaseReg == 0 || BaseReg == X86::RIP)
950 // Allow re-materialization of PIC load.
951 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
953 const MachineFunction &MF = *MI->getParent()->getParent();
954 const MachineRegisterInfo &MRI = MF.getRegInfo();
955 bool isPICBase = false;
956 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
957 E = MRI.def_end(); I != E; ++I) {
958 MachineInstr *DefMI = I.getOperand().getParent();
959 if (DefMI->getOpcode() != X86::MOVPC32r)
961 assert(!isPICBase && "More than one PIC base?");
971 if (MI->getOperand(2).isImm() &&
972 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
973 !MI->getOperand(4).isReg()) {
974 // lea fi#, lea GV, etc. are all rematerializable.
975 if (!MI->getOperand(1).isReg())
977 unsigned BaseReg = MI->getOperand(1).getReg();
980 // Allow re-materialization of lea PICBase + x.
981 const MachineFunction &MF = *MI->getParent()->getParent();
982 const MachineRegisterInfo &MRI = MF.getRegInfo();
983 return regIsPICBase(BaseReg, MRI);
989 // All other instructions marked M_REMATERIALIZABLE are always trivially
994 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
995 /// would clobber the EFLAGS condition register. Note the result may be
996 /// conservative. If it cannot definitely determine the safety after visiting
997 /// a few instructions in each direction it assumes it's not safe.
998 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
999 MachineBasicBlock::iterator I) {
1000 // It's always safe to clobber EFLAGS at the end of a block.
1004 // For compile time consideration, if we are not able to determine the
1005 // safety after visiting 4 instructions in each direction, we will assume
1007 MachineBasicBlock::iterator Iter = I;
1008 for (unsigned i = 0; i < 4; ++i) {
1009 bool SeenDef = false;
1010 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1011 MachineOperand &MO = Iter->getOperand(j);
1014 if (MO.getReg() == X86::EFLAGS) {
1022 // This instruction defines EFLAGS, no need to look any further.
1026 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1027 if (Iter == MBB.end())
1032 for (unsigned i = 0; i < 4; ++i) {
1033 // If we make it to the beginning of the block, it's safe to clobber
1034 // EFLAGS iff EFLAGS is not live-in.
1035 if (Iter == MBB.begin())
1036 return !MBB.isLiveIn(X86::EFLAGS);
1039 bool SawKill = false;
1040 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1041 MachineOperand &MO = Iter->getOperand(j);
1042 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1043 if (MO.isDef()) return MO.isDead();
1044 if (MO.isKill()) SawKill = true;
1049 // This instruction kills EFLAGS and doesn't redefine it, so
1050 // there's no need to look further.
1054 // Conservative answer.
1058 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1059 MachineBasicBlock::iterator I,
1060 unsigned DestReg, unsigned SubIdx,
1061 const MachineInstr *Orig,
1062 const TargetRegisterInfo *TRI) const {
1063 DebugLoc DL = MBB.findDebugLoc(I);
1065 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1066 DestReg = TRI->getSubReg(DestReg, SubIdx);
1070 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1071 // Re-materialize them as movri instructions to avoid side effects.
1073 unsigned Opc = Orig->getOpcode();
1079 case X86::MOV64r0: {
1080 if (!isSafeToClobberEFLAGS(MBB, I)) {
1083 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1084 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1085 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1086 case X86::MOV64r0: Opc = X86::MOV64ri; break;
1095 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1096 MI->getOperand(0).setReg(DestReg);
1099 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1102 MachineInstr *NewMI = prior(I);
1103 NewMI->getOperand(0).setSubReg(SubIdx);
1106 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1107 /// is not marked dead.
1108 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1109 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1110 MachineOperand &MO = MI->getOperand(i);
1111 if (MO.isReg() && MO.isDef() &&
1112 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1119 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1120 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1121 /// to a 32-bit superregister and then truncating back down to a 16-bit
1124 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1125 MachineFunction::iterator &MFI,
1126 MachineBasicBlock::iterator &MBBI,
1127 LiveVariables *LV) const {
1128 MachineInstr *MI = MBBI;
1129 unsigned Dest = MI->getOperand(0).getReg();
1130 unsigned Src = MI->getOperand(1).getReg();
1131 bool isDead = MI->getOperand(0).isDead();
1132 bool isKill = MI->getOperand(1).isKill();
1134 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1135 ? X86::LEA64_32r : X86::LEA32r;
1136 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1137 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1138 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1140 // Build and insert into an implicit UNDEF value. This is OK because
1141 // well be shifting and then extracting the lower 16-bits.
1142 // This has the potential to cause partial register stall. e.g.
1143 // movw (%rbp,%rcx,2), %dx
1144 // leal -65(%rdx), %esi
1145 // But testing has shown this *does* help performance in 64-bit mode (at
1146 // least on modern x86 machines).
1147 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1148 MachineInstr *InsMI =
1149 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1151 .addReg(Src, getKillRegState(isKill))
1152 .addImm(X86::SUBREG_16BIT);
1154 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1155 get(Opc), leaOutReg);
1158 llvm_unreachable(0);
1160 case X86::SHL16ri: {
1161 unsigned ShAmt = MI->getOperand(2).getImm();
1162 MIB.addReg(0).addImm(1 << ShAmt)
1163 .addReg(leaInReg, RegState::Kill).addImm(0);
1167 case X86::INC64_16r:
1168 addLeaRegOffset(MIB, leaInReg, true, 1);
1171 case X86::DEC64_16r:
1172 addLeaRegOffset(MIB, leaInReg, true, -1);
1176 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1178 case X86::ADD16rr: {
1179 unsigned Src2 = MI->getOperand(2).getReg();
1180 bool isKill2 = MI->getOperand(2).isKill();
1181 unsigned leaInReg2 = 0;
1182 MachineInstr *InsMI2 = 0;
1184 // ADD16rr %reg1028<kill>, %reg1028
1185 // just a single insert_subreg.
1186 addRegReg(MIB, leaInReg, true, leaInReg, false);
1188 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1189 // Build and insert into an implicit UNDEF value. This is OK because
1190 // well be shifting and then extracting the lower 16-bits.
1191 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1193 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1195 .addReg(Src2, getKillRegState(isKill2))
1196 .addImm(X86::SUBREG_16BIT);
1197 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1199 if (LV && isKill2 && InsMI2)
1200 LV->replaceKillInstruction(Src2, MI, InsMI2);
1205 MachineInstr *NewMI = MIB;
1206 MachineInstr *ExtMI =
1207 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1208 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1209 .addReg(leaOutReg, RegState::Kill)
1210 .addImm(X86::SUBREG_16BIT);
1213 // Update live variables
1214 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1215 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1217 LV->replaceKillInstruction(Src, MI, InsMI);
1219 LV->replaceKillInstruction(Dest, MI, ExtMI);
1225 /// convertToThreeAddress - This method must be implemented by targets that
1226 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1227 /// may be able to convert a two-address instruction into a true
1228 /// three-address instruction on demand. This allows the X86 target (for
1229 /// example) to convert ADD and SHL instructions into LEA instructions if they
1230 /// would require register copies due to two-addressness.
1232 /// This method returns a null pointer if the transformation cannot be
1233 /// performed, otherwise it returns the new instruction.
1236 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1237 MachineBasicBlock::iterator &MBBI,
1238 LiveVariables *LV) const {
1239 MachineInstr *MI = MBBI;
1240 MachineFunction &MF = *MI->getParent()->getParent();
1241 // All instructions input are two-addr instructions. Get the known operands.
1242 unsigned Dest = MI->getOperand(0).getReg();
1243 unsigned Src = MI->getOperand(1).getReg();
1244 bool isDead = MI->getOperand(0).isDead();
1245 bool isKill = MI->getOperand(1).isKill();
1247 MachineInstr *NewMI = NULL;
1248 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1249 // we have better subtarget support, enable the 16-bit LEA generation here.
1250 // 16-bit LEA is also slow on Core2.
1251 bool DisableLEA16 = true;
1252 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1254 unsigned MIOpc = MI->getOpcode();
1256 case X86::SHUFPSrri: {
1257 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1258 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1260 unsigned B = MI->getOperand(1).getReg();
1261 unsigned C = MI->getOperand(2).getReg();
1262 if (B != C) return 0;
1263 unsigned A = MI->getOperand(0).getReg();
1264 unsigned M = MI->getOperand(3).getImm();
1265 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1266 .addReg(A, RegState::Define | getDeadRegState(isDead))
1267 .addReg(B, getKillRegState(isKill)).addImm(M);
1270 case X86::SHL64ri: {
1271 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1272 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1273 // the flags produced by a shift yet, so this is safe.
1274 unsigned ShAmt = MI->getOperand(2).getImm();
1275 if (ShAmt == 0 || ShAmt >= 4) return 0;
1277 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1278 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1279 .addReg(0).addImm(1 << ShAmt)
1280 .addReg(Src, getKillRegState(isKill))
1284 case X86::SHL32ri: {
1285 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1286 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1287 // the flags produced by a shift yet, so this is safe.
1288 unsigned ShAmt = MI->getOperand(2).getImm();
1289 if (ShAmt == 0 || ShAmt >= 4) return 0;
1291 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1292 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1293 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1294 .addReg(0).addImm(1 << ShAmt)
1295 .addReg(Src, getKillRegState(isKill)).addImm(0);
1298 case X86::SHL16ri: {
1299 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1300 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1301 // the flags produced by a shift yet, so this is safe.
1302 unsigned ShAmt = MI->getOperand(2).getImm();
1303 if (ShAmt == 0 || ShAmt >= 4) return 0;
1306 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1307 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1308 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1309 .addReg(0).addImm(1 << ShAmt)
1310 .addReg(Src, getKillRegState(isKill))
1315 // The following opcodes also sets the condition code register(s). Only
1316 // convert them to equivalent lea if the condition code register def's
1318 if (hasLiveCondCodeDef(MI))
1325 case X86::INC64_32r: {
1326 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1327 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1328 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1329 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1330 .addReg(Dest, RegState::Define |
1331 getDeadRegState(isDead)),
1336 case X86::INC64_16r:
1338 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1339 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1340 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1341 .addReg(Dest, RegState::Define |
1342 getDeadRegState(isDead)),
1347 case X86::DEC64_32r: {
1348 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1349 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1350 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1351 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1352 .addReg(Dest, RegState::Define |
1353 getDeadRegState(isDead)),
1358 case X86::DEC64_16r:
1360 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1361 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1362 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1363 .addReg(Dest, RegState::Define |
1364 getDeadRegState(isDead)),
1368 case X86::ADD32rr: {
1369 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1370 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1371 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1372 unsigned Src2 = MI->getOperand(2).getReg();
1373 bool isKill2 = MI->getOperand(2).isKill();
1374 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1375 .addReg(Dest, RegState::Define |
1376 getDeadRegState(isDead)),
1377 Src, isKill, Src2, isKill2);
1379 LV->replaceKillInstruction(Src2, MI, NewMI);
1382 case X86::ADD16rr: {
1384 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1385 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1386 unsigned Src2 = MI->getOperand(2).getReg();
1387 bool isKill2 = MI->getOperand(2).isKill();
1388 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1389 .addReg(Dest, RegState::Define |
1390 getDeadRegState(isDead)),
1391 Src, isKill, Src2, isKill2);
1393 LV->replaceKillInstruction(Src2, MI, NewMI);
1396 case X86::ADD64ri32:
1398 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1399 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1400 .addReg(Dest, RegState::Define |
1401 getDeadRegState(isDead)),
1402 Src, isKill, MI->getOperand(2).getImm());
1405 case X86::ADD32ri8: {
1406 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1407 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1408 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1409 .addReg(Dest, RegState::Define |
1410 getDeadRegState(isDead)),
1411 Src, isKill, MI->getOperand(2).getImm());
1417 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1418 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1419 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1420 .addReg(Dest, RegState::Define |
1421 getDeadRegState(isDead)),
1422 Src, isKill, MI->getOperand(2).getImm());
1428 if (!NewMI) return 0;
1430 if (LV) { // Update live variables
1432 LV->replaceKillInstruction(Src, MI, NewMI);
1434 LV->replaceKillInstruction(Dest, MI, NewMI);
1437 MFI->insert(MBBI, NewMI); // Insert the new inst
1441 /// commuteInstruction - We have a few instructions that must be hacked on to
1445 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1446 switch (MI->getOpcode()) {
1447 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1448 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1449 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1450 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1451 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1452 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1455 switch (MI->getOpcode()) {
1456 default: llvm_unreachable("Unreachable!");
1457 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1458 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1459 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1460 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1461 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1462 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1464 unsigned Amt = MI->getOperand(3).getImm();
1466 MachineFunction &MF = *MI->getParent()->getParent();
1467 MI = MF.CloneMachineInstr(MI);
1470 MI->setDesc(get(Opc));
1471 MI->getOperand(3).setImm(Size-Amt);
1472 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1474 case X86::CMOVB16rr:
1475 case X86::CMOVB32rr:
1476 case X86::CMOVB64rr:
1477 case X86::CMOVAE16rr:
1478 case X86::CMOVAE32rr:
1479 case X86::CMOVAE64rr:
1480 case X86::CMOVE16rr:
1481 case X86::CMOVE32rr:
1482 case X86::CMOVE64rr:
1483 case X86::CMOVNE16rr:
1484 case X86::CMOVNE32rr:
1485 case X86::CMOVNE64rr:
1486 case X86::CMOVBE16rr:
1487 case X86::CMOVBE32rr:
1488 case X86::CMOVBE64rr:
1489 case X86::CMOVA16rr:
1490 case X86::CMOVA32rr:
1491 case X86::CMOVA64rr:
1492 case X86::CMOVL16rr:
1493 case X86::CMOVL32rr:
1494 case X86::CMOVL64rr:
1495 case X86::CMOVGE16rr:
1496 case X86::CMOVGE32rr:
1497 case X86::CMOVGE64rr:
1498 case X86::CMOVLE16rr:
1499 case X86::CMOVLE32rr:
1500 case X86::CMOVLE64rr:
1501 case X86::CMOVG16rr:
1502 case X86::CMOVG32rr:
1503 case X86::CMOVG64rr:
1504 case X86::CMOVS16rr:
1505 case X86::CMOVS32rr:
1506 case X86::CMOVS64rr:
1507 case X86::CMOVNS16rr:
1508 case X86::CMOVNS32rr:
1509 case X86::CMOVNS64rr:
1510 case X86::CMOVP16rr:
1511 case X86::CMOVP32rr:
1512 case X86::CMOVP64rr:
1513 case X86::CMOVNP16rr:
1514 case X86::CMOVNP32rr:
1515 case X86::CMOVNP64rr:
1516 case X86::CMOVO16rr:
1517 case X86::CMOVO32rr:
1518 case X86::CMOVO64rr:
1519 case X86::CMOVNO16rr:
1520 case X86::CMOVNO32rr:
1521 case X86::CMOVNO64rr: {
1523 switch (MI->getOpcode()) {
1525 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1526 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1527 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1528 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1529 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1530 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1531 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1532 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1533 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1534 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1535 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1536 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1537 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1538 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1539 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1540 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1541 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1542 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1543 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1544 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1545 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1546 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1547 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1548 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1549 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1550 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1551 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1552 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1553 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1554 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1555 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1556 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1557 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1558 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1559 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1560 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1561 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1562 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1563 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1564 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1565 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1566 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1567 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1568 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1569 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1570 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1571 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1572 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1575 MachineFunction &MF = *MI->getParent()->getParent();
1576 MI = MF.CloneMachineInstr(MI);
1579 MI->setDesc(get(Opc));
1580 // Fallthrough intended.
1583 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1587 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1589 default: return X86::COND_INVALID;
1590 case X86::JE_4: return X86::COND_E;
1591 case X86::JNE_4: return X86::COND_NE;
1592 case X86::JL_4: return X86::COND_L;
1593 case X86::JLE_4: return X86::COND_LE;
1594 case X86::JG_4: return X86::COND_G;
1595 case X86::JGE_4: return X86::COND_GE;
1596 case X86::JB_4: return X86::COND_B;
1597 case X86::JBE_4: return X86::COND_BE;
1598 case X86::JA_4: return X86::COND_A;
1599 case X86::JAE_4: return X86::COND_AE;
1600 case X86::JS_4: return X86::COND_S;
1601 case X86::JNS_4: return X86::COND_NS;
1602 case X86::JP_4: return X86::COND_P;
1603 case X86::JNP_4: return X86::COND_NP;
1604 case X86::JO_4: return X86::COND_O;
1605 case X86::JNO_4: return X86::COND_NO;
1609 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1611 default: llvm_unreachable("Illegal condition code!");
1612 case X86::COND_E: return X86::JE_4;
1613 case X86::COND_NE: return X86::JNE_4;
1614 case X86::COND_L: return X86::JL_4;
1615 case X86::COND_LE: return X86::JLE_4;
1616 case X86::COND_G: return X86::JG_4;
1617 case X86::COND_GE: return X86::JGE_4;
1618 case X86::COND_B: return X86::JB_4;
1619 case X86::COND_BE: return X86::JBE_4;
1620 case X86::COND_A: return X86::JA_4;
1621 case X86::COND_AE: return X86::JAE_4;
1622 case X86::COND_S: return X86::JS_4;
1623 case X86::COND_NS: return X86::JNS_4;
1624 case X86::COND_P: return X86::JP_4;
1625 case X86::COND_NP: return X86::JNP_4;
1626 case X86::COND_O: return X86::JO_4;
1627 case X86::COND_NO: return X86::JNO_4;
1631 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1632 /// e.g. turning COND_E to COND_NE.
1633 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1635 default: llvm_unreachable("Illegal condition code!");
1636 case X86::COND_E: return X86::COND_NE;
1637 case X86::COND_NE: return X86::COND_E;
1638 case X86::COND_L: return X86::COND_GE;
1639 case X86::COND_LE: return X86::COND_G;
1640 case X86::COND_G: return X86::COND_LE;
1641 case X86::COND_GE: return X86::COND_L;
1642 case X86::COND_B: return X86::COND_AE;
1643 case X86::COND_BE: return X86::COND_A;
1644 case X86::COND_A: return X86::COND_BE;
1645 case X86::COND_AE: return X86::COND_B;
1646 case X86::COND_S: return X86::COND_NS;
1647 case X86::COND_NS: return X86::COND_S;
1648 case X86::COND_P: return X86::COND_NP;
1649 case X86::COND_NP: return X86::COND_P;
1650 case X86::COND_O: return X86::COND_NO;
1651 case X86::COND_NO: return X86::COND_O;
1655 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1656 const TargetInstrDesc &TID = MI->getDesc();
1657 if (!TID.isTerminator()) return false;
1659 // Conditional branch is a special case.
1660 if (TID.isBranch() && !TID.isBarrier())
1662 if (!TID.isPredicable())
1664 return !isPredicated(MI);
1667 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1668 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1669 const X86InstrInfo &TII) {
1670 if (MI->getOpcode() == X86::FP_REG_KILL)
1672 return TII.isUnpredicatedTerminator(MI);
1675 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1676 MachineBasicBlock *&TBB,
1677 MachineBasicBlock *&FBB,
1678 SmallVectorImpl<MachineOperand> &Cond,
1679 bool AllowModify) const {
1680 // Start from the bottom of the block and work up, examining the
1681 // terminator instructions.
1682 MachineBasicBlock::iterator I = MBB.end();
1683 while (I != MBB.begin()) {
1686 // Working from the bottom, when we see a non-terminator instruction, we're
1688 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1691 // A terminator that isn't a branch can't easily be handled by this
1693 if (!I->getDesc().isBranch())
1696 // Handle unconditional branches.
1697 if (I->getOpcode() == X86::JMP_4) {
1699 TBB = I->getOperand(0).getMBB();
1703 // If the block has any instructions after a JMP, delete them.
1704 while (llvm::next(I) != MBB.end())
1705 llvm::next(I)->eraseFromParent();
1710 // Delete the JMP if it's equivalent to a fall-through.
1711 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1713 I->eraseFromParent();
1718 // TBB is used to indicate the unconditinal destination.
1719 TBB = I->getOperand(0).getMBB();
1723 // Handle conditional branches.
1724 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1725 if (BranchCode == X86::COND_INVALID)
1726 return true; // Can't handle indirect branch.
1728 // Working from the bottom, handle the first conditional branch.
1731 TBB = I->getOperand(0).getMBB();
1732 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1736 // Handle subsequent conditional branches. Only handle the case where all
1737 // conditional branches branch to the same destination and their condition
1738 // opcodes fit one of the special multi-branch idioms.
1739 assert(Cond.size() == 1);
1742 // Only handle the case where all conditional branches branch to the same
1744 if (TBB != I->getOperand(0).getMBB())
1747 // If the conditions are the same, we can leave them alone.
1748 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1749 if (OldBranchCode == BranchCode)
1752 // If they differ, see if they fit one of the known patterns. Theoretically,
1753 // we could handle more patterns here, but we shouldn't expect to see them
1754 // if instruction selection has done a reasonable job.
1755 if ((OldBranchCode == X86::COND_NP &&
1756 BranchCode == X86::COND_E) ||
1757 (OldBranchCode == X86::COND_E &&
1758 BranchCode == X86::COND_NP))
1759 BranchCode = X86::COND_NP_OR_E;
1760 else if ((OldBranchCode == X86::COND_P &&
1761 BranchCode == X86::COND_NE) ||
1762 (OldBranchCode == X86::COND_NE &&
1763 BranchCode == X86::COND_P))
1764 BranchCode = X86::COND_NE_OR_P;
1768 // Update the MachineOperand.
1769 Cond[0].setImm(BranchCode);
1775 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1776 MachineBasicBlock::iterator I = MBB.end();
1779 while (I != MBB.begin()) {
1781 if (I->getOpcode() != X86::JMP_4 &&
1782 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1784 // Remove the branch.
1785 I->eraseFromParent();
1794 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1795 MachineBasicBlock *FBB,
1796 const SmallVectorImpl<MachineOperand> &Cond) const {
1797 // FIXME this should probably have a DebugLoc operand
1798 DebugLoc dl = DebugLoc::getUnknownLoc();
1799 // Shouldn't be a fall through.
1800 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1801 assert((Cond.size() == 1 || Cond.size() == 0) &&
1802 "X86 branch conditions have one component!");
1805 // Unconditional branch?
1806 assert(!FBB && "Unconditional branch with multiple successors!");
1807 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
1811 // Conditional branch.
1813 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1815 case X86::COND_NP_OR_E:
1816 // Synthesize NP_OR_E with two branches.
1817 BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
1819 BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
1822 case X86::COND_NE_OR_P:
1823 // Synthesize NE_OR_P with two branches.
1824 BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
1826 BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
1830 unsigned Opc = GetCondBranchFromCond(CC);
1831 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1836 // Two-way Conditional branch. Insert the second branch.
1837 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
1843 /// isHReg - Test if the given register is a physical h register.
1844 static bool isHReg(unsigned Reg) {
1845 return X86::GR8_ABCD_HRegClass.contains(Reg);
1848 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1849 MachineBasicBlock::iterator MI,
1850 unsigned DestReg, unsigned SrcReg,
1851 const TargetRegisterClass *DestRC,
1852 const TargetRegisterClass *SrcRC) const {
1853 DebugLoc DL = MBB.findDebugLoc(MI);
1855 // Determine if DstRC and SrcRC have a common superclass in common.
1856 const TargetRegisterClass *CommonRC = DestRC;
1857 if (DestRC == SrcRC)
1858 /* Source and destination have the same register class. */;
1859 else if (CommonRC->hasSuperClass(SrcRC))
1861 else if (!DestRC->hasSubClass(SrcRC)) {
1862 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1863 // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1864 // GR32_NOSP, copy as GR32.
1865 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1866 DestRC->hasSuperClass(&X86::GR64RegClass))
1867 CommonRC = &X86::GR64RegClass;
1868 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1869 DestRC->hasSuperClass(&X86::GR32RegClass))
1870 CommonRC = &X86::GR32RegClass;
1877 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1879 } else if (CommonRC == &X86::GR32RegClass ||
1880 CommonRC == &X86::GR32_NOSPRegClass) {
1882 } else if (CommonRC == &X86::GR16RegClass) {
1884 } else if (CommonRC == &X86::GR8RegClass) {
1885 // Copying to or from a physical H register on x86-64 requires a NOREX
1886 // move. Otherwise use a normal move.
1887 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1888 TM.getSubtarget<X86Subtarget>().is64Bit())
1889 Opc = X86::MOV8rr_NOREX;
1892 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1894 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1896 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1898 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1900 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1901 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1902 Opc = X86::MOV8rr_NOREX;
1905 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1906 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1908 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1910 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1912 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1914 } else if (CommonRC == &X86::RFP32RegClass) {
1915 Opc = X86::MOV_Fp3232;
1916 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1917 Opc = X86::MOV_Fp6464;
1918 } else if (CommonRC == &X86::RFP80RegClass) {
1919 Opc = X86::MOV_Fp8080;
1920 } else if (CommonRC == &X86::FR32RegClass) {
1921 Opc = X86::FsMOVAPSrr;
1922 } else if (CommonRC == &X86::FR64RegClass) {
1923 Opc = X86::FsMOVAPDrr;
1924 } else if (CommonRC == &X86::VR128RegClass) {
1925 Opc = X86::MOVAPSrr;
1926 } else if (CommonRC == &X86::VR64RegClass) {
1927 Opc = X86::MMX_MOVQ64rr;
1931 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1935 // Moving EFLAGS to / from another register requires a push and a pop.
1936 if (SrcRC == &X86::CCRRegClass) {
1937 if (SrcReg != X86::EFLAGS)
1939 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1940 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
1941 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1943 } else if (DestRC == &X86::GR32RegClass ||
1944 DestRC == &X86::GR32_NOSPRegClass) {
1945 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1946 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1949 } else if (DestRC == &X86::CCRRegClass) {
1950 if (DestReg != X86::EFLAGS)
1952 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1953 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1954 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1956 } else if (SrcRC == &X86::GR32RegClass ||
1957 DestRC == &X86::GR32_NOSPRegClass) {
1958 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1959 BuildMI(MBB, MI, DL, get(X86::POPFD));
1964 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1965 if (SrcRC == &X86::RSTRegClass) {
1966 // Copying from ST(0)/ST(1).
1967 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1968 // Can only copy from ST(0)/ST(1) right now
1970 bool isST0 = SrcReg == X86::ST0;
1972 if (DestRC == &X86::RFP32RegClass)
1973 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1974 else if (DestRC == &X86::RFP64RegClass)
1975 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1977 if (DestRC != &X86::RFP80RegClass)
1979 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1981 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1985 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1986 if (DestRC == &X86::RSTRegClass) {
1987 // Copying to ST(0) / ST(1).
1988 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1989 // Can only copy to TOS right now
1991 bool isST0 = DestReg == X86::ST0;
1993 if (SrcRC == &X86::RFP32RegClass)
1994 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1995 else if (SrcRC == &X86::RFP64RegClass)
1996 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1998 if (SrcRC != &X86::RFP80RegClass)
2000 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
2002 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
2006 // Not yet supported!
2010 static unsigned getStoreRegOpcode(unsigned SrcReg,
2011 const TargetRegisterClass *RC,
2012 bool isStackAligned,
2013 TargetMachine &TM) {
2015 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2017 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2019 } else if (RC == &X86::GR16RegClass) {
2021 } else if (RC == &X86::GR8RegClass) {
2022 // Copying to or from a physical H register on x86-64 requires a NOREX
2023 // move. Otherwise use a normal move.
2024 if (isHReg(SrcReg) &&
2025 TM.getSubtarget<X86Subtarget>().is64Bit())
2026 Opc = X86::MOV8mr_NOREX;
2029 } else if (RC == &X86::GR64_ABCDRegClass) {
2031 } else if (RC == &X86::GR32_ABCDRegClass) {
2033 } else if (RC == &X86::GR16_ABCDRegClass) {
2035 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2037 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2038 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2039 Opc = X86::MOV8mr_NOREX;
2042 } else if (RC == &X86::GR64_NOREXRegClass ||
2043 RC == &X86::GR64_NOREX_NOSPRegClass) {
2045 } else if (RC == &X86::GR32_NOREXRegClass) {
2047 } else if (RC == &X86::GR16_NOREXRegClass) {
2049 } else if (RC == &X86::GR8_NOREXRegClass) {
2051 } else if (RC == &X86::RFP80RegClass) {
2052 Opc = X86::ST_FpP80m; // pops
2053 } else if (RC == &X86::RFP64RegClass) {
2054 Opc = X86::ST_Fp64m;
2055 } else if (RC == &X86::RFP32RegClass) {
2056 Opc = X86::ST_Fp32m;
2057 } else if (RC == &X86::FR32RegClass) {
2059 } else if (RC == &X86::FR64RegClass) {
2061 } else if (RC == &X86::VR128RegClass) {
2062 // If stack is realigned we can use aligned stores.
2063 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
2064 } else if (RC == &X86::VR64RegClass) {
2065 Opc = X86::MMX_MOVQ64mr;
2067 llvm_unreachable("Unknown regclass");
2073 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2074 MachineBasicBlock::iterator MI,
2075 unsigned SrcReg, bool isKill, int FrameIdx,
2076 const TargetRegisterClass *RC) const {
2077 const MachineFunction &MF = *MBB.getParent();
2078 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2079 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2080 DebugLoc DL = MBB.findDebugLoc(MI);
2081 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2082 .addReg(SrcReg, getKillRegState(isKill));
2085 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2087 SmallVectorImpl<MachineOperand> &Addr,
2088 const TargetRegisterClass *RC,
2089 MachineInstr::mmo_iterator MMOBegin,
2090 MachineInstr::mmo_iterator MMOEnd,
2091 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2092 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2093 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2094 DebugLoc DL = DebugLoc::getUnknownLoc();
2095 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2096 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2097 MIB.addOperand(Addr[i]);
2098 MIB.addReg(SrcReg, getKillRegState(isKill));
2099 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2100 NewMIs.push_back(MIB);
2103 static unsigned getLoadRegOpcode(unsigned DestReg,
2104 const TargetRegisterClass *RC,
2105 bool isStackAligned,
2106 const TargetMachine &TM) {
2108 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2110 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2112 } else if (RC == &X86::GR16RegClass) {
2114 } else if (RC == &X86::GR8RegClass) {
2115 // Copying to or from a physical H register on x86-64 requires a NOREX
2116 // move. Otherwise use a normal move.
2117 if (isHReg(DestReg) &&
2118 TM.getSubtarget<X86Subtarget>().is64Bit())
2119 Opc = X86::MOV8rm_NOREX;
2122 } else if (RC == &X86::GR64_ABCDRegClass) {
2124 } else if (RC == &X86::GR32_ABCDRegClass) {
2126 } else if (RC == &X86::GR16_ABCDRegClass) {
2128 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2130 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2131 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2132 Opc = X86::MOV8rm_NOREX;
2135 } else if (RC == &X86::GR64_NOREXRegClass ||
2136 RC == &X86::GR64_NOREX_NOSPRegClass) {
2138 } else if (RC == &X86::GR32_NOREXRegClass) {
2140 } else if (RC == &X86::GR16_NOREXRegClass) {
2142 } else if (RC == &X86::GR8_NOREXRegClass) {
2144 } else if (RC == &X86::RFP80RegClass) {
2145 Opc = X86::LD_Fp80m;
2146 } else if (RC == &X86::RFP64RegClass) {
2147 Opc = X86::LD_Fp64m;
2148 } else if (RC == &X86::RFP32RegClass) {
2149 Opc = X86::LD_Fp32m;
2150 } else if (RC == &X86::FR32RegClass) {
2152 } else if (RC == &X86::FR64RegClass) {
2154 } else if (RC == &X86::VR128RegClass) {
2155 // If stack is realigned we can use aligned loads.
2156 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2157 } else if (RC == &X86::VR64RegClass) {
2158 Opc = X86::MMX_MOVQ64rm;
2160 llvm_unreachable("Unknown regclass");
2166 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2167 MachineBasicBlock::iterator MI,
2168 unsigned DestReg, int FrameIdx,
2169 const TargetRegisterClass *RC) const{
2170 const MachineFunction &MF = *MBB.getParent();
2171 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2172 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2173 DebugLoc DL = MBB.findDebugLoc(MI);
2174 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2177 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2178 SmallVectorImpl<MachineOperand> &Addr,
2179 const TargetRegisterClass *RC,
2180 MachineInstr::mmo_iterator MMOBegin,
2181 MachineInstr::mmo_iterator MMOEnd,
2182 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2183 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2184 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2185 DebugLoc DL = DebugLoc::getUnknownLoc();
2186 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2187 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2188 MIB.addOperand(Addr[i]);
2189 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2190 NewMIs.push_back(MIB);
2193 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2194 MachineBasicBlock::iterator MI,
2195 const std::vector<CalleeSavedInfo> &CSI) const {
2199 DebugLoc DL = MBB.findDebugLoc(MI);
2201 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2202 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2203 unsigned SlotSize = is64Bit ? 8 : 4;
2205 MachineFunction &MF = *MBB.getParent();
2206 unsigned FPReg = RI.getFrameRegister(MF);
2207 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2208 unsigned CalleeFrameSize = 0;
2210 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2211 for (unsigned i = CSI.size(); i != 0; --i) {
2212 unsigned Reg = CSI[i-1].getReg();
2213 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2214 // Add the callee-saved register as live-in. It's killed at the spill.
2217 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2219 if (RegClass != &X86::VR128RegClass && !isWin64) {
2220 CalleeFrameSize += SlotSize;
2221 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2223 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2227 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2231 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2232 MachineBasicBlock::iterator MI,
2233 const std::vector<CalleeSavedInfo> &CSI) const {
2237 DebugLoc DL = MBB.findDebugLoc(MI);
2239 MachineFunction &MF = *MBB.getParent();
2240 unsigned FPReg = RI.getFrameRegister(MF);
2241 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2242 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2243 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2244 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2245 unsigned Reg = CSI[i].getReg();
2247 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2249 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2250 if (RegClass != &X86::VR128RegClass && !isWin64) {
2251 BuildMI(MBB, MI, DL, get(Opc), Reg);
2253 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2259 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2260 const SmallVectorImpl<MachineOperand> &MOs,
2262 const TargetInstrInfo &TII) {
2263 // Create the base instruction with the memory operand as the first part.
2264 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2265 MI->getDebugLoc(), true);
2266 MachineInstrBuilder MIB(NewMI);
2267 unsigned NumAddrOps = MOs.size();
2268 for (unsigned i = 0; i != NumAddrOps; ++i)
2269 MIB.addOperand(MOs[i]);
2270 if (NumAddrOps < 4) // FrameIndex only
2273 // Loop over the rest of the ri operands, converting them over.
2274 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2275 for (unsigned i = 0; i != NumOps; ++i) {
2276 MachineOperand &MO = MI->getOperand(i+2);
2279 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2280 MachineOperand &MO = MI->getOperand(i);
2286 static MachineInstr *FuseInst(MachineFunction &MF,
2287 unsigned Opcode, unsigned OpNo,
2288 const SmallVectorImpl<MachineOperand> &MOs,
2289 MachineInstr *MI, const TargetInstrInfo &TII) {
2290 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2291 MI->getDebugLoc(), true);
2292 MachineInstrBuilder MIB(NewMI);
2294 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2295 MachineOperand &MO = MI->getOperand(i);
2297 assert(MO.isReg() && "Expected to fold into reg operand!");
2298 unsigned NumAddrOps = MOs.size();
2299 for (unsigned i = 0; i != NumAddrOps; ++i)
2300 MIB.addOperand(MOs[i]);
2301 if (NumAddrOps < 4) // FrameIndex only
2310 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2311 const SmallVectorImpl<MachineOperand> &MOs,
2313 MachineFunction &MF = *MI->getParent()->getParent();
2314 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2316 unsigned NumAddrOps = MOs.size();
2317 for (unsigned i = 0; i != NumAddrOps; ++i)
2318 MIB.addOperand(MOs[i]);
2319 if (NumAddrOps < 4) // FrameIndex only
2321 return MIB.addImm(0);
2325 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2326 MachineInstr *MI, unsigned i,
2327 const SmallVectorImpl<MachineOperand> &MOs,
2328 unsigned Size, unsigned Align) const {
2329 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2330 bool isTwoAddrFold = false;
2331 unsigned NumOps = MI->getDesc().getNumOperands();
2332 bool isTwoAddr = NumOps > 1 &&
2333 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2335 MachineInstr *NewMI = NULL;
2336 // Folding a memory location into the two-address part of a two-address
2337 // instruction is different than folding it other places. It requires
2338 // replacing the *two* registers with the memory location.
2339 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2340 MI->getOperand(0).isReg() &&
2341 MI->getOperand(1).isReg() &&
2342 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2343 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2344 isTwoAddrFold = true;
2345 } else if (i == 0) { // If operand 0
2346 if (MI->getOpcode() == X86::MOV64r0)
2347 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2348 else if (MI->getOpcode() == X86::MOV32r0)
2349 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2350 else if (MI->getOpcode() == X86::MOV16r0)
2351 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2352 else if (MI->getOpcode() == X86::MOV8r0)
2353 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2357 OpcodeTablePtr = &RegOp2MemOpTable0;
2358 } else if (i == 1) {
2359 OpcodeTablePtr = &RegOp2MemOpTable1;
2360 } else if (i == 2) {
2361 OpcodeTablePtr = &RegOp2MemOpTable2;
2364 // If table selected...
2365 if (OpcodeTablePtr) {
2366 // Find the Opcode to fuse
2367 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2368 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2369 if (I != OpcodeTablePtr->end()) {
2370 unsigned Opcode = I->second.first;
2371 unsigned MinAlign = I->second.second;
2372 if (Align < MinAlign)
2374 bool NarrowToMOV32rm = false;
2376 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2377 if (Size < RCSize) {
2378 // Check if it's safe to fold the load. If the size of the object is
2379 // narrower than the load width, then it's not.
2380 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2382 // If this is a 64-bit load, but the spill slot is 32, then we can do
2383 // a 32-bit load which is implicitly zero-extended. This likely is due
2384 // to liveintervalanalysis remat'ing a load from stack slot.
2385 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2387 Opcode = X86::MOV32rm;
2388 NarrowToMOV32rm = true;
2393 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2395 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2397 if (NarrowToMOV32rm) {
2398 // If this is the special case where we use a MOV32rm to load a 32-bit
2399 // value and zero-extend the top bits. Change the destination register
2401 unsigned DstReg = NewMI->getOperand(0).getReg();
2402 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2403 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2404 4/*x86_subreg_32bit*/));
2406 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2413 if (PrintFailedFusing)
2414 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2419 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2421 const SmallVectorImpl<unsigned> &Ops,
2422 int FrameIndex) const {
2423 // Check switch flag
2424 if (NoFusing) return NULL;
2426 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2427 switch (MI->getOpcode()) {
2428 case X86::CVTSD2SSrr:
2429 case X86::Int_CVTSD2SSrr:
2430 case X86::CVTSS2SDrr:
2431 case X86::Int_CVTSS2SDrr:
2433 case X86::RCPSSr_Int:
2434 case X86::ROUNDSDr_Int:
2435 case X86::ROUNDSSr_Int:
2437 case X86::RSQRTSSr_Int:
2439 case X86::SQRTSSr_Int:
2443 const MachineFrameInfo *MFI = MF.getFrameInfo();
2444 unsigned Size = MFI->getObjectSize(FrameIndex);
2445 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2446 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2447 unsigned NewOpc = 0;
2448 unsigned RCSize = 0;
2449 switch (MI->getOpcode()) {
2450 default: return NULL;
2451 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2452 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2453 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2454 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2456 // Check if it's safe to fold the load. If the size of the object is
2457 // narrower than the load width, then it's not.
2460 // Change to CMPXXri r, 0 first.
2461 MI->setDesc(get(NewOpc));
2462 MI->getOperand(1).ChangeToImmediate(0);
2463 } else if (Ops.size() != 1)
2466 SmallVector<MachineOperand,4> MOs;
2467 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2468 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2471 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2473 const SmallVectorImpl<unsigned> &Ops,
2474 MachineInstr *LoadMI) const {
2475 // Check switch flag
2476 if (NoFusing) return NULL;
2478 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2479 switch (MI->getOpcode()) {
2480 case X86::CVTSD2SSrr:
2481 case X86::Int_CVTSD2SSrr:
2482 case X86::CVTSS2SDrr:
2483 case X86::Int_CVTSS2SDrr:
2485 case X86::RCPSSr_Int:
2486 case X86::ROUNDSDr_Int:
2487 case X86::ROUNDSSr_Int:
2489 case X86::RSQRTSSr_Int:
2491 case X86::SQRTSSr_Int:
2495 // Determine the alignment of the load.
2496 unsigned Alignment = 0;
2497 if (LoadMI->hasOneMemOperand())
2498 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2500 switch (LoadMI->getOpcode()) {
2502 case X86::V_SETALLONES:
2512 llvm_unreachable("Don't know how to fold this instruction!");
2514 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2515 unsigned NewOpc = 0;
2516 switch (MI->getOpcode()) {
2517 default: return NULL;
2518 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2519 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2520 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2521 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2523 // Change to CMPXXri r, 0 first.
2524 MI->setDesc(get(NewOpc));
2525 MI->getOperand(1).ChangeToImmediate(0);
2526 } else if (Ops.size() != 1)
2529 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2530 switch (LoadMI->getOpcode()) {
2532 case X86::V_SETALLONES:
2534 case X86::FsFLD0SS: {
2535 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2536 // Create a constant-pool entry and operands to load from it.
2538 // x86-32 PIC requires a PIC base register for constant pools.
2539 unsigned PICBase = 0;
2540 if (TM.getRelocationModel() == Reloc::PIC_) {
2541 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2544 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2545 // This doesn't work for several reasons.
2546 // 1. GlobalBaseReg may have been spilled.
2547 // 2. It may not be live at MI.
2551 // Create a constant-pool entry.
2552 MachineConstantPool &MCP = *MF.getConstantPool();
2554 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2555 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2556 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2557 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2559 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2560 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2561 Constant::getAllOnesValue(Ty) :
2562 Constant::getNullValue(Ty);
2563 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2565 // Create operands to load from the constant pool entry.
2566 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2567 MOs.push_back(MachineOperand::CreateImm(1));
2568 MOs.push_back(MachineOperand::CreateReg(0, false));
2569 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2570 MOs.push_back(MachineOperand::CreateReg(0, false));
2574 // Folding a normal load. Just copy the load's address operands.
2575 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2576 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2577 MOs.push_back(LoadMI->getOperand(i));
2581 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2585 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2586 const SmallVectorImpl<unsigned> &Ops) const {
2587 // Check switch flag
2588 if (NoFusing) return 0;
2590 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2591 switch (MI->getOpcode()) {
2592 default: return false;
2601 if (Ops.size() != 1)
2604 unsigned OpNum = Ops[0];
2605 unsigned Opc = MI->getOpcode();
2606 unsigned NumOps = MI->getDesc().getNumOperands();
2607 bool isTwoAddr = NumOps > 1 &&
2608 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2610 // Folding a memory location into the two-address part of a two-address
2611 // instruction is different than folding it other places. It requires
2612 // replacing the *two* registers with the memory location.
2613 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2614 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2615 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2616 } else if (OpNum == 0) { // If operand 0
2625 OpcodeTablePtr = &RegOp2MemOpTable0;
2626 } else if (OpNum == 1) {
2627 OpcodeTablePtr = &RegOp2MemOpTable1;
2628 } else if (OpNum == 2) {
2629 OpcodeTablePtr = &RegOp2MemOpTable2;
2632 if (OpcodeTablePtr) {
2633 // Find the Opcode to fuse
2634 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2635 OpcodeTablePtr->find((unsigned*)Opc);
2636 if (I != OpcodeTablePtr->end())
2642 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2643 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2644 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2645 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2646 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2647 if (I == MemOp2RegOpTable.end())
2649 unsigned Opc = I->second.first;
2650 unsigned Index = I->second.second & 0xf;
2651 bool FoldedLoad = I->second.second & (1 << 4);
2652 bool FoldedStore = I->second.second & (1 << 5);
2653 if (UnfoldLoad && !FoldedLoad)
2655 UnfoldLoad &= FoldedLoad;
2656 if (UnfoldStore && !FoldedStore)
2658 UnfoldStore &= FoldedStore;
2660 const TargetInstrDesc &TID = get(Opc);
2661 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2662 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2663 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2664 SmallVector<MachineOperand,2> BeforeOps;
2665 SmallVector<MachineOperand,2> AfterOps;
2666 SmallVector<MachineOperand,4> ImpOps;
2667 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2668 MachineOperand &Op = MI->getOperand(i);
2669 if (i >= Index && i < Index + X86AddrNumOperands)
2670 AddrOps.push_back(Op);
2671 else if (Op.isReg() && Op.isImplicit())
2672 ImpOps.push_back(Op);
2674 BeforeOps.push_back(Op);
2676 AfterOps.push_back(Op);
2679 // Emit the load instruction.
2681 std::pair<MachineInstr::mmo_iterator,
2682 MachineInstr::mmo_iterator> MMOs =
2683 MF.extractLoadMemRefs(MI->memoperands_begin(),
2684 MI->memoperands_end());
2685 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2687 // Address operands cannot be marked isKill.
2688 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2689 MachineOperand &MO = NewMIs[0]->getOperand(i);
2691 MO.setIsKill(false);
2696 // Emit the data processing instruction.
2697 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2698 MachineInstrBuilder MIB(DataMI);
2701 MIB.addReg(Reg, RegState::Define);
2702 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2703 MIB.addOperand(BeforeOps[i]);
2706 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2707 MIB.addOperand(AfterOps[i]);
2708 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2709 MachineOperand &MO = ImpOps[i];
2710 MIB.addReg(MO.getReg(),
2711 getDefRegState(MO.isDef()) |
2712 RegState::Implicit |
2713 getKillRegState(MO.isKill()) |
2714 getDeadRegState(MO.isDead()) |
2715 getUndefRegState(MO.isUndef()));
2717 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2718 unsigned NewOpc = 0;
2719 switch (DataMI->getOpcode()) {
2721 case X86::CMP64ri32:
2725 MachineOperand &MO0 = DataMI->getOperand(0);
2726 MachineOperand &MO1 = DataMI->getOperand(1);
2727 if (MO1.getImm() == 0) {
2728 switch (DataMI->getOpcode()) {
2730 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2731 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2732 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2733 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2735 DataMI->setDesc(get(NewOpc));
2736 MO1.ChangeToRegister(MO0.getReg(), false);
2740 NewMIs.push_back(DataMI);
2742 // Emit the store instruction.
2744 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2745 std::pair<MachineInstr::mmo_iterator,
2746 MachineInstr::mmo_iterator> MMOs =
2747 MF.extractStoreMemRefs(MI->memoperands_begin(),
2748 MI->memoperands_end());
2749 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2756 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2757 SmallVectorImpl<SDNode*> &NewNodes) const {
2758 if (!N->isMachineOpcode())
2761 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2762 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2763 if (I == MemOp2RegOpTable.end())
2765 unsigned Opc = I->second.first;
2766 unsigned Index = I->second.second & 0xf;
2767 bool FoldedLoad = I->second.second & (1 << 4);
2768 bool FoldedStore = I->second.second & (1 << 5);
2769 const TargetInstrDesc &TID = get(Opc);
2770 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2771 unsigned NumDefs = TID.NumDefs;
2772 std::vector<SDValue> AddrOps;
2773 std::vector<SDValue> BeforeOps;
2774 std::vector<SDValue> AfterOps;
2775 DebugLoc dl = N->getDebugLoc();
2776 unsigned NumOps = N->getNumOperands();
2777 for (unsigned i = 0; i != NumOps-1; ++i) {
2778 SDValue Op = N->getOperand(i);
2779 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2780 AddrOps.push_back(Op);
2781 else if (i < Index-NumDefs)
2782 BeforeOps.push_back(Op);
2783 else if (i > Index-NumDefs)
2784 AfterOps.push_back(Op);
2786 SDValue Chain = N->getOperand(NumOps-1);
2787 AddrOps.push_back(Chain);
2789 // Emit the load instruction.
2791 MachineFunction &MF = DAG.getMachineFunction();
2793 EVT VT = *RC->vt_begin();
2794 std::pair<MachineInstr::mmo_iterator,
2795 MachineInstr::mmo_iterator> MMOs =
2796 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2797 cast<MachineSDNode>(N)->memoperands_end());
2798 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2799 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2800 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2801 NewNodes.push_back(Load);
2803 // Preserve memory reference information.
2804 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2807 // Emit the data processing instruction.
2808 std::vector<EVT> VTs;
2809 const TargetRegisterClass *DstRC = 0;
2810 if (TID.getNumDefs() > 0) {
2811 DstRC = TID.OpInfo[0].getRegClass(&RI);
2812 VTs.push_back(*DstRC->vt_begin());
2814 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2815 EVT VT = N->getValueType(i);
2816 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2820 BeforeOps.push_back(SDValue(Load, 0));
2821 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2822 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2824 NewNodes.push_back(NewNode);
2826 // Emit the store instruction.
2829 AddrOps.push_back(SDValue(NewNode, 0));
2830 AddrOps.push_back(Chain);
2831 std::pair<MachineInstr::mmo_iterator,
2832 MachineInstr::mmo_iterator> MMOs =
2833 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2834 cast<MachineSDNode>(N)->memoperands_end());
2835 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2836 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2839 &AddrOps[0], AddrOps.size());
2840 NewNodes.push_back(Store);
2842 // Preserve memory reference information.
2843 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2849 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2850 bool UnfoldLoad, bool UnfoldStore,
2851 unsigned *LoadRegIndex) const {
2852 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2853 MemOp2RegOpTable.find((unsigned*)Opc);
2854 if (I == MemOp2RegOpTable.end())
2856 bool FoldedLoad = I->second.second & (1 << 4);
2857 bool FoldedStore = I->second.second & (1 << 5);
2858 if (UnfoldLoad && !FoldedLoad)
2860 if (UnfoldStore && !FoldedStore)
2863 *LoadRegIndex = I->second.second & 0xf;
2864 return I->second.first;
2868 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2869 int64_t &Offset1, int64_t &Offset2) const {
2870 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2872 unsigned Opc1 = Load1->getMachineOpcode();
2873 unsigned Opc2 = Load2->getMachineOpcode();
2875 default: return false;
2885 case X86::MMX_MOVD64rm:
2886 case X86::MMX_MOVQ64rm:
2887 case X86::FsMOVAPSrm:
2888 case X86::FsMOVAPDrm:
2891 case X86::MOVUPSrm_Int:
2895 case X86::MOVDQUrm_Int:
2899 default: return false;
2909 case X86::MMX_MOVD64rm:
2910 case X86::MMX_MOVQ64rm:
2911 case X86::FsMOVAPSrm:
2912 case X86::FsMOVAPDrm:
2915 case X86::MOVUPSrm_Int:
2919 case X86::MOVDQUrm_Int:
2923 // Check if chain operands and base addresses match.
2924 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2925 Load1->getOperand(5) != Load2->getOperand(5))
2927 // Segment operands should match as well.
2928 if (Load1->getOperand(4) != Load2->getOperand(4))
2930 // Scale should be 1, Index should be Reg0.
2931 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2932 Load1->getOperand(2) == Load2->getOperand(2)) {
2933 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2935 SDValue Op2 = Load1->getOperand(2);
2936 if (!isa<RegisterSDNode>(Op2) ||
2937 cast<RegisterSDNode>(Op2)->getReg() != 0)
2940 // Now let's examine the displacements.
2941 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2942 isa<ConstantSDNode>(Load2->getOperand(3))) {
2943 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2944 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2951 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2952 int64_t Offset1, int64_t Offset2,
2953 unsigned NumLoads) const {
2954 assert(Offset2 > Offset1);
2955 if ((Offset2 - Offset1) / 8 > 64)
2958 unsigned Opc1 = Load1->getMachineOpcode();
2959 unsigned Opc2 = Load2->getMachineOpcode();
2961 return false; // FIXME: overly conservative?
2968 case X86::MMX_MOVD64rm:
2969 case X86::MMX_MOVQ64rm:
2973 EVT VT = Load1->getValueType(0);
2974 switch (VT.getSimpleVT().SimpleTy) {
2976 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
2977 // have 16 of them to play with.
2978 if (TM.getSubtargetImpl()->is64Bit()) {
2981 } else if (NumLoads)
3000 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3001 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3002 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3003 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3005 Cond[0].setImm(GetOppositeBranchCondition(CC));
3010 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3011 // FIXME: Return false for x87 stack register classes for now. We can't
3012 // allow any loads of these registers before FpGet_ST0_80.
3013 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3014 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3018 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3019 /// register? e.g. r8, xmm8, xmm13, etc.
3020 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3023 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3024 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3025 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3026 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3027 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3028 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3029 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3030 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3031 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3032 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3039 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
3040 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
3041 /// size, and 3) use of X86-64 extended registers.
3042 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
3044 const TargetInstrDesc &Desc = MI.getDesc();
3046 // Pseudo instructions do not need REX prefix byte.
3047 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
3049 if (Desc.TSFlags & X86II::REX_W)
3052 unsigned NumOps = Desc.getNumOperands();
3054 bool isTwoAddr = NumOps > 1 &&
3055 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
3057 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
3058 unsigned i = isTwoAddr ? 1 : 0;
3059 for (unsigned e = NumOps; i != e; ++i) {
3060 const MachineOperand& MO = MI.getOperand(i);
3062 unsigned Reg = MO.getReg();
3063 if (isX86_64NonExtLowByteReg(Reg))
3068 switch (Desc.TSFlags & X86II::FormMask) {
3069 case X86II::MRMInitReg:
3070 if (isX86_64ExtendedReg(MI.getOperand(0)))
3071 REX |= (1 << 0) | (1 << 2);
3073 case X86II::MRMSrcReg: {
3074 if (isX86_64ExtendedReg(MI.getOperand(0)))
3076 i = isTwoAddr ? 2 : 1;
3077 for (unsigned e = NumOps; i != e; ++i) {
3078 const MachineOperand& MO = MI.getOperand(i);
3079 if (isX86_64ExtendedReg(MO))
3084 case X86II::MRMSrcMem: {
3085 if (isX86_64ExtendedReg(MI.getOperand(0)))
3088 i = isTwoAddr ? 2 : 1;
3089 for (; i != NumOps; ++i) {
3090 const MachineOperand& MO = MI.getOperand(i);
3092 if (isX86_64ExtendedReg(MO))
3099 case X86II::MRM0m: case X86II::MRM1m:
3100 case X86II::MRM2m: case X86II::MRM3m:
3101 case X86II::MRM4m: case X86II::MRM5m:
3102 case X86II::MRM6m: case X86II::MRM7m:
3103 case X86II::MRMDestMem: {
3104 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
3105 i = isTwoAddr ? 1 : 0;
3106 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
3109 for (; i != e; ++i) {
3110 const MachineOperand& MO = MI.getOperand(i);
3112 if (isX86_64ExtendedReg(MO))
3120 if (isX86_64ExtendedReg(MI.getOperand(0)))
3122 i = isTwoAddr ? 2 : 1;
3123 for (unsigned e = NumOps; i != e; ++i) {
3124 const MachineOperand& MO = MI.getOperand(i);
3125 if (isX86_64ExtendedReg(MO))
3135 /// sizePCRelativeBlockAddress - This method returns the size of a PC
3136 /// relative block address instruction
3138 static unsigned sizePCRelativeBlockAddress() {
3142 /// sizeGlobalAddress - Give the size of the emission of this global address
3144 static unsigned sizeGlobalAddress(bool dword) {
3145 return dword ? 8 : 4;
3148 /// sizeConstPoolAddress - Give the size of the emission of this constant
3151 static unsigned sizeConstPoolAddress(bool dword) {
3152 return dword ? 8 : 4;
3155 /// sizeExternalSymbolAddress - Give the size of the emission of this external
3158 static unsigned sizeExternalSymbolAddress(bool dword) {
3159 return dword ? 8 : 4;
3162 /// sizeJumpTableAddress - Give the size of the emission of this jump
3165 static unsigned sizeJumpTableAddress(bool dword) {
3166 return dword ? 8 : 4;
3169 static unsigned sizeConstant(unsigned Size) {
3173 static unsigned sizeRegModRMByte(){
3177 static unsigned sizeSIBByte(){
3181 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3182 unsigned FinalSize = 0;
3183 // If this is a simple integer displacement that doesn't require a relocation.
3185 FinalSize += sizeConstant(4);
3189 // Otherwise, this is something that requires a relocation.
3190 if (RelocOp->isGlobal()) {
3191 FinalSize += sizeGlobalAddress(false);
3192 } else if (RelocOp->isCPI()) {
3193 FinalSize += sizeConstPoolAddress(false);
3194 } else if (RelocOp->isJTI()) {
3195 FinalSize += sizeJumpTableAddress(false);
3197 llvm_unreachable("Unknown value to relocate!");
3202 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3203 bool IsPIC, bool Is64BitMode) {
3204 const MachineOperand &Op3 = MI.getOperand(Op+3);
3206 const MachineOperand *DispForReloc = 0;
3207 unsigned FinalSize = 0;
3209 // Figure out what sort of displacement we have to handle here.
3210 if (Op3.isGlobal()) {
3211 DispForReloc = &Op3;
3212 } else if (Op3.isCPI()) {
3213 if (Is64BitMode || IsPIC) {
3214 DispForReloc = &Op3;
3218 } else if (Op3.isJTI()) {
3219 if (Is64BitMode || IsPIC) {
3220 DispForReloc = &Op3;
3228 const MachineOperand &Base = MI.getOperand(Op);
3229 const MachineOperand &IndexReg = MI.getOperand(Op+2);
3231 unsigned BaseReg = Base.getReg();
3233 // Is a SIB byte needed?
3234 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3235 IndexReg.getReg() == 0 &&
3236 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3237 if (BaseReg == 0) { // Just a displacement?
3238 // Emit special case [disp32] encoding
3240 FinalSize += getDisplacementFieldSize(DispForReloc);
3242 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3243 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3244 // Emit simple indirect register encoding... [EAX] f.e.
3246 // Be pessimistic and assume it's a disp32, not a disp8
3248 // Emit the most general non-SIB encoding: [REG+disp32]
3250 FinalSize += getDisplacementFieldSize(DispForReloc);
3254 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
3255 assert(IndexReg.getReg() != X86::ESP &&
3256 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3258 bool ForceDisp32 = false;
3259 if (BaseReg == 0 || DispForReloc) {
3260 // Emit the normal disp32 encoding.
3267 FinalSize += sizeSIBByte();
3269 // Do we need to output a displacement?
3270 if (DispVal != 0 || ForceDisp32) {
3271 FinalSize += getDisplacementFieldSize(DispForReloc);
3278 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3279 const TargetInstrDesc *Desc,
3280 bool IsPIC, bool Is64BitMode) {
3282 unsigned Opcode = Desc->Opcode;
3283 unsigned FinalSize = 0;
3285 // Emit the lock opcode prefix as needed.
3286 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3288 // Emit segment override opcode prefix as needed.
3289 switch (Desc->TSFlags & X86II::SegOvrMask) {
3294 default: llvm_unreachable("Invalid segment!");
3295 case 0: break; // No segment override!
3298 // Emit the repeat opcode prefix as needed.
3299 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3301 // Emit the operand size opcode prefix as needed.
3302 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3304 // Emit the address size opcode prefix as needed.
3305 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3307 bool Need0FPrefix = false;
3308 switch (Desc->TSFlags & X86II::Op0Mask) {
3309 case X86II::TB: // Two-byte opcode prefix
3310 case X86II::T8: // 0F 38
3311 case X86II::TA: // 0F 3A
3312 Need0FPrefix = true;
3314 case X86II::TF: // F2 0F 38
3316 Need0FPrefix = true;
3318 case X86II::REP: break; // already handled.
3319 case X86II::XS: // F3 0F
3321 Need0FPrefix = true;
3323 case X86II::XD: // F2 0F
3325 Need0FPrefix = true;
3327 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3328 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3330 break; // Two-byte opcode prefix
3331 default: llvm_unreachable("Invalid prefix!");
3332 case 0: break; // No prefix!
3337 unsigned REX = X86InstrInfo::determineREX(MI);
3342 // 0x0F escape code must be emitted just before the opcode.
3346 switch (Desc->TSFlags & X86II::Op0Mask) {
3347 case X86II::T8: // 0F 38
3350 case X86II::TA: // 0F 3A
3353 case X86II::TF: // F2 0F 38
3358 // If this is a two-address instruction, skip one of the register operands.
3359 unsigned NumOps = Desc->getNumOperands();
3361 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3363 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3364 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3367 switch (Desc->TSFlags & X86II::FormMask) {
3368 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3370 // Remember the current PC offset, this is the PIC relocation
3375 case TargetOpcode::INLINEASM: {
3376 const MachineFunction *MF = MI.getParent()->getParent();
3377 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3378 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3379 *MF->getTarget().getMCAsmInfo());
3382 case TargetOpcode::DBG_LABEL:
3383 case TargetOpcode::EH_LABEL:
3385 case TargetOpcode::IMPLICIT_DEF:
3386 case TargetOpcode::KILL:
3387 case X86::FP_REG_KILL:
3389 case X86::MOVPC32r: {
3390 // This emits the "call" portion of this pseudo instruction.
3392 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3401 if (CurOp != NumOps) {
3402 const MachineOperand &MO = MI.getOperand(CurOp++);
3404 FinalSize += sizePCRelativeBlockAddress();
3405 } else if (MO.isGlobal()) {
3406 FinalSize += sizeGlobalAddress(false);
3407 } else if (MO.isSymbol()) {
3408 FinalSize += sizeExternalSymbolAddress(false);
3409 } else if (MO.isImm()) {
3410 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3412 llvm_unreachable("Unknown RawFrm operand!");
3417 case X86II::AddRegFrm:
3421 if (CurOp != NumOps) {
3422 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3423 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3425 FinalSize += sizeConstant(Size);
3428 if (Opcode == X86::MOV64ri)
3430 if (MO1.isGlobal()) {
3431 FinalSize += sizeGlobalAddress(dword);
3432 } else if (MO1.isSymbol())
3433 FinalSize += sizeExternalSymbolAddress(dword);
3434 else if (MO1.isCPI())
3435 FinalSize += sizeConstPoolAddress(dword);
3436 else if (MO1.isJTI())
3437 FinalSize += sizeJumpTableAddress(dword);
3442 case X86II::MRMDestReg: {
3444 FinalSize += sizeRegModRMByte();
3446 if (CurOp != NumOps) {
3448 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3452 case X86II::MRMDestMem: {
3454 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3455 CurOp += X86AddrNumOperands + 1;
3456 if (CurOp != NumOps) {
3458 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3463 case X86II::MRMSrcReg:
3465 FinalSize += sizeRegModRMByte();
3467 if (CurOp != NumOps) {
3469 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3473 case X86II::MRMSrcMem: {
3475 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3476 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3477 AddrOperands = X86AddrNumOperands - 1; // No segment register
3479 AddrOperands = X86AddrNumOperands;
3482 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3483 CurOp += AddrOperands + 1;
3484 if (CurOp != NumOps) {
3486 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3491 case X86II::MRM0r: case X86II::MRM1r:
3492 case X86II::MRM2r: case X86II::MRM3r:
3493 case X86II::MRM4r: case X86II::MRM5r:
3494 case X86II::MRM6r: case X86II::MRM7r:
3496 if (Desc->getOpcode() == X86::LFENCE ||
3497 Desc->getOpcode() == X86::MFENCE) {
3498 // Special handling of lfence and mfence;
3499 FinalSize += sizeRegModRMByte();
3500 } else if (Desc->getOpcode() == X86::MONITOR ||
3501 Desc->getOpcode() == X86::MWAIT) {
3502 // Special handling of monitor and mwait.
3503 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3506 FinalSize += sizeRegModRMByte();
3509 if (CurOp != NumOps) {
3510 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3511 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3513 FinalSize += sizeConstant(Size);
3516 if (Opcode == X86::MOV64ri32)
3518 if (MO1.isGlobal()) {
3519 FinalSize += sizeGlobalAddress(dword);
3520 } else if (MO1.isSymbol())
3521 FinalSize += sizeExternalSymbolAddress(dword);
3522 else if (MO1.isCPI())
3523 FinalSize += sizeConstPoolAddress(dword);
3524 else if (MO1.isJTI())
3525 FinalSize += sizeJumpTableAddress(dword);
3530 case X86II::MRM0m: case X86II::MRM1m:
3531 case X86II::MRM2m: case X86II::MRM3m:
3532 case X86II::MRM4m: case X86II::MRM5m:
3533 case X86II::MRM6m: case X86II::MRM7m: {
3536 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3537 CurOp += X86AddrNumOperands;
3539 if (CurOp != NumOps) {
3540 const MachineOperand &MO = MI.getOperand(CurOp++);
3541 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3543 FinalSize += sizeConstant(Size);
3546 if (Opcode == X86::MOV64mi32)
3548 if (MO.isGlobal()) {
3549 FinalSize += sizeGlobalAddress(dword);
3550 } else if (MO.isSymbol())
3551 FinalSize += sizeExternalSymbolAddress(dword);
3552 else if (MO.isCPI())
3553 FinalSize += sizeConstPoolAddress(dword);
3554 else if (MO.isJTI())
3555 FinalSize += sizeJumpTableAddress(dword);
3569 case X86II::MRMInitReg:
3571 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3572 FinalSize += sizeRegModRMByte();
3577 if (!Desc->isVariadic() && CurOp != NumOps) {
3579 raw_string_ostream Msg(msg);
3580 Msg << "Cannot determine size: " << MI;
3581 llvm_report_error(Msg.str());
3589 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3590 const TargetInstrDesc &Desc = MI->getDesc();
3591 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3592 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3593 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3594 if (Desc.getOpcode() == X86::MOVPC32r)
3595 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3599 /// getGlobalBaseReg - Return a virtual register initialized with the
3600 /// the global base register value. Output instructions required to
3601 /// initialize the register in the function entry block, if necessary.
3603 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3604 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3605 "X86-64 PIC uses RIP relative addressing");
3607 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3608 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3609 if (GlobalBaseReg != 0)
3610 return GlobalBaseReg;
3612 // Insert the set of GlobalBaseReg into the first MBB of the function
3613 MachineBasicBlock &FirstMBB = MF->front();
3614 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3615 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3616 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3617 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3619 const TargetInstrInfo *TII = TM.getInstrInfo();
3620 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3621 // only used in JIT code emission as displacement to pc.
3622 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3624 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3625 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3626 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3627 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3628 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3629 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3630 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3631 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3636 X86FI->setGlobalBaseReg(GlobalBaseReg);
3637 return GlobalBaseReg;