1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "X86GenInstrInfo.inc"
21 X86InstrInfo::X86InstrInfo()
22 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
26 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& destReg) const {
29 MachineOpCode oc = MI.getOpcode();
30 if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
32 assert(MI.getNumOperands() == 2 &&
33 MI.getOperand(0).isRegister() &&
34 MI.getOperand(1).isRegister() &&
35 "invalid register-register move instruction");
36 sourceReg = MI.getOperand(1).getReg();
37 destReg = MI.getOperand(0).getReg();
43 /// convertToThreeAddress - This method must be implemented by targets that
44 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
45 /// may be able to convert a two-address instruction into a true
46 /// three-address instruction on demand. This allows the X86 target (for
47 /// example) to convert ADD and SHL instructions into LEA instructions if they
48 /// would require register copies due to two-addressness.
50 /// This method returns a null pointer if the transformation cannot be
51 /// performed, otherwise it returns the new instruction.
53 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
54 // All instructions input are two-addr instructions. Get the known operands.
55 unsigned Dest = MI->getOperand(0).getReg();
56 unsigned Src = MI->getOperand(1).getReg();
58 // FIXME: None of these instructions are promotable to LEAs without
59 // additional information. In particular, LEA doesn't set the flags that
63 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
64 // we have subtarget support, enable the 16-bit LEA generation here.
65 bool DisableLEA16 = true;
67 switch (MI->getOpcode()) {
69 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
70 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
72 if (DisableLEA16) return 0;
73 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
74 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
76 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
77 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
79 if (DisableLEA16) return 0;
80 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
81 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
83 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
84 return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
85 MI->getOperand(2).getReg());
87 if (DisableLEA16) return 0;
88 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
89 return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
90 MI->getOperand(2).getReg());
92 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
93 if (MI->getOperand(2).isImmediate())
94 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
95 MI->getOperand(2).getImmedValue());
98 if (DisableLEA16) return 0;
99 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
100 if (MI->getOperand(2).isImmediate())
101 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
102 MI->getOperand(2).getImmedValue());
106 if (DisableLEA16) return 0;
108 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
109 "Unknown shl instruction!");
110 unsigned ShAmt = MI->getOperand(2).getImmedValue();
111 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
113 AM.Scale = 1 << ShAmt;
115 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
116 return addFullAddress(BuildMI(Opc, 5, Dest), AM);
125 void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
126 MachineBasicBlock& TMBB) const {
127 BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
130 MachineBasicBlock::iterator
131 X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
132 unsigned Opcode = MI->getOpcode();
133 assert(isBranch(Opcode) && "MachineInstr must be a branch");
136 default: assert(0 && "Cannot reverse unconditional branches!");
137 case X86::JB: ROpcode = X86::JAE; break;
138 case X86::JAE: ROpcode = X86::JB; break;
139 case X86::JE: ROpcode = X86::JNE; break;
140 case X86::JNE: ROpcode = X86::JE; break;
141 case X86::JBE: ROpcode = X86::JA; break;
142 case X86::JA: ROpcode = X86::JBE; break;
143 case X86::JS: ROpcode = X86::JNS; break;
144 case X86::JNS: ROpcode = X86::JS; break;
145 case X86::JP: ROpcode = X86::JNP; break;
146 case X86::JNP: ROpcode = X86::JP; break;
147 case X86::JL: ROpcode = X86::JGE; break;
148 case X86::JGE: ROpcode = X86::JL; break;
149 case X86::JLE: ROpcode = X86::JG; break;
150 case X86::JG: ROpcode = X86::JLE; break;
152 MachineBasicBlock* MBB = MI->getParent();
153 MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
154 return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);