1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/MC/MCAsmInfo.h"
43 NoFusing("disable-spill-fusing",
44 cl::desc("Disable fusing of spill code into instructions"));
46 PrintFailedFusing("print-failed-fuse-candidates",
47 cl::desc("Print instructions that the allocator wants to"
48 " fuse, but the X86 backend currently can't"),
51 ReMatPICStubLoad("remat-pic-stub-load",
52 cl::desc("Re-materialize load from stub in PIC mode"),
53 cl::init(false), cl::Hidden);
55 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
56 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
57 TM(tm), RI(tm, *this) {
58 SmallVector<unsigned,16> AmbEntries;
59 static const unsigned OpTbl2Addr[][2] = {
60 { X86::ADC32ri, X86::ADC32mi },
61 { X86::ADC32ri8, X86::ADC32mi8 },
62 { X86::ADC32rr, X86::ADC32mr },
63 { X86::ADC64ri32, X86::ADC64mi32 },
64 { X86::ADC64ri8, X86::ADC64mi8 },
65 { X86::ADC64rr, X86::ADC64mr },
66 { X86::ADD16ri, X86::ADD16mi },
67 { X86::ADD16ri8, X86::ADD16mi8 },
68 { X86::ADD16rr, X86::ADD16mr },
69 { X86::ADD32ri, X86::ADD32mi },
70 { X86::ADD32ri8, X86::ADD32mi8 },
71 { X86::ADD32rr, X86::ADD32mr },
72 { X86::ADD64ri32, X86::ADD64mi32 },
73 { X86::ADD64ri8, X86::ADD64mi8 },
74 { X86::ADD64rr, X86::ADD64mr },
75 { X86::ADD8ri, X86::ADD8mi },
76 { X86::ADD8rr, X86::ADD8mr },
77 { X86::AND16ri, X86::AND16mi },
78 { X86::AND16ri8, X86::AND16mi8 },
79 { X86::AND16rr, X86::AND16mr },
80 { X86::AND32ri, X86::AND32mi },
81 { X86::AND32ri8, X86::AND32mi8 },
82 { X86::AND32rr, X86::AND32mr },
83 { X86::AND64ri32, X86::AND64mi32 },
84 { X86::AND64ri8, X86::AND64mi8 },
85 { X86::AND64rr, X86::AND64mr },
86 { X86::AND8ri, X86::AND8mi },
87 { X86::AND8rr, X86::AND8mr },
88 { X86::DEC16r, X86::DEC16m },
89 { X86::DEC32r, X86::DEC32m },
90 { X86::DEC64_16r, X86::DEC64_16m },
91 { X86::DEC64_32r, X86::DEC64_32m },
92 { X86::DEC64r, X86::DEC64m },
93 { X86::DEC8r, X86::DEC8m },
94 { X86::INC16r, X86::INC16m },
95 { X86::INC32r, X86::INC32m },
96 { X86::INC64_16r, X86::INC64_16m },
97 { X86::INC64_32r, X86::INC64_32m },
98 { X86::INC64r, X86::INC64m },
99 { X86::INC8r, X86::INC8m },
100 { X86::NEG16r, X86::NEG16m },
101 { X86::NEG32r, X86::NEG32m },
102 { X86::NEG64r, X86::NEG64m },
103 { X86::NEG8r, X86::NEG8m },
104 { X86::NOT16r, X86::NOT16m },
105 { X86::NOT32r, X86::NOT32m },
106 { X86::NOT64r, X86::NOT64m },
107 { X86::NOT8r, X86::NOT8m },
108 { X86::OR16ri, X86::OR16mi },
109 { X86::OR16ri8, X86::OR16mi8 },
110 { X86::OR16rr, X86::OR16mr },
111 { X86::OR32ri, X86::OR32mi },
112 { X86::OR32ri8, X86::OR32mi8 },
113 { X86::OR32rr, X86::OR32mr },
114 { X86::OR64ri32, X86::OR64mi32 },
115 { X86::OR64ri8, X86::OR64mi8 },
116 { X86::OR64rr, X86::OR64mr },
117 { X86::OR8ri, X86::OR8mi },
118 { X86::OR8rr, X86::OR8mr },
119 { X86::ROL16r1, X86::ROL16m1 },
120 { X86::ROL16rCL, X86::ROL16mCL },
121 { X86::ROL16ri, X86::ROL16mi },
122 { X86::ROL32r1, X86::ROL32m1 },
123 { X86::ROL32rCL, X86::ROL32mCL },
124 { X86::ROL32ri, X86::ROL32mi },
125 { X86::ROL64r1, X86::ROL64m1 },
126 { X86::ROL64rCL, X86::ROL64mCL },
127 { X86::ROL64ri, X86::ROL64mi },
128 { X86::ROL8r1, X86::ROL8m1 },
129 { X86::ROL8rCL, X86::ROL8mCL },
130 { X86::ROL8ri, X86::ROL8mi },
131 { X86::ROR16r1, X86::ROR16m1 },
132 { X86::ROR16rCL, X86::ROR16mCL },
133 { X86::ROR16ri, X86::ROR16mi },
134 { X86::ROR32r1, X86::ROR32m1 },
135 { X86::ROR32rCL, X86::ROR32mCL },
136 { X86::ROR32ri, X86::ROR32mi },
137 { X86::ROR64r1, X86::ROR64m1 },
138 { X86::ROR64rCL, X86::ROR64mCL },
139 { X86::ROR64ri, X86::ROR64mi },
140 { X86::ROR8r1, X86::ROR8m1 },
141 { X86::ROR8rCL, X86::ROR8mCL },
142 { X86::ROR8ri, X86::ROR8mi },
143 { X86::SAR16r1, X86::SAR16m1 },
144 { X86::SAR16rCL, X86::SAR16mCL },
145 { X86::SAR16ri, X86::SAR16mi },
146 { X86::SAR32r1, X86::SAR32m1 },
147 { X86::SAR32rCL, X86::SAR32mCL },
148 { X86::SAR32ri, X86::SAR32mi },
149 { X86::SAR64r1, X86::SAR64m1 },
150 { X86::SAR64rCL, X86::SAR64mCL },
151 { X86::SAR64ri, X86::SAR64mi },
152 { X86::SAR8r1, X86::SAR8m1 },
153 { X86::SAR8rCL, X86::SAR8mCL },
154 { X86::SAR8ri, X86::SAR8mi },
155 { X86::SBB32ri, X86::SBB32mi },
156 { X86::SBB32ri8, X86::SBB32mi8 },
157 { X86::SBB32rr, X86::SBB32mr },
158 { X86::SBB64ri32, X86::SBB64mi32 },
159 { X86::SBB64ri8, X86::SBB64mi8 },
160 { X86::SBB64rr, X86::SBB64mr },
161 { X86::SHL16rCL, X86::SHL16mCL },
162 { X86::SHL16ri, X86::SHL16mi },
163 { X86::SHL32rCL, X86::SHL32mCL },
164 { X86::SHL32ri, X86::SHL32mi },
165 { X86::SHL64rCL, X86::SHL64mCL },
166 { X86::SHL64ri, X86::SHL64mi },
167 { X86::SHL8rCL, X86::SHL8mCL },
168 { X86::SHL8ri, X86::SHL8mi },
169 { X86::SHLD16rrCL, X86::SHLD16mrCL },
170 { X86::SHLD16rri8, X86::SHLD16mri8 },
171 { X86::SHLD32rrCL, X86::SHLD32mrCL },
172 { X86::SHLD32rri8, X86::SHLD32mri8 },
173 { X86::SHLD64rrCL, X86::SHLD64mrCL },
174 { X86::SHLD64rri8, X86::SHLD64mri8 },
175 { X86::SHR16r1, X86::SHR16m1 },
176 { X86::SHR16rCL, X86::SHR16mCL },
177 { X86::SHR16ri, X86::SHR16mi },
178 { X86::SHR32r1, X86::SHR32m1 },
179 { X86::SHR32rCL, X86::SHR32mCL },
180 { X86::SHR32ri, X86::SHR32mi },
181 { X86::SHR64r1, X86::SHR64m1 },
182 { X86::SHR64rCL, X86::SHR64mCL },
183 { X86::SHR64ri, X86::SHR64mi },
184 { X86::SHR8r1, X86::SHR8m1 },
185 { X86::SHR8rCL, X86::SHR8mCL },
186 { X86::SHR8ri, X86::SHR8mi },
187 { X86::SHRD16rrCL, X86::SHRD16mrCL },
188 { X86::SHRD16rri8, X86::SHRD16mri8 },
189 { X86::SHRD32rrCL, X86::SHRD32mrCL },
190 { X86::SHRD32rri8, X86::SHRD32mri8 },
191 { X86::SHRD64rrCL, X86::SHRD64mrCL },
192 { X86::SHRD64rri8, X86::SHRD64mri8 },
193 { X86::SUB16ri, X86::SUB16mi },
194 { X86::SUB16ri8, X86::SUB16mi8 },
195 { X86::SUB16rr, X86::SUB16mr },
196 { X86::SUB32ri, X86::SUB32mi },
197 { X86::SUB32ri8, X86::SUB32mi8 },
198 { X86::SUB32rr, X86::SUB32mr },
199 { X86::SUB64ri32, X86::SUB64mi32 },
200 { X86::SUB64ri8, X86::SUB64mi8 },
201 { X86::SUB64rr, X86::SUB64mr },
202 { X86::SUB8ri, X86::SUB8mi },
203 { X86::SUB8rr, X86::SUB8mr },
204 { X86::XOR16ri, X86::XOR16mi },
205 { X86::XOR16ri8, X86::XOR16mi8 },
206 { X86::XOR16rr, X86::XOR16mr },
207 { X86::XOR32ri, X86::XOR32mi },
208 { X86::XOR32ri8, X86::XOR32mi8 },
209 { X86::XOR32rr, X86::XOR32mr },
210 { X86::XOR64ri32, X86::XOR64mi32 },
211 { X86::XOR64ri8, X86::XOR64mi8 },
212 { X86::XOR64rr, X86::XOR64mr },
213 { X86::XOR8ri, X86::XOR8mi },
214 { X86::XOR8rr, X86::XOR8mr }
217 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
218 unsigned RegOp = OpTbl2Addr[i][0];
219 unsigned MemOp = OpTbl2Addr[i][1];
220 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
221 std::make_pair(MemOp,0))).second)
222 assert(false && "Duplicated entries?");
223 // Index 0, folded load and store, no alignment requirement.
224 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
225 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
226 std::make_pair(RegOp,
228 AmbEntries.push_back(MemOp);
231 // If the third value is 1, then it's folding either a load or a store.
232 static const unsigned OpTbl0[][4] = {
233 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
234 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
235 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
236 { X86::CALL32r, X86::CALL32m, 1, 0 },
237 { X86::CALL64r, X86::CALL64m, 1, 0 },
238 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
239 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
240 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
241 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
242 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
243 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
244 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
245 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
246 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
247 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
248 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
249 { X86::DIV16r, X86::DIV16m, 1, 0 },
250 { X86::DIV32r, X86::DIV32m, 1, 0 },
251 { X86::DIV64r, X86::DIV64m, 1, 0 },
252 { X86::DIV8r, X86::DIV8m, 1, 0 },
253 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
254 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
255 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
256 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
257 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
258 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
259 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
260 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
261 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
262 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
263 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
264 { X86::JMP32r, X86::JMP32m, 1, 0 },
265 { X86::JMP64r, X86::JMP64m, 1, 0 },
266 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
267 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
268 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
269 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
270 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 },
271 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
272 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
273 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
274 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
275 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
276 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
277 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
278 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
279 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
280 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
281 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
282 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
285 { X86::MUL16r, X86::MUL16m, 1, 0 },
286 { X86::MUL32r, X86::MUL32m, 1, 0 },
287 { X86::MUL64r, X86::MUL64m, 1, 0 },
288 { X86::MUL8r, X86::MUL8m, 1, 0 },
289 { X86::SETAEr, X86::SETAEm, 0, 0 },
290 { X86::SETAr, X86::SETAm, 0, 0 },
291 { X86::SETBEr, X86::SETBEm, 0, 0 },
292 { X86::SETBr, X86::SETBm, 0, 0 },
293 { X86::SETEr, X86::SETEm, 0, 0 },
294 { X86::SETGEr, X86::SETGEm, 0, 0 },
295 { X86::SETGr, X86::SETGm, 0, 0 },
296 { X86::SETLEr, X86::SETLEm, 0, 0 },
297 { X86::SETLr, X86::SETLm, 0, 0 },
298 { X86::SETNEr, X86::SETNEm, 0, 0 },
299 { X86::SETNOr, X86::SETNOm, 0, 0 },
300 { X86::SETNPr, X86::SETNPm, 0, 0 },
301 { X86::SETNSr, X86::SETNSm, 0, 0 },
302 { X86::SETOr, X86::SETOm, 0, 0 },
303 { X86::SETPr, X86::SETPm, 0, 0 },
304 { X86::SETSr, X86::SETSm, 0, 0 },
305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
306 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
307 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
308 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
309 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
310 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
314 unsigned RegOp = OpTbl0[i][0];
315 unsigned MemOp = OpTbl0[i][1];
316 unsigned Align = OpTbl0[i][3];
317 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
318 std::make_pair(MemOp,Align))).second)
319 assert(false && "Duplicated entries?");
320 unsigned FoldedLoad = OpTbl0[i][2];
321 // Index 0, folded load or store.
322 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
323 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
324 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
325 std::make_pair(RegOp, AuxInfo))).second)
326 AmbEntries.push_back(MemOp);
329 static const unsigned OpTbl1[][3] = {
330 { X86::CMP16rr, X86::CMP16rm, 0 },
331 { X86::CMP32rr, X86::CMP32rm, 0 },
332 { X86::CMP64rr, X86::CMP64rm, 0 },
333 { X86::CMP8rr, X86::CMP8rm, 0 },
334 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
335 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
336 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
337 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
338 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
339 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
340 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
341 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
342 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
343 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
344 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
345 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
346 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
347 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
348 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
349 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
350 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
351 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
352 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
353 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
354 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
355 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
356 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
357 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
358 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
359 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
360 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
361 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
362 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
363 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
364 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
365 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
366 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
367 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
368 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
369 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
370 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
371 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
372 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
373 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
374 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
375 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
376 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
377 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
378 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
379 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
380 { X86::MOV16rr, X86::MOV16rm, 0 },
381 { X86::MOV32rr, X86::MOV32rm, 0 },
382 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 },
383 { X86::MOV64rr, X86::MOV64rm, 0 },
384 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
385 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
386 { X86::MOV8rr, X86::MOV8rm, 0 },
387 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
388 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
389 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
390 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
391 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
392 { X86::MOVDQArr, X86::MOVDQArm, 16 },
393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
395 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
396 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
397 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
398 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
399 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
400 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
401 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
402 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
403 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
404 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
405 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
406 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
407 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
408 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
409 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
410 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
411 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
412 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
413 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
414 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
415 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
416 { X86::RCPPSr, X86::RCPPSm, 16 },
417 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
418 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
419 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
420 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
421 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
422 { X86::SQRTPDr, X86::SQRTPDm, 16 },
423 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
424 { X86::SQRTPSr, X86::SQRTPSm, 16 },
425 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
426 { X86::SQRTSDr, X86::SQRTSDm, 0 },
427 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
428 { X86::SQRTSSr, X86::SQRTSSm, 0 },
429 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
430 { X86::TEST16rr, X86::TEST16rm, 0 },
431 { X86::TEST32rr, X86::TEST32rm, 0 },
432 { X86::TEST64rr, X86::TEST64rm, 0 },
433 { X86::TEST8rr, X86::TEST8rm, 0 },
434 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
435 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
436 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
439 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
440 unsigned RegOp = OpTbl1[i][0];
441 unsigned MemOp = OpTbl1[i][1];
442 unsigned Align = OpTbl1[i][2];
443 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
444 std::make_pair(MemOp,Align))).second)
445 assert(false && "Duplicated entries?");
446 // Index 1, folded load
447 unsigned AuxInfo = 1 | (1 << 4);
448 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
449 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
450 std::make_pair(RegOp, AuxInfo))).second)
451 AmbEntries.push_back(MemOp);
454 static const unsigned OpTbl2[][3] = {
455 { X86::ADC32rr, X86::ADC32rm, 0 },
456 { X86::ADC64rr, X86::ADC64rm, 0 },
457 { X86::ADD16rr, X86::ADD16rm, 0 },
458 { X86::ADD32rr, X86::ADD32rm, 0 },
459 { X86::ADD64rr, X86::ADD64rm, 0 },
460 { X86::ADD8rr, X86::ADD8rm, 0 },
461 { X86::ADDPDrr, X86::ADDPDrm, 16 },
462 { X86::ADDPSrr, X86::ADDPSrm, 16 },
463 { X86::ADDSDrr, X86::ADDSDrm, 0 },
464 { X86::ADDSSrr, X86::ADDSSrm, 0 },
465 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
466 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
467 { X86::AND16rr, X86::AND16rm, 0 },
468 { X86::AND32rr, X86::AND32rm, 0 },
469 { X86::AND64rr, X86::AND64rm, 0 },
470 { X86::AND8rr, X86::AND8rm, 0 },
471 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
472 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
473 { X86::ANDPDrr, X86::ANDPDrm, 16 },
474 { X86::ANDPSrr, X86::ANDPSrm, 16 },
475 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
476 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
477 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
478 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
479 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
480 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
481 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
482 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
483 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
484 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
485 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
486 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
487 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
488 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
489 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
490 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
491 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
492 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
493 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
494 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
495 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
496 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
497 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
498 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
499 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
500 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
501 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
502 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
503 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
504 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
505 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
506 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
507 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
508 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
509 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
510 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
511 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
512 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
513 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
514 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
515 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
516 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
517 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
518 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
519 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
520 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
521 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
522 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
523 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
524 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
525 { X86::CMPSDrr, X86::CMPSDrm, 0 },
526 { X86::CMPSSrr, X86::CMPSSrm, 0 },
527 { X86::DIVPDrr, X86::DIVPDrm, 16 },
528 { X86::DIVPSrr, X86::DIVPSrm, 16 },
529 { X86::DIVSDrr, X86::DIVSDrm, 0 },
530 { X86::DIVSSrr, X86::DIVSSrm, 0 },
531 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
532 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
533 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
534 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
535 { X86::FsORPDrr, X86::FsORPDrm, 16 },
536 { X86::FsORPSrr, X86::FsORPSrm, 16 },
537 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
538 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
539 { X86::HADDPDrr, X86::HADDPDrm, 16 },
540 { X86::HADDPSrr, X86::HADDPSrm, 16 },
541 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
542 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
543 { X86::IMUL16rr, X86::IMUL16rm, 0 },
544 { X86::IMUL32rr, X86::IMUL32rm, 0 },
545 { X86::IMUL64rr, X86::IMUL64rm, 0 },
546 { X86::MAXPDrr, X86::MAXPDrm, 16 },
547 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
548 { X86::MAXPSrr, X86::MAXPSrm, 16 },
549 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
550 { X86::MAXSDrr, X86::MAXSDrm, 0 },
551 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
552 { X86::MAXSSrr, X86::MAXSSrm, 0 },
553 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
554 { X86::MINPDrr, X86::MINPDrm, 16 },
555 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
556 { X86::MINPSrr, X86::MINPSrm, 16 },
557 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
558 { X86::MINSDrr, X86::MINSDrm, 0 },
559 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
560 { X86::MINSSrr, X86::MINSSrm, 0 },
561 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
562 { X86::MULPDrr, X86::MULPDrm, 16 },
563 { X86::MULPSrr, X86::MULPSrm, 16 },
564 { X86::MULSDrr, X86::MULSDrm, 0 },
565 { X86::MULSSrr, X86::MULSSrm, 0 },
566 { X86::OR16rr, X86::OR16rm, 0 },
567 { X86::OR32rr, X86::OR32rm, 0 },
568 { X86::OR64rr, X86::OR64rm, 0 },
569 { X86::OR8rr, X86::OR8rm, 0 },
570 { X86::ORPDrr, X86::ORPDrm, 16 },
571 { X86::ORPSrr, X86::ORPSrm, 16 },
572 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
573 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
574 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
575 { X86::PADDBrr, X86::PADDBrm, 16 },
576 { X86::PADDDrr, X86::PADDDrm, 16 },
577 { X86::PADDQrr, X86::PADDQrm, 16 },
578 { X86::PADDSBrr, X86::PADDSBrm, 16 },
579 { X86::PADDSWrr, X86::PADDSWrm, 16 },
580 { X86::PADDWrr, X86::PADDWrm, 16 },
581 { X86::PANDNrr, X86::PANDNrm, 16 },
582 { X86::PANDrr, X86::PANDrm, 16 },
583 { X86::PAVGBrr, X86::PAVGBrm, 16 },
584 { X86::PAVGWrr, X86::PAVGWrm, 16 },
585 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
586 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
587 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
588 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
589 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
590 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
591 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
592 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
593 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
594 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
595 { X86::PMINSWrr, X86::PMINSWrm, 16 },
596 { X86::PMINUBrr, X86::PMINUBrm, 16 },
597 { X86::PMULDQrr, X86::PMULDQrm, 16 },
598 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
599 { X86::PMULHWrr, X86::PMULHWrm, 16 },
600 { X86::PMULLDrr, X86::PMULLDrm, 16 },
601 { X86::PMULLWrr, X86::PMULLWrm, 16 },
602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
603 { X86::PORrr, X86::PORrm, 16 },
604 { X86::PSADBWrr, X86::PSADBWrm, 16 },
605 { X86::PSLLDrr, X86::PSLLDrm, 16 },
606 { X86::PSLLQrr, X86::PSLLQrm, 16 },
607 { X86::PSLLWrr, X86::PSLLWrm, 16 },
608 { X86::PSRADrr, X86::PSRADrm, 16 },
609 { X86::PSRAWrr, X86::PSRAWrm, 16 },
610 { X86::PSRLDrr, X86::PSRLDrm, 16 },
611 { X86::PSRLQrr, X86::PSRLQrm, 16 },
612 { X86::PSRLWrr, X86::PSRLWrm, 16 },
613 { X86::PSUBBrr, X86::PSUBBrm, 16 },
614 { X86::PSUBDrr, X86::PSUBDrm, 16 },
615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
617 { X86::PSUBWrr, X86::PSUBWrm, 16 },
618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
626 { X86::PXORrr, X86::PXORrm, 16 },
627 { X86::SBB32rr, X86::SBB32rm, 0 },
628 { X86::SBB64rr, X86::SBB64rm, 0 },
629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
631 { X86::SUB16rr, X86::SUB16rm, 0 },
632 { X86::SUB32rr, X86::SUB32rm, 0 },
633 { X86::SUB64rr, X86::SUB64rm, 0 },
634 { X86::SUB8rr, X86::SUB8rm, 0 },
635 { X86::SUBPDrr, X86::SUBPDrm, 16 },
636 { X86::SUBPSrr, X86::SUBPSrm, 16 },
637 { X86::SUBSDrr, X86::SUBSDrm, 0 },
638 { X86::SUBSSrr, X86::SUBSSrm, 0 },
639 // FIXME: TEST*rr -> swapped operand of TEST*mr.
640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
644 { X86::XOR16rr, X86::XOR16rm, 0 },
645 { X86::XOR32rr, X86::XOR32rm, 0 },
646 { X86::XOR64rr, X86::XOR64rm, 0 },
647 { X86::XOR8rr, X86::XOR8rm, 0 },
648 { X86::XORPDrr, X86::XORPDrm, 16 },
649 { X86::XORPSrr, X86::XORPSrm, 16 }
652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
653 unsigned RegOp = OpTbl2[i][0];
654 unsigned MemOp = OpTbl2[i][1];
655 unsigned Align = OpTbl2[i][2];
656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
657 std::make_pair(MemOp,Align))).second)
658 assert(false && "Duplicated entries?");
659 // Index 2, folded load
660 unsigned AuxInfo = 2 | (1 << 4);
661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
662 std::make_pair(RegOp, AuxInfo))).second)
663 AmbEntries.push_back(MemOp);
666 // Remove ambiguous entries.
667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
670 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
671 unsigned &SrcReg, unsigned &DstReg,
672 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
673 switch (MI.getOpcode()) {
677 case X86::MOV8rr_NOREX:
681 case X86::MOV32rr_TC:
682 case X86::MOV64rr_TC:
684 // FP Stack register class copies
685 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
686 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
687 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
689 // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
690 // copies are done with FsMOVAPSrr and FsMOVAPDrr.
692 case X86::FsMOVAPSrr:
693 case X86::FsMOVAPDrr:
697 case X86::MMX_MOVQ64rr:
698 assert(MI.getNumOperands() >= 2 &&
699 MI.getOperand(0).isReg() &&
700 MI.getOperand(1).isReg() &&
701 "invalid register-register move instruction");
702 SrcReg = MI.getOperand(1).getReg();
703 DstReg = MI.getOperand(0).getReg();
704 SrcSubIdx = MI.getOperand(1).getSubReg();
705 DstSubIdx = MI.getOperand(0).getSubReg();
711 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
712 unsigned &SrcReg, unsigned &DstReg,
713 unsigned &SubIdx) const {
714 switch (MI.getOpcode()) {
716 case X86::MOVSX16rr8:
717 case X86::MOVZX16rr8:
718 case X86::MOVSX32rr8:
719 case X86::MOVZX32rr8:
720 case X86::MOVSX64rr8:
721 case X86::MOVZX64rr8:
722 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
723 // It's not always legal to reference the low 8-bit of the larger
724 // register in 32-bit mode.
726 case X86::MOVSX32rr16:
727 case X86::MOVZX32rr16:
728 case X86::MOVSX64rr16:
729 case X86::MOVZX64rr16:
730 case X86::MOVSX64rr32:
731 case X86::MOVZX64rr32: {
732 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
735 SrcReg = MI.getOperand(1).getReg();
736 DstReg = MI.getOperand(0).getReg();
737 switch (MI.getOpcode()) {
741 case X86::MOVSX16rr8:
742 case X86::MOVZX16rr8:
743 case X86::MOVSX32rr8:
744 case X86::MOVZX32rr8:
745 case X86::MOVSX64rr8:
746 case X86::MOVZX64rr8:
749 case X86::MOVSX32rr16:
750 case X86::MOVZX32rr16:
751 case X86::MOVSX64rr16:
752 case X86::MOVZX64rr16:
755 case X86::MOVSX64rr32:
756 case X86::MOVZX64rr32:
766 /// isFrameOperand - Return true and the FrameIndex if the specified
767 /// operand and follow operands form a reference to the stack frame.
768 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
769 int &FrameIndex) const {
770 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
771 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
772 MI->getOperand(Op+1).getImm() == 1 &&
773 MI->getOperand(Op+2).getReg() == 0 &&
774 MI->getOperand(Op+3).getImm() == 0) {
775 FrameIndex = MI->getOperand(Op).getIndex();
781 static bool isFrameLoadOpcode(int Opcode) {
794 case X86::MMX_MOVD64rm:
795 case X86::MMX_MOVQ64rm:
802 static bool isFrameStoreOpcode(int Opcode) {
815 case X86::MMX_MOVD64mr:
816 case X86::MMX_MOVQ64mr:
817 case X86::MMX_MOVNTQmr:
823 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
824 int &FrameIndex) const {
825 if (isFrameLoadOpcode(MI->getOpcode()))
826 if (isFrameOperand(MI, 1, FrameIndex))
827 return MI->getOperand(0).getReg();
831 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
832 int &FrameIndex) const {
833 if (isFrameLoadOpcode(MI->getOpcode())) {
835 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
837 // Check for post-frame index elimination operations
838 const MachineMemOperand *Dummy;
839 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
844 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
845 const MachineMemOperand *&MMO,
846 int &FrameIndex) const {
847 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
848 oe = MI->memoperands_end();
851 if ((*o)->isLoad() && (*o)->getValue())
852 if (const FixedStackPseudoSourceValue *Value =
853 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
854 FrameIndex = Value->getFrameIndex();
862 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
863 int &FrameIndex) const {
864 if (isFrameStoreOpcode(MI->getOpcode()))
865 if (isFrameOperand(MI, 0, FrameIndex))
866 return MI->getOperand(X86AddrNumOperands).getReg();
870 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
871 int &FrameIndex) const {
872 if (isFrameStoreOpcode(MI->getOpcode())) {
874 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
876 // Check for post-frame index elimination operations
877 const MachineMemOperand *Dummy;
878 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
883 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
884 const MachineMemOperand *&MMO,
885 int &FrameIndex) const {
886 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
887 oe = MI->memoperands_end();
890 if ((*o)->isStore() && (*o)->getValue())
891 if (const FixedStackPseudoSourceValue *Value =
892 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
893 FrameIndex = Value->getFrameIndex();
901 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
903 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
904 bool isPICBase = false;
905 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
906 E = MRI.def_end(); I != E; ++I) {
907 MachineInstr *DefMI = I.getOperand().getParent();
908 if (DefMI->getOpcode() != X86::MOVPC32r)
910 assert(!isPICBase && "More than one PIC base?");
917 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
918 AliasAnalysis *AA) const {
919 switch (MI->getOpcode()) {
930 case X86::MOVUPSrm_Int:
933 case X86::MMX_MOVD64rm:
934 case X86::MMX_MOVQ64rm:
935 case X86::FsMOVAPSrm:
936 case X86::FsMOVAPDrm: {
937 // Loads from constant pools are trivially rematerializable.
938 if (MI->getOperand(1).isReg() &&
939 MI->getOperand(2).isImm() &&
940 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
941 MI->isInvariantLoad(AA)) {
942 unsigned BaseReg = MI->getOperand(1).getReg();
943 if (BaseReg == 0 || BaseReg == X86::RIP)
945 // Allow re-materialization of PIC load.
946 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
948 const MachineFunction &MF = *MI->getParent()->getParent();
949 const MachineRegisterInfo &MRI = MF.getRegInfo();
950 bool isPICBase = false;
951 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
952 E = MRI.def_end(); I != E; ++I) {
953 MachineInstr *DefMI = I.getOperand().getParent();
954 if (DefMI->getOpcode() != X86::MOVPC32r)
956 assert(!isPICBase && "More than one PIC base?");
966 if (MI->getOperand(2).isImm() &&
967 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
968 !MI->getOperand(4).isReg()) {
969 // lea fi#, lea GV, etc. are all rematerializable.
970 if (!MI->getOperand(1).isReg())
972 unsigned BaseReg = MI->getOperand(1).getReg();
975 // Allow re-materialization of lea PICBase + x.
976 const MachineFunction &MF = *MI->getParent()->getParent();
977 const MachineRegisterInfo &MRI = MF.getRegInfo();
978 return regIsPICBase(BaseReg, MRI);
984 // All other instructions marked M_REMATERIALIZABLE are always trivially
989 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
990 /// would clobber the EFLAGS condition register. Note the result may be
991 /// conservative. If it cannot definitely determine the safety after visiting
992 /// a few instructions in each direction it assumes it's not safe.
993 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
994 MachineBasicBlock::iterator I) {
995 MachineBasicBlock::iterator E = MBB.end();
997 // It's always safe to clobber EFLAGS at the end of a block.
1001 // For compile time consideration, if we are not able to determine the
1002 // safety after visiting 4 instructions in each direction, we will assume
1004 MachineBasicBlock::iterator Iter = I;
1005 for (unsigned i = 0; i < 4; ++i) {
1006 bool SeenDef = false;
1007 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1008 MachineOperand &MO = Iter->getOperand(j);
1011 if (MO.getReg() == X86::EFLAGS) {
1019 // This instruction defines EFLAGS, no need to look any further.
1022 // Skip over DBG_VALUE.
1023 while (Iter != E && Iter->isDebugValue())
1026 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1031 MachineBasicBlock::iterator B = MBB.begin();
1033 for (unsigned i = 0; i < 4; ++i) {
1034 // If we make it to the beginning of the block, it's safe to clobber
1035 // EFLAGS iff EFLAGS is not live-in.
1037 return !MBB.isLiveIn(X86::EFLAGS);
1040 // Skip over DBG_VALUE.
1041 while (Iter != B && Iter->isDebugValue())
1044 bool SawKill = false;
1045 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1046 MachineOperand &MO = Iter->getOperand(j);
1047 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1048 if (MO.isDef()) return MO.isDead();
1049 if (MO.isKill()) SawKill = true;
1054 // This instruction kills EFLAGS and doesn't redefine it, so
1055 // there's no need to look further.
1059 // Conservative answer.
1063 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1064 MachineBasicBlock::iterator I,
1065 unsigned DestReg, unsigned SubIdx,
1066 const MachineInstr *Orig,
1067 const TargetRegisterInfo *TRI) const {
1068 DebugLoc DL = MBB.findDebugLoc(I);
1070 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1071 DestReg = TRI->getSubReg(DestReg, SubIdx);
1075 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1076 // Re-materialize them as movri instructions to avoid side effects.
1078 unsigned Opc = Orig->getOpcode();
1084 case X86::MOV64r0: {
1085 if (!isSafeToClobberEFLAGS(MBB, I)) {
1088 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1089 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1090 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1091 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1100 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1101 MI->getOperand(0).setReg(DestReg);
1104 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1107 MachineInstr *NewMI = prior(I);
1108 NewMI->getOperand(0).setSubReg(SubIdx);
1111 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1112 /// is not marked dead.
1113 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1114 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1115 MachineOperand &MO = MI->getOperand(i);
1116 if (MO.isReg() && MO.isDef() &&
1117 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1124 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1125 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1126 /// to a 32-bit superregister and then truncating back down to a 16-bit
1129 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1130 MachineFunction::iterator &MFI,
1131 MachineBasicBlock::iterator &MBBI,
1132 LiveVariables *LV) const {
1133 MachineInstr *MI = MBBI;
1134 unsigned Dest = MI->getOperand(0).getReg();
1135 unsigned Src = MI->getOperand(1).getReg();
1136 bool isDead = MI->getOperand(0).isDead();
1137 bool isKill = MI->getOperand(1).isKill();
1139 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1140 ? X86::LEA64_32r : X86::LEA32r;
1141 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1142 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1143 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1145 // Build and insert into an implicit UNDEF value. This is OK because
1146 // well be shifting and then extracting the lower 16-bits.
1147 // This has the potential to cause partial register stall. e.g.
1148 // movw (%rbp,%rcx,2), %dx
1149 // leal -65(%rdx), %esi
1150 // But testing has shown this *does* help performance in 64-bit mode (at
1151 // least on modern x86 machines).
1152 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1153 MachineInstr *InsMI =
1154 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1156 .addReg(Src, getKillRegState(isKill))
1157 .addImm(X86::SUBREG_16BIT);
1159 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1160 get(Opc), leaOutReg);
1163 llvm_unreachable(0);
1165 case X86::SHL16ri: {
1166 unsigned ShAmt = MI->getOperand(2).getImm();
1167 MIB.addReg(0).addImm(1 << ShAmt)
1168 .addReg(leaInReg, RegState::Kill).addImm(0);
1172 case X86::INC64_16r:
1173 addLeaRegOffset(MIB, leaInReg, true, 1);
1176 case X86::DEC64_16r:
1177 addLeaRegOffset(MIB, leaInReg, true, -1);
1181 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1183 case X86::ADD16rr: {
1184 unsigned Src2 = MI->getOperand(2).getReg();
1185 bool isKill2 = MI->getOperand(2).isKill();
1186 unsigned leaInReg2 = 0;
1187 MachineInstr *InsMI2 = 0;
1189 // ADD16rr %reg1028<kill>, %reg1028
1190 // just a single insert_subreg.
1191 addRegReg(MIB, leaInReg, true, leaInReg, false);
1193 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1194 // Build and insert into an implicit UNDEF value. This is OK because
1195 // well be shifting and then extracting the lower 16-bits.
1196 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1198 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1200 .addReg(Src2, getKillRegState(isKill2))
1201 .addImm(X86::SUBREG_16BIT);
1202 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1204 if (LV && isKill2 && InsMI2)
1205 LV->replaceKillInstruction(Src2, MI, InsMI2);
1210 MachineInstr *NewMI = MIB;
1211 MachineInstr *ExtMI =
1212 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1213 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1214 .addReg(leaOutReg, RegState::Kill)
1215 .addImm(X86::SUBREG_16BIT);
1218 // Update live variables
1219 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1220 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1222 LV->replaceKillInstruction(Src, MI, InsMI);
1224 LV->replaceKillInstruction(Dest, MI, ExtMI);
1230 /// convertToThreeAddress - This method must be implemented by targets that
1231 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1232 /// may be able to convert a two-address instruction into a true
1233 /// three-address instruction on demand. This allows the X86 target (for
1234 /// example) to convert ADD and SHL instructions into LEA instructions if they
1235 /// would require register copies due to two-addressness.
1237 /// This method returns a null pointer if the transformation cannot be
1238 /// performed, otherwise it returns the new instruction.
1241 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1242 MachineBasicBlock::iterator &MBBI,
1243 LiveVariables *LV) const {
1244 MachineInstr *MI = MBBI;
1245 MachineFunction &MF = *MI->getParent()->getParent();
1246 // All instructions input are two-addr instructions. Get the known operands.
1247 unsigned Dest = MI->getOperand(0).getReg();
1248 unsigned Src = MI->getOperand(1).getReg();
1249 bool isDead = MI->getOperand(0).isDead();
1250 bool isKill = MI->getOperand(1).isKill();
1252 MachineInstr *NewMI = NULL;
1253 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1254 // we have better subtarget support, enable the 16-bit LEA generation here.
1255 // 16-bit LEA is also slow on Core2.
1256 bool DisableLEA16 = true;
1257 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1259 unsigned MIOpc = MI->getOpcode();
1261 case X86::SHUFPSrri: {
1262 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1263 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1265 unsigned B = MI->getOperand(1).getReg();
1266 unsigned C = MI->getOperand(2).getReg();
1267 if (B != C) return 0;
1268 unsigned A = MI->getOperand(0).getReg();
1269 unsigned M = MI->getOperand(3).getImm();
1270 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1271 .addReg(A, RegState::Define | getDeadRegState(isDead))
1272 .addReg(B, getKillRegState(isKill)).addImm(M);
1275 case X86::SHL64ri: {
1276 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1277 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1278 // the flags produced by a shift yet, so this is safe.
1279 unsigned ShAmt = MI->getOperand(2).getImm();
1280 if (ShAmt == 0 || ShAmt >= 4) return 0;
1282 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1283 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1284 .addReg(0).addImm(1 << ShAmt)
1285 .addReg(Src, getKillRegState(isKill))
1289 case X86::SHL32ri: {
1290 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1291 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1292 // the flags produced by a shift yet, so this is safe.
1293 unsigned ShAmt = MI->getOperand(2).getImm();
1294 if (ShAmt == 0 || ShAmt >= 4) return 0;
1296 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1297 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1298 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1299 .addReg(0).addImm(1 << ShAmt)
1300 .addReg(Src, getKillRegState(isKill)).addImm(0);
1303 case X86::SHL16ri: {
1304 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1305 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1306 // the flags produced by a shift yet, so this is safe.
1307 unsigned ShAmt = MI->getOperand(2).getImm();
1308 if (ShAmt == 0 || ShAmt >= 4) return 0;
1311 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1312 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1313 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1314 .addReg(0).addImm(1 << ShAmt)
1315 .addReg(Src, getKillRegState(isKill))
1320 // The following opcodes also sets the condition code register(s). Only
1321 // convert them to equivalent lea if the condition code register def's
1323 if (hasLiveCondCodeDef(MI))
1330 case X86::INC64_32r: {
1331 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1332 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1333 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1334 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1335 .addReg(Dest, RegState::Define |
1336 getDeadRegState(isDead)),
1341 case X86::INC64_16r:
1343 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1344 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1345 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1346 .addReg(Dest, RegState::Define |
1347 getDeadRegState(isDead)),
1352 case X86::DEC64_32r: {
1353 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1354 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1355 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1356 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1357 .addReg(Dest, RegState::Define |
1358 getDeadRegState(isDead)),
1363 case X86::DEC64_16r:
1365 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1366 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1367 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1368 .addReg(Dest, RegState::Define |
1369 getDeadRegState(isDead)),
1373 case X86::ADD32rr: {
1374 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1375 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1376 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1377 unsigned Src2 = MI->getOperand(2).getReg();
1378 bool isKill2 = MI->getOperand(2).isKill();
1379 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1380 .addReg(Dest, RegState::Define |
1381 getDeadRegState(isDead)),
1382 Src, isKill, Src2, isKill2);
1384 LV->replaceKillInstruction(Src2, MI, NewMI);
1387 case X86::ADD16rr: {
1389 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1390 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1391 unsigned Src2 = MI->getOperand(2).getReg();
1392 bool isKill2 = MI->getOperand(2).isKill();
1393 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1394 .addReg(Dest, RegState::Define |
1395 getDeadRegState(isDead)),
1396 Src, isKill, Src2, isKill2);
1398 LV->replaceKillInstruction(Src2, MI, NewMI);
1401 case X86::ADD64ri32:
1403 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1404 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1405 .addReg(Dest, RegState::Define |
1406 getDeadRegState(isDead)),
1407 Src, isKill, MI->getOperand(2).getImm());
1410 case X86::ADD32ri8: {
1411 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1412 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1413 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1414 .addReg(Dest, RegState::Define |
1415 getDeadRegState(isDead)),
1416 Src, isKill, MI->getOperand(2).getImm());
1422 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1423 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1424 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1425 .addReg(Dest, RegState::Define |
1426 getDeadRegState(isDead)),
1427 Src, isKill, MI->getOperand(2).getImm());
1433 if (!NewMI) return 0;
1435 if (LV) { // Update live variables
1437 LV->replaceKillInstruction(Src, MI, NewMI);
1439 LV->replaceKillInstruction(Dest, MI, NewMI);
1442 MFI->insert(MBBI, NewMI); // Insert the new inst
1446 /// commuteInstruction - We have a few instructions that must be hacked on to
1450 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1451 switch (MI->getOpcode()) {
1452 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1453 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1454 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1455 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1456 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1457 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1460 switch (MI->getOpcode()) {
1461 default: llvm_unreachable("Unreachable!");
1462 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1463 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1464 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1465 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1466 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1467 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1469 unsigned Amt = MI->getOperand(3).getImm();
1471 MachineFunction &MF = *MI->getParent()->getParent();
1472 MI = MF.CloneMachineInstr(MI);
1475 MI->setDesc(get(Opc));
1476 MI->getOperand(3).setImm(Size-Amt);
1477 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1479 case X86::CMOVB16rr:
1480 case X86::CMOVB32rr:
1481 case X86::CMOVB64rr:
1482 case X86::CMOVAE16rr:
1483 case X86::CMOVAE32rr:
1484 case X86::CMOVAE64rr:
1485 case X86::CMOVE16rr:
1486 case X86::CMOVE32rr:
1487 case X86::CMOVE64rr:
1488 case X86::CMOVNE16rr:
1489 case X86::CMOVNE32rr:
1490 case X86::CMOVNE64rr:
1491 case X86::CMOVBE16rr:
1492 case X86::CMOVBE32rr:
1493 case X86::CMOVBE64rr:
1494 case X86::CMOVA16rr:
1495 case X86::CMOVA32rr:
1496 case X86::CMOVA64rr:
1497 case X86::CMOVL16rr:
1498 case X86::CMOVL32rr:
1499 case X86::CMOVL64rr:
1500 case X86::CMOVGE16rr:
1501 case X86::CMOVGE32rr:
1502 case X86::CMOVGE64rr:
1503 case X86::CMOVLE16rr:
1504 case X86::CMOVLE32rr:
1505 case X86::CMOVLE64rr:
1506 case X86::CMOVG16rr:
1507 case X86::CMOVG32rr:
1508 case X86::CMOVG64rr:
1509 case X86::CMOVS16rr:
1510 case X86::CMOVS32rr:
1511 case X86::CMOVS64rr:
1512 case X86::CMOVNS16rr:
1513 case X86::CMOVNS32rr:
1514 case X86::CMOVNS64rr:
1515 case X86::CMOVP16rr:
1516 case X86::CMOVP32rr:
1517 case X86::CMOVP64rr:
1518 case X86::CMOVNP16rr:
1519 case X86::CMOVNP32rr:
1520 case X86::CMOVNP64rr:
1521 case X86::CMOVO16rr:
1522 case X86::CMOVO32rr:
1523 case X86::CMOVO64rr:
1524 case X86::CMOVNO16rr:
1525 case X86::CMOVNO32rr:
1526 case X86::CMOVNO64rr: {
1528 switch (MI->getOpcode()) {
1530 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1531 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1532 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1533 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1534 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1535 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1536 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1537 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1538 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1539 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1540 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1541 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1542 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1543 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1544 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1545 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1546 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1547 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1548 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1549 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1550 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1551 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1552 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1553 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1554 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1555 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1556 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1557 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1558 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1559 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1560 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1561 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1562 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1563 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1564 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1565 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1566 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1567 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1568 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1569 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1570 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1571 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1572 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1573 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1574 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1575 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1576 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1577 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1580 MachineFunction &MF = *MI->getParent()->getParent();
1581 MI = MF.CloneMachineInstr(MI);
1584 MI->setDesc(get(Opc));
1585 // Fallthrough intended.
1588 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1592 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1594 default: return X86::COND_INVALID;
1595 case X86::JE_4: return X86::COND_E;
1596 case X86::JNE_4: return X86::COND_NE;
1597 case X86::JL_4: return X86::COND_L;
1598 case X86::JLE_4: return X86::COND_LE;
1599 case X86::JG_4: return X86::COND_G;
1600 case X86::JGE_4: return X86::COND_GE;
1601 case X86::JB_4: return X86::COND_B;
1602 case X86::JBE_4: return X86::COND_BE;
1603 case X86::JA_4: return X86::COND_A;
1604 case X86::JAE_4: return X86::COND_AE;
1605 case X86::JS_4: return X86::COND_S;
1606 case X86::JNS_4: return X86::COND_NS;
1607 case X86::JP_4: return X86::COND_P;
1608 case X86::JNP_4: return X86::COND_NP;
1609 case X86::JO_4: return X86::COND_O;
1610 case X86::JNO_4: return X86::COND_NO;
1614 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1616 default: llvm_unreachable("Illegal condition code!");
1617 case X86::COND_E: return X86::JE_4;
1618 case X86::COND_NE: return X86::JNE_4;
1619 case X86::COND_L: return X86::JL_4;
1620 case X86::COND_LE: return X86::JLE_4;
1621 case X86::COND_G: return X86::JG_4;
1622 case X86::COND_GE: return X86::JGE_4;
1623 case X86::COND_B: return X86::JB_4;
1624 case X86::COND_BE: return X86::JBE_4;
1625 case X86::COND_A: return X86::JA_4;
1626 case X86::COND_AE: return X86::JAE_4;
1627 case X86::COND_S: return X86::JS_4;
1628 case X86::COND_NS: return X86::JNS_4;
1629 case X86::COND_P: return X86::JP_4;
1630 case X86::COND_NP: return X86::JNP_4;
1631 case X86::COND_O: return X86::JO_4;
1632 case X86::COND_NO: return X86::JNO_4;
1636 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1637 /// e.g. turning COND_E to COND_NE.
1638 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1640 default: llvm_unreachable("Illegal condition code!");
1641 case X86::COND_E: return X86::COND_NE;
1642 case X86::COND_NE: return X86::COND_E;
1643 case X86::COND_L: return X86::COND_GE;
1644 case X86::COND_LE: return X86::COND_G;
1645 case X86::COND_G: return X86::COND_LE;
1646 case X86::COND_GE: return X86::COND_L;
1647 case X86::COND_B: return X86::COND_AE;
1648 case X86::COND_BE: return X86::COND_A;
1649 case X86::COND_A: return X86::COND_BE;
1650 case X86::COND_AE: return X86::COND_B;
1651 case X86::COND_S: return X86::COND_NS;
1652 case X86::COND_NS: return X86::COND_S;
1653 case X86::COND_P: return X86::COND_NP;
1654 case X86::COND_NP: return X86::COND_P;
1655 case X86::COND_O: return X86::COND_NO;
1656 case X86::COND_NO: return X86::COND_O;
1660 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1661 const TargetInstrDesc &TID = MI->getDesc();
1662 if (!TID.isTerminator()) return false;
1664 // Conditional branch is a special case.
1665 if (TID.isBranch() && !TID.isBarrier())
1667 if (!TID.isPredicable())
1669 return !isPredicated(MI);
1672 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1673 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1674 const X86InstrInfo &TII) {
1675 if (MI->getOpcode() == X86::FP_REG_KILL)
1677 return TII.isUnpredicatedTerminator(MI);
1680 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1681 MachineBasicBlock *&TBB,
1682 MachineBasicBlock *&FBB,
1683 SmallVectorImpl<MachineOperand> &Cond,
1684 bool AllowModify) const {
1685 // Start from the bottom of the block and work up, examining the
1686 // terminator instructions.
1687 MachineBasicBlock::iterator I = MBB.end();
1688 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1689 while (I != MBB.begin()) {
1691 if (I->isDebugValue())
1694 // Working from the bottom, when we see a non-terminator instruction, we're
1696 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1699 // A terminator that isn't a branch can't easily be handled by this
1701 if (!I->getDesc().isBranch())
1704 // Handle unconditional branches.
1705 if (I->getOpcode() == X86::JMP_4) {
1709 TBB = I->getOperand(0).getMBB();
1713 // If the block has any instructions after a JMP, delete them.
1714 while (llvm::next(I) != MBB.end())
1715 llvm::next(I)->eraseFromParent();
1720 // Delete the JMP if it's equivalent to a fall-through.
1721 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1723 I->eraseFromParent();
1725 UnCondBrIter = MBB.end();
1729 // TBB is used to indicate the unconditional destination.
1730 TBB = I->getOperand(0).getMBB();
1734 // Handle conditional branches.
1735 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1736 if (BranchCode == X86::COND_INVALID)
1737 return true; // Can't handle indirect branch.
1739 // Working from the bottom, handle the first conditional branch.
1741 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1742 if (AllowModify && UnCondBrIter != MBB.end() &&
1743 MBB.isLayoutSuccessor(TargetBB)) {
1744 // If we can modify the code and it ends in something like:
1752 // Then we can change this to:
1759 // Which is a bit more efficient.
1760 // We conditionally jump to the fall-through block.
1761 BranchCode = GetOppositeBranchCondition(BranchCode);
1762 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1763 MachineBasicBlock::iterator OldInst = I;
1765 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1766 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1767 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1769 MBB.addSuccessor(TargetBB);
1771 OldInst->eraseFromParent();
1772 UnCondBrIter->eraseFromParent();
1774 // Restart the analysis.
1775 UnCondBrIter = MBB.end();
1781 TBB = I->getOperand(0).getMBB();
1782 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1786 // Handle subsequent conditional branches. Only handle the case where all
1787 // conditional branches branch to the same destination and their condition
1788 // opcodes fit one of the special multi-branch idioms.
1789 assert(Cond.size() == 1);
1792 // Only handle the case where all conditional branches branch to the same
1794 if (TBB != I->getOperand(0).getMBB())
1797 // If the conditions are the same, we can leave them alone.
1798 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1799 if (OldBranchCode == BranchCode)
1802 // If they differ, see if they fit one of the known patterns. Theoretically,
1803 // we could handle more patterns here, but we shouldn't expect to see them
1804 // if instruction selection has done a reasonable job.
1805 if ((OldBranchCode == X86::COND_NP &&
1806 BranchCode == X86::COND_E) ||
1807 (OldBranchCode == X86::COND_E &&
1808 BranchCode == X86::COND_NP))
1809 BranchCode = X86::COND_NP_OR_E;
1810 else if ((OldBranchCode == X86::COND_P &&
1811 BranchCode == X86::COND_NE) ||
1812 (OldBranchCode == X86::COND_NE &&
1813 BranchCode == X86::COND_P))
1814 BranchCode = X86::COND_NE_OR_P;
1818 // Update the MachineOperand.
1819 Cond[0].setImm(BranchCode);
1825 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1826 MachineBasicBlock::iterator I = MBB.end();
1829 while (I != MBB.begin()) {
1831 if (I->isDebugValue())
1833 if (I->getOpcode() != X86::JMP_4 &&
1834 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1836 // Remove the branch.
1837 I->eraseFromParent();
1846 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1847 MachineBasicBlock *FBB,
1848 const SmallVectorImpl<MachineOperand> &Cond) const {
1849 // FIXME this should probably have a DebugLoc operand
1851 // Shouldn't be a fall through.
1852 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1853 assert((Cond.size() == 1 || Cond.size() == 0) &&
1854 "X86 branch conditions have one component!");
1857 // Unconditional branch?
1858 assert(!FBB && "Unconditional branch with multiple successors!");
1859 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
1863 // Conditional branch.
1865 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1867 case X86::COND_NP_OR_E:
1868 // Synthesize NP_OR_E with two branches.
1869 BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
1871 BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
1874 case X86::COND_NE_OR_P:
1875 // Synthesize NE_OR_P with two branches.
1876 BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
1878 BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
1882 unsigned Opc = GetCondBranchFromCond(CC);
1883 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1888 // Two-way Conditional branch. Insert the second branch.
1889 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
1895 /// isHReg - Test if the given register is a physical h register.
1896 static bool isHReg(unsigned Reg) {
1897 return X86::GR8_ABCD_HRegClass.contains(Reg);
1900 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1901 MachineBasicBlock::iterator MI,
1902 unsigned DestReg, unsigned SrcReg,
1903 const TargetRegisterClass *DestRC,
1904 const TargetRegisterClass *SrcRC) const {
1905 DebugLoc DL = MBB.findDebugLoc(MI);
1907 // Determine if DstRC and SrcRC have a common superclass in common.
1908 const TargetRegisterClass *CommonRC = DestRC;
1909 if (DestRC == SrcRC)
1910 /* Source and destination have the same register class. */;
1911 else if (CommonRC->hasSuperClass(SrcRC))
1913 else if (!DestRC->hasSubClass(SrcRC)) {
1914 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1915 // but we want to copy them as GR64. Similarly, for GR32_NOREX and
1916 // GR32_NOSP, copy as GR32.
1917 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1918 DestRC->hasSuperClass(&X86::GR64RegClass))
1919 CommonRC = &X86::GR64RegClass;
1920 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1921 DestRC->hasSuperClass(&X86::GR32RegClass))
1922 CommonRC = &X86::GR32RegClass;
1929 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1931 } else if (CommonRC == &X86::GR32RegClass ||
1932 CommonRC == &X86::GR32_NOSPRegClass) {
1934 } else if (CommonRC == &X86::GR16RegClass) {
1936 } else if (CommonRC == &X86::GR8RegClass) {
1937 // Copying to or from a physical H register on x86-64 requires a NOREX
1938 // move. Otherwise use a normal move.
1939 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1940 TM.getSubtarget<X86Subtarget>().is64Bit())
1941 Opc = X86::MOV8rr_NOREX;
1944 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1946 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1948 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1950 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1952 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1953 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1954 Opc = X86::MOV8rr_NOREX;
1957 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1958 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1960 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1962 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1964 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1966 } else if (CommonRC == &X86::GR64_TCRegClass) {
1967 Opc = X86::MOV64rr_TC;
1968 } else if (CommonRC == &X86::GR32_TCRegClass) {
1969 Opc = X86::MOV32rr_TC;
1970 } else if (CommonRC == &X86::RFP32RegClass) {
1971 Opc = X86::MOV_Fp3232;
1972 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1973 Opc = X86::MOV_Fp6464;
1974 } else if (CommonRC == &X86::RFP80RegClass) {
1975 Opc = X86::MOV_Fp8080;
1976 } else if (CommonRC == &X86::FR32RegClass) {
1977 Opc = X86::FsMOVAPSrr;
1978 } else if (CommonRC == &X86::FR64RegClass) {
1979 Opc = X86::FsMOVAPDrr;
1980 } else if (CommonRC == &X86::VR128RegClass) {
1981 Opc = X86::MOVAPSrr;
1982 } else if (CommonRC == &X86::VR64RegClass) {
1983 Opc = X86::MMX_MOVQ64rr;
1987 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1991 // Moving EFLAGS to / from another register requires a push and a pop.
1992 if (SrcRC == &X86::CCRRegClass) {
1993 if (SrcReg != X86::EFLAGS)
1995 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1996 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
1997 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1999 } else if (DestRC == &X86::GR32RegClass ||
2000 DestRC == &X86::GR32_NOSPRegClass) {
2001 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
2002 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2005 } else if (DestRC == &X86::CCRRegClass) {
2006 if (DestReg != X86::EFLAGS)
2008 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
2009 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
2010 BuildMI(MBB, MI, DL, get(X86::POPFQ));
2012 } else if (SrcRC == &X86::GR32RegClass ||
2013 DestRC == &X86::GR32_NOSPRegClass) {
2014 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
2015 BuildMI(MBB, MI, DL, get(X86::POPFD));
2020 // Moving from ST(0) turns into FpGET_ST0_32 etc.
2021 if (SrcRC == &X86::RSTRegClass) {
2022 // Copying from ST(0)/ST(1).
2023 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
2024 // Can only copy from ST(0)/ST(1) right now
2026 bool isST0 = SrcReg == X86::ST0;
2028 if (DestRC == &X86::RFP32RegClass)
2029 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
2030 else if (DestRC == &X86::RFP64RegClass)
2031 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
2033 if (DestRC != &X86::RFP80RegClass)
2035 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
2037 BuildMI(MBB, MI, DL, get(Opc), DestReg);
2041 // Moving to ST(0) turns into FpSET_ST0_32 etc.
2042 if (DestRC == &X86::RSTRegClass) {
2043 // Copying to ST(0) / ST(1).
2044 if (DestReg != X86::ST0 && DestReg != X86::ST1)
2045 // Can only copy to TOS right now
2047 bool isST0 = DestReg == X86::ST0;
2049 if (SrcRC == &X86::RFP32RegClass)
2050 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
2051 else if (SrcRC == &X86::RFP64RegClass)
2052 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
2054 if (SrcRC != &X86::RFP80RegClass)
2056 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
2058 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
2062 // Not yet supported!
2066 static unsigned getStoreRegOpcode(unsigned SrcReg,
2067 const TargetRegisterClass *RC,
2068 bool isStackAligned,
2069 TargetMachine &TM) {
2071 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2073 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2075 } else if (RC == &X86::GR16RegClass) {
2077 } else if (RC == &X86::GR8RegClass) {
2078 // Copying to or from a physical H register on x86-64 requires a NOREX
2079 // move. Otherwise use a normal move.
2080 if (isHReg(SrcReg) &&
2081 TM.getSubtarget<X86Subtarget>().is64Bit())
2082 Opc = X86::MOV8mr_NOREX;
2085 } else if (RC == &X86::GR64_ABCDRegClass) {
2087 } else if (RC == &X86::GR32_ABCDRegClass) {
2089 } else if (RC == &X86::GR16_ABCDRegClass) {
2091 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2093 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2094 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2095 Opc = X86::MOV8mr_NOREX;
2098 } else if (RC == &X86::GR64_NOREXRegClass ||
2099 RC == &X86::GR64_NOREX_NOSPRegClass) {
2101 } else if (RC == &X86::GR32_NOREXRegClass) {
2103 } else if (RC == &X86::GR16_NOREXRegClass) {
2105 } else if (RC == &X86::GR8_NOREXRegClass) {
2107 } else if (RC == &X86::GR64_TCRegClass) {
2108 Opc = X86::MOV64mr_TC;
2109 } else if (RC == &X86::GR32_TCRegClass) {
2110 Opc = X86::MOV32mr_TC;
2111 } else if (RC == &X86::RFP80RegClass) {
2112 Opc = X86::ST_FpP80m; // pops
2113 } else if (RC == &X86::RFP64RegClass) {
2114 Opc = X86::ST_Fp64m;
2115 } else if (RC == &X86::RFP32RegClass) {
2116 Opc = X86::ST_Fp32m;
2117 } else if (RC == &X86::FR32RegClass) {
2119 } else if (RC == &X86::FR64RegClass) {
2121 } else if (RC == &X86::VR128RegClass) {
2122 // If stack is realigned we can use aligned stores.
2123 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
2124 } else if (RC == &X86::VR64RegClass) {
2125 Opc = X86::MMX_MOVQ64mr;
2127 llvm_unreachable("Unknown regclass");
2133 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2134 MachineBasicBlock::iterator MI,
2135 unsigned SrcReg, bool isKill, int FrameIdx,
2136 const TargetRegisterClass *RC) const {
2137 const MachineFunction &MF = *MBB.getParent();
2138 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2139 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2140 DebugLoc DL = MBB.findDebugLoc(MI);
2141 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2142 .addReg(SrcReg, getKillRegState(isKill));
2145 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2147 SmallVectorImpl<MachineOperand> &Addr,
2148 const TargetRegisterClass *RC,
2149 MachineInstr::mmo_iterator MMOBegin,
2150 MachineInstr::mmo_iterator MMOEnd,
2151 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2152 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2153 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2155 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2156 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2157 MIB.addOperand(Addr[i]);
2158 MIB.addReg(SrcReg, getKillRegState(isKill));
2159 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2160 NewMIs.push_back(MIB);
2163 static unsigned getLoadRegOpcode(unsigned DestReg,
2164 const TargetRegisterClass *RC,
2165 bool isStackAligned,
2166 const TargetMachine &TM) {
2168 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2170 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2172 } else if (RC == &X86::GR16RegClass) {
2174 } else if (RC == &X86::GR8RegClass) {
2175 // Copying to or from a physical H register on x86-64 requires a NOREX
2176 // move. Otherwise use a normal move.
2177 if (isHReg(DestReg) &&
2178 TM.getSubtarget<X86Subtarget>().is64Bit())
2179 Opc = X86::MOV8rm_NOREX;
2182 } else if (RC == &X86::GR64_ABCDRegClass) {
2184 } else if (RC == &X86::GR32_ABCDRegClass) {
2186 } else if (RC == &X86::GR16_ABCDRegClass) {
2188 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2190 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2191 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2192 Opc = X86::MOV8rm_NOREX;
2195 } else if (RC == &X86::GR64_NOREXRegClass ||
2196 RC == &X86::GR64_NOREX_NOSPRegClass) {
2198 } else if (RC == &X86::GR32_NOREXRegClass) {
2200 } else if (RC == &X86::GR16_NOREXRegClass) {
2202 } else if (RC == &X86::GR8_NOREXRegClass) {
2204 } else if (RC == &X86::GR64_TCRegClass) {
2205 Opc = X86::MOV64rm_TC;
2206 } else if (RC == &X86::GR32_TCRegClass) {
2207 Opc = X86::MOV32rm_TC;
2208 } else if (RC == &X86::RFP80RegClass) {
2209 Opc = X86::LD_Fp80m;
2210 } else if (RC == &X86::RFP64RegClass) {
2211 Opc = X86::LD_Fp64m;
2212 } else if (RC == &X86::RFP32RegClass) {
2213 Opc = X86::LD_Fp32m;
2214 } else if (RC == &X86::FR32RegClass) {
2216 } else if (RC == &X86::FR64RegClass) {
2218 } else if (RC == &X86::VR128RegClass) {
2219 // If stack is realigned we can use aligned loads.
2220 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2221 } else if (RC == &X86::VR64RegClass) {
2222 Opc = X86::MMX_MOVQ64rm;
2224 llvm_unreachable("Unknown regclass");
2230 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2231 MachineBasicBlock::iterator MI,
2232 unsigned DestReg, int FrameIdx,
2233 const TargetRegisterClass *RC) const{
2234 const MachineFunction &MF = *MBB.getParent();
2235 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2236 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2237 DebugLoc DL = MBB.findDebugLoc(MI);
2238 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2241 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2242 SmallVectorImpl<MachineOperand> &Addr,
2243 const TargetRegisterClass *RC,
2244 MachineInstr::mmo_iterator MMOBegin,
2245 MachineInstr::mmo_iterator MMOEnd,
2246 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2247 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2248 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2250 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2251 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2252 MIB.addOperand(Addr[i]);
2253 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2254 NewMIs.push_back(MIB);
2257 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2258 MachineBasicBlock::iterator MI,
2259 const std::vector<CalleeSavedInfo> &CSI) const {
2263 DebugLoc DL = MBB.findDebugLoc(MI);
2265 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2266 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2267 unsigned SlotSize = is64Bit ? 8 : 4;
2269 MachineFunction &MF = *MBB.getParent();
2270 unsigned FPReg = RI.getFrameRegister(MF);
2271 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2272 unsigned CalleeFrameSize = 0;
2274 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2275 for (unsigned i = CSI.size(); i != 0; --i) {
2276 unsigned Reg = CSI[i-1].getReg();
2277 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2278 // Add the callee-saved register as live-in. It's killed at the spill.
2281 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2283 if (RegClass != &X86::VR128RegClass && !isWin64) {
2284 CalleeFrameSize += SlotSize;
2285 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2287 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2291 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2295 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2296 MachineBasicBlock::iterator MI,
2297 const std::vector<CalleeSavedInfo> &CSI) const {
2301 DebugLoc DL = MBB.findDebugLoc(MI);
2303 MachineFunction &MF = *MBB.getParent();
2304 unsigned FPReg = RI.getFrameRegister(MF);
2305 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2306 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2307 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2308 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2309 unsigned Reg = CSI[i].getReg();
2311 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2313 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2314 if (RegClass != &X86::VR128RegClass && !isWin64) {
2315 BuildMI(MBB, MI, DL, get(Opc), Reg);
2317 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2324 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2325 int FrameIx, uint64_t Offset,
2326 const MDNode *MDPtr,
2327 DebugLoc DL) const {
2329 AM.BaseType = X86AddressMode::FrameIndexBase;
2330 AM.Base.FrameIndex = FrameIx;
2331 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2332 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2336 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2337 const SmallVectorImpl<MachineOperand> &MOs,
2339 const TargetInstrInfo &TII) {
2340 // Create the base instruction with the memory operand as the first part.
2341 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2342 MI->getDebugLoc(), true);
2343 MachineInstrBuilder MIB(NewMI);
2344 unsigned NumAddrOps = MOs.size();
2345 for (unsigned i = 0; i != NumAddrOps; ++i)
2346 MIB.addOperand(MOs[i]);
2347 if (NumAddrOps < 4) // FrameIndex only
2350 // Loop over the rest of the ri operands, converting them over.
2351 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2352 for (unsigned i = 0; i != NumOps; ++i) {
2353 MachineOperand &MO = MI->getOperand(i+2);
2356 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2357 MachineOperand &MO = MI->getOperand(i);
2363 static MachineInstr *FuseInst(MachineFunction &MF,
2364 unsigned Opcode, unsigned OpNo,
2365 const SmallVectorImpl<MachineOperand> &MOs,
2366 MachineInstr *MI, const TargetInstrInfo &TII) {
2367 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2368 MI->getDebugLoc(), true);
2369 MachineInstrBuilder MIB(NewMI);
2371 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2372 MachineOperand &MO = MI->getOperand(i);
2374 assert(MO.isReg() && "Expected to fold into reg operand!");
2375 unsigned NumAddrOps = MOs.size();
2376 for (unsigned i = 0; i != NumAddrOps; ++i)
2377 MIB.addOperand(MOs[i]);
2378 if (NumAddrOps < 4) // FrameIndex only
2387 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2388 const SmallVectorImpl<MachineOperand> &MOs,
2390 MachineFunction &MF = *MI->getParent()->getParent();
2391 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2393 unsigned NumAddrOps = MOs.size();
2394 for (unsigned i = 0; i != NumAddrOps; ++i)
2395 MIB.addOperand(MOs[i]);
2396 if (NumAddrOps < 4) // FrameIndex only
2398 return MIB.addImm(0);
2402 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2403 MachineInstr *MI, unsigned i,
2404 const SmallVectorImpl<MachineOperand> &MOs,
2405 unsigned Size, unsigned Align) const {
2406 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2407 bool isTwoAddrFold = false;
2408 unsigned NumOps = MI->getDesc().getNumOperands();
2409 bool isTwoAddr = NumOps > 1 &&
2410 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2412 MachineInstr *NewMI = NULL;
2413 // Folding a memory location into the two-address part of a two-address
2414 // instruction is different than folding it other places. It requires
2415 // replacing the *two* registers with the memory location.
2416 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2417 MI->getOperand(0).isReg() &&
2418 MI->getOperand(1).isReg() &&
2419 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2420 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2421 isTwoAddrFold = true;
2422 } else if (i == 0) { // If operand 0
2423 if (MI->getOpcode() == X86::MOV64r0)
2424 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2425 else if (MI->getOpcode() == X86::MOV32r0)
2426 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2427 else if (MI->getOpcode() == X86::MOV16r0)
2428 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2429 else if (MI->getOpcode() == X86::MOV8r0)
2430 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2434 OpcodeTablePtr = &RegOp2MemOpTable0;
2435 } else if (i == 1) {
2436 OpcodeTablePtr = &RegOp2MemOpTable1;
2437 } else if (i == 2) {
2438 OpcodeTablePtr = &RegOp2MemOpTable2;
2441 // If table selected...
2442 if (OpcodeTablePtr) {
2443 // Find the Opcode to fuse
2444 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2445 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2446 if (I != OpcodeTablePtr->end()) {
2447 unsigned Opcode = I->second.first;
2448 unsigned MinAlign = I->second.second;
2449 if (Align < MinAlign)
2451 bool NarrowToMOV32rm = false;
2453 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2454 if (Size < RCSize) {
2455 // Check if it's safe to fold the load. If the size of the object is
2456 // narrower than the load width, then it's not.
2457 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2459 // If this is a 64-bit load, but the spill slot is 32, then we can do
2460 // a 32-bit load which is implicitly zero-extended. This likely is due
2461 // to liveintervalanalysis remat'ing a load from stack slot.
2462 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2464 Opcode = X86::MOV32rm;
2465 NarrowToMOV32rm = true;
2470 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2472 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2474 if (NarrowToMOV32rm) {
2475 // If this is the special case where we use a MOV32rm to load a 32-bit
2476 // value and zero-extend the top bits. Change the destination register
2478 unsigned DstReg = NewMI->getOperand(0).getReg();
2479 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2480 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2481 4/*x86_subreg_32bit*/));
2483 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2490 if (PrintFailedFusing)
2491 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2496 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2498 const SmallVectorImpl<unsigned> &Ops,
2499 int FrameIndex) const {
2500 // Check switch flag
2501 if (NoFusing) return NULL;
2503 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2504 switch (MI->getOpcode()) {
2505 case X86::CVTSD2SSrr:
2506 case X86::Int_CVTSD2SSrr:
2507 case X86::CVTSS2SDrr:
2508 case X86::Int_CVTSS2SDrr:
2510 case X86::RCPSSr_Int:
2511 case X86::ROUNDSDr_Int:
2512 case X86::ROUNDSSr_Int:
2514 case X86::RSQRTSSr_Int:
2516 case X86::SQRTSSr_Int:
2520 const MachineFrameInfo *MFI = MF.getFrameInfo();
2521 unsigned Size = MFI->getObjectSize(FrameIndex);
2522 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2523 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2524 unsigned NewOpc = 0;
2525 unsigned RCSize = 0;
2526 switch (MI->getOpcode()) {
2527 default: return NULL;
2528 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2529 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2530 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2531 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2533 // Check if it's safe to fold the load. If the size of the object is
2534 // narrower than the load width, then it's not.
2537 // Change to CMPXXri r, 0 first.
2538 MI->setDesc(get(NewOpc));
2539 MI->getOperand(1).ChangeToImmediate(0);
2540 } else if (Ops.size() != 1)
2543 SmallVector<MachineOperand,4> MOs;
2544 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2545 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2548 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2550 const SmallVectorImpl<unsigned> &Ops,
2551 MachineInstr *LoadMI) const {
2552 // Check switch flag
2553 if (NoFusing) return NULL;
2555 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2556 switch (MI->getOpcode()) {
2557 case X86::CVTSD2SSrr:
2558 case X86::Int_CVTSD2SSrr:
2559 case X86::CVTSS2SDrr:
2560 case X86::Int_CVTSS2SDrr:
2562 case X86::RCPSSr_Int:
2563 case X86::ROUNDSDr_Int:
2564 case X86::ROUNDSSr_Int:
2566 case X86::RSQRTSSr_Int:
2568 case X86::SQRTSSr_Int:
2572 // Determine the alignment of the load.
2573 unsigned Alignment = 0;
2574 if (LoadMI->hasOneMemOperand())
2575 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2577 switch (LoadMI->getOpcode()) {
2581 case X86::V_SETALLONES:
2591 llvm_unreachable("Don't know how to fold this instruction!");
2593 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2594 unsigned NewOpc = 0;
2595 switch (MI->getOpcode()) {
2596 default: return NULL;
2597 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2598 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2599 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2600 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2602 // Change to CMPXXri r, 0 first.
2603 MI->setDesc(get(NewOpc));
2604 MI->getOperand(1).ChangeToImmediate(0);
2605 } else if (Ops.size() != 1)
2608 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2609 switch (LoadMI->getOpcode()) {
2613 case X86::V_SETALLONES:
2615 case X86::FsFLD0SS: {
2616 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2617 // Create a constant-pool entry and operands to load from it.
2619 // Medium and large mode can't fold loads this way.
2620 if (TM.getCodeModel() != CodeModel::Small &&
2621 TM.getCodeModel() != CodeModel::Kernel)
2624 // x86-32 PIC requires a PIC base register for constant pools.
2625 unsigned PICBase = 0;
2626 if (TM.getRelocationModel() == Reloc::PIC_) {
2627 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2630 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2631 // This doesn't work for several reasons.
2632 // 1. GlobalBaseReg may have been spilled.
2633 // 2. It may not be live at MI.
2637 // Create a constant-pool entry.
2638 MachineConstantPool &MCP = *MF.getConstantPool();
2640 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2641 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2642 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2643 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2645 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2646 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2647 Constant::getAllOnesValue(Ty) :
2648 Constant::getNullValue(Ty);
2649 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2651 // Create operands to load from the constant pool entry.
2652 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2653 MOs.push_back(MachineOperand::CreateImm(1));
2654 MOs.push_back(MachineOperand::CreateReg(0, false));
2655 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2656 MOs.push_back(MachineOperand::CreateReg(0, false));
2660 // Folding a normal load. Just copy the load's address operands.
2661 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2662 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2663 MOs.push_back(LoadMI->getOperand(i));
2667 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2671 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2672 const SmallVectorImpl<unsigned> &Ops) const {
2673 // Check switch flag
2674 if (NoFusing) return 0;
2676 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2677 switch (MI->getOpcode()) {
2678 default: return false;
2687 if (Ops.size() != 1)
2690 unsigned OpNum = Ops[0];
2691 unsigned Opc = MI->getOpcode();
2692 unsigned NumOps = MI->getDesc().getNumOperands();
2693 bool isTwoAddr = NumOps > 1 &&
2694 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2696 // Folding a memory location into the two-address part of a two-address
2697 // instruction is different than folding it other places. It requires
2698 // replacing the *two* registers with the memory location.
2699 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2700 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2701 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2702 } else if (OpNum == 0) { // If operand 0
2711 OpcodeTablePtr = &RegOp2MemOpTable0;
2712 } else if (OpNum == 1) {
2713 OpcodeTablePtr = &RegOp2MemOpTable1;
2714 } else if (OpNum == 2) {
2715 OpcodeTablePtr = &RegOp2MemOpTable2;
2718 if (OpcodeTablePtr) {
2719 // Find the Opcode to fuse
2720 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2721 OpcodeTablePtr->find((unsigned*)Opc);
2722 if (I != OpcodeTablePtr->end())
2728 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2729 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2730 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2731 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2732 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2733 if (I == MemOp2RegOpTable.end())
2735 unsigned Opc = I->second.first;
2736 unsigned Index = I->second.second & 0xf;
2737 bool FoldedLoad = I->second.second & (1 << 4);
2738 bool FoldedStore = I->second.second & (1 << 5);
2739 if (UnfoldLoad && !FoldedLoad)
2741 UnfoldLoad &= FoldedLoad;
2742 if (UnfoldStore && !FoldedStore)
2744 UnfoldStore &= FoldedStore;
2746 const TargetInstrDesc &TID = get(Opc);
2747 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2748 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2749 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2750 SmallVector<MachineOperand,2> BeforeOps;
2751 SmallVector<MachineOperand,2> AfterOps;
2752 SmallVector<MachineOperand,4> ImpOps;
2753 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2754 MachineOperand &Op = MI->getOperand(i);
2755 if (i >= Index && i < Index + X86AddrNumOperands)
2756 AddrOps.push_back(Op);
2757 else if (Op.isReg() && Op.isImplicit())
2758 ImpOps.push_back(Op);
2760 BeforeOps.push_back(Op);
2762 AfterOps.push_back(Op);
2765 // Emit the load instruction.
2767 std::pair<MachineInstr::mmo_iterator,
2768 MachineInstr::mmo_iterator> MMOs =
2769 MF.extractLoadMemRefs(MI->memoperands_begin(),
2770 MI->memoperands_end());
2771 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2773 // Address operands cannot be marked isKill.
2774 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2775 MachineOperand &MO = NewMIs[0]->getOperand(i);
2777 MO.setIsKill(false);
2782 // Emit the data processing instruction.
2783 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2784 MachineInstrBuilder MIB(DataMI);
2787 MIB.addReg(Reg, RegState::Define);
2788 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2789 MIB.addOperand(BeforeOps[i]);
2792 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2793 MIB.addOperand(AfterOps[i]);
2794 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2795 MachineOperand &MO = ImpOps[i];
2796 MIB.addReg(MO.getReg(),
2797 getDefRegState(MO.isDef()) |
2798 RegState::Implicit |
2799 getKillRegState(MO.isKill()) |
2800 getDeadRegState(MO.isDead()) |
2801 getUndefRegState(MO.isUndef()));
2803 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2804 unsigned NewOpc = 0;
2805 switch (DataMI->getOpcode()) {
2807 case X86::CMP64ri32:
2811 MachineOperand &MO0 = DataMI->getOperand(0);
2812 MachineOperand &MO1 = DataMI->getOperand(1);
2813 if (MO1.getImm() == 0) {
2814 switch (DataMI->getOpcode()) {
2816 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2817 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2818 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2819 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2821 DataMI->setDesc(get(NewOpc));
2822 MO1.ChangeToRegister(MO0.getReg(), false);
2826 NewMIs.push_back(DataMI);
2828 // Emit the store instruction.
2830 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2831 std::pair<MachineInstr::mmo_iterator,
2832 MachineInstr::mmo_iterator> MMOs =
2833 MF.extractStoreMemRefs(MI->memoperands_begin(),
2834 MI->memoperands_end());
2835 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2842 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2843 SmallVectorImpl<SDNode*> &NewNodes) const {
2844 if (!N->isMachineOpcode())
2847 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2848 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2849 if (I == MemOp2RegOpTable.end())
2851 unsigned Opc = I->second.first;
2852 unsigned Index = I->second.second & 0xf;
2853 bool FoldedLoad = I->second.second & (1 << 4);
2854 bool FoldedStore = I->second.second & (1 << 5);
2855 const TargetInstrDesc &TID = get(Opc);
2856 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2857 unsigned NumDefs = TID.NumDefs;
2858 std::vector<SDValue> AddrOps;
2859 std::vector<SDValue> BeforeOps;
2860 std::vector<SDValue> AfterOps;
2861 DebugLoc dl = N->getDebugLoc();
2862 unsigned NumOps = N->getNumOperands();
2863 for (unsigned i = 0; i != NumOps-1; ++i) {
2864 SDValue Op = N->getOperand(i);
2865 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2866 AddrOps.push_back(Op);
2867 else if (i < Index-NumDefs)
2868 BeforeOps.push_back(Op);
2869 else if (i > Index-NumDefs)
2870 AfterOps.push_back(Op);
2872 SDValue Chain = N->getOperand(NumOps-1);
2873 AddrOps.push_back(Chain);
2875 // Emit the load instruction.
2877 MachineFunction &MF = DAG.getMachineFunction();
2879 EVT VT = *RC->vt_begin();
2880 std::pair<MachineInstr::mmo_iterator,
2881 MachineInstr::mmo_iterator> MMOs =
2882 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2883 cast<MachineSDNode>(N)->memoperands_end());
2884 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2885 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2886 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2887 NewNodes.push_back(Load);
2889 // Preserve memory reference information.
2890 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2893 // Emit the data processing instruction.
2894 std::vector<EVT> VTs;
2895 const TargetRegisterClass *DstRC = 0;
2896 if (TID.getNumDefs() > 0) {
2897 DstRC = TID.OpInfo[0].getRegClass(&RI);
2898 VTs.push_back(*DstRC->vt_begin());
2900 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2901 EVT VT = N->getValueType(i);
2902 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2906 BeforeOps.push_back(SDValue(Load, 0));
2907 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2908 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2910 NewNodes.push_back(NewNode);
2912 // Emit the store instruction.
2915 AddrOps.push_back(SDValue(NewNode, 0));
2916 AddrOps.push_back(Chain);
2917 std::pair<MachineInstr::mmo_iterator,
2918 MachineInstr::mmo_iterator> MMOs =
2919 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2920 cast<MachineSDNode>(N)->memoperands_end());
2921 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2922 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2925 &AddrOps[0], AddrOps.size());
2926 NewNodes.push_back(Store);
2928 // Preserve memory reference information.
2929 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2935 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2936 bool UnfoldLoad, bool UnfoldStore,
2937 unsigned *LoadRegIndex) const {
2938 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2939 MemOp2RegOpTable.find((unsigned*)Opc);
2940 if (I == MemOp2RegOpTable.end())
2942 bool FoldedLoad = I->second.second & (1 << 4);
2943 bool FoldedStore = I->second.second & (1 << 5);
2944 if (UnfoldLoad && !FoldedLoad)
2946 if (UnfoldStore && !FoldedStore)
2949 *LoadRegIndex = I->second.second & 0xf;
2950 return I->second.first;
2954 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2955 int64_t &Offset1, int64_t &Offset2) const {
2956 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2958 unsigned Opc1 = Load1->getMachineOpcode();
2959 unsigned Opc2 = Load2->getMachineOpcode();
2961 default: return false;
2971 case X86::MMX_MOVD64rm:
2972 case X86::MMX_MOVQ64rm:
2973 case X86::FsMOVAPSrm:
2974 case X86::FsMOVAPDrm:
2977 case X86::MOVUPSrm_Int:
2981 case X86::MOVDQUrm_Int:
2985 default: return false;
2995 case X86::MMX_MOVD64rm:
2996 case X86::MMX_MOVQ64rm:
2997 case X86::FsMOVAPSrm:
2998 case X86::FsMOVAPDrm:
3001 case X86::MOVUPSrm_Int:
3005 case X86::MOVDQUrm_Int:
3009 // Check if chain operands and base addresses match.
3010 if (Load1->getOperand(0) != Load2->getOperand(0) ||
3011 Load1->getOperand(5) != Load2->getOperand(5))
3013 // Segment operands should match as well.
3014 if (Load1->getOperand(4) != Load2->getOperand(4))
3016 // Scale should be 1, Index should be Reg0.
3017 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3018 Load1->getOperand(2) == Load2->getOperand(2)) {
3019 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3022 // Now let's examine the displacements.
3023 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3024 isa<ConstantSDNode>(Load2->getOperand(3))) {
3025 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3026 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3033 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3034 int64_t Offset1, int64_t Offset2,
3035 unsigned NumLoads) const {
3036 assert(Offset2 > Offset1);
3037 if ((Offset2 - Offset1) / 8 > 64)
3040 unsigned Opc1 = Load1->getMachineOpcode();
3041 unsigned Opc2 = Load2->getMachineOpcode();
3043 return false; // FIXME: overly conservative?
3050 case X86::MMX_MOVD64rm:
3051 case X86::MMX_MOVQ64rm:
3055 EVT VT = Load1->getValueType(0);
3056 switch (VT.getSimpleVT().SimpleTy) {
3058 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3059 // have 16 of them to play with.
3060 if (TM.getSubtargetImpl()->is64Bit()) {
3063 } else if (NumLoads)
3082 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3083 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3084 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3085 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3087 Cond[0].setImm(GetOppositeBranchCondition(CC));
3092 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3093 // FIXME: Return false for x87 stack register classes for now. We can't
3094 // allow any loads of these registers before FpGet_ST0_80.
3095 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3096 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3100 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3101 /// register? e.g. r8, xmm8, xmm13, etc.
3102 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3105 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3106 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3107 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3108 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3109 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3110 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3111 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3112 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3113 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3114 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3121 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
3122 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
3123 /// size, and 3) use of X86-64 extended registers.
3124 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
3126 const TargetInstrDesc &Desc = MI.getDesc();
3128 // Pseudo instructions do not need REX prefix byte.
3129 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
3131 if (Desc.TSFlags & X86II::REX_W)
3134 unsigned NumOps = Desc.getNumOperands();
3136 bool isTwoAddr = NumOps > 1 &&
3137 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
3139 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
3140 unsigned i = isTwoAddr ? 1 : 0;
3141 for (unsigned e = NumOps; i != e; ++i) {
3142 const MachineOperand& MO = MI.getOperand(i);
3144 unsigned Reg = MO.getReg();
3145 if (isX86_64NonExtLowByteReg(Reg))
3150 switch (Desc.TSFlags & X86II::FormMask) {
3151 case X86II::MRMInitReg:
3152 if (isX86_64ExtendedReg(MI.getOperand(0)))
3153 REX |= (1 << 0) | (1 << 2);
3155 case X86II::MRMSrcReg: {
3156 if (isX86_64ExtendedReg(MI.getOperand(0)))
3158 i = isTwoAddr ? 2 : 1;
3159 for (unsigned e = NumOps; i != e; ++i) {
3160 const MachineOperand& MO = MI.getOperand(i);
3161 if (isX86_64ExtendedReg(MO))
3166 case X86II::MRMSrcMem: {
3167 if (isX86_64ExtendedReg(MI.getOperand(0)))
3170 i = isTwoAddr ? 2 : 1;
3171 for (; i != NumOps; ++i) {
3172 const MachineOperand& MO = MI.getOperand(i);
3174 if (isX86_64ExtendedReg(MO))
3181 case X86II::MRM0m: case X86II::MRM1m:
3182 case X86II::MRM2m: case X86II::MRM3m:
3183 case X86II::MRM4m: case X86II::MRM5m:
3184 case X86II::MRM6m: case X86II::MRM7m:
3185 case X86II::MRMDestMem: {
3186 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
3187 i = isTwoAddr ? 1 : 0;
3188 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
3191 for (; i != e; ++i) {
3192 const MachineOperand& MO = MI.getOperand(i);
3194 if (isX86_64ExtendedReg(MO))
3202 if (isX86_64ExtendedReg(MI.getOperand(0)))
3204 i = isTwoAddr ? 2 : 1;
3205 for (unsigned e = NumOps; i != e; ++i) {
3206 const MachineOperand& MO = MI.getOperand(i);
3207 if (isX86_64ExtendedReg(MO))
3217 /// sizePCRelativeBlockAddress - This method returns the size of a PC
3218 /// relative block address instruction
3220 static unsigned sizePCRelativeBlockAddress() {
3224 /// sizeGlobalAddress - Give the size of the emission of this global address
3226 static unsigned sizeGlobalAddress(bool dword) {
3227 return dword ? 8 : 4;
3230 /// sizeConstPoolAddress - Give the size of the emission of this constant
3233 static unsigned sizeConstPoolAddress(bool dword) {
3234 return dword ? 8 : 4;
3237 /// sizeExternalSymbolAddress - Give the size of the emission of this external
3240 static unsigned sizeExternalSymbolAddress(bool dword) {
3241 return dword ? 8 : 4;
3244 /// sizeJumpTableAddress - Give the size of the emission of this jump
3247 static unsigned sizeJumpTableAddress(bool dword) {
3248 return dword ? 8 : 4;
3251 static unsigned sizeConstant(unsigned Size) {
3255 static unsigned sizeRegModRMByte(){
3259 static unsigned sizeSIBByte(){
3263 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3264 unsigned FinalSize = 0;
3265 // If this is a simple integer displacement that doesn't require a relocation.
3267 FinalSize += sizeConstant(4);
3271 // Otherwise, this is something that requires a relocation.
3272 if (RelocOp->isGlobal()) {
3273 FinalSize += sizeGlobalAddress(false);
3274 } else if (RelocOp->isCPI()) {
3275 FinalSize += sizeConstPoolAddress(false);
3276 } else if (RelocOp->isJTI()) {
3277 FinalSize += sizeJumpTableAddress(false);
3279 llvm_unreachable("Unknown value to relocate!");
3284 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3285 bool IsPIC, bool Is64BitMode) {
3286 const MachineOperand &Op3 = MI.getOperand(Op+3);
3288 const MachineOperand *DispForReloc = 0;
3289 unsigned FinalSize = 0;
3291 // Figure out what sort of displacement we have to handle here.
3292 if (Op3.isGlobal()) {
3293 DispForReloc = &Op3;
3294 } else if (Op3.isCPI()) {
3295 if (Is64BitMode || IsPIC) {
3296 DispForReloc = &Op3;
3300 } else if (Op3.isJTI()) {
3301 if (Is64BitMode || IsPIC) {
3302 DispForReloc = &Op3;
3310 const MachineOperand &Base = MI.getOperand(Op);
3311 const MachineOperand &IndexReg = MI.getOperand(Op+2);
3313 unsigned BaseReg = Base.getReg();
3315 // Is a SIB byte needed?
3316 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3317 IndexReg.getReg() == 0 &&
3318 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3319 if (BaseReg == 0) { // Just a displacement?
3320 // Emit special case [disp32] encoding
3322 FinalSize += getDisplacementFieldSize(DispForReloc);
3324 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3325 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3326 // Emit simple indirect register encoding... [EAX] f.e.
3328 // Be pessimistic and assume it's a disp32, not a disp8
3330 // Emit the most general non-SIB encoding: [REG+disp32]
3332 FinalSize += getDisplacementFieldSize(DispForReloc);
3336 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
3337 assert(IndexReg.getReg() != X86::ESP &&
3338 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3340 bool ForceDisp32 = false;
3341 if (BaseReg == 0 || DispForReloc) {
3342 // Emit the normal disp32 encoding.
3349 FinalSize += sizeSIBByte();
3351 // Do we need to output a displacement?
3352 if (DispVal != 0 || ForceDisp32) {
3353 FinalSize += getDisplacementFieldSize(DispForReloc);
3360 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3361 const TargetInstrDesc *Desc,
3362 bool IsPIC, bool Is64BitMode) {
3364 unsigned Opcode = Desc->Opcode;
3365 unsigned FinalSize = 0;
3367 // Emit the lock opcode prefix as needed.
3368 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3370 // Emit segment override opcode prefix as needed.
3371 switch (Desc->TSFlags & X86II::SegOvrMask) {
3376 default: llvm_unreachable("Invalid segment!");
3377 case 0: break; // No segment override!
3380 // Emit the repeat opcode prefix as needed.
3381 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3383 // Emit the operand size opcode prefix as needed.
3384 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3386 // Emit the address size opcode prefix as needed.
3387 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3389 bool Need0FPrefix = false;
3390 switch (Desc->TSFlags & X86II::Op0Mask) {
3391 case X86II::TB: // Two-byte opcode prefix
3392 case X86II::T8: // 0F 38
3393 case X86II::TA: // 0F 3A
3394 Need0FPrefix = true;
3396 case X86II::TF: // F2 0F 38
3398 Need0FPrefix = true;
3400 case X86II::REP: break; // already handled.
3401 case X86II::XS: // F3 0F
3403 Need0FPrefix = true;
3405 case X86II::XD: // F2 0F
3407 Need0FPrefix = true;
3409 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3410 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3412 break; // Two-byte opcode prefix
3413 default: llvm_unreachable("Invalid prefix!");
3414 case 0: break; // No prefix!
3419 unsigned REX = X86InstrInfo::determineREX(MI);
3424 // 0x0F escape code must be emitted just before the opcode.
3428 switch (Desc->TSFlags & X86II::Op0Mask) {
3429 case X86II::T8: // 0F 38
3432 case X86II::TA: // 0F 3A
3435 case X86II::TF: // F2 0F 38
3440 // If this is a two-address instruction, skip one of the register operands.
3441 unsigned NumOps = Desc->getNumOperands();
3443 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3445 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3446 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3449 switch (Desc->TSFlags & X86II::FormMask) {
3450 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3452 // Remember the current PC offset, this is the PIC relocation
3457 case TargetOpcode::INLINEASM: {
3458 const MachineFunction *MF = MI.getParent()->getParent();
3459 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3460 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3461 *MF->getTarget().getMCAsmInfo());
3464 case TargetOpcode::DBG_LABEL:
3465 case TargetOpcode::EH_LABEL:
3466 case TargetOpcode::DBG_VALUE:
3468 case TargetOpcode::IMPLICIT_DEF:
3469 case TargetOpcode::KILL:
3470 case X86::FP_REG_KILL:
3472 case X86::MOVPC32r: {
3473 // This emits the "call" portion of this pseudo instruction.
3475 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3484 if (CurOp != NumOps) {
3485 const MachineOperand &MO = MI.getOperand(CurOp++);
3487 FinalSize += sizePCRelativeBlockAddress();
3488 } else if (MO.isGlobal()) {
3489 FinalSize += sizeGlobalAddress(false);
3490 } else if (MO.isSymbol()) {
3491 FinalSize += sizeExternalSymbolAddress(false);
3492 } else if (MO.isImm()) {
3493 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3495 llvm_unreachable("Unknown RawFrm operand!");
3500 case X86II::AddRegFrm:
3504 if (CurOp != NumOps) {
3505 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3506 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3508 FinalSize += sizeConstant(Size);
3511 if (Opcode == X86::MOV64ri)
3513 if (MO1.isGlobal()) {
3514 FinalSize += sizeGlobalAddress(dword);
3515 } else if (MO1.isSymbol())
3516 FinalSize += sizeExternalSymbolAddress(dword);
3517 else if (MO1.isCPI())
3518 FinalSize += sizeConstPoolAddress(dword);
3519 else if (MO1.isJTI())
3520 FinalSize += sizeJumpTableAddress(dword);
3525 case X86II::MRMDestReg: {
3527 FinalSize += sizeRegModRMByte();
3529 if (CurOp != NumOps) {
3531 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3535 case X86II::MRMDestMem: {
3537 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3538 CurOp += X86AddrNumOperands + 1;
3539 if (CurOp != NumOps) {
3541 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3546 case X86II::MRMSrcReg:
3548 FinalSize += sizeRegModRMByte();
3550 if (CurOp != NumOps) {
3552 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3556 case X86II::MRMSrcMem: {
3558 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3559 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3560 AddrOperands = X86AddrNumOperands - 1; // No segment register
3562 AddrOperands = X86AddrNumOperands;
3565 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3566 CurOp += AddrOperands + 1;
3567 if (CurOp != NumOps) {
3569 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3574 case X86II::MRM0r: case X86II::MRM1r:
3575 case X86II::MRM2r: case X86II::MRM3r:
3576 case X86II::MRM4r: case X86II::MRM5r:
3577 case X86II::MRM6r: case X86II::MRM7r:
3579 if (Desc->getOpcode() == X86::LFENCE ||
3580 Desc->getOpcode() == X86::MFENCE) {
3581 // Special handling of lfence and mfence;
3582 FinalSize += sizeRegModRMByte();
3583 } else if (Desc->getOpcode() == X86::MONITOR ||
3584 Desc->getOpcode() == X86::MWAIT) {
3585 // Special handling of monitor and mwait.
3586 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3589 FinalSize += sizeRegModRMByte();
3592 if (CurOp != NumOps) {
3593 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3594 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3596 FinalSize += sizeConstant(Size);
3599 if (Opcode == X86::MOV64ri32)
3601 if (MO1.isGlobal()) {
3602 FinalSize += sizeGlobalAddress(dword);
3603 } else if (MO1.isSymbol())
3604 FinalSize += sizeExternalSymbolAddress(dword);
3605 else if (MO1.isCPI())
3606 FinalSize += sizeConstPoolAddress(dword);
3607 else if (MO1.isJTI())
3608 FinalSize += sizeJumpTableAddress(dword);
3613 case X86II::MRM0m: case X86II::MRM1m:
3614 case X86II::MRM2m: case X86II::MRM3m:
3615 case X86II::MRM4m: case X86II::MRM5m:
3616 case X86II::MRM6m: case X86II::MRM7m: {
3619 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3620 CurOp += X86AddrNumOperands;
3622 if (CurOp != NumOps) {
3623 const MachineOperand &MO = MI.getOperand(CurOp++);
3624 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3626 FinalSize += sizeConstant(Size);
3629 if (Opcode == X86::MOV64mi32)
3631 if (MO.isGlobal()) {
3632 FinalSize += sizeGlobalAddress(dword);
3633 } else if (MO.isSymbol())
3634 FinalSize += sizeExternalSymbolAddress(dword);
3635 else if (MO.isCPI())
3636 FinalSize += sizeConstPoolAddress(dword);
3637 else if (MO.isJTI())
3638 FinalSize += sizeJumpTableAddress(dword);
3652 case X86II::MRMInitReg:
3654 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3655 FinalSize += sizeRegModRMByte();
3660 if (!Desc->isVariadic() && CurOp != NumOps) {
3662 raw_string_ostream Msg(msg);
3663 Msg << "Cannot determine size: " << MI;
3664 report_fatal_error(Msg.str());
3672 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3673 const TargetInstrDesc &Desc = MI->getDesc();
3674 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3675 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3676 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3677 if (Desc.getOpcode() == X86::MOVPC32r)
3678 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3682 /// getGlobalBaseReg - Return a virtual register initialized with the
3683 /// the global base register value. Output instructions required to
3684 /// initialize the register in the function entry block, if necessary.
3686 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3687 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3688 "X86-64 PIC uses RIP relative addressing");
3690 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3691 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3692 if (GlobalBaseReg != 0)
3693 return GlobalBaseReg;
3695 // Insert the set of GlobalBaseReg into the first MBB of the function
3696 MachineBasicBlock &FirstMBB = MF->front();
3697 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3698 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3699 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3700 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3702 const TargetInstrInfo *TII = TM.getInstrInfo();
3703 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3704 // only used in JIT code emission as displacement to pc.
3705 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3707 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3708 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3709 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3710 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3711 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3712 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3713 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3714 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3719 X86FI->setGlobalBaseReg(GlobalBaseReg);
3720 return GlobalBaseReg;
3723 // These are the replaceable SSE instructions. Some of these have Int variants
3724 // that we don't include here. We don't want to replace instructions selected
3726 static const unsigned ReplaceableInstrs[][3] = {
3727 //PackedInt PackedSingle PackedDouble
3728 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3729 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3730 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3731 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3732 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3733 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3734 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3735 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3736 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3737 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3738 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3739 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3740 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3741 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3742 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3745 // FIXME: Some shuffle and unpack instructions have equivalents in different
3746 // domains, but they require a bit more work than just switching opcodes.
3748 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3749 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3750 if (ReplaceableInstrs[i][domain-1] == opcode)
3751 return ReplaceableInstrs[i];
3755 std::pair<uint16_t, uint16_t>
3756 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3757 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3758 return std::make_pair(domain,
3759 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3762 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3763 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3764 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3765 assert(dom && "Not an SSE instruction");
3766 const unsigned *table = lookup(MI->getOpcode(), dom);
3767 assert(table && "Cannot change domain");
3768 MI->setDesc(get(table[Domain-1]));
3771 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3772 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3773 NopInst.setOpcode(X86::NOOP);