1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetAsmInfo.h"
38 NoFusing("disable-spill-fusing",
39 cl::desc("Disable fusing of spill code into instructions"));
41 PrintFailedFusing("print-failed-fuse-candidates",
42 cl::desc("Print instructions that the allocator wants to"
43 " fuse, but the X86 backend currently can't"),
46 ReMatPICStubLoad("remat-pic-stub-load",
47 cl::desc("Re-materialize load from stub in PIC mode"),
48 cl::init(false), cl::Hidden);
51 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
52 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
53 TM(tm), RI(tm, *this) {
54 SmallVector<unsigned,16> AmbEntries;
55 static const unsigned OpTbl2Addr[][2] = {
56 { X86::ADC32ri, X86::ADC32mi },
57 { X86::ADC32ri8, X86::ADC32mi8 },
58 { X86::ADC32rr, X86::ADC32mr },
59 { X86::ADC64ri32, X86::ADC64mi32 },
60 { X86::ADC64ri8, X86::ADC64mi8 },
61 { X86::ADC64rr, X86::ADC64mr },
62 { X86::ADD16ri, X86::ADD16mi },
63 { X86::ADD16ri8, X86::ADD16mi8 },
64 { X86::ADD16rr, X86::ADD16mr },
65 { X86::ADD32ri, X86::ADD32mi },
66 { X86::ADD32ri8, X86::ADD32mi8 },
67 { X86::ADD32rr, X86::ADD32mr },
68 { X86::ADD64ri32, X86::ADD64mi32 },
69 { X86::ADD64ri8, X86::ADD64mi8 },
70 { X86::ADD64rr, X86::ADD64mr },
71 { X86::ADD8ri, X86::ADD8mi },
72 { X86::ADD8rr, X86::ADD8mr },
73 { X86::AND16ri, X86::AND16mi },
74 { X86::AND16ri8, X86::AND16mi8 },
75 { X86::AND16rr, X86::AND16mr },
76 { X86::AND32ri, X86::AND32mi },
77 { X86::AND32ri8, X86::AND32mi8 },
78 { X86::AND32rr, X86::AND32mr },
79 { X86::AND64ri32, X86::AND64mi32 },
80 { X86::AND64ri8, X86::AND64mi8 },
81 { X86::AND64rr, X86::AND64mr },
82 { X86::AND8ri, X86::AND8mi },
83 { X86::AND8rr, X86::AND8mr },
84 { X86::DEC16r, X86::DEC16m },
85 { X86::DEC32r, X86::DEC32m },
86 { X86::DEC64_16r, X86::DEC64_16m },
87 { X86::DEC64_32r, X86::DEC64_32m },
88 { X86::DEC64r, X86::DEC64m },
89 { X86::DEC8r, X86::DEC8m },
90 { X86::INC16r, X86::INC16m },
91 { X86::INC32r, X86::INC32m },
92 { X86::INC64_16r, X86::INC64_16m },
93 { X86::INC64_32r, X86::INC64_32m },
94 { X86::INC64r, X86::INC64m },
95 { X86::INC8r, X86::INC8m },
96 { X86::NEG16r, X86::NEG16m },
97 { X86::NEG32r, X86::NEG32m },
98 { X86::NEG64r, X86::NEG64m },
99 { X86::NEG8r, X86::NEG8m },
100 { X86::NOT16r, X86::NOT16m },
101 { X86::NOT32r, X86::NOT32m },
102 { X86::NOT64r, X86::NOT64m },
103 { X86::NOT8r, X86::NOT8m },
104 { X86::OR16ri, X86::OR16mi },
105 { X86::OR16ri8, X86::OR16mi8 },
106 { X86::OR16rr, X86::OR16mr },
107 { X86::OR32ri, X86::OR32mi },
108 { X86::OR32ri8, X86::OR32mi8 },
109 { X86::OR32rr, X86::OR32mr },
110 { X86::OR64ri32, X86::OR64mi32 },
111 { X86::OR64ri8, X86::OR64mi8 },
112 { X86::OR64rr, X86::OR64mr },
113 { X86::OR8ri, X86::OR8mi },
114 { X86::OR8rr, X86::OR8mr },
115 { X86::ROL16r1, X86::ROL16m1 },
116 { X86::ROL16rCL, X86::ROL16mCL },
117 { X86::ROL16ri, X86::ROL16mi },
118 { X86::ROL32r1, X86::ROL32m1 },
119 { X86::ROL32rCL, X86::ROL32mCL },
120 { X86::ROL32ri, X86::ROL32mi },
121 { X86::ROL64r1, X86::ROL64m1 },
122 { X86::ROL64rCL, X86::ROL64mCL },
123 { X86::ROL64ri, X86::ROL64mi },
124 { X86::ROL8r1, X86::ROL8m1 },
125 { X86::ROL8rCL, X86::ROL8mCL },
126 { X86::ROL8ri, X86::ROL8mi },
127 { X86::ROR16r1, X86::ROR16m1 },
128 { X86::ROR16rCL, X86::ROR16mCL },
129 { X86::ROR16ri, X86::ROR16mi },
130 { X86::ROR32r1, X86::ROR32m1 },
131 { X86::ROR32rCL, X86::ROR32mCL },
132 { X86::ROR32ri, X86::ROR32mi },
133 { X86::ROR64r1, X86::ROR64m1 },
134 { X86::ROR64rCL, X86::ROR64mCL },
135 { X86::ROR64ri, X86::ROR64mi },
136 { X86::ROR8r1, X86::ROR8m1 },
137 { X86::ROR8rCL, X86::ROR8mCL },
138 { X86::ROR8ri, X86::ROR8mi },
139 { X86::SAR16r1, X86::SAR16m1 },
140 { X86::SAR16rCL, X86::SAR16mCL },
141 { X86::SAR16ri, X86::SAR16mi },
142 { X86::SAR32r1, X86::SAR32m1 },
143 { X86::SAR32rCL, X86::SAR32mCL },
144 { X86::SAR32ri, X86::SAR32mi },
145 { X86::SAR64r1, X86::SAR64m1 },
146 { X86::SAR64rCL, X86::SAR64mCL },
147 { X86::SAR64ri, X86::SAR64mi },
148 { X86::SAR8r1, X86::SAR8m1 },
149 { X86::SAR8rCL, X86::SAR8mCL },
150 { X86::SAR8ri, X86::SAR8mi },
151 { X86::SBB32ri, X86::SBB32mi },
152 { X86::SBB32ri8, X86::SBB32mi8 },
153 { X86::SBB32rr, X86::SBB32mr },
154 { X86::SBB64ri32, X86::SBB64mi32 },
155 { X86::SBB64ri8, X86::SBB64mi8 },
156 { X86::SBB64rr, X86::SBB64mr },
157 { X86::SHL16rCL, X86::SHL16mCL },
158 { X86::SHL16ri, X86::SHL16mi },
159 { X86::SHL32rCL, X86::SHL32mCL },
160 { X86::SHL32ri, X86::SHL32mi },
161 { X86::SHL64rCL, X86::SHL64mCL },
162 { X86::SHL64ri, X86::SHL64mi },
163 { X86::SHL8rCL, X86::SHL8mCL },
164 { X86::SHL8ri, X86::SHL8mi },
165 { X86::SHLD16rrCL, X86::SHLD16mrCL },
166 { X86::SHLD16rri8, X86::SHLD16mri8 },
167 { X86::SHLD32rrCL, X86::SHLD32mrCL },
168 { X86::SHLD32rri8, X86::SHLD32mri8 },
169 { X86::SHLD64rrCL, X86::SHLD64mrCL },
170 { X86::SHLD64rri8, X86::SHLD64mri8 },
171 { X86::SHR16r1, X86::SHR16m1 },
172 { X86::SHR16rCL, X86::SHR16mCL },
173 { X86::SHR16ri, X86::SHR16mi },
174 { X86::SHR32r1, X86::SHR32m1 },
175 { X86::SHR32rCL, X86::SHR32mCL },
176 { X86::SHR32ri, X86::SHR32mi },
177 { X86::SHR64r1, X86::SHR64m1 },
178 { X86::SHR64rCL, X86::SHR64mCL },
179 { X86::SHR64ri, X86::SHR64mi },
180 { X86::SHR8r1, X86::SHR8m1 },
181 { X86::SHR8rCL, X86::SHR8mCL },
182 { X86::SHR8ri, X86::SHR8mi },
183 { X86::SHRD16rrCL, X86::SHRD16mrCL },
184 { X86::SHRD16rri8, X86::SHRD16mri8 },
185 { X86::SHRD32rrCL, X86::SHRD32mrCL },
186 { X86::SHRD32rri8, X86::SHRD32mri8 },
187 { X86::SHRD64rrCL, X86::SHRD64mrCL },
188 { X86::SHRD64rri8, X86::SHRD64mri8 },
189 { X86::SUB16ri, X86::SUB16mi },
190 { X86::SUB16ri8, X86::SUB16mi8 },
191 { X86::SUB16rr, X86::SUB16mr },
192 { X86::SUB32ri, X86::SUB32mi },
193 { X86::SUB32ri8, X86::SUB32mi8 },
194 { X86::SUB32rr, X86::SUB32mr },
195 { X86::SUB64ri32, X86::SUB64mi32 },
196 { X86::SUB64ri8, X86::SUB64mi8 },
197 { X86::SUB64rr, X86::SUB64mr },
198 { X86::SUB8ri, X86::SUB8mi },
199 { X86::SUB8rr, X86::SUB8mr },
200 { X86::XOR16ri, X86::XOR16mi },
201 { X86::XOR16ri8, X86::XOR16mi8 },
202 { X86::XOR16rr, X86::XOR16mr },
203 { X86::XOR32ri, X86::XOR32mi },
204 { X86::XOR32ri8, X86::XOR32mi8 },
205 { X86::XOR32rr, X86::XOR32mr },
206 { X86::XOR64ri32, X86::XOR64mi32 },
207 { X86::XOR64ri8, X86::XOR64mi8 },
208 { X86::XOR64rr, X86::XOR64mr },
209 { X86::XOR8ri, X86::XOR8mi },
210 { X86::XOR8rr, X86::XOR8mr }
213 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
214 unsigned RegOp = OpTbl2Addr[i][0];
215 unsigned MemOp = OpTbl2Addr[i][1];
216 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
218 assert(false && "Duplicated entries?");
219 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
220 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
221 std::make_pair(RegOp,
223 AmbEntries.push_back(MemOp);
226 // If the third value is 1, then it's folding either a load or a store.
227 static const unsigned OpTbl0[][3] = {
228 { X86::BT16ri8, X86::BT16mi8, 1 },
229 { X86::BT32ri8, X86::BT32mi8, 1 },
230 { X86::BT64ri8, X86::BT64mi8, 1 },
231 { X86::CALL32r, X86::CALL32m, 1 },
232 { X86::CALL64r, X86::CALL64m, 1 },
233 { X86::CMP16ri, X86::CMP16mi, 1 },
234 { X86::CMP16ri8, X86::CMP16mi8, 1 },
235 { X86::CMP16rr, X86::CMP16mr, 1 },
236 { X86::CMP32ri, X86::CMP32mi, 1 },
237 { X86::CMP32ri8, X86::CMP32mi8, 1 },
238 { X86::CMP32rr, X86::CMP32mr, 1 },
239 { X86::CMP64ri32, X86::CMP64mi32, 1 },
240 { X86::CMP64ri8, X86::CMP64mi8, 1 },
241 { X86::CMP64rr, X86::CMP64mr, 1 },
242 { X86::CMP8ri, X86::CMP8mi, 1 },
243 { X86::CMP8rr, X86::CMP8mr, 1 },
244 { X86::DIV16r, X86::DIV16m, 1 },
245 { X86::DIV32r, X86::DIV32m, 1 },
246 { X86::DIV64r, X86::DIV64m, 1 },
247 { X86::DIV8r, X86::DIV8m, 1 },
248 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 },
249 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
250 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
251 { X86::IDIV16r, X86::IDIV16m, 1 },
252 { X86::IDIV32r, X86::IDIV32m, 1 },
253 { X86::IDIV64r, X86::IDIV64m, 1 },
254 { X86::IDIV8r, X86::IDIV8m, 1 },
255 { X86::IMUL16r, X86::IMUL16m, 1 },
256 { X86::IMUL32r, X86::IMUL32m, 1 },
257 { X86::IMUL64r, X86::IMUL64m, 1 },
258 { X86::IMUL8r, X86::IMUL8m, 1 },
259 { X86::JMP32r, X86::JMP32m, 1 },
260 { X86::JMP64r, X86::JMP64m, 1 },
261 { X86::MOV16ri, X86::MOV16mi, 0 },
262 { X86::MOV16rr, X86::MOV16mr, 0 },
263 { X86::MOV32ri, X86::MOV32mi, 0 },
264 { X86::MOV32rr, X86::MOV32mr, 0 },
265 { X86::MOV64ri32, X86::MOV64mi32, 0 },
266 { X86::MOV64rr, X86::MOV64mr, 0 },
267 { X86::MOV8ri, X86::MOV8mi, 0 },
268 { X86::MOV8rr, X86::MOV8mr, 0 },
269 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0 },
270 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
271 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
272 { X86::MOVDQArr, X86::MOVDQAmr, 0 },
273 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
274 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
275 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
276 { X86::MOVSDrr, X86::MOVSDmr, 0 },
277 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
278 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
279 { X86::MOVSSrr, X86::MOVSSmr, 0 },
280 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
281 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
282 { X86::MUL16r, X86::MUL16m, 1 },
283 { X86::MUL32r, X86::MUL32m, 1 },
284 { X86::MUL64r, X86::MUL64m, 1 },
285 { X86::MUL8r, X86::MUL8m, 1 },
286 { X86::SETAEr, X86::SETAEm, 0 },
287 { X86::SETAr, X86::SETAm, 0 },
288 { X86::SETBEr, X86::SETBEm, 0 },
289 { X86::SETBr, X86::SETBm, 0 },
290 { X86::SETEr, X86::SETEm, 0 },
291 { X86::SETGEr, X86::SETGEm, 0 },
292 { X86::SETGr, X86::SETGm, 0 },
293 { X86::SETLEr, X86::SETLEm, 0 },
294 { X86::SETLr, X86::SETLm, 0 },
295 { X86::SETNEr, X86::SETNEm, 0 },
296 { X86::SETNOr, X86::SETNOm, 0 },
297 { X86::SETNPr, X86::SETNPm, 0 },
298 { X86::SETNSr, X86::SETNSm, 0 },
299 { X86::SETOr, X86::SETOm, 0 },
300 { X86::SETPr, X86::SETPm, 0 },
301 { X86::SETSr, X86::SETSm, 0 },
302 { X86::TAILJMPr, X86::TAILJMPm, 1 },
303 { X86::TEST16ri, X86::TEST16mi, 1 },
304 { X86::TEST32ri, X86::TEST32mi, 1 },
305 { X86::TEST64ri32, X86::TEST64mi32, 1 },
306 { X86::TEST8ri, X86::TEST8mi, 1 }
309 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
310 unsigned RegOp = OpTbl0[i][0];
311 unsigned MemOp = OpTbl0[i][1];
312 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
314 assert(false && "Duplicated entries?");
315 unsigned FoldedLoad = OpTbl0[i][2];
316 // Index 0, folded load or store.
317 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
318 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
319 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
320 std::make_pair(RegOp, AuxInfo))).second)
321 AmbEntries.push_back(MemOp);
324 static const unsigned OpTbl1[][2] = {
325 { X86::CMP16rr, X86::CMP16rm },
326 { X86::CMP32rr, X86::CMP32rm },
327 { X86::CMP64rr, X86::CMP64rm },
328 { X86::CMP8rr, X86::CMP8rm },
329 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
330 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
331 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
332 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
333 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
334 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
335 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
336 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
337 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
338 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
339 { X86::FsMOVAPDrr, X86::MOVSDrm },
340 { X86::FsMOVAPSrr, X86::MOVSSrm },
341 { X86::IMUL16rri, X86::IMUL16rmi },
342 { X86::IMUL16rri8, X86::IMUL16rmi8 },
343 { X86::IMUL32rri, X86::IMUL32rmi },
344 { X86::IMUL32rri8, X86::IMUL32rmi8 },
345 { X86::IMUL64rri32, X86::IMUL64rmi32 },
346 { X86::IMUL64rri8, X86::IMUL64rmi8 },
347 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
348 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
349 { X86::Int_COMISDrr, X86::Int_COMISDrm },
350 { X86::Int_COMISSrr, X86::Int_COMISSrm },
351 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
352 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
353 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
354 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
355 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
356 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
357 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
358 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
359 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
360 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
361 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
362 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
363 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
364 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
365 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
366 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
367 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
368 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
369 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
370 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
371 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
372 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
373 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
374 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
375 { X86::MOV16rr, X86::MOV16rm },
376 { X86::MOV32rr, X86::MOV32rm },
377 { X86::MOV64rr, X86::MOV64rm },
378 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
379 { X86::MOV64toSDrr, X86::MOV64toSDrm },
380 { X86::MOV8rr, X86::MOV8rm },
381 { X86::MOVAPDrr, X86::MOVAPDrm },
382 { X86::MOVAPSrr, X86::MOVAPSrm },
383 { X86::MOVDDUPrr, X86::MOVDDUPrm },
384 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
385 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
386 { X86::MOVDQArr, X86::MOVDQArm },
387 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
388 { X86::MOVSDrr, X86::MOVSDrm },
389 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
390 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
391 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
392 { X86::MOVSSrr, X86::MOVSSrm },
393 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
394 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
395 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
396 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
397 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
398 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
399 { X86::MOVUPDrr, X86::MOVUPDrm },
400 { X86::MOVUPSrr, X86::MOVUPSrm },
401 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
402 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
403 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
404 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
405 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
406 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8 },
407 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
408 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
409 { X86::MOVZX64rr32, X86::MOVZX64rm32 },
410 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
411 { X86::PSHUFDri, X86::PSHUFDmi },
412 { X86::PSHUFHWri, X86::PSHUFHWmi },
413 { X86::PSHUFLWri, X86::PSHUFLWmi },
414 { X86::RCPPSr, X86::RCPPSm },
415 { X86::RCPPSr_Int, X86::RCPPSm_Int },
416 { X86::RSQRTPSr, X86::RSQRTPSm },
417 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
418 { X86::RSQRTSSr, X86::RSQRTSSm },
419 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
420 { X86::SQRTPDr, X86::SQRTPDm },
421 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
422 { X86::SQRTPSr, X86::SQRTPSm },
423 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
424 { X86::SQRTSDr, X86::SQRTSDm },
425 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
426 { X86::SQRTSSr, X86::SQRTSSm },
427 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
428 { X86::TEST16rr, X86::TEST16rm },
429 { X86::TEST32rr, X86::TEST32rm },
430 { X86::TEST64rr, X86::TEST64rm },
431 { X86::TEST8rr, X86::TEST8rm },
432 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
433 { X86::UCOMISDrr, X86::UCOMISDrm },
434 { X86::UCOMISSrr, X86::UCOMISSrm }
437 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
438 unsigned RegOp = OpTbl1[i][0];
439 unsigned MemOp = OpTbl1[i][1];
440 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
442 assert(false && "Duplicated entries?");
443 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
444 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
445 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
446 std::make_pair(RegOp, AuxInfo))).second)
447 AmbEntries.push_back(MemOp);
450 static const unsigned OpTbl2[][2] = {
451 { X86::ADC32rr, X86::ADC32rm },
452 { X86::ADC64rr, X86::ADC64rm },
453 { X86::ADD16rr, X86::ADD16rm },
454 { X86::ADD32rr, X86::ADD32rm },
455 { X86::ADD64rr, X86::ADD64rm },
456 { X86::ADD8rr, X86::ADD8rm },
457 { X86::ADDPDrr, X86::ADDPDrm },
458 { X86::ADDPSrr, X86::ADDPSrm },
459 { X86::ADDSDrr, X86::ADDSDrm },
460 { X86::ADDSSrr, X86::ADDSSrm },
461 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
462 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
463 { X86::AND16rr, X86::AND16rm },
464 { X86::AND32rr, X86::AND32rm },
465 { X86::AND64rr, X86::AND64rm },
466 { X86::AND8rr, X86::AND8rm },
467 { X86::ANDNPDrr, X86::ANDNPDrm },
468 { X86::ANDNPSrr, X86::ANDNPSrm },
469 { X86::ANDPDrr, X86::ANDPDrm },
470 { X86::ANDPSrr, X86::ANDPSrm },
471 { X86::CMOVA16rr, X86::CMOVA16rm },
472 { X86::CMOVA32rr, X86::CMOVA32rm },
473 { X86::CMOVA64rr, X86::CMOVA64rm },
474 { X86::CMOVAE16rr, X86::CMOVAE16rm },
475 { X86::CMOVAE32rr, X86::CMOVAE32rm },
476 { X86::CMOVAE64rr, X86::CMOVAE64rm },
477 { X86::CMOVB16rr, X86::CMOVB16rm },
478 { X86::CMOVB32rr, X86::CMOVB32rm },
479 { X86::CMOVB64rr, X86::CMOVB64rm },
480 { X86::CMOVBE16rr, X86::CMOVBE16rm },
481 { X86::CMOVBE32rr, X86::CMOVBE32rm },
482 { X86::CMOVBE64rr, X86::CMOVBE64rm },
483 { X86::CMOVE16rr, X86::CMOVE16rm },
484 { X86::CMOVE32rr, X86::CMOVE32rm },
485 { X86::CMOVE64rr, X86::CMOVE64rm },
486 { X86::CMOVG16rr, X86::CMOVG16rm },
487 { X86::CMOVG32rr, X86::CMOVG32rm },
488 { X86::CMOVG64rr, X86::CMOVG64rm },
489 { X86::CMOVGE16rr, X86::CMOVGE16rm },
490 { X86::CMOVGE32rr, X86::CMOVGE32rm },
491 { X86::CMOVGE64rr, X86::CMOVGE64rm },
492 { X86::CMOVL16rr, X86::CMOVL16rm },
493 { X86::CMOVL32rr, X86::CMOVL32rm },
494 { X86::CMOVL64rr, X86::CMOVL64rm },
495 { X86::CMOVLE16rr, X86::CMOVLE16rm },
496 { X86::CMOVLE32rr, X86::CMOVLE32rm },
497 { X86::CMOVLE64rr, X86::CMOVLE64rm },
498 { X86::CMOVNE16rr, X86::CMOVNE16rm },
499 { X86::CMOVNE32rr, X86::CMOVNE32rm },
500 { X86::CMOVNE64rr, X86::CMOVNE64rm },
501 { X86::CMOVNO16rr, X86::CMOVNO16rm },
502 { X86::CMOVNO32rr, X86::CMOVNO32rm },
503 { X86::CMOVNO64rr, X86::CMOVNO64rm },
504 { X86::CMOVNP16rr, X86::CMOVNP16rm },
505 { X86::CMOVNP32rr, X86::CMOVNP32rm },
506 { X86::CMOVNP64rr, X86::CMOVNP64rm },
507 { X86::CMOVNS16rr, X86::CMOVNS16rm },
508 { X86::CMOVNS32rr, X86::CMOVNS32rm },
509 { X86::CMOVNS64rr, X86::CMOVNS64rm },
510 { X86::CMOVO16rr, X86::CMOVO16rm },
511 { X86::CMOVO32rr, X86::CMOVO32rm },
512 { X86::CMOVO64rr, X86::CMOVO64rm },
513 { X86::CMOVP16rr, X86::CMOVP16rm },
514 { X86::CMOVP32rr, X86::CMOVP32rm },
515 { X86::CMOVP64rr, X86::CMOVP64rm },
516 { X86::CMOVS16rr, X86::CMOVS16rm },
517 { X86::CMOVS32rr, X86::CMOVS32rm },
518 { X86::CMOVS64rr, X86::CMOVS64rm },
519 { X86::CMPPDrri, X86::CMPPDrmi },
520 { X86::CMPPSrri, X86::CMPPSrmi },
521 { X86::CMPSDrr, X86::CMPSDrm },
522 { X86::CMPSSrr, X86::CMPSSrm },
523 { X86::DIVPDrr, X86::DIVPDrm },
524 { X86::DIVPSrr, X86::DIVPSrm },
525 { X86::DIVSDrr, X86::DIVSDrm },
526 { X86::DIVSSrr, X86::DIVSSrm },
527 { X86::FsANDNPDrr, X86::FsANDNPDrm },
528 { X86::FsANDNPSrr, X86::FsANDNPSrm },
529 { X86::FsANDPDrr, X86::FsANDPDrm },
530 { X86::FsANDPSrr, X86::FsANDPSrm },
531 { X86::FsORPDrr, X86::FsORPDrm },
532 { X86::FsORPSrr, X86::FsORPSrm },
533 { X86::FsXORPDrr, X86::FsXORPDrm },
534 { X86::FsXORPSrr, X86::FsXORPSrm },
535 { X86::HADDPDrr, X86::HADDPDrm },
536 { X86::HADDPSrr, X86::HADDPSrm },
537 { X86::HSUBPDrr, X86::HSUBPDrm },
538 { X86::HSUBPSrr, X86::HSUBPSrm },
539 { X86::IMUL16rr, X86::IMUL16rm },
540 { X86::IMUL32rr, X86::IMUL32rm },
541 { X86::IMUL64rr, X86::IMUL64rm },
542 { X86::MAXPDrr, X86::MAXPDrm },
543 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
544 { X86::MAXPSrr, X86::MAXPSrm },
545 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
546 { X86::MAXSDrr, X86::MAXSDrm },
547 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
548 { X86::MAXSSrr, X86::MAXSSrm },
549 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
550 { X86::MINPDrr, X86::MINPDrm },
551 { X86::MINPDrr_Int, X86::MINPDrm_Int },
552 { X86::MINPSrr, X86::MINPSrm },
553 { X86::MINPSrr_Int, X86::MINPSrm_Int },
554 { X86::MINSDrr, X86::MINSDrm },
555 { X86::MINSDrr_Int, X86::MINSDrm_Int },
556 { X86::MINSSrr, X86::MINSSrm },
557 { X86::MINSSrr_Int, X86::MINSSrm_Int },
558 { X86::MULPDrr, X86::MULPDrm },
559 { X86::MULPSrr, X86::MULPSrm },
560 { X86::MULSDrr, X86::MULSDrm },
561 { X86::MULSSrr, X86::MULSSrm },
562 { X86::OR16rr, X86::OR16rm },
563 { X86::OR32rr, X86::OR32rm },
564 { X86::OR64rr, X86::OR64rm },
565 { X86::OR8rr, X86::OR8rm },
566 { X86::ORPDrr, X86::ORPDrm },
567 { X86::ORPSrr, X86::ORPSrm },
568 { X86::PACKSSDWrr, X86::PACKSSDWrm },
569 { X86::PACKSSWBrr, X86::PACKSSWBrm },
570 { X86::PACKUSWBrr, X86::PACKUSWBrm },
571 { X86::PADDBrr, X86::PADDBrm },
572 { X86::PADDDrr, X86::PADDDrm },
573 { X86::PADDQrr, X86::PADDQrm },
574 { X86::PADDSBrr, X86::PADDSBrm },
575 { X86::PADDSWrr, X86::PADDSWrm },
576 { X86::PADDWrr, X86::PADDWrm },
577 { X86::PANDNrr, X86::PANDNrm },
578 { X86::PANDrr, X86::PANDrm },
579 { X86::PAVGBrr, X86::PAVGBrm },
580 { X86::PAVGWrr, X86::PAVGWrm },
581 { X86::PCMPEQBrr, X86::PCMPEQBrm },
582 { X86::PCMPEQDrr, X86::PCMPEQDrm },
583 { X86::PCMPEQWrr, X86::PCMPEQWrm },
584 { X86::PCMPGTBrr, X86::PCMPGTBrm },
585 { X86::PCMPGTDrr, X86::PCMPGTDrm },
586 { X86::PCMPGTWrr, X86::PCMPGTWrm },
587 { X86::PINSRWrri, X86::PINSRWrmi },
588 { X86::PMADDWDrr, X86::PMADDWDrm },
589 { X86::PMAXSWrr, X86::PMAXSWrm },
590 { X86::PMAXUBrr, X86::PMAXUBrm },
591 { X86::PMINSWrr, X86::PMINSWrm },
592 { X86::PMINUBrr, X86::PMINUBrm },
593 { X86::PMULDQrr, X86::PMULDQrm },
594 { X86::PMULHUWrr, X86::PMULHUWrm },
595 { X86::PMULHWrr, X86::PMULHWrm },
596 { X86::PMULLDrr, X86::PMULLDrm },
597 { X86::PMULLDrr_int, X86::PMULLDrm_int },
598 { X86::PMULLWrr, X86::PMULLWrm },
599 { X86::PMULUDQrr, X86::PMULUDQrm },
600 { X86::PORrr, X86::PORrm },
601 { X86::PSADBWrr, X86::PSADBWrm },
602 { X86::PSLLDrr, X86::PSLLDrm },
603 { X86::PSLLQrr, X86::PSLLQrm },
604 { X86::PSLLWrr, X86::PSLLWrm },
605 { X86::PSRADrr, X86::PSRADrm },
606 { X86::PSRAWrr, X86::PSRAWrm },
607 { X86::PSRLDrr, X86::PSRLDrm },
608 { X86::PSRLQrr, X86::PSRLQrm },
609 { X86::PSRLWrr, X86::PSRLWrm },
610 { X86::PSUBBrr, X86::PSUBBrm },
611 { X86::PSUBDrr, X86::PSUBDrm },
612 { X86::PSUBSBrr, X86::PSUBSBrm },
613 { X86::PSUBSWrr, X86::PSUBSWrm },
614 { X86::PSUBWrr, X86::PSUBWrm },
615 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
616 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
617 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
618 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
619 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
620 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
621 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
622 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
623 { X86::PXORrr, X86::PXORrm },
624 { X86::SBB32rr, X86::SBB32rm },
625 { X86::SBB64rr, X86::SBB64rm },
626 { X86::SHUFPDrri, X86::SHUFPDrmi },
627 { X86::SHUFPSrri, X86::SHUFPSrmi },
628 { X86::SUB16rr, X86::SUB16rm },
629 { X86::SUB32rr, X86::SUB32rm },
630 { X86::SUB64rr, X86::SUB64rm },
631 { X86::SUB8rr, X86::SUB8rm },
632 { X86::SUBPDrr, X86::SUBPDrm },
633 { X86::SUBPSrr, X86::SUBPSrm },
634 { X86::SUBSDrr, X86::SUBSDrm },
635 { X86::SUBSSrr, X86::SUBSSrm },
636 // FIXME: TEST*rr -> swapped operand of TEST*mr.
637 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
638 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
639 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
640 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
641 { X86::XOR16rr, X86::XOR16rm },
642 { X86::XOR32rr, X86::XOR32rm },
643 { X86::XOR64rr, X86::XOR64rm },
644 { X86::XOR8rr, X86::XOR8rm },
645 { X86::XORPDrr, X86::XORPDrm },
646 { X86::XORPSrr, X86::XORPSrm }
649 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
650 unsigned RegOp = OpTbl2[i][0];
651 unsigned MemOp = OpTbl2[i][1];
652 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
654 assert(false && "Duplicated entries?");
655 unsigned AuxInfo = 2 | (1 << 4); // Index 2, folded load
656 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
657 std::make_pair(RegOp, AuxInfo))).second)
658 AmbEntries.push_back(MemOp);
661 // Remove ambiguous entries.
662 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
665 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
666 unsigned &SrcReg, unsigned &DstReg,
667 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
668 switch (MI.getOpcode()) {
672 case X86::MOV8rr_NOREX:
679 // FP Stack register class copies
680 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
681 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
682 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
684 case X86::FsMOVAPSrr:
685 case X86::FsMOVAPDrr:
689 case X86::MOVSS2PSrr:
690 case X86::MOVSD2PDrr:
691 case X86::MOVPS2SSrr:
692 case X86::MOVPD2SDrr:
693 case X86::MMX_MOVQ64rr:
694 assert(MI.getNumOperands() >= 2 &&
695 MI.getOperand(0).isReg() &&
696 MI.getOperand(1).isReg() &&
697 "invalid register-register move instruction");
698 SrcReg = MI.getOperand(1).getReg();
699 DstReg = MI.getOperand(0).getReg();
700 SrcSubIdx = MI.getOperand(1).getSubReg();
701 DstSubIdx = MI.getOperand(0).getSubReg();
706 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
707 int &FrameIndex) const {
708 switch (MI->getOpcode()) {
720 case X86::MMX_MOVD64rm:
721 case X86::MMX_MOVQ64rm:
722 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
723 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
724 MI->getOperand(2).getImm() == 1 &&
725 MI->getOperand(3).getReg() == 0 &&
726 MI->getOperand(4).getImm() == 0) {
727 FrameIndex = MI->getOperand(1).getIndex();
728 return MI->getOperand(0).getReg();
735 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
736 int &FrameIndex) const {
737 switch (MI->getOpcode()) {
749 case X86::MMX_MOVD64mr:
750 case X86::MMX_MOVQ64mr:
751 case X86::MMX_MOVNTQmr:
752 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
753 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
754 MI->getOperand(1).getImm() == 1 &&
755 MI->getOperand(2).getReg() == 0 &&
756 MI->getOperand(3).getImm() == 0) {
757 FrameIndex = MI->getOperand(0).getIndex();
758 return MI->getOperand(X86AddrNumOperands).getReg();
766 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
768 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
769 bool isPICBase = false;
770 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
771 E = MRI.def_end(); I != E; ++I) {
772 MachineInstr *DefMI = I.getOperand().getParent();
773 if (DefMI->getOpcode() != X86::MOVPC32r)
775 assert(!isPICBase && "More than one PIC base?");
781 /// isGVStub - Return true if the GV requires an extra load to get the
783 static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
784 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
787 /// CanRematLoadWithDispOperand - Return true if a load with the specified
788 /// operand is a candidate for remat: for this to be true we need to know that
789 /// the load will always return the same value, even if moved.
790 static bool CanRematLoadWithDispOperand(const MachineOperand &MO,
791 X86TargetMachine &TM) {
792 // Loads from constant pool entries can be remat'd.
793 if (MO.isCPI()) return true;
795 // We can remat globals in some cases.
797 // If this is a load of a stub, not of the global, we can remat it. This
798 // access will always return the address of the global.
799 if (isGVStub(MO.getGlobal(), TM))
802 // If the global itself is constant, we can remat the load.
803 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal()))
804 if (GV->isConstant())
811 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
812 switch (MI->getOpcode()) {
824 case X86::MMX_MOVD64rm:
825 case X86::MMX_MOVQ64rm: {
826 // Loads from constant pools are trivially rematerializable.
827 if (MI->getOperand(1).isReg() &&
828 MI->getOperand(2).isImm() &&
829 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
830 CanRematLoadWithDispOperand(MI->getOperand(4), TM)) {
831 unsigned BaseReg = MI->getOperand(1).getReg();
832 if (BaseReg == 0 || BaseReg == X86::RIP)
834 // Allow re-materialization of PIC load.
835 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
837 const MachineFunction &MF = *MI->getParent()->getParent();
838 const MachineRegisterInfo &MRI = MF.getRegInfo();
839 bool isPICBase = false;
840 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
841 E = MRI.def_end(); I != E; ++I) {
842 MachineInstr *DefMI = I.getOperand().getParent();
843 if (DefMI->getOpcode() != X86::MOVPC32r)
845 assert(!isPICBase && "More than one PIC base?");
855 if (MI->getOperand(2).isImm() &&
856 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
857 !MI->getOperand(4).isReg()) {
858 // lea fi#, lea GV, etc. are all rematerializable.
859 if (!MI->getOperand(1).isReg())
861 unsigned BaseReg = MI->getOperand(1).getReg();
864 // Allow re-materialization of lea PICBase + x.
865 const MachineFunction &MF = *MI->getParent()->getParent();
866 const MachineRegisterInfo &MRI = MF.getRegInfo();
867 return regIsPICBase(BaseReg, MRI);
873 // All other instructions marked M_REMATERIALIZABLE are always trivially
878 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
879 /// would clobber the EFLAGS condition register. Note the result may be
880 /// conservative. If it cannot definitely determine the safety after visiting
881 /// two instructions it assumes it's not safe.
882 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
883 MachineBasicBlock::iterator I) {
884 // It's always safe to clobber EFLAGS at the end of a block.
888 // For compile time consideration, if we are not able to determine the
889 // safety after visiting 2 instructions, we will assume it's not safe.
890 for (unsigned i = 0; i < 2; ++i) {
891 bool SeenDef = false;
892 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
893 MachineOperand &MO = I->getOperand(j);
896 if (MO.getReg() == X86::EFLAGS) {
904 // This instruction defines EFLAGS, no need to look any further.
908 // If we make it to the end of the block, it's safe to clobber EFLAGS.
913 // Conservative answer.
917 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
918 MachineBasicBlock::iterator I,
920 const MachineInstr *Orig) const {
921 DebugLoc DL = DebugLoc::getUnknownLoc();
922 if (I != MBB.end()) DL = I->getDebugLoc();
924 unsigned SubIdx = Orig->getOperand(0).isReg()
925 ? Orig->getOperand(0).getSubReg() : 0;
926 bool ChangeSubIdx = SubIdx != 0;
927 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
928 DestReg = RI.getSubReg(DestReg, SubIdx);
932 // MOV32r0 etc. are implemented with xor which clobbers condition code.
933 // Re-materialize them as movri instructions to avoid side effects.
934 bool Emitted = false;
935 switch (Orig->getOpcode()) {
941 if (!isSafeToClobberEFLAGS(MBB, I)) {
943 switch (Orig->getOpcode()) {
945 case X86::MOV8r0: Opc = X86::MOV8ri; break;
946 case X86::MOV16r0: Opc = X86::MOV16ri; break;
947 case X86::MOV32r0: Opc = X86::MOV32ri; break;
948 case X86::MOV64r0: Opc = X86::MOV64ri32; break;
950 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
958 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
959 MI->getOperand(0).setReg(DestReg);
964 MachineInstr *NewMI = prior(I);
965 NewMI->getOperand(0).setSubReg(SubIdx);
969 /// isInvariantLoad - Return true if the specified instruction (which is marked
970 /// mayLoad) is loading from a location whose value is invariant across the
971 /// function. For example, loading a value from the constant pool or from
972 /// from the argument area of a function if it does not change. This should
973 /// only return true of *all* loads the instruction does are invariant (if it
974 /// does multiple loads).
975 bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
976 // This code cares about loads from three cases: constant pool entries,
977 // invariant argument slots, and global stubs. In order to handle these cases
978 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
979 // operand and base our analysis on it. This is safe because the address of
980 // none of these three cases is ever used as anything other than a load base
981 // and X86 doesn't have any instructions that load from multiple places.
983 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
984 const MachineOperand &MO = MI->getOperand(i);
985 // Loads from constant pools are trivially invariant.
990 return isGVStub(MO.getGlobal(), TM);
992 // If this is a load from an invariant stack slot, the load is a constant.
994 const MachineFrameInfo &MFI =
995 *MI->getParent()->getParent()->getFrameInfo();
996 int Idx = MO.getIndex();
997 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
1001 // All other instances of these instructions are presumed to have other
1006 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1007 /// is not marked dead.
1008 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1009 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1010 MachineOperand &MO = MI->getOperand(i);
1011 if (MO.isReg() && MO.isDef() &&
1012 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1019 /// convertToThreeAddress - This method must be implemented by targets that
1020 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1021 /// may be able to convert a two-address instruction into a true
1022 /// three-address instruction on demand. This allows the X86 target (for
1023 /// example) to convert ADD and SHL instructions into LEA instructions if they
1024 /// would require register copies due to two-addressness.
1026 /// This method returns a null pointer if the transformation cannot be
1027 /// performed, otherwise it returns the new instruction.
1030 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1031 MachineBasicBlock::iterator &MBBI,
1032 LiveVariables *LV) const {
1033 MachineInstr *MI = MBBI;
1034 MachineFunction &MF = *MI->getParent()->getParent();
1035 // All instructions input are two-addr instructions. Get the known operands.
1036 unsigned Dest = MI->getOperand(0).getReg();
1037 unsigned Src = MI->getOperand(1).getReg();
1038 bool isDead = MI->getOperand(0).isDead();
1039 bool isKill = MI->getOperand(1).isKill();
1041 MachineInstr *NewMI = NULL;
1042 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1043 // we have better subtarget support, enable the 16-bit LEA generation here.
1044 bool DisableLEA16 = true;
1046 unsigned MIOpc = MI->getOpcode();
1048 case X86::SHUFPSrri: {
1049 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1050 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1052 unsigned B = MI->getOperand(1).getReg();
1053 unsigned C = MI->getOperand(2).getReg();
1054 if (B != C) return 0;
1055 unsigned A = MI->getOperand(0).getReg();
1056 unsigned M = MI->getOperand(3).getImm();
1057 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1058 .addReg(A, RegState::Define | getDeadRegState(isDead))
1059 .addReg(B, getKillRegState(isKill)).addImm(M);
1062 case X86::SHL64ri: {
1063 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1064 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1065 // the flags produced by a shift yet, so this is safe.
1066 unsigned ShAmt = MI->getOperand(2).getImm();
1067 if (ShAmt == 0 || ShAmt >= 4) return 0;
1069 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1070 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1071 .addReg(0).addImm(1 << ShAmt)
1072 .addReg(Src, getKillRegState(isKill))
1076 case X86::SHL32ri: {
1077 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1078 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1079 // the flags produced by a shift yet, so this is safe.
1080 unsigned ShAmt = MI->getOperand(2).getImm();
1081 if (ShAmt == 0 || ShAmt >= 4) return 0;
1083 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1084 X86::LEA64_32r : X86::LEA32r;
1085 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1086 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1087 .addReg(0).addImm(1 << ShAmt)
1088 .addReg(Src, getKillRegState(isKill)).addImm(0);
1091 case X86::SHL16ri: {
1092 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1093 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1094 // the flags produced by a shift yet, so this is safe.
1095 unsigned ShAmt = MI->getOperand(2).getImm();
1096 if (ShAmt == 0 || ShAmt >= 4) return 0;
1099 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1100 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1101 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1102 ? X86::LEA64_32r : X86::LEA32r;
1103 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1104 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1106 // Build and insert into an implicit UNDEF value. This is OK because
1107 // well be shifting and then extracting the lower 16-bits.
1108 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1109 MachineInstr *InsMI =
1110 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1112 .addReg(Src, getKillRegState(isKill))
1113 .addImm(X86::SUBREG_16BIT);
1115 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1116 .addReg(0).addImm(1 << ShAmt)
1117 .addReg(leaInReg, RegState::Kill)
1120 MachineInstr *ExtMI =
1121 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1122 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1123 .addReg(leaOutReg, RegState::Kill)
1124 .addImm(X86::SUBREG_16BIT);
1127 // Update live variables
1128 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1129 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1131 LV->replaceKillInstruction(Src, MI, InsMI);
1133 LV->replaceKillInstruction(Dest, MI, ExtMI);
1137 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1138 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1139 .addReg(0).addImm(1 << ShAmt)
1140 .addReg(Src, getKillRegState(isKill))
1146 // The following opcodes also sets the condition code register(s). Only
1147 // convert them to equivalent lea if the condition code register def's
1149 if (hasLiveCondCodeDef(MI))
1152 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1157 case X86::INC64_32r: {
1158 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1159 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1160 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1161 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1162 .addReg(Dest, RegState::Define |
1163 getDeadRegState(isDead)),
1168 case X86::INC64_16r:
1169 if (DisableLEA16) return 0;
1170 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1171 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1172 .addReg(Dest, RegState::Define |
1173 getDeadRegState(isDead)),
1178 case X86::DEC64_32r: {
1179 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1180 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1181 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1182 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1183 .addReg(Dest, RegState::Define |
1184 getDeadRegState(isDead)),
1189 case X86::DEC64_16r:
1190 if (DisableLEA16) return 0;
1191 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1192 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1193 .addReg(Dest, RegState::Define |
1194 getDeadRegState(isDead)),
1198 case X86::ADD32rr: {
1199 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1200 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1201 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1202 unsigned Src2 = MI->getOperand(2).getReg();
1203 bool isKill2 = MI->getOperand(2).isKill();
1204 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1205 .addReg(Dest, RegState::Define |
1206 getDeadRegState(isDead)),
1207 Src, isKill, Src2, isKill2);
1209 LV->replaceKillInstruction(Src2, MI, NewMI);
1212 case X86::ADD16rr: {
1213 if (DisableLEA16) return 0;
1214 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1215 unsigned Src2 = MI->getOperand(2).getReg();
1216 bool isKill2 = MI->getOperand(2).isKill();
1217 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1218 .addReg(Dest, RegState::Define |
1219 getDeadRegState(isDead)),
1220 Src, isKill, Src2, isKill2);
1222 LV->replaceKillInstruction(Src2, MI, NewMI);
1225 case X86::ADD64ri32:
1227 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1228 if (MI->getOperand(2).isImm())
1229 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1230 .addReg(Dest, RegState::Define |
1231 getDeadRegState(isDead)),
1232 Src, isKill, MI->getOperand(2).getImm());
1236 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1237 if (MI->getOperand(2).isImm()) {
1238 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1239 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1240 .addReg(Dest, RegState::Define |
1241 getDeadRegState(isDead)),
1242 Src, isKill, MI->getOperand(2).getImm());
1247 if (DisableLEA16) return 0;
1248 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1249 if (MI->getOperand(2).isImm())
1250 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1251 .addReg(Dest, RegState::Define |
1252 getDeadRegState(isDead)),
1253 Src, isKill, MI->getOperand(2).getImm());
1256 if (DisableLEA16) return 0;
1258 case X86::SHL64ri: {
1259 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1260 "Unknown shl instruction!");
1261 unsigned ShAmt = MI->getOperand(2).getImm();
1262 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1264 AM.Scale = 1 << ShAmt;
1266 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1267 : (MIOpc == X86::SHL32ri
1268 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1269 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1270 .addReg(Dest, RegState::Define |
1271 getDeadRegState(isDead)), AM);
1273 NewMI->getOperand(3).setIsKill(true);
1281 if (!NewMI) return 0;
1283 if (LV) { // Update live variables
1285 LV->replaceKillInstruction(Src, MI, NewMI);
1287 LV->replaceKillInstruction(Dest, MI, NewMI);
1290 MFI->insert(MBBI, NewMI); // Insert the new inst
1294 /// commuteInstruction - We have a few instructions that must be hacked on to
1298 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1299 switch (MI->getOpcode()) {
1300 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1301 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1302 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1303 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1304 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1305 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1308 switch (MI->getOpcode()) {
1309 default: assert(0 && "Unreachable!");
1310 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1311 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1312 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1313 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1314 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1315 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1317 unsigned Amt = MI->getOperand(3).getImm();
1319 MachineFunction &MF = *MI->getParent()->getParent();
1320 MI = MF.CloneMachineInstr(MI);
1323 MI->setDesc(get(Opc));
1324 MI->getOperand(3).setImm(Size-Amt);
1325 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1327 case X86::CMOVB16rr:
1328 case X86::CMOVB32rr:
1329 case X86::CMOVB64rr:
1330 case X86::CMOVAE16rr:
1331 case X86::CMOVAE32rr:
1332 case X86::CMOVAE64rr:
1333 case X86::CMOVE16rr:
1334 case X86::CMOVE32rr:
1335 case X86::CMOVE64rr:
1336 case X86::CMOVNE16rr:
1337 case X86::CMOVNE32rr:
1338 case X86::CMOVNE64rr:
1339 case X86::CMOVBE16rr:
1340 case X86::CMOVBE32rr:
1341 case X86::CMOVBE64rr:
1342 case X86::CMOVA16rr:
1343 case X86::CMOVA32rr:
1344 case X86::CMOVA64rr:
1345 case X86::CMOVL16rr:
1346 case X86::CMOVL32rr:
1347 case X86::CMOVL64rr:
1348 case X86::CMOVGE16rr:
1349 case X86::CMOVGE32rr:
1350 case X86::CMOVGE64rr:
1351 case X86::CMOVLE16rr:
1352 case X86::CMOVLE32rr:
1353 case X86::CMOVLE64rr:
1354 case X86::CMOVG16rr:
1355 case X86::CMOVG32rr:
1356 case X86::CMOVG64rr:
1357 case X86::CMOVS16rr:
1358 case X86::CMOVS32rr:
1359 case X86::CMOVS64rr:
1360 case X86::CMOVNS16rr:
1361 case X86::CMOVNS32rr:
1362 case X86::CMOVNS64rr:
1363 case X86::CMOVP16rr:
1364 case X86::CMOVP32rr:
1365 case X86::CMOVP64rr:
1366 case X86::CMOVNP16rr:
1367 case X86::CMOVNP32rr:
1368 case X86::CMOVNP64rr:
1369 case X86::CMOVO16rr:
1370 case X86::CMOVO32rr:
1371 case X86::CMOVO64rr:
1372 case X86::CMOVNO16rr:
1373 case X86::CMOVNO32rr:
1374 case X86::CMOVNO64rr: {
1376 switch (MI->getOpcode()) {
1378 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1379 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1380 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1381 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1382 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1383 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1384 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1385 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1386 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1387 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1388 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1389 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1390 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1391 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1392 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1393 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1394 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1395 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1396 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1397 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1398 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1399 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1400 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1401 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1402 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1403 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1404 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1405 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1406 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1407 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1408 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1409 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1410 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1411 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1412 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1413 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1414 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1415 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1416 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1417 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1418 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1419 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1420 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1421 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1422 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1423 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1424 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1425 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1428 MachineFunction &MF = *MI->getParent()->getParent();
1429 MI = MF.CloneMachineInstr(MI);
1432 MI->setDesc(get(Opc));
1433 // Fallthrough intended.
1436 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1440 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1442 default: return X86::COND_INVALID;
1443 case X86::JE: return X86::COND_E;
1444 case X86::JNE: return X86::COND_NE;
1445 case X86::JL: return X86::COND_L;
1446 case X86::JLE: return X86::COND_LE;
1447 case X86::JG: return X86::COND_G;
1448 case X86::JGE: return X86::COND_GE;
1449 case X86::JB: return X86::COND_B;
1450 case X86::JBE: return X86::COND_BE;
1451 case X86::JA: return X86::COND_A;
1452 case X86::JAE: return X86::COND_AE;
1453 case X86::JS: return X86::COND_S;
1454 case X86::JNS: return X86::COND_NS;
1455 case X86::JP: return X86::COND_P;
1456 case X86::JNP: return X86::COND_NP;
1457 case X86::JO: return X86::COND_O;
1458 case X86::JNO: return X86::COND_NO;
1462 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1464 default: assert(0 && "Illegal condition code!");
1465 case X86::COND_E: return X86::JE;
1466 case X86::COND_NE: return X86::JNE;
1467 case X86::COND_L: return X86::JL;
1468 case X86::COND_LE: return X86::JLE;
1469 case X86::COND_G: return X86::JG;
1470 case X86::COND_GE: return X86::JGE;
1471 case X86::COND_B: return X86::JB;
1472 case X86::COND_BE: return X86::JBE;
1473 case X86::COND_A: return X86::JA;
1474 case X86::COND_AE: return X86::JAE;
1475 case X86::COND_S: return X86::JS;
1476 case X86::COND_NS: return X86::JNS;
1477 case X86::COND_P: return X86::JP;
1478 case X86::COND_NP: return X86::JNP;
1479 case X86::COND_O: return X86::JO;
1480 case X86::COND_NO: return X86::JNO;
1484 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1485 /// e.g. turning COND_E to COND_NE.
1486 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1488 default: assert(0 && "Illegal condition code!");
1489 case X86::COND_E: return X86::COND_NE;
1490 case X86::COND_NE: return X86::COND_E;
1491 case X86::COND_L: return X86::COND_GE;
1492 case X86::COND_LE: return X86::COND_G;
1493 case X86::COND_G: return X86::COND_LE;
1494 case X86::COND_GE: return X86::COND_L;
1495 case X86::COND_B: return X86::COND_AE;
1496 case X86::COND_BE: return X86::COND_A;
1497 case X86::COND_A: return X86::COND_BE;
1498 case X86::COND_AE: return X86::COND_B;
1499 case X86::COND_S: return X86::COND_NS;
1500 case X86::COND_NS: return X86::COND_S;
1501 case X86::COND_P: return X86::COND_NP;
1502 case X86::COND_NP: return X86::COND_P;
1503 case X86::COND_O: return X86::COND_NO;
1504 case X86::COND_NO: return X86::COND_O;
1508 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1509 const TargetInstrDesc &TID = MI->getDesc();
1510 if (!TID.isTerminator()) return false;
1512 // Conditional branch is a special case.
1513 if (TID.isBranch() && !TID.isBarrier())
1515 if (!TID.isPredicable())
1517 return !isPredicated(MI);
1520 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1521 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1522 const X86InstrInfo &TII) {
1523 if (MI->getOpcode() == X86::FP_REG_KILL)
1525 return TII.isUnpredicatedTerminator(MI);
1528 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1529 MachineBasicBlock *&TBB,
1530 MachineBasicBlock *&FBB,
1531 SmallVectorImpl<MachineOperand> &Cond,
1532 bool AllowModify) const {
1533 // Start from the bottom of the block and work up, examining the
1534 // terminator instructions.
1535 MachineBasicBlock::iterator I = MBB.end();
1536 while (I != MBB.begin()) {
1538 // Working from the bottom, when we see a non-terminator
1539 // instruction, we're done.
1540 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1542 // A terminator that isn't a branch can't easily be handled
1543 // by this analysis.
1544 if (!I->getDesc().isBranch())
1546 // Handle unconditional branches.
1547 if (I->getOpcode() == X86::JMP) {
1549 TBB = I->getOperand(0).getMBB();
1553 // If the block has any instructions after a JMP, delete them.
1554 while (next(I) != MBB.end())
1555 next(I)->eraseFromParent();
1558 // Delete the JMP if it's equivalent to a fall-through.
1559 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1561 I->eraseFromParent();
1565 // TBB is used to indicate the unconditinal destination.
1566 TBB = I->getOperand(0).getMBB();
1569 // Handle conditional branches.
1570 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1571 if (BranchCode == X86::COND_INVALID)
1572 return true; // Can't handle indirect branch.
1573 // Working from the bottom, handle the first conditional branch.
1576 TBB = I->getOperand(0).getMBB();
1577 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1580 // Handle subsequent conditional branches. Only handle the case
1581 // where all conditional branches branch to the same destination
1582 // and their condition opcodes fit one of the special
1583 // multi-branch idioms.
1584 assert(Cond.size() == 1);
1586 // Only handle the case where all conditional branches branch to
1587 // the same destination.
1588 if (TBB != I->getOperand(0).getMBB())
1590 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1591 // If the conditions are the same, we can leave them alone.
1592 if (OldBranchCode == BranchCode)
1594 // If they differ, see if they fit one of the known patterns.
1595 // Theoretically we could handle more patterns here, but
1596 // we shouldn't expect to see them if instruction selection
1597 // has done a reasonable job.
1598 if ((OldBranchCode == X86::COND_NP &&
1599 BranchCode == X86::COND_E) ||
1600 (OldBranchCode == X86::COND_E &&
1601 BranchCode == X86::COND_NP))
1602 BranchCode = X86::COND_NP_OR_E;
1603 else if ((OldBranchCode == X86::COND_P &&
1604 BranchCode == X86::COND_NE) ||
1605 (OldBranchCode == X86::COND_NE &&
1606 BranchCode == X86::COND_P))
1607 BranchCode = X86::COND_NE_OR_P;
1610 // Update the MachineOperand.
1611 Cond[0].setImm(BranchCode);
1617 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1618 MachineBasicBlock::iterator I = MBB.end();
1621 while (I != MBB.begin()) {
1623 if (I->getOpcode() != X86::JMP &&
1624 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1626 // Remove the branch.
1627 I->eraseFromParent();
1636 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1637 MachineBasicBlock *FBB,
1638 const SmallVectorImpl<MachineOperand> &Cond) const {
1639 // FIXME this should probably have a DebugLoc operand
1640 DebugLoc dl = DebugLoc::getUnknownLoc();
1641 // Shouldn't be a fall through.
1642 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1643 assert((Cond.size() == 1 || Cond.size() == 0) &&
1644 "X86 branch conditions have one component!");
1647 // Unconditional branch?
1648 assert(!FBB && "Unconditional branch with multiple successors!");
1649 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1653 // Conditional branch.
1655 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1657 case X86::COND_NP_OR_E:
1658 // Synthesize NP_OR_E with two branches.
1659 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1661 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1664 case X86::COND_NE_OR_P:
1665 // Synthesize NE_OR_P with two branches.
1666 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1668 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1672 unsigned Opc = GetCondBranchFromCond(CC);
1673 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1678 // Two-way Conditional branch. Insert the second branch.
1679 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1685 /// isHReg - Test if the given register is a physical h register.
1686 static bool isHReg(unsigned Reg) {
1687 return X86::GR8_ABCD_HRegClass.contains(Reg);
1690 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1691 MachineBasicBlock::iterator MI,
1692 unsigned DestReg, unsigned SrcReg,
1693 const TargetRegisterClass *DestRC,
1694 const TargetRegisterClass *SrcRC) const {
1695 DebugLoc DL = DebugLoc::getUnknownLoc();
1696 if (MI != MBB.end()) DL = MI->getDebugLoc();
1698 // Determine if DstRC and SrcRC have a common superclass in common.
1699 const TargetRegisterClass *CommonRC = DestRC;
1700 if (DestRC == SrcRC)
1701 /* Source and destination have the same register class. */;
1702 else if (CommonRC->hasSuperClass(SrcRC))
1704 else if (!DestRC->hasSubClass(SrcRC))
1709 if (CommonRC == &X86::GR64RegClass) {
1711 } else if (CommonRC == &X86::GR32RegClass) {
1713 } else if (CommonRC == &X86::GR16RegClass) {
1715 } else if (CommonRC == &X86::GR8RegClass) {
1716 // Copying to or from a physical H register on x86-64 requires a NOREX
1717 // move. Otherwise use a normal move.
1718 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1719 TM.getSubtarget<X86Subtarget>().is64Bit())
1720 Opc = X86::MOV8rr_NOREX;
1723 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1725 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1727 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1729 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1731 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1732 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1733 Opc = X86::MOV8rr_NOREX;
1736 } else if (CommonRC == &X86::GR64_NOREXRegClass) {
1738 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1740 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1742 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1744 } else if (CommonRC == &X86::RFP32RegClass) {
1745 Opc = X86::MOV_Fp3232;
1746 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1747 Opc = X86::MOV_Fp6464;
1748 } else if (CommonRC == &X86::RFP80RegClass) {
1749 Opc = X86::MOV_Fp8080;
1750 } else if (CommonRC == &X86::FR32RegClass) {
1751 Opc = X86::FsMOVAPSrr;
1752 } else if (CommonRC == &X86::FR64RegClass) {
1753 Opc = X86::FsMOVAPDrr;
1754 } else if (CommonRC == &X86::VR128RegClass) {
1755 Opc = X86::MOVAPSrr;
1756 } else if (CommonRC == &X86::VR64RegClass) {
1757 Opc = X86::MMX_MOVQ64rr;
1761 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1765 // Moving EFLAGS to / from another register requires a push and a pop.
1766 if (SrcRC == &X86::CCRRegClass) {
1767 if (SrcReg != X86::EFLAGS)
1769 if (DestRC == &X86::GR64RegClass) {
1770 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1771 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1773 } else if (DestRC == &X86::GR32RegClass) {
1774 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1775 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1778 } else if (DestRC == &X86::CCRRegClass) {
1779 if (DestReg != X86::EFLAGS)
1781 if (SrcRC == &X86::GR64RegClass) {
1782 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1783 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1785 } else if (SrcRC == &X86::GR32RegClass) {
1786 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1787 BuildMI(MBB, MI, DL, get(X86::POPFD));
1792 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1793 if (SrcRC == &X86::RSTRegClass) {
1794 // Copying from ST(0)/ST(1).
1795 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1796 // Can only copy from ST(0)/ST(1) right now
1798 bool isST0 = SrcReg == X86::ST0;
1800 if (DestRC == &X86::RFP32RegClass)
1801 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1802 else if (DestRC == &X86::RFP64RegClass)
1803 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1805 if (DestRC != &X86::RFP80RegClass)
1807 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1809 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1813 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1814 if (DestRC == &X86::RSTRegClass) {
1815 // Copying to ST(0) / ST(1).
1816 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1817 // Can only copy to TOS right now
1819 bool isST0 = DestReg == X86::ST0;
1821 if (SrcRC == &X86::RFP32RegClass)
1822 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1823 else if (SrcRC == &X86::RFP64RegClass)
1824 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1826 if (SrcRC != &X86::RFP80RegClass)
1828 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1830 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1834 // Not yet supported!
1838 static unsigned getStoreRegOpcode(unsigned SrcReg,
1839 const TargetRegisterClass *RC,
1840 bool isStackAligned,
1841 TargetMachine &TM) {
1843 if (RC == &X86::GR64RegClass) {
1845 } else if (RC == &X86::GR32RegClass) {
1847 } else if (RC == &X86::GR16RegClass) {
1849 } else if (RC == &X86::GR8RegClass) {
1850 // Copying to or from a physical H register on x86-64 requires a NOREX
1851 // move. Otherwise use a normal move.
1852 if (isHReg(SrcReg) &&
1853 TM.getSubtarget<X86Subtarget>().is64Bit())
1854 Opc = X86::MOV8mr_NOREX;
1857 } else if (RC == &X86::GR64_ABCDRegClass) {
1859 } else if (RC == &X86::GR32_ABCDRegClass) {
1861 } else if (RC == &X86::GR16_ABCDRegClass) {
1863 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1865 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1866 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1867 Opc = X86::MOV8mr_NOREX;
1870 } else if (RC == &X86::GR64_NOREXRegClass) {
1872 } else if (RC == &X86::GR32_NOREXRegClass) {
1874 } else if (RC == &X86::GR16_NOREXRegClass) {
1876 } else if (RC == &X86::GR8_NOREXRegClass) {
1878 } else if (RC == &X86::RFP80RegClass) {
1879 Opc = X86::ST_FpP80m; // pops
1880 } else if (RC == &X86::RFP64RegClass) {
1881 Opc = X86::ST_Fp64m;
1882 } else if (RC == &X86::RFP32RegClass) {
1883 Opc = X86::ST_Fp32m;
1884 } else if (RC == &X86::FR32RegClass) {
1886 } else if (RC == &X86::FR64RegClass) {
1888 } else if (RC == &X86::VR128RegClass) {
1889 // If stack is realigned we can use aligned stores.
1890 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1891 } else if (RC == &X86::VR64RegClass) {
1892 Opc = X86::MMX_MOVQ64mr;
1894 LLVM_UNREACHABLE("Unknown regclass");
1900 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1901 MachineBasicBlock::iterator MI,
1902 unsigned SrcReg, bool isKill, int FrameIdx,
1903 const TargetRegisterClass *RC) const {
1904 const MachineFunction &MF = *MBB.getParent();
1905 bool isAligned = (RI.getStackAlignment() >= 16) ||
1906 RI.needsStackRealignment(MF);
1907 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1908 DebugLoc DL = DebugLoc::getUnknownLoc();
1909 if (MI != MBB.end()) DL = MI->getDebugLoc();
1910 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1911 .addReg(SrcReg, getKillRegState(isKill));
1914 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1916 SmallVectorImpl<MachineOperand> &Addr,
1917 const TargetRegisterClass *RC,
1918 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1919 bool isAligned = (RI.getStackAlignment() >= 16) ||
1920 RI.needsStackRealignment(MF);
1921 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1922 DebugLoc DL = DebugLoc::getUnknownLoc();
1923 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1924 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1925 MIB.addOperand(Addr[i]);
1926 MIB.addReg(SrcReg, getKillRegState(isKill));
1927 NewMIs.push_back(MIB);
1930 static unsigned getLoadRegOpcode(unsigned DestReg,
1931 const TargetRegisterClass *RC,
1932 bool isStackAligned,
1933 const TargetMachine &TM) {
1935 if (RC == &X86::GR64RegClass) {
1937 } else if (RC == &X86::GR32RegClass) {
1939 } else if (RC == &X86::GR16RegClass) {
1941 } else if (RC == &X86::GR8RegClass) {
1942 // Copying to or from a physical H register on x86-64 requires a NOREX
1943 // move. Otherwise use a normal move.
1944 if (isHReg(DestReg) &&
1945 TM.getSubtarget<X86Subtarget>().is64Bit())
1946 Opc = X86::MOV8rm_NOREX;
1949 } else if (RC == &X86::GR64_ABCDRegClass) {
1951 } else if (RC == &X86::GR32_ABCDRegClass) {
1953 } else if (RC == &X86::GR16_ABCDRegClass) {
1955 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1957 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1958 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1959 Opc = X86::MOV8rm_NOREX;
1962 } else if (RC == &X86::GR64_NOREXRegClass) {
1964 } else if (RC == &X86::GR32_NOREXRegClass) {
1966 } else if (RC == &X86::GR16_NOREXRegClass) {
1968 } else if (RC == &X86::GR8_NOREXRegClass) {
1970 } else if (RC == &X86::RFP80RegClass) {
1971 Opc = X86::LD_Fp80m;
1972 } else if (RC == &X86::RFP64RegClass) {
1973 Opc = X86::LD_Fp64m;
1974 } else if (RC == &X86::RFP32RegClass) {
1975 Opc = X86::LD_Fp32m;
1976 } else if (RC == &X86::FR32RegClass) {
1978 } else if (RC == &X86::FR64RegClass) {
1980 } else if (RC == &X86::VR128RegClass) {
1981 // If stack is realigned we can use aligned loads.
1982 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1983 } else if (RC == &X86::VR64RegClass) {
1984 Opc = X86::MMX_MOVQ64rm;
1986 LLVM_UNREACHABLE("Unknown regclass");
1992 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1993 MachineBasicBlock::iterator MI,
1994 unsigned DestReg, int FrameIdx,
1995 const TargetRegisterClass *RC) const{
1996 const MachineFunction &MF = *MBB.getParent();
1997 bool isAligned = (RI.getStackAlignment() >= 16) ||
1998 RI.needsStackRealignment(MF);
1999 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2000 DebugLoc DL = DebugLoc::getUnknownLoc();
2001 if (MI != MBB.end()) DL = MI->getDebugLoc();
2002 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2005 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2006 SmallVectorImpl<MachineOperand> &Addr,
2007 const TargetRegisterClass *RC,
2008 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2009 bool isAligned = (RI.getStackAlignment() >= 16) ||
2010 RI.needsStackRealignment(MF);
2011 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2012 DebugLoc DL = DebugLoc::getUnknownLoc();
2013 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2014 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2015 MIB.addOperand(Addr[i]);
2016 NewMIs.push_back(MIB);
2019 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2020 MachineBasicBlock::iterator MI,
2021 const std::vector<CalleeSavedInfo> &CSI) const {
2025 DebugLoc DL = DebugLoc::getUnknownLoc();
2026 if (MI != MBB.end()) DL = MI->getDebugLoc();
2028 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2029 unsigned SlotSize = is64Bit ? 8 : 4;
2031 MachineFunction &MF = *MBB.getParent();
2032 unsigned FPReg = RI.getFrameRegister(MF);
2033 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2034 unsigned CalleeFrameSize = 0;
2036 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2037 for (unsigned i = CSI.size(); i != 0; --i) {
2038 unsigned Reg = CSI[i-1].getReg();
2039 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2040 // Add the callee-saved register as live-in. It's killed at the spill.
2043 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2045 if (RegClass != &X86::VR128RegClass) {
2046 CalleeFrameSize += SlotSize;
2047 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2049 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2053 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2057 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2058 MachineBasicBlock::iterator MI,
2059 const std::vector<CalleeSavedInfo> &CSI) const {
2063 DebugLoc DL = DebugLoc::getUnknownLoc();
2064 if (MI != MBB.end()) DL = MI->getDebugLoc();
2066 MachineFunction &MF = *MBB.getParent();
2067 unsigned FPReg = RI.getFrameRegister(MF);
2068 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2069 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2070 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2071 unsigned Reg = CSI[i].getReg();
2073 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2075 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2076 if (RegClass != &X86::VR128RegClass) {
2077 BuildMI(MBB, MI, DL, get(Opc), Reg);
2079 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2085 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2086 const SmallVectorImpl<MachineOperand> &MOs,
2088 const TargetInstrInfo &TII) {
2089 // Create the base instruction with the memory operand as the first part.
2090 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2091 MI->getDebugLoc(), true);
2092 MachineInstrBuilder MIB(NewMI);
2093 unsigned NumAddrOps = MOs.size();
2094 for (unsigned i = 0; i != NumAddrOps; ++i)
2095 MIB.addOperand(MOs[i]);
2096 if (NumAddrOps < 4) // FrameIndex only
2099 // Loop over the rest of the ri operands, converting them over.
2100 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2101 for (unsigned i = 0; i != NumOps; ++i) {
2102 MachineOperand &MO = MI->getOperand(i+2);
2105 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2106 MachineOperand &MO = MI->getOperand(i);
2112 static MachineInstr *FuseInst(MachineFunction &MF,
2113 unsigned Opcode, unsigned OpNo,
2114 const SmallVectorImpl<MachineOperand> &MOs,
2115 MachineInstr *MI, const TargetInstrInfo &TII) {
2116 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2117 MI->getDebugLoc(), true);
2118 MachineInstrBuilder MIB(NewMI);
2120 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2121 MachineOperand &MO = MI->getOperand(i);
2123 assert(MO.isReg() && "Expected to fold into reg operand!");
2124 unsigned NumAddrOps = MOs.size();
2125 for (unsigned i = 0; i != NumAddrOps; ++i)
2126 MIB.addOperand(MOs[i]);
2127 if (NumAddrOps < 4) // FrameIndex only
2136 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2137 const SmallVectorImpl<MachineOperand> &MOs,
2139 MachineFunction &MF = *MI->getParent()->getParent();
2140 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2142 unsigned NumAddrOps = MOs.size();
2143 for (unsigned i = 0; i != NumAddrOps; ++i)
2144 MIB.addOperand(MOs[i]);
2145 if (NumAddrOps < 4) // FrameIndex only
2147 return MIB.addImm(0);
2151 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2152 MachineInstr *MI, unsigned i,
2153 const SmallVectorImpl<MachineOperand> &MOs) const{
2154 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2155 bool isTwoAddrFold = false;
2156 unsigned NumOps = MI->getDesc().getNumOperands();
2157 bool isTwoAddr = NumOps > 1 &&
2158 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2160 MachineInstr *NewMI = NULL;
2161 // Folding a memory location into the two-address part of a two-address
2162 // instruction is different than folding it other places. It requires
2163 // replacing the *two* registers with the memory location.
2164 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2165 MI->getOperand(0).isReg() &&
2166 MI->getOperand(1).isReg() &&
2167 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2168 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2169 isTwoAddrFold = true;
2170 } else if (i == 0) { // If operand 0
2171 if (MI->getOpcode() == X86::MOV16r0)
2172 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2173 else if (MI->getOpcode() == X86::MOV32r0)
2174 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2175 else if (MI->getOpcode() == X86::MOV64r0)
2176 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2177 else if (MI->getOpcode() == X86::MOV8r0)
2178 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2182 OpcodeTablePtr = &RegOp2MemOpTable0;
2183 } else if (i == 1) {
2184 OpcodeTablePtr = &RegOp2MemOpTable1;
2185 } else if (i == 2) {
2186 OpcodeTablePtr = &RegOp2MemOpTable2;
2189 // If table selected...
2190 if (OpcodeTablePtr) {
2191 // Find the Opcode to fuse
2192 DenseMap<unsigned*, unsigned>::iterator I =
2193 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2194 if (I != OpcodeTablePtr->end()) {
2196 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
2198 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
2204 if (PrintFailedFusing)
2205 cerr << "We failed to fuse operand " << i << " in " << *MI;
2210 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2212 const SmallVectorImpl<unsigned> &Ops,
2213 int FrameIndex) const {
2214 // Check switch flag
2215 if (NoFusing) return NULL;
2217 const MachineFrameInfo *MFI = MF.getFrameInfo();
2218 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2219 // FIXME: Move alignment requirement into tables?
2220 if (Alignment < 16) {
2221 switch (MI->getOpcode()) {
2223 // Not always safe to fold movsd into these instructions since their load
2224 // folding variants expects the address to be 16 byte aligned.
2225 case X86::FsANDNPDrr:
2226 case X86::FsANDNPSrr:
2227 case X86::FsANDPDrr:
2228 case X86::FsANDPSrr:
2231 case X86::FsXORPDrr:
2232 case X86::FsXORPSrr:
2237 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2238 unsigned NewOpc = 0;
2239 switch (MI->getOpcode()) {
2240 default: return NULL;
2241 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2242 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2243 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2244 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2246 // Change to CMPXXri r, 0 first.
2247 MI->setDesc(get(NewOpc));
2248 MI->getOperand(1).ChangeToImmediate(0);
2249 } else if (Ops.size() != 1)
2252 SmallVector<MachineOperand,4> MOs;
2253 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2254 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2257 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2259 const SmallVectorImpl<unsigned> &Ops,
2260 MachineInstr *LoadMI) const {
2261 // Check switch flag
2262 if (NoFusing) return NULL;
2264 // Determine the alignment of the load.
2265 unsigned Alignment = 0;
2266 if (LoadMI->hasOneMemOperand())
2267 Alignment = LoadMI->memoperands_begin()->getAlignment();
2269 // FIXME: Move alignment requirement into tables?
2270 if (Alignment < 16) {
2271 switch (MI->getOpcode()) {
2273 // Not always safe to fold movsd into these instructions since their load
2274 // folding variants expects the address to be 16 byte aligned.
2275 case X86::FsANDNPDrr:
2276 case X86::FsANDNPSrr:
2277 case X86::FsANDPDrr:
2278 case X86::FsANDPSrr:
2281 case X86::FsXORPDrr:
2282 case X86::FsXORPSrr:
2287 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2288 unsigned NewOpc = 0;
2289 switch (MI->getOpcode()) {
2290 default: return NULL;
2291 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2292 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2293 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2294 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2296 // Change to CMPXXri r, 0 first.
2297 MI->setDesc(get(NewOpc));
2298 MI->getOperand(1).ChangeToImmediate(0);
2299 } else if (Ops.size() != 1)
2302 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2303 if (LoadMI->getOpcode() == X86::V_SET0 ||
2304 LoadMI->getOpcode() == X86::V_SETALLONES) {
2305 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2306 // Create a constant-pool entry and operands to load from it.
2308 // x86-32 PIC requires a PIC base register for constant pools.
2309 unsigned PICBase = 0;
2310 if (TM.getRelocationModel() == Reloc::PIC_ &&
2311 !TM.getSubtarget<X86Subtarget>().is64Bit())
2312 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2313 // This doesn't work for several reasons.
2314 // 1. GlobalBaseReg may have been spilled.
2315 // 2. It may not be live at MI.
2318 // Create a v4i32 constant-pool entry.
2319 MachineConstantPool &MCP = *MF.getConstantPool();
2320 const VectorType *Ty = VectorType::get(Type::Int32Ty, 4);
2321 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2322 ConstantVector::getNullValue(Ty) :
2323 ConstantVector::getAllOnesValue(Ty);
2324 unsigned CPI = MCP.getConstantPoolIndex(C, 16);
2326 // Create operands to load from the constant pool entry.
2327 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2328 MOs.push_back(MachineOperand::CreateImm(1));
2329 MOs.push_back(MachineOperand::CreateReg(0, false));
2330 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2331 MOs.push_back(MachineOperand::CreateReg(0, false));
2333 // Folding a normal load. Just copy the load's address operands.
2334 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2335 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2336 MOs.push_back(LoadMI->getOperand(i));
2338 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2342 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2343 const SmallVectorImpl<unsigned> &Ops) const {
2344 // Check switch flag
2345 if (NoFusing) return 0;
2347 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2348 switch (MI->getOpcode()) {
2349 default: return false;
2358 if (Ops.size() != 1)
2361 unsigned OpNum = Ops[0];
2362 unsigned Opc = MI->getOpcode();
2363 unsigned NumOps = MI->getDesc().getNumOperands();
2364 bool isTwoAddr = NumOps > 1 &&
2365 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2367 // Folding a memory location into the two-address part of a two-address
2368 // instruction is different than folding it other places. It requires
2369 // replacing the *two* registers with the memory location.
2370 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2371 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2372 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2373 } else if (OpNum == 0) { // If operand 0
2382 OpcodeTablePtr = &RegOp2MemOpTable0;
2383 } else if (OpNum == 1) {
2384 OpcodeTablePtr = &RegOp2MemOpTable1;
2385 } else if (OpNum == 2) {
2386 OpcodeTablePtr = &RegOp2MemOpTable2;
2389 if (OpcodeTablePtr) {
2390 // Find the Opcode to fuse
2391 DenseMap<unsigned*, unsigned>::iterator I =
2392 OpcodeTablePtr->find((unsigned*)Opc);
2393 if (I != OpcodeTablePtr->end())
2399 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2400 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2401 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2402 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2403 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2404 if (I == MemOp2RegOpTable.end())
2406 DebugLoc dl = MI->getDebugLoc();
2407 unsigned Opc = I->second.first;
2408 unsigned Index = I->second.second & 0xf;
2409 bool FoldedLoad = I->second.second & (1 << 4);
2410 bool FoldedStore = I->second.second & (1 << 5);
2411 if (UnfoldLoad && !FoldedLoad)
2413 UnfoldLoad &= FoldedLoad;
2414 if (UnfoldStore && !FoldedStore)
2416 UnfoldStore &= FoldedStore;
2418 const TargetInstrDesc &TID = get(Opc);
2419 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2420 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2421 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2422 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2423 SmallVector<MachineOperand,2> BeforeOps;
2424 SmallVector<MachineOperand,2> AfterOps;
2425 SmallVector<MachineOperand,4> ImpOps;
2426 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2427 MachineOperand &Op = MI->getOperand(i);
2428 if (i >= Index && i < Index + X86AddrNumOperands)
2429 AddrOps.push_back(Op);
2430 else if (Op.isReg() && Op.isImplicit())
2431 ImpOps.push_back(Op);
2433 BeforeOps.push_back(Op);
2435 AfterOps.push_back(Op);
2438 // Emit the load instruction.
2440 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2442 // Address operands cannot be marked isKill.
2443 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2444 MachineOperand &MO = NewMIs[0]->getOperand(i);
2446 MO.setIsKill(false);
2451 // Emit the data processing instruction.
2452 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2453 MachineInstrBuilder MIB(DataMI);
2456 MIB.addReg(Reg, RegState::Define);
2457 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2458 MIB.addOperand(BeforeOps[i]);
2461 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2462 MIB.addOperand(AfterOps[i]);
2463 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2464 MachineOperand &MO = ImpOps[i];
2465 MIB.addReg(MO.getReg(),
2466 getDefRegState(MO.isDef()) |
2467 RegState::Implicit |
2468 getKillRegState(MO.isKill()) |
2469 getDeadRegState(MO.isDead()) |
2470 getUndefRegState(MO.isUndef()));
2472 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2473 unsigned NewOpc = 0;
2474 switch (DataMI->getOpcode()) {
2476 case X86::CMP64ri32:
2480 MachineOperand &MO0 = DataMI->getOperand(0);
2481 MachineOperand &MO1 = DataMI->getOperand(1);
2482 if (MO1.getImm() == 0) {
2483 switch (DataMI->getOpcode()) {
2485 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2486 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2487 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2488 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2490 DataMI->setDesc(get(NewOpc));
2491 MO1.ChangeToRegister(MO0.getReg(), false);
2495 NewMIs.push_back(DataMI);
2497 // Emit the store instruction.
2499 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2500 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2501 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2502 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2509 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2510 SmallVectorImpl<SDNode*> &NewNodes) const {
2511 if (!N->isMachineOpcode())
2514 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2515 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2516 if (I == MemOp2RegOpTable.end())
2518 unsigned Opc = I->second.first;
2519 unsigned Index = I->second.second & 0xf;
2520 bool FoldedLoad = I->second.second & (1 << 4);
2521 bool FoldedStore = I->second.second & (1 << 5);
2522 const TargetInstrDesc &TID = get(Opc);
2523 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2524 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2525 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2526 unsigned NumDefs = TID.NumDefs;
2527 std::vector<SDValue> AddrOps;
2528 std::vector<SDValue> BeforeOps;
2529 std::vector<SDValue> AfterOps;
2530 DebugLoc dl = N->getDebugLoc();
2531 unsigned NumOps = N->getNumOperands();
2532 for (unsigned i = 0; i != NumOps-1; ++i) {
2533 SDValue Op = N->getOperand(i);
2534 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2535 AddrOps.push_back(Op);
2536 else if (i < Index-NumDefs)
2537 BeforeOps.push_back(Op);
2538 else if (i > Index-NumDefs)
2539 AfterOps.push_back(Op);
2541 SDValue Chain = N->getOperand(NumOps-1);
2542 AddrOps.push_back(Chain);
2544 // Emit the load instruction.
2546 const MachineFunction &MF = DAG.getMachineFunction();
2548 MVT VT = *RC->vt_begin();
2549 bool isAligned = (RI.getStackAlignment() >= 16) ||
2550 RI.needsStackRealignment(MF);
2551 Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2552 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2553 NewNodes.push_back(Load);
2556 // Emit the data processing instruction.
2557 std::vector<MVT> VTs;
2558 const TargetRegisterClass *DstRC = 0;
2559 if (TID.getNumDefs() > 0) {
2560 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2561 DstRC = DstTOI.isLookupPtrRegClass()
2562 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2563 VTs.push_back(*DstRC->vt_begin());
2565 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2566 MVT VT = N->getValueType(i);
2567 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2571 BeforeOps.push_back(SDValue(Load, 0));
2572 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2573 SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
2575 NewNodes.push_back(NewNode);
2577 // Emit the store instruction.
2580 AddrOps.push_back(SDValue(NewNode, 0));
2581 AddrOps.push_back(Chain);
2582 bool isAligned = (RI.getStackAlignment() >= 16) ||
2583 RI.needsStackRealignment(MF);
2584 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
2587 &AddrOps[0], AddrOps.size());
2588 NewNodes.push_back(Store);
2594 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2595 bool UnfoldLoad, bool UnfoldStore) const {
2596 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2597 MemOp2RegOpTable.find((unsigned*)Opc);
2598 if (I == MemOp2RegOpTable.end())
2600 bool FoldedLoad = I->second.second & (1 << 4);
2601 bool FoldedStore = I->second.second & (1 << 5);
2602 if (UnfoldLoad && !FoldedLoad)
2604 if (UnfoldStore && !FoldedStore)
2606 return I->second.first;
2609 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2610 if (MBB.empty()) return false;
2612 switch (MBB.back().getOpcode()) {
2613 case X86::TCRETURNri:
2614 case X86::TCRETURNdi:
2615 case X86::RET: // Return.
2620 case X86::JMP: // Uncond branch.
2621 case X86::JMP32r: // Indirect branch.
2622 case X86::JMP64r: // Indirect branch (64-bit).
2623 case X86::JMP32m: // Indirect branch through mem.
2624 case X86::JMP64m: // Indirect branch through mem (64-bit).
2626 default: return false;
2631 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2632 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2633 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2634 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2636 Cond[0].setImm(GetOppositeBranchCondition(CC));
2641 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2642 // FIXME: Return false for x87 stack register classes for now. We can't
2643 // allow any loads of these registers before FpGet_ST0_80.
2644 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2645 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2648 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2649 switch (Desc->TSFlags & X86II::ImmMask) {
2650 case X86II::Imm8: return 1;
2651 case X86II::Imm16: return 2;
2652 case X86II::Imm32: return 4;
2653 case X86II::Imm64: return 8;
2654 default: assert(0 && "Immediate size not set!");
2659 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2660 /// e.g. r8, xmm8, etc.
2661 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2662 if (!MO.isReg()) return false;
2663 switch (MO.getReg()) {
2665 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2666 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2667 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2668 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2669 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2670 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2671 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2672 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2673 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2674 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2681 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2682 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2683 /// size, and 3) use of X86-64 extended registers.
2684 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2686 const TargetInstrDesc &Desc = MI.getDesc();
2688 // Pseudo instructions do not need REX prefix byte.
2689 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2691 if (Desc.TSFlags & X86II::REX_W)
2694 unsigned NumOps = Desc.getNumOperands();
2696 bool isTwoAddr = NumOps > 1 &&
2697 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2699 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2700 unsigned i = isTwoAddr ? 1 : 0;
2701 for (unsigned e = NumOps; i != e; ++i) {
2702 const MachineOperand& MO = MI.getOperand(i);
2704 unsigned Reg = MO.getReg();
2705 if (isX86_64NonExtLowByteReg(Reg))
2710 switch (Desc.TSFlags & X86II::FormMask) {
2711 case X86II::MRMInitReg:
2712 if (isX86_64ExtendedReg(MI.getOperand(0)))
2713 REX |= (1 << 0) | (1 << 2);
2715 case X86II::MRMSrcReg: {
2716 if (isX86_64ExtendedReg(MI.getOperand(0)))
2718 i = isTwoAddr ? 2 : 1;
2719 for (unsigned e = NumOps; i != e; ++i) {
2720 const MachineOperand& MO = MI.getOperand(i);
2721 if (isX86_64ExtendedReg(MO))
2726 case X86II::MRMSrcMem: {
2727 if (isX86_64ExtendedReg(MI.getOperand(0)))
2730 i = isTwoAddr ? 2 : 1;
2731 for (; i != NumOps; ++i) {
2732 const MachineOperand& MO = MI.getOperand(i);
2734 if (isX86_64ExtendedReg(MO))
2741 case X86II::MRM0m: case X86II::MRM1m:
2742 case X86II::MRM2m: case X86II::MRM3m:
2743 case X86II::MRM4m: case X86II::MRM5m:
2744 case X86II::MRM6m: case X86II::MRM7m:
2745 case X86II::MRMDestMem: {
2746 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2747 i = isTwoAddr ? 1 : 0;
2748 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2751 for (; i != e; ++i) {
2752 const MachineOperand& MO = MI.getOperand(i);
2754 if (isX86_64ExtendedReg(MO))
2762 if (isX86_64ExtendedReg(MI.getOperand(0)))
2764 i = isTwoAddr ? 2 : 1;
2765 for (unsigned e = NumOps; i != e; ++i) {
2766 const MachineOperand& MO = MI.getOperand(i);
2767 if (isX86_64ExtendedReg(MO))
2777 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2778 /// relative block address instruction
2780 static unsigned sizePCRelativeBlockAddress() {
2784 /// sizeGlobalAddress - Give the size of the emission of this global address
2786 static unsigned sizeGlobalAddress(bool dword) {
2787 return dword ? 8 : 4;
2790 /// sizeConstPoolAddress - Give the size of the emission of this constant
2793 static unsigned sizeConstPoolAddress(bool dword) {
2794 return dword ? 8 : 4;
2797 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2800 static unsigned sizeExternalSymbolAddress(bool dword) {
2801 return dword ? 8 : 4;
2804 /// sizeJumpTableAddress - Give the size of the emission of this jump
2807 static unsigned sizeJumpTableAddress(bool dword) {
2808 return dword ? 8 : 4;
2811 static unsigned sizeConstant(unsigned Size) {
2815 static unsigned sizeRegModRMByte(){
2819 static unsigned sizeSIBByte(){
2823 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2824 unsigned FinalSize = 0;
2825 // If this is a simple integer displacement that doesn't require a relocation.
2827 FinalSize += sizeConstant(4);
2831 // Otherwise, this is something that requires a relocation.
2832 if (RelocOp->isGlobal()) {
2833 FinalSize += sizeGlobalAddress(false);
2834 } else if (RelocOp->isCPI()) {
2835 FinalSize += sizeConstPoolAddress(false);
2836 } else if (RelocOp->isJTI()) {
2837 FinalSize += sizeJumpTableAddress(false);
2839 assert(0 && "Unknown value to relocate!");
2844 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2845 bool IsPIC, bool Is64BitMode) {
2846 const MachineOperand &Op3 = MI.getOperand(Op+3);
2848 const MachineOperand *DispForReloc = 0;
2849 unsigned FinalSize = 0;
2851 // Figure out what sort of displacement we have to handle here.
2852 if (Op3.isGlobal()) {
2853 DispForReloc = &Op3;
2854 } else if (Op3.isCPI()) {
2855 if (Is64BitMode || IsPIC) {
2856 DispForReloc = &Op3;
2860 } else if (Op3.isJTI()) {
2861 if (Is64BitMode || IsPIC) {
2862 DispForReloc = &Op3;
2870 const MachineOperand &Base = MI.getOperand(Op);
2871 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2873 unsigned BaseReg = Base.getReg();
2875 // Is a SIB byte needed?
2876 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2877 IndexReg.getReg() == 0 &&
2878 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2879 if (BaseReg == 0) { // Just a displacement?
2880 // Emit special case [disp32] encoding
2882 FinalSize += getDisplacementFieldSize(DispForReloc);
2884 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2885 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2886 // Emit simple indirect register encoding... [EAX] f.e.
2888 // Be pessimistic and assume it's a disp32, not a disp8
2890 // Emit the most general non-SIB encoding: [REG+disp32]
2892 FinalSize += getDisplacementFieldSize(DispForReloc);
2896 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2897 assert(IndexReg.getReg() != X86::ESP &&
2898 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2900 bool ForceDisp32 = false;
2901 if (BaseReg == 0 || DispForReloc) {
2902 // Emit the normal disp32 encoding.
2909 FinalSize += sizeSIBByte();
2911 // Do we need to output a displacement?
2912 if (DispVal != 0 || ForceDisp32) {
2913 FinalSize += getDisplacementFieldSize(DispForReloc);
2920 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2921 const TargetInstrDesc *Desc,
2922 bool IsPIC, bool Is64BitMode) {
2924 unsigned Opcode = Desc->Opcode;
2925 unsigned FinalSize = 0;
2927 // Emit the lock opcode prefix as needed.
2928 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2930 // Emit segment override opcode prefix as needed.
2931 switch (Desc->TSFlags & X86II::SegOvrMask) {
2936 default: assert(0 && "Invalid segment!");
2937 case 0: break; // No segment override!
2940 // Emit the repeat opcode prefix as needed.
2941 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2943 // Emit the operand size opcode prefix as needed.
2944 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2946 // Emit the address size opcode prefix as needed.
2947 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2949 bool Need0FPrefix = false;
2950 switch (Desc->TSFlags & X86II::Op0Mask) {
2951 case X86II::TB: // Two-byte opcode prefix
2952 case X86II::T8: // 0F 38
2953 case X86II::TA: // 0F 3A
2954 Need0FPrefix = true;
2956 case X86II::REP: break; // already handled.
2957 case X86II::XS: // F3 0F
2959 Need0FPrefix = true;
2961 case X86II::XD: // F2 0F
2963 Need0FPrefix = true;
2965 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2966 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2968 break; // Two-byte opcode prefix
2969 default: assert(0 && "Invalid prefix!");
2970 case 0: break; // No prefix!
2975 unsigned REX = X86InstrInfo::determineREX(MI);
2980 // 0x0F escape code must be emitted just before the opcode.
2984 switch (Desc->TSFlags & X86II::Op0Mask) {
2985 case X86II::T8: // 0F 38
2988 case X86II::TA: // 0F 3A
2993 // If this is a two-address instruction, skip one of the register operands.
2994 unsigned NumOps = Desc->getNumOperands();
2996 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2998 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
2999 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3002 switch (Desc->TSFlags & X86II::FormMask) {
3003 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
3005 // Remember the current PC offset, this is the PIC relocation
3010 case TargetInstrInfo::INLINEASM: {
3011 const MachineFunction *MF = MI.getParent()->getParent();
3012 const char *AsmStr = MI.getOperand(0).getSymbolName();
3013 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
3014 FinalSize += AI->getInlineAsmLength(AsmStr);
3017 case TargetInstrInfo::DBG_LABEL:
3018 case TargetInstrInfo::EH_LABEL:
3020 case TargetInstrInfo::IMPLICIT_DEF:
3021 case TargetInstrInfo::DECLARE:
3022 case X86::DWARF_LOC:
3023 case X86::FP_REG_KILL:
3025 case X86::MOVPC32r: {
3026 // This emits the "call" portion of this pseudo instruction.
3028 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3037 if (CurOp != NumOps) {
3038 const MachineOperand &MO = MI.getOperand(CurOp++);
3040 FinalSize += sizePCRelativeBlockAddress();
3041 } else if (MO.isGlobal()) {
3042 FinalSize += sizeGlobalAddress(false);
3043 } else if (MO.isSymbol()) {
3044 FinalSize += sizeExternalSymbolAddress(false);
3045 } else if (MO.isImm()) {
3046 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3048 assert(0 && "Unknown RawFrm operand!");
3053 case X86II::AddRegFrm:
3057 if (CurOp != NumOps) {
3058 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3059 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3061 FinalSize += sizeConstant(Size);
3064 if (Opcode == X86::MOV64ri)
3066 if (MO1.isGlobal()) {
3067 FinalSize += sizeGlobalAddress(dword);
3068 } else if (MO1.isSymbol())
3069 FinalSize += sizeExternalSymbolAddress(dword);
3070 else if (MO1.isCPI())
3071 FinalSize += sizeConstPoolAddress(dword);
3072 else if (MO1.isJTI())
3073 FinalSize += sizeJumpTableAddress(dword);
3078 case X86II::MRMDestReg: {
3080 FinalSize += sizeRegModRMByte();
3082 if (CurOp != NumOps) {
3084 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3088 case X86II::MRMDestMem: {
3090 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3091 CurOp += X86AddrNumOperands + 1;
3092 if (CurOp != NumOps) {
3094 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3099 case X86II::MRMSrcReg:
3101 FinalSize += sizeRegModRMByte();
3103 if (CurOp != NumOps) {
3105 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3109 case X86II::MRMSrcMem: {
3111 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3112 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3113 AddrOperands = X86AddrNumOperands - 1; // No segment register
3115 AddrOperands = X86AddrNumOperands;
3118 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3119 CurOp += AddrOperands + 1;
3120 if (CurOp != NumOps) {
3122 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3127 case X86II::MRM0r: case X86II::MRM1r:
3128 case X86II::MRM2r: case X86II::MRM3r:
3129 case X86II::MRM4r: case X86II::MRM5r:
3130 case X86II::MRM6r: case X86II::MRM7r:
3132 if (Desc->getOpcode() == X86::LFENCE ||
3133 Desc->getOpcode() == X86::MFENCE) {
3134 // Special handling of lfence and mfence;
3135 FinalSize += sizeRegModRMByte();
3136 } else if (Desc->getOpcode() == X86::MONITOR ||
3137 Desc->getOpcode() == X86::MWAIT) {
3138 // Special handling of monitor and mwait.
3139 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3142 FinalSize += sizeRegModRMByte();
3145 if (CurOp != NumOps) {
3146 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3147 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3149 FinalSize += sizeConstant(Size);
3152 if (Opcode == X86::MOV64ri32)
3154 if (MO1.isGlobal()) {
3155 FinalSize += sizeGlobalAddress(dword);
3156 } else if (MO1.isSymbol())
3157 FinalSize += sizeExternalSymbolAddress(dword);
3158 else if (MO1.isCPI())
3159 FinalSize += sizeConstPoolAddress(dword);
3160 else if (MO1.isJTI())
3161 FinalSize += sizeJumpTableAddress(dword);
3166 case X86II::MRM0m: case X86II::MRM1m:
3167 case X86II::MRM2m: case X86II::MRM3m:
3168 case X86II::MRM4m: case X86II::MRM5m:
3169 case X86II::MRM6m: case X86II::MRM7m: {
3172 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3173 CurOp += X86AddrNumOperands;
3175 if (CurOp != NumOps) {
3176 const MachineOperand &MO = MI.getOperand(CurOp++);
3177 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3179 FinalSize += sizeConstant(Size);
3182 if (Opcode == X86::MOV64mi32)
3184 if (MO.isGlobal()) {
3185 FinalSize += sizeGlobalAddress(dword);
3186 } else if (MO.isSymbol())
3187 FinalSize += sizeExternalSymbolAddress(dword);
3188 else if (MO.isCPI())
3189 FinalSize += sizeConstPoolAddress(dword);
3190 else if (MO.isJTI())
3191 FinalSize += sizeJumpTableAddress(dword);
3197 case X86II::MRMInitReg:
3199 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3200 FinalSize += sizeRegModRMByte();
3205 if (!Desc->isVariadic() && CurOp != NumOps) {
3207 raw_string_ostream Msg(msg);
3208 Msg << "Cannot determine size: " << MI;
3209 llvm_report_error(Msg.str());
3217 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3218 const TargetInstrDesc &Desc = MI->getDesc();
3219 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
3220 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3221 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3222 if (Desc.getOpcode() == X86::MOVPC32r)
3223 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3227 /// getGlobalBaseReg - Return a virtual register initialized with the
3228 /// the global base register value. Output instructions required to
3229 /// initialize the register in the function entry block, if necessary.
3231 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3232 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3233 "X86-64 PIC uses RIP relative addressing");
3235 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3236 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3237 if (GlobalBaseReg != 0)
3238 return GlobalBaseReg;
3240 // Insert the set of GlobalBaseReg into the first MBB of the function
3241 MachineBasicBlock &FirstMBB = MF->front();
3242 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3243 DebugLoc DL = DebugLoc::getUnknownLoc();
3244 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3245 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3246 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3248 const TargetInstrInfo *TII = TM.getInstrInfo();
3249 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3250 // only used in JIT code emission as displacement to pc.
3251 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3253 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3254 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3255 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3256 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3257 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3258 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3259 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 0,
3260 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3265 X86FI->setGlobalBaseReg(GlobalBaseReg);
3266 return GlobalBaseReg;