1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "X86GenInstrInfo.inc"
21 X86InstrInfo::X86InstrInfo()
22 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
26 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& destReg) const {
29 MachineOpCode oc = MI.getOpcode();
30 if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
31 oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
32 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
33 assert(MI.getNumOperands() == 2 &&
34 MI.getOperand(0).isRegister() &&
35 MI.getOperand(1).isRegister() &&
36 "invalid register-register move instruction");
37 sourceReg = MI.getOperand(1).getReg();
38 destReg = MI.getOperand(0).getReg();
44 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
45 int &FrameIndex) const {
46 switch (MI->getOpcode()) {
54 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
55 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
56 MI->getOperand(2).getImmedValue() == 1 &&
57 MI->getOperand(3).getReg() == 0 &&
58 MI->getOperand(4).getImmedValue() == 0) {
59 FrameIndex = MI->getOperand(1).getFrameIndex();
60 return MI->getOperand(0).getReg();
67 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
68 int &FrameIndex) const {
69 switch (MI->getOpcode()) {
77 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
78 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
79 MI->getOperand(1).getImmedValue() == 1 &&
80 MI->getOperand(2).getReg() == 0 &&
81 MI->getOperand(3).getImmedValue() == 0) {
82 FrameIndex = MI->getOperand(0).getFrameIndex();
83 return MI->getOperand(4).getReg();
92 /// convertToThreeAddress - This method must be implemented by targets that
93 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
94 /// may be able to convert a two-address instruction into a true
95 /// three-address instruction on demand. This allows the X86 target (for
96 /// example) to convert ADD and SHL instructions into LEA instructions if they
97 /// would require register copies due to two-addressness.
99 /// This method returns a null pointer if the transformation cannot be
100 /// performed, otherwise it returns the new instruction.
102 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
103 // All instructions input are two-addr instructions. Get the known operands.
104 unsigned Dest = MI->getOperand(0).getReg();
105 unsigned Src = MI->getOperand(1).getReg();
107 // FIXME: None of these instructions are promotable to LEAs without
108 // additional information. In particular, LEA doesn't set the flags that
109 // add and inc do. :(
112 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
113 // we have subtarget support, enable the 16-bit LEA generation here.
114 bool DisableLEA16 = true;
116 switch (MI->getOpcode()) {
118 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
119 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
121 if (DisableLEA16) return 0;
122 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
123 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
125 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
126 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
128 if (DisableLEA16) return 0;
129 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
130 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
132 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
133 return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
134 MI->getOperand(2).getReg());
136 if (DisableLEA16) return 0;
137 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
138 return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
139 MI->getOperand(2).getReg());
141 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
142 if (MI->getOperand(2).isImmediate())
143 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
144 MI->getOperand(2).getImmedValue());
147 if (DisableLEA16) return 0;
148 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
149 if (MI->getOperand(2).isImmediate())
150 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
151 MI->getOperand(2).getImmedValue());
155 if (DisableLEA16) return 0;
157 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
158 "Unknown shl instruction!");
159 unsigned ShAmt = MI->getOperand(2).getImmedValue();
160 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
162 AM.Scale = 1 << ShAmt;
164 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
165 return addFullAddress(BuildMI(Opc, 5, Dest), AM);
173 /// commuteInstruction - We have a few instructions that must be hacked on to
176 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
177 switch (MI->getOpcode()) {
178 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
179 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
180 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
181 case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
184 switch (MI->getOpcode()) {
185 default: assert(0 && "Unreachable!");
186 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
187 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
188 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
189 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
191 unsigned Amt = MI->getOperand(3).getImmedValue();
192 unsigned A = MI->getOperand(0).getReg();
193 unsigned B = MI->getOperand(1).getReg();
194 unsigned C = MI->getOperand(2).getReg();
195 return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
198 return TargetInstrInfo::commuteInstruction(MI);
203 void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
204 MachineBasicBlock& TMBB) const {
205 BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
208 MachineBasicBlock::iterator
209 X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
210 unsigned Opcode = MI->getOpcode();
211 assert(isBranch(Opcode) && "MachineInstr must be a branch");
214 default: assert(0 && "Cannot reverse unconditional branches!");
215 case X86::JB: ROpcode = X86::JAE; break;
216 case X86::JAE: ROpcode = X86::JB; break;
217 case X86::JE: ROpcode = X86::JNE; break;
218 case X86::JNE: ROpcode = X86::JE; break;
219 case X86::JBE: ROpcode = X86::JA; break;
220 case X86::JA: ROpcode = X86::JBE; break;
221 case X86::JS: ROpcode = X86::JNS; break;
222 case X86::JNS: ROpcode = X86::JS; break;
223 case X86::JP: ROpcode = X86::JNP; break;
224 case X86::JNP: ROpcode = X86::JP; break;
225 case X86::JL: ROpcode = X86::JGE; break;
226 case X86::JGE: ROpcode = X86::JL; break;
227 case X86::JLE: ROpcode = X86::JG; break;
228 case X86::JG: ROpcode = X86::JLE; break;
230 MachineBasicBlock* MBB = MI->getParent();
231 MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
232 return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);