1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/Target/TargetOptions.h"
29 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
30 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
31 TM(tm), RI(tm, *this) {
34 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
36 unsigned& destReg) const {
37 MachineOpCode oc = MI.getOpcode();
38 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
39 oc == X86::MOV32rr || oc == X86::MOV64rr ||
40 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
41 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
42 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
43 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
44 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
45 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
46 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
47 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
48 assert(MI.getNumOperands() >= 2 &&
49 MI.getOperand(0).isRegister() &&
50 MI.getOperand(1).isRegister() &&
51 "invalid register-register move instruction");
52 sourceReg = MI.getOperand(1).getReg();
53 destReg = MI.getOperand(0).getReg();
59 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
60 int &FrameIndex) const {
61 switch (MI->getOpcode()) {
74 case X86::MMX_MOVD64rm:
75 case X86::MMX_MOVQ64rm:
76 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
77 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
78 MI->getOperand(2).getImm() == 1 &&
79 MI->getOperand(3).getReg() == 0 &&
80 MI->getOperand(4).getImm() == 0) {
81 FrameIndex = MI->getOperand(1).getIndex();
82 return MI->getOperand(0).getReg();
89 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
90 int &FrameIndex) const {
91 switch (MI->getOpcode()) {
104 case X86::MMX_MOVD64mr:
105 case X86::MMX_MOVQ64mr:
106 case X86::MMX_MOVNTQmr:
107 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
108 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
109 MI->getOperand(1).getImm() == 1 &&
110 MI->getOperand(2).getReg() == 0 &&
111 MI->getOperand(3).getImm() == 0) {
112 FrameIndex = MI->getOperand(0).getIndex();
113 return MI->getOperand(4).getReg();
121 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
122 switch (MI->getOpcode()) {
135 case X86::MMX_MOVD64rm:
136 case X86::MMX_MOVQ64rm:
137 // Loads from constant pools are trivially rematerializable.
138 if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
139 MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
140 MI->getOperand(1).getReg() == 0 &&
141 MI->getOperand(2).getImm() == 1 &&
142 MI->getOperand(3).getReg() == 0)
145 // If this is a load from a fixed argument slot, we know the value is
146 // invariant across the whole function, because we don't redefine argument
149 // FIXME: This is disabled due to a remat bug. rdar://5671644
150 MachineFunction *MF = MI->getParent()->getParent();
151 if (MI->getOperand(1).isFI() &&
152 MF->getFrameInfo()->isFixedObjectIndex(MI->getOperand(1).getIndex()))
158 // All other instructions marked M_REMATERIALIZABLE are always trivially
163 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
164 /// method is called to determine if the specific instance of this instruction
165 /// has side effects. This is useful in cases of instructions, like loads, which
166 /// generally always have side effects. A load from a constant pool doesn't have
167 /// side effects, though. So we need to differentiate it from the general case.
168 bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
169 switch (MI->getOpcode()) {
172 if (MI->getOperand(1).isRegister()) {
173 unsigned Reg = MI->getOperand(1).getReg();
175 // Loads from global addresses which aren't redefined in the function are
177 if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
178 MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
179 MI->getOperand(4).isGlobal() && MI->getOperand(2).getImm() == 1 &&
180 MI->getOperand(3).getReg() == 0)
194 case X86::MMX_MOVD64rm:
195 case X86::MMX_MOVQ64rm:
196 // Loads from constant pools are trivially rematerializable.
197 if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
198 MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
199 MI->getOperand(1).getReg() == 0 &&
200 MI->getOperand(2).getImm() == 1 &&
201 MI->getOperand(3).getReg() == 0)
204 // If this is a load from a fixed argument slot, we know the value is
205 // invariant across the whole function, because we don't redefine argument
207 MachineFunction *MF = MI->getParent()->getParent();
208 if (MI->getOperand(1).isFI() &&
209 MF->getFrameInfo()->isFixedObjectIndex(MI->getOperand(1).getIndex()))
215 // All other instances of these instructions are presumed to have side
220 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
221 /// is not marked dead.
222 static bool hasLiveCondCodeDef(MachineInstr *MI) {
223 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
224 MachineOperand &MO = MI->getOperand(i);
225 if (MO.isRegister() && MO.isDef() &&
226 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
233 /// convertToThreeAddress - This method must be implemented by targets that
234 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
235 /// may be able to convert a two-address instruction into a true
236 /// three-address instruction on demand. This allows the X86 target (for
237 /// example) to convert ADD and SHL instructions into LEA instructions if they
238 /// would require register copies due to two-addressness.
240 /// This method returns a null pointer if the transformation cannot be
241 /// performed, otherwise it returns the new instruction.
244 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
245 MachineBasicBlock::iterator &MBBI,
246 LiveVariables &LV) const {
247 MachineInstr *MI = MBBI;
248 // All instructions input are two-addr instructions. Get the known operands.
249 unsigned Dest = MI->getOperand(0).getReg();
250 unsigned Src = MI->getOperand(1).getReg();
252 MachineInstr *NewMI = NULL;
253 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
254 // we have better subtarget support, enable the 16-bit LEA generation here.
255 bool DisableLEA16 = true;
257 unsigned MIOpc = MI->getOpcode();
259 case X86::SHUFPSrri: {
260 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
261 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
263 unsigned A = MI->getOperand(0).getReg();
264 unsigned B = MI->getOperand(1).getReg();
265 unsigned C = MI->getOperand(2).getReg();
266 unsigned M = MI->getOperand(3).getImm();
267 if (B != C) return 0;
268 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
272 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
273 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
274 // the flags produced by a shift yet, so this is safe.
275 unsigned Dest = MI->getOperand(0).getReg();
276 unsigned Src = MI->getOperand(1).getReg();
277 unsigned ShAmt = MI->getOperand(2).getImm();
278 if (ShAmt == 0 || ShAmt >= 4) return 0;
280 NewMI = BuildMI(get(X86::LEA64r), Dest)
281 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
285 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
286 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
287 // the flags produced by a shift yet, so this is safe.
288 unsigned Dest = MI->getOperand(0).getReg();
289 unsigned Src = MI->getOperand(1).getReg();
290 unsigned ShAmt = MI->getOperand(2).getImm();
291 if (ShAmt == 0 || ShAmt >= 4) return 0;
293 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
294 X86::LEA64_32r : X86::LEA32r;
295 NewMI = BuildMI(get(Opc), Dest)
296 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
300 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
301 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
302 // the flags produced by a shift yet, so this is safe.
303 unsigned Dest = MI->getOperand(0).getReg();
304 unsigned Src = MI->getOperand(1).getReg();
305 unsigned ShAmt = MI->getOperand(2).getImm();
306 if (ShAmt == 0 || ShAmt >= 4) return 0;
309 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
310 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
311 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
312 ? X86::LEA64_32r : X86::LEA32r;
313 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
314 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
317 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
318 Ins->copyKillDeadInfo(MI);
320 NewMI = BuildMI(get(Opc), leaOutReg)
321 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
324 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
325 Ext->copyKillDeadInfo(MI);
327 MFI->insert(MBBI, Ins); // Insert the insert_subreg
328 LV.instructionChanged(MI, NewMI); // Update live variables
329 LV.addVirtualRegisterKilled(leaInReg, NewMI);
330 MFI->insert(MBBI, NewMI); // Insert the new inst
331 LV.addVirtualRegisterKilled(leaOutReg, Ext);
332 MFI->insert(MBBI, Ext); // Insert the extract_subreg
335 NewMI = BuildMI(get(X86::LEA16r), Dest)
336 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
341 // The following opcodes also sets the condition code register(s). Only
342 // convert them to equivalent lea if the condition code register def's
344 if (hasLiveCondCodeDef(MI))
347 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
352 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
353 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
354 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
355 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
360 if (DisableLEA16) return 0;
361 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
362 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
366 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
367 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
368 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
369 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
374 if (DisableLEA16) return 0;
375 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
376 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
380 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
381 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
382 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
383 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
384 MI->getOperand(2).getReg());
388 if (DisableLEA16) return 0;
389 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
390 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
391 MI->getOperand(2).getReg());
395 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
396 if (MI->getOperand(2).isImmediate())
397 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
398 MI->getOperand(2).getImm());
402 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
403 if (MI->getOperand(2).isImmediate()) {
404 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
405 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
406 MI->getOperand(2).getImm());
411 if (DisableLEA16) return 0;
412 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
413 if (MI->getOperand(2).isImmediate())
414 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
415 MI->getOperand(2).getImm());
418 if (DisableLEA16) return 0;
421 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
422 "Unknown shl instruction!");
423 unsigned ShAmt = MI->getOperand(2).getImm();
424 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
426 AM.Scale = 1 << ShAmt;
428 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
429 : (MIOpc == X86::SHL32ri
430 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
431 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
439 NewMI->copyKillDeadInfo(MI);
440 LV.instructionChanged(MI, NewMI); // Update live variables
441 MFI->insert(MBBI, NewMI); // Insert the new inst
445 /// commuteInstruction - We have a few instructions that must be hacked on to
448 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
449 switch (MI->getOpcode()) {
450 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
451 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
452 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
453 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
454 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
455 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
458 switch (MI->getOpcode()) {
459 default: assert(0 && "Unreachable!");
460 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
461 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
462 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
463 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
464 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
465 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
467 unsigned Amt = MI->getOperand(3).getImm();
468 unsigned A = MI->getOperand(0).getReg();
469 unsigned B = MI->getOperand(1).getReg();
470 unsigned C = MI->getOperand(2).getReg();
471 bool BisKill = MI->getOperand(1).isKill();
472 bool CisKill = MI->getOperand(2).isKill();
473 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
474 .addReg(B, false, false, BisKill).addImm(Size-Amt);
479 case X86::CMOVAE16rr:
480 case X86::CMOVAE32rr:
481 case X86::CMOVAE64rr:
485 case X86::CMOVNE16rr:
486 case X86::CMOVNE32rr:
487 case X86::CMOVNE64rr:
488 case X86::CMOVBE16rr:
489 case X86::CMOVBE32rr:
490 case X86::CMOVBE64rr:
497 case X86::CMOVGE16rr:
498 case X86::CMOVGE32rr:
499 case X86::CMOVGE64rr:
500 case X86::CMOVLE16rr:
501 case X86::CMOVLE32rr:
502 case X86::CMOVLE64rr:
509 case X86::CMOVNS16rr:
510 case X86::CMOVNS32rr:
511 case X86::CMOVNS64rr:
515 case X86::CMOVNP16rr:
516 case X86::CMOVNP32rr:
517 case X86::CMOVNP64rr: {
519 switch (MI->getOpcode()) {
521 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
522 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
523 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
524 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
525 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
526 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
527 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
528 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
529 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
530 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
531 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
532 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
533 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
534 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
535 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
536 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
537 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
538 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
539 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
540 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
541 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
542 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
543 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
544 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
545 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
546 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
547 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
548 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
549 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
550 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
551 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
552 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
553 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
554 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
555 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
556 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
557 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
558 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
559 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
560 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
561 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
562 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
565 MI->setInstrDescriptor(get(Opc));
566 // Fallthrough intended.
569 return TargetInstrInfoImpl::commuteInstruction(MI);
573 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
575 default: return X86::COND_INVALID;
576 case X86::JE: return X86::COND_E;
577 case X86::JNE: return X86::COND_NE;
578 case X86::JL: return X86::COND_L;
579 case X86::JLE: return X86::COND_LE;
580 case X86::JG: return X86::COND_G;
581 case X86::JGE: return X86::COND_GE;
582 case X86::JB: return X86::COND_B;
583 case X86::JBE: return X86::COND_BE;
584 case X86::JA: return X86::COND_A;
585 case X86::JAE: return X86::COND_AE;
586 case X86::JS: return X86::COND_S;
587 case X86::JNS: return X86::COND_NS;
588 case X86::JP: return X86::COND_P;
589 case X86::JNP: return X86::COND_NP;
590 case X86::JO: return X86::COND_O;
591 case X86::JNO: return X86::COND_NO;
595 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
597 default: assert(0 && "Illegal condition code!");
598 case X86::COND_E: return X86::JE;
599 case X86::COND_NE: return X86::JNE;
600 case X86::COND_L: return X86::JL;
601 case X86::COND_LE: return X86::JLE;
602 case X86::COND_G: return X86::JG;
603 case X86::COND_GE: return X86::JGE;
604 case X86::COND_B: return X86::JB;
605 case X86::COND_BE: return X86::JBE;
606 case X86::COND_A: return X86::JA;
607 case X86::COND_AE: return X86::JAE;
608 case X86::COND_S: return X86::JS;
609 case X86::COND_NS: return X86::JNS;
610 case X86::COND_P: return X86::JP;
611 case X86::COND_NP: return X86::JNP;
612 case X86::COND_O: return X86::JO;
613 case X86::COND_NO: return X86::JNO;
617 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
618 /// e.g. turning COND_E to COND_NE.
619 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
621 default: assert(0 && "Illegal condition code!");
622 case X86::COND_E: return X86::COND_NE;
623 case X86::COND_NE: return X86::COND_E;
624 case X86::COND_L: return X86::COND_GE;
625 case X86::COND_LE: return X86::COND_G;
626 case X86::COND_G: return X86::COND_LE;
627 case X86::COND_GE: return X86::COND_L;
628 case X86::COND_B: return X86::COND_AE;
629 case X86::COND_BE: return X86::COND_A;
630 case X86::COND_A: return X86::COND_BE;
631 case X86::COND_AE: return X86::COND_B;
632 case X86::COND_S: return X86::COND_NS;
633 case X86::COND_NS: return X86::COND_S;
634 case X86::COND_P: return X86::COND_NP;
635 case X86::COND_NP: return X86::COND_P;
636 case X86::COND_O: return X86::COND_NO;
637 case X86::COND_NO: return X86::COND_O;
641 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
642 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
643 if (TID->Flags & M_TERMINATOR_FLAG) {
644 // Conditional branch is a special case.
645 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
647 if ((TID->Flags & M_PREDICABLE) == 0)
649 return !isPredicated(MI);
654 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
655 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
656 const X86InstrInfo &TII) {
657 if (MI->getOpcode() == X86::FP_REG_KILL)
659 return TII.isUnpredicatedTerminator(MI);
662 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
663 MachineBasicBlock *&TBB,
664 MachineBasicBlock *&FBB,
665 std::vector<MachineOperand> &Cond) const {
666 // If the block has no terminators, it just falls into the block after it.
667 MachineBasicBlock::iterator I = MBB.end();
668 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
671 // Get the last instruction in the block.
672 MachineInstr *LastInst = I;
674 // If there is only one terminator instruction, process it.
675 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
676 if (!isBranch(LastInst->getOpcode()))
679 // If the block ends with a branch there are 3 possibilities:
680 // it's an unconditional, conditional, or indirect branch.
682 if (LastInst->getOpcode() == X86::JMP) {
683 TBB = LastInst->getOperand(0).getMBB();
686 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
687 if (BranchCode == X86::COND_INVALID)
688 return true; // Can't handle indirect branch.
690 // Otherwise, block ends with fall-through condbranch.
691 TBB = LastInst->getOperand(0).getMBB();
692 Cond.push_back(MachineOperand::CreateImm(BranchCode));
696 // Get the instruction before it if it's a terminator.
697 MachineInstr *SecondLastInst = I;
699 // If there are three terminators, we don't know what sort of block this is.
700 if (SecondLastInst && I != MBB.begin() &&
701 isBrAnalysisUnpredicatedTerminator(--I, *this))
704 // If the block ends with X86::JMP and a conditional branch, handle it.
705 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
706 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
707 TBB = SecondLastInst->getOperand(0).getMBB();
708 Cond.push_back(MachineOperand::CreateImm(BranchCode));
709 FBB = LastInst->getOperand(0).getMBB();
713 // If the block ends with two X86::JMPs, handle it. The second one is not
714 // executed, so remove it.
715 if (SecondLastInst->getOpcode() == X86::JMP &&
716 LastInst->getOpcode() == X86::JMP) {
717 TBB = SecondLastInst->getOperand(0).getMBB();
719 I->eraseFromParent();
723 // Otherwise, can't handle this.
727 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
728 MachineBasicBlock::iterator I = MBB.end();
729 if (I == MBB.begin()) return 0;
731 if (I->getOpcode() != X86::JMP &&
732 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
735 // Remove the branch.
736 I->eraseFromParent();
740 if (I == MBB.begin()) return 1;
742 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
745 // Remove the branch.
746 I->eraseFromParent();
750 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
751 MachineOperand &MO) {
753 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
754 false, false, MO.getSubReg());
755 else if (MO.isImmediate())
756 MIB = MIB.addImm(MO.getImm());
757 else if (MO.isFrameIndex())
758 MIB = MIB.addFrameIndex(MO.getIndex());
759 else if (MO.isGlobalAddress())
760 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
761 else if (MO.isConstantPoolIndex())
762 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
763 else if (MO.isJumpTableIndex())
764 MIB = MIB.addJumpTableIndex(MO.getIndex());
765 else if (MO.isExternalSymbol())
766 MIB = MIB.addExternalSymbol(MO.getSymbolName());
768 assert(0 && "Unknown operand for X86InstrAddOperand!");
774 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
775 MachineBasicBlock *FBB,
776 const std::vector<MachineOperand> &Cond) const {
777 // Shouldn't be a fall through.
778 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
779 assert((Cond.size() == 1 || Cond.size() == 0) &&
780 "X86 branch conditions have one component!");
782 if (FBB == 0) { // One way branch.
784 // Unconditional branch?
785 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
787 // Conditional branch.
788 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
789 BuildMI(&MBB, get(Opc)).addMBB(TBB);
794 // Two-way Conditional branch.
795 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
796 BuildMI(&MBB, get(Opc)).addMBB(TBB);
797 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
801 void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
802 MachineBasicBlock::iterator MI,
803 unsigned DestReg, unsigned SrcReg,
804 const TargetRegisterClass *DestRC,
805 const TargetRegisterClass *SrcRC) const {
806 if (DestRC != SrcRC) {
807 // Moving EFLAGS to / from another register requires a push and a pop.
808 if (SrcRC == &X86::CCRRegClass) {
809 assert(SrcReg == X86::EFLAGS);
810 if (DestRC == &X86::GR64RegClass) {
811 BuildMI(MBB, MI, get(X86::PUSHFQ));
812 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
814 } else if (DestRC == &X86::GR32RegClass) {
815 BuildMI(MBB, MI, get(X86::PUSHFD));
816 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
819 } else if (DestRC == &X86::CCRRegClass) {
820 assert(DestReg == X86::EFLAGS);
821 if (SrcRC == &X86::GR64RegClass) {
822 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
823 BuildMI(MBB, MI, get(X86::POPFQ));
825 } else if (SrcRC == &X86::GR32RegClass) {
826 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
827 BuildMI(MBB, MI, get(X86::POPFD));
831 cerr << "Not yet supported!";
836 if (DestRC == &X86::GR64RegClass) {
838 } else if (DestRC == &X86::GR32RegClass) {
840 } else if (DestRC == &X86::GR16RegClass) {
842 } else if (DestRC == &X86::GR8RegClass) {
844 } else if (DestRC == &X86::GR32_RegClass) {
846 } else if (DestRC == &X86::GR16_RegClass) {
848 } else if (DestRC == &X86::RFP32RegClass) {
849 Opc = X86::MOV_Fp3232;
850 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
851 Opc = X86::MOV_Fp6464;
852 } else if (DestRC == &X86::RFP80RegClass) {
853 Opc = X86::MOV_Fp8080;
854 } else if (DestRC == &X86::FR32RegClass) {
855 Opc = X86::FsMOVAPSrr;
856 } else if (DestRC == &X86::FR64RegClass) {
857 Opc = X86::FsMOVAPDrr;
858 } else if (DestRC == &X86::VR128RegClass) {
860 } else if (DestRC == &X86::VR64RegClass) {
861 Opc = X86::MMX_MOVQ64rr;
863 assert(0 && "Unknown regclass");
866 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
869 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
870 unsigned StackAlign) {
872 if (RC == &X86::GR64RegClass) {
874 } else if (RC == &X86::GR32RegClass) {
876 } else if (RC == &X86::GR16RegClass) {
878 } else if (RC == &X86::GR8RegClass) {
880 } else if (RC == &X86::GR32_RegClass) {
882 } else if (RC == &X86::GR16_RegClass) {
884 } else if (RC == &X86::RFP80RegClass) {
885 Opc = X86::ST_FpP80m; // pops
886 } else if (RC == &X86::RFP64RegClass) {
888 } else if (RC == &X86::RFP32RegClass) {
890 } else if (RC == &X86::FR32RegClass) {
892 } else if (RC == &X86::FR64RegClass) {
894 } else if (RC == &X86::VR128RegClass) {
895 // FIXME: Use movaps once we are capable of selectively
896 // aligning functions that spill SSE registers on 16-byte boundaries.
897 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
898 } else if (RC == &X86::VR64RegClass) {
899 Opc = X86::MMX_MOVQ64mr;
901 assert(0 && "Unknown regclass");
908 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
909 MachineBasicBlock::iterator MI,
910 unsigned SrcReg, bool isKill, int FrameIdx,
911 const TargetRegisterClass *RC) const {
912 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
913 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
914 .addReg(SrcReg, false, false, isKill);
917 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
919 SmallVectorImpl<MachineOperand> &Addr,
920 const TargetRegisterClass *RC,
921 SmallVectorImpl<MachineInstr*> &NewMIs) const {
922 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
923 MachineInstrBuilder MIB = BuildMI(get(Opc));
924 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
925 MIB = X86InstrAddOperand(MIB, Addr[i]);
926 MIB.addReg(SrcReg, false, false, isKill);
927 NewMIs.push_back(MIB);
930 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
931 unsigned StackAlign) {
933 if (RC == &X86::GR64RegClass) {
935 } else if (RC == &X86::GR32RegClass) {
937 } else if (RC == &X86::GR16RegClass) {
939 } else if (RC == &X86::GR8RegClass) {
941 } else if (RC == &X86::GR32_RegClass) {
943 } else if (RC == &X86::GR16_RegClass) {
945 } else if (RC == &X86::RFP80RegClass) {
947 } else if (RC == &X86::RFP64RegClass) {
949 } else if (RC == &X86::RFP32RegClass) {
951 } else if (RC == &X86::FR32RegClass) {
953 } else if (RC == &X86::FR64RegClass) {
955 } else if (RC == &X86::VR128RegClass) {
956 // FIXME: Use movaps once we are capable of selectively
957 // aligning functions that spill SSE registers on 16-byte boundaries.
958 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
959 } else if (RC == &X86::VR64RegClass) {
960 Opc = X86::MMX_MOVQ64rm;
962 assert(0 && "Unknown regclass");
969 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
970 MachineBasicBlock::iterator MI,
971 unsigned DestReg, int FrameIdx,
972 const TargetRegisterClass *RC) const{
973 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
974 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
977 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
978 SmallVectorImpl<MachineOperand> &Addr,
979 const TargetRegisterClass *RC,
980 SmallVectorImpl<MachineInstr*> &NewMIs) const {
981 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
982 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
983 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
984 MIB = X86InstrAddOperand(MIB, Addr[i]);
985 NewMIs.push_back(MIB);
988 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
989 MachineBasicBlock::iterator MI,
990 const std::vector<CalleeSavedInfo> &CSI) const {
994 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
995 unsigned SlotSize = is64Bit ? 8 : 4;
997 MachineFunction &MF = *MBB.getParent();
998 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
999 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1001 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1002 for (unsigned i = CSI.size(); i != 0; --i) {
1003 unsigned Reg = CSI[i-1].getReg();
1004 // Add the callee-saved register as live-in. It's killed at the spill.
1006 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1011 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1012 MachineBasicBlock::iterator MI,
1013 const std::vector<CalleeSavedInfo> &CSI) const {
1017 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1019 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1020 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1021 unsigned Reg = CSI[i].getReg();
1022 BuildMI(MBB, MI, get(Opc), Reg);
1027 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
1028 if (MBB.empty()) return false;
1030 switch (MBB.back().getOpcode()) {
1031 case X86::TCRETURNri:
1032 case X86::TCRETURNdi:
1033 case X86::RET: // Return.
1038 case X86::JMP: // Uncond branch.
1039 case X86::JMP32r: // Indirect branch.
1040 case X86::JMP64r: // Indirect branch (64-bit).
1041 case X86::JMP32m: // Indirect branch through mem.
1042 case X86::JMP64m: // Indirect branch through mem (64-bit).
1044 default: return false;
1049 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
1050 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
1051 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
1055 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
1056 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
1057 if (Subtarget->is64Bit())
1058 return &X86::GR64RegClass;
1060 return &X86::GR32RegClass;