1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/SSARegMap.h"
25 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
26 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
27 TM(tm), RI(tm, *this) {
30 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
32 unsigned& destReg) const {
33 MachineOpCode oc = MI.getOpcode();
34 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
35 oc == X86::MOV32rr || oc == X86::MOV64rr ||
36 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
37 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
38 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
39 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
40 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
41 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
42 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
43 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
44 assert(MI.getNumOperands() >= 2 &&
45 MI.getOperand(0).isRegister() &&
46 MI.getOperand(1).isRegister() &&
47 "invalid register-register move instruction");
48 sourceReg = MI.getOperand(1).getReg();
49 destReg = MI.getOperand(0).getReg();
55 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
56 int &FrameIndex) const {
57 switch (MI->getOpcode()) {
70 case X86::MMX_MOVD64rm:
71 case X86::MMX_MOVQ64rm:
72 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
73 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
74 MI->getOperand(2).getImmedValue() == 1 &&
75 MI->getOperand(3).getReg() == 0 &&
76 MI->getOperand(4).getImmedValue() == 0) {
77 FrameIndex = MI->getOperand(1).getFrameIndex();
78 return MI->getOperand(0).getReg();
85 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
86 int &FrameIndex) const {
87 switch (MI->getOpcode()) {
100 case X86::MMX_MOVD64mr:
101 case X86::MMX_MOVQ64mr:
102 case X86::MMX_MOVNTQmr:
103 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
104 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
105 MI->getOperand(1).getImmedValue() == 1 &&
106 MI->getOperand(2).getReg() == 0 &&
107 MI->getOperand(3).getImmedValue() == 0) {
108 FrameIndex = MI->getOperand(0).getFrameIndex();
109 return MI->getOperand(4).getReg();
117 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
118 switch (MI->getOpcode()) {
131 case X86::MMX_MOVD64rm:
132 case X86::MMX_MOVQ64rm:
133 // Loads from constant pools are trivially rematerializable.
134 return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
135 MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
136 MI->getOperand(1).getReg() == 0 &&
137 MI->getOperand(2).getImmedValue() == 1 &&
138 MI->getOperand(3).getReg() == 0;
140 // All other instructions marked M_REMATERIALIZABLE are always trivially
145 /// convertToThreeAddress - This method must be implemented by targets that
146 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
147 /// may be able to convert a two-address instruction into a true
148 /// three-address instruction on demand. This allows the X86 target (for
149 /// example) to convert ADD and SHL instructions into LEA instructions if they
150 /// would require register copies due to two-addressness.
152 /// This method returns a null pointer if the transformation cannot be
153 /// performed, otherwise it returns the new instruction.
156 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
157 MachineBasicBlock::iterator &MBBI,
158 LiveVariables &LV) const {
159 MachineInstr *MI = MBBI;
160 // All instructions input are two-addr instructions. Get the known operands.
161 unsigned Dest = MI->getOperand(0).getReg();
162 unsigned Src = MI->getOperand(1).getReg();
164 MachineInstr *NewMI = NULL;
165 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
166 // we have better subtarget support, enable the 16-bit LEA generation here.
167 bool DisableLEA16 = true;
169 switch (MI->getOpcode()) {
171 case X86::SHUFPSrri: {
172 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
173 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
175 unsigned A = MI->getOperand(0).getReg();
176 unsigned B = MI->getOperand(1).getReg();
177 unsigned C = MI->getOperand(2).getReg();
178 unsigned M = MI->getOperand(3).getImm();
179 if (B != C) return 0;
180 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
184 assert(MI->getNumOperands() == 3 && "Unknown shift instruction!");
185 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
186 // the flags produced by a shift yet, so this is safe.
187 unsigned Dest = MI->getOperand(0).getReg();
188 unsigned Src = MI->getOperand(1).getReg();
189 unsigned ShAmt = MI->getOperand(2).getImm();
190 if (ShAmt == 0 || ShAmt >= 4) return 0;
192 NewMI = BuildMI(get(X86::LEA64r), Dest)
193 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
197 assert(MI->getNumOperands() == 3 && "Unknown shift instruction!");
198 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
199 // the flags produced by a shift yet, so this is safe.
200 unsigned Dest = MI->getOperand(0).getReg();
201 unsigned Src = MI->getOperand(1).getReg();
202 unsigned ShAmt = MI->getOperand(2).getImm();
203 if (ShAmt == 0 || ShAmt >= 4) return 0;
205 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
206 X86::LEA64_32r : X86::LEA32r;
207 NewMI = BuildMI(get(Opc), Dest)
208 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
212 assert(MI->getNumOperands() == 3 && "Unknown shift instruction!");
213 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
214 // the flags produced by a shift yet, so this is safe.
215 unsigned Dest = MI->getOperand(0).getReg();
216 unsigned Src = MI->getOperand(1).getReg();
217 unsigned ShAmt = MI->getOperand(2).getImm();
218 if (ShAmt == 0 || ShAmt >= 4) return 0;
221 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
222 SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
223 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
224 ? X86::LEA64_32r : X86::LEA32r;
225 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
226 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
229 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
230 Ins->copyKillDeadInfo(MI);
232 NewMI = BuildMI(get(Opc), leaOutReg)
233 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
236 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
237 Ext->copyKillDeadInfo(MI);
239 MFI->insert(MBBI, Ins); // Insert the insert_subreg
240 LV.instructionChanged(MI, NewMI); // Update live variables
241 LV.addVirtualRegisterKilled(leaInReg, NewMI);
242 MFI->insert(MBBI, NewMI); // Insert the new inst
243 LV.addVirtualRegisterKilled(leaOutReg, Ext);
244 MFI->insert(MBBI, Ext); // Insert the extract_subreg
247 NewMI = BuildMI(get(X86::LEA16r), Dest)
248 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
254 // FIXME: None of these instructions are promotable to LEAs without
255 // additional information. In particular, LEA doesn't set the flags that
256 // add and inc do. :(
258 switch (MI->getOpcode()) {
261 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
262 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1);
266 if (DisableLEA16) return 0;
267 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
268 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
272 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
273 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1);
277 if (DisableLEA16) return 0;
278 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
279 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
282 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
283 NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src,
284 MI->getOperand(2).getReg());
287 if (DisableLEA16) return 0;
288 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
289 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
290 MI->getOperand(2).getReg());
294 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
295 if (MI->getOperand(2).isImmediate())
296 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src,
297 MI->getOperand(2).getImmedValue());
301 if (DisableLEA16) return 0;
302 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
303 if (MI->getOperand(2).isImmediate())
304 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
305 MI->getOperand(2).getImmedValue());
308 if (DisableLEA16) return 0;
310 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
311 "Unknown shl instruction!");
312 unsigned ShAmt = MI->getOperand(2).getImmedValue();
313 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
315 AM.Scale = 1 << ShAmt;
317 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
318 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
324 NewMI->copyKillDeadInfo(MI);
325 LV.instructionChanged(MI, NewMI); // Update live variables
326 MFI->insert(MBBI, NewMI); // Insert the new inst
331 /// commuteInstruction - We have a few instructions that must be hacked on to
334 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
335 // FIXME: Can commute cmoves by changing the condition!
336 switch (MI->getOpcode()) {
337 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
338 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
339 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
340 case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
343 switch (MI->getOpcode()) {
344 default: assert(0 && "Unreachable!");
345 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
346 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
347 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
348 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
350 unsigned Amt = MI->getOperand(3).getImmedValue();
351 unsigned A = MI->getOperand(0).getReg();
352 unsigned B = MI->getOperand(1).getReg();
353 unsigned C = MI->getOperand(2).getReg();
354 bool BisKill = MI->getOperand(1).isKill();
355 bool CisKill = MI->getOperand(2).isKill();
356 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
357 .addReg(B, false, false, BisKill).addImm(Size-Amt);
360 return TargetInstrInfo::commuteInstruction(MI);
364 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
366 default: return X86::COND_INVALID;
367 case X86::JE: return X86::COND_E;
368 case X86::JNE: return X86::COND_NE;
369 case X86::JL: return X86::COND_L;
370 case X86::JLE: return X86::COND_LE;
371 case X86::JG: return X86::COND_G;
372 case X86::JGE: return X86::COND_GE;
373 case X86::JB: return X86::COND_B;
374 case X86::JBE: return X86::COND_BE;
375 case X86::JA: return X86::COND_A;
376 case X86::JAE: return X86::COND_AE;
377 case X86::JS: return X86::COND_S;
378 case X86::JNS: return X86::COND_NS;
379 case X86::JP: return X86::COND_P;
380 case X86::JNP: return X86::COND_NP;
381 case X86::JO: return X86::COND_O;
382 case X86::JNO: return X86::COND_NO;
386 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
388 default: assert(0 && "Illegal condition code!");
389 case X86::COND_E: return X86::JE;
390 case X86::COND_NE: return X86::JNE;
391 case X86::COND_L: return X86::JL;
392 case X86::COND_LE: return X86::JLE;
393 case X86::COND_G: return X86::JG;
394 case X86::COND_GE: return X86::JGE;
395 case X86::COND_B: return X86::JB;
396 case X86::COND_BE: return X86::JBE;
397 case X86::COND_A: return X86::JA;
398 case X86::COND_AE: return X86::JAE;
399 case X86::COND_S: return X86::JS;
400 case X86::COND_NS: return X86::JNS;
401 case X86::COND_P: return X86::JP;
402 case X86::COND_NP: return X86::JNP;
403 case X86::COND_O: return X86::JO;
404 case X86::COND_NO: return X86::JNO;
408 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
409 /// e.g. turning COND_E to COND_NE.
410 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
412 default: assert(0 && "Illegal condition code!");
413 case X86::COND_E: return X86::COND_NE;
414 case X86::COND_NE: return X86::COND_E;
415 case X86::COND_L: return X86::COND_GE;
416 case X86::COND_LE: return X86::COND_G;
417 case X86::COND_G: return X86::COND_LE;
418 case X86::COND_GE: return X86::COND_L;
419 case X86::COND_B: return X86::COND_AE;
420 case X86::COND_BE: return X86::COND_A;
421 case X86::COND_A: return X86::COND_BE;
422 case X86::COND_AE: return X86::COND_B;
423 case X86::COND_S: return X86::COND_NS;
424 case X86::COND_NS: return X86::COND_S;
425 case X86::COND_P: return X86::COND_NP;
426 case X86::COND_NP: return X86::COND_P;
427 case X86::COND_O: return X86::COND_NO;
428 case X86::COND_NO: return X86::COND_O;
432 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
433 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
434 if (TID->Flags & M_TERMINATOR_FLAG) {
435 // Conditional branch is a special case.
436 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
438 if ((TID->Flags & M_PREDICABLE) == 0)
440 return !isPredicated(MI);
445 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
446 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
447 const X86InstrInfo &TII) {
448 if (MI->getOpcode() == X86::FP_REG_KILL)
450 return TII.isUnpredicatedTerminator(MI);
453 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
454 MachineBasicBlock *&TBB,
455 MachineBasicBlock *&FBB,
456 std::vector<MachineOperand> &Cond) const {
457 // If the block has no terminators, it just falls into the block after it.
458 MachineBasicBlock::iterator I = MBB.end();
459 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
462 // Get the last instruction in the block.
463 MachineInstr *LastInst = I;
465 // If there is only one terminator instruction, process it.
466 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
467 if (!isBranch(LastInst->getOpcode()))
470 // If the block ends with a branch there are 3 possibilities:
471 // it's an unconditional, conditional, or indirect branch.
473 if (LastInst->getOpcode() == X86::JMP) {
474 TBB = LastInst->getOperand(0).getMachineBasicBlock();
477 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
478 if (BranchCode == X86::COND_INVALID)
479 return true; // Can't handle indirect branch.
481 // Otherwise, block ends with fall-through condbranch.
482 TBB = LastInst->getOperand(0).getMachineBasicBlock();
483 Cond.push_back(MachineOperand::CreateImm(BranchCode));
487 // Get the instruction before it if it's a terminator.
488 MachineInstr *SecondLastInst = I;
490 // If there are three terminators, we don't know what sort of block this is.
491 if (SecondLastInst && I != MBB.begin() &&
492 isBrAnalysisUnpredicatedTerminator(--I, *this))
495 // If the block ends with X86::JMP and a conditional branch, handle it.
496 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
497 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
498 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
499 Cond.push_back(MachineOperand::CreateImm(BranchCode));
500 FBB = LastInst->getOperand(0).getMachineBasicBlock();
504 // If the block ends with two X86::JMPs, handle it. The second one is not
505 // executed, so remove it.
506 if (SecondLastInst->getOpcode() == X86::JMP &&
507 LastInst->getOpcode() == X86::JMP) {
508 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
510 I->eraseFromParent();
514 // Otherwise, can't handle this.
518 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
519 MachineBasicBlock::iterator I = MBB.end();
520 if (I == MBB.begin()) return 0;
522 if (I->getOpcode() != X86::JMP &&
523 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
526 // Remove the branch.
527 I->eraseFromParent();
531 if (I == MBB.begin()) return 1;
533 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
536 // Remove the branch.
537 I->eraseFromParent();
542 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
543 MachineBasicBlock *FBB,
544 const std::vector<MachineOperand> &Cond) const {
545 // Shouldn't be a fall through.
546 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
547 assert((Cond.size() == 1 || Cond.size() == 0) &&
548 "X86 branch conditions have one component!");
550 if (FBB == 0) { // One way branch.
552 // Unconditional branch?
553 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
555 // Conditional branch.
556 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
557 BuildMI(&MBB, get(Opc)).addMBB(TBB);
562 // Two-way Conditional branch.
563 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
564 BuildMI(&MBB, get(Opc)).addMBB(TBB);
565 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
569 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
570 if (MBB.empty()) return false;
572 switch (MBB.back().getOpcode()) {
573 case X86::RET: // Return.
578 case X86::JMP: // Uncond branch.
579 case X86::JMP32r: // Indirect branch.
580 case X86::JMP32m: // Indirect branch through mem.
582 default: return false;
587 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
588 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
589 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
593 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
594 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
595 if (Subtarget->is64Bit())
596 return &X86::GR64RegClass;
598 return &X86::GR32RegClass;