1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/MC/MCAsmInfo.h"
41 NoFusing("disable-spill-fusing",
42 cl::desc("Disable fusing of spill code into instructions"));
44 PrintFailedFusing("print-failed-fuse-candidates",
45 cl::desc("Print instructions that the allocator wants to"
46 " fuse, but the X86 backend currently can't"),
49 ReMatPICStubLoad("remat-pic-stub-load",
50 cl::desc("Re-materialize load from stub in PIC mode"),
51 cl::init(false), cl::Hidden);
53 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
54 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
55 TM(tm), RI(tm, *this) {
56 SmallVector<unsigned,16> AmbEntries;
57 static const unsigned OpTbl2Addr[][2] = {
58 { X86::ADC32ri, X86::ADC32mi },
59 { X86::ADC32ri8, X86::ADC32mi8 },
60 { X86::ADC32rr, X86::ADC32mr },
61 { X86::ADC64ri32, X86::ADC64mi32 },
62 { X86::ADC64ri8, X86::ADC64mi8 },
63 { X86::ADC64rr, X86::ADC64mr },
64 { X86::ADD16ri, X86::ADD16mi },
65 { X86::ADD16ri8, X86::ADD16mi8 },
66 { X86::ADD16rr, X86::ADD16mr },
67 { X86::ADD32ri, X86::ADD32mi },
68 { X86::ADD32ri8, X86::ADD32mi8 },
69 { X86::ADD32rr, X86::ADD32mr },
70 { X86::ADD64ri32, X86::ADD64mi32 },
71 { X86::ADD64ri8, X86::ADD64mi8 },
72 { X86::ADD64rr, X86::ADD64mr },
73 { X86::ADD8ri, X86::ADD8mi },
74 { X86::ADD8rr, X86::ADD8mr },
75 { X86::AND16ri, X86::AND16mi },
76 { X86::AND16ri8, X86::AND16mi8 },
77 { X86::AND16rr, X86::AND16mr },
78 { X86::AND32ri, X86::AND32mi },
79 { X86::AND32ri8, X86::AND32mi8 },
80 { X86::AND32rr, X86::AND32mr },
81 { X86::AND64ri32, X86::AND64mi32 },
82 { X86::AND64ri8, X86::AND64mi8 },
83 { X86::AND64rr, X86::AND64mr },
84 { X86::AND8ri, X86::AND8mi },
85 { X86::AND8rr, X86::AND8mr },
86 { X86::DEC16r, X86::DEC16m },
87 { X86::DEC32r, X86::DEC32m },
88 { X86::DEC64_16r, X86::DEC64_16m },
89 { X86::DEC64_32r, X86::DEC64_32m },
90 { X86::DEC64r, X86::DEC64m },
91 { X86::DEC8r, X86::DEC8m },
92 { X86::INC16r, X86::INC16m },
93 { X86::INC32r, X86::INC32m },
94 { X86::INC64_16r, X86::INC64_16m },
95 { X86::INC64_32r, X86::INC64_32m },
96 { X86::INC64r, X86::INC64m },
97 { X86::INC8r, X86::INC8m },
98 { X86::NEG16r, X86::NEG16m },
99 { X86::NEG32r, X86::NEG32m },
100 { X86::NEG64r, X86::NEG64m },
101 { X86::NEG8r, X86::NEG8m },
102 { X86::NOT16r, X86::NOT16m },
103 { X86::NOT32r, X86::NOT32m },
104 { X86::NOT64r, X86::NOT64m },
105 { X86::NOT8r, X86::NOT8m },
106 { X86::OR16ri, X86::OR16mi },
107 { X86::OR16ri8, X86::OR16mi8 },
108 { X86::OR16rr, X86::OR16mr },
109 { X86::OR32ri, X86::OR32mi },
110 { X86::OR32ri8, X86::OR32mi8 },
111 { X86::OR32rr, X86::OR32mr },
112 { X86::OR64ri32, X86::OR64mi32 },
113 { X86::OR64ri8, X86::OR64mi8 },
114 { X86::OR64rr, X86::OR64mr },
115 { X86::OR8ri, X86::OR8mi },
116 { X86::OR8rr, X86::OR8mr },
117 { X86::ROL16r1, X86::ROL16m1 },
118 { X86::ROL16rCL, X86::ROL16mCL },
119 { X86::ROL16ri, X86::ROL16mi },
120 { X86::ROL32r1, X86::ROL32m1 },
121 { X86::ROL32rCL, X86::ROL32mCL },
122 { X86::ROL32ri, X86::ROL32mi },
123 { X86::ROL64r1, X86::ROL64m1 },
124 { X86::ROL64rCL, X86::ROL64mCL },
125 { X86::ROL64ri, X86::ROL64mi },
126 { X86::ROL8r1, X86::ROL8m1 },
127 { X86::ROL8rCL, X86::ROL8mCL },
128 { X86::ROL8ri, X86::ROL8mi },
129 { X86::ROR16r1, X86::ROR16m1 },
130 { X86::ROR16rCL, X86::ROR16mCL },
131 { X86::ROR16ri, X86::ROR16mi },
132 { X86::ROR32r1, X86::ROR32m1 },
133 { X86::ROR32rCL, X86::ROR32mCL },
134 { X86::ROR32ri, X86::ROR32mi },
135 { X86::ROR64r1, X86::ROR64m1 },
136 { X86::ROR64rCL, X86::ROR64mCL },
137 { X86::ROR64ri, X86::ROR64mi },
138 { X86::ROR8r1, X86::ROR8m1 },
139 { X86::ROR8rCL, X86::ROR8mCL },
140 { X86::ROR8ri, X86::ROR8mi },
141 { X86::SAR16r1, X86::SAR16m1 },
142 { X86::SAR16rCL, X86::SAR16mCL },
143 { X86::SAR16ri, X86::SAR16mi },
144 { X86::SAR32r1, X86::SAR32m1 },
145 { X86::SAR32rCL, X86::SAR32mCL },
146 { X86::SAR32ri, X86::SAR32mi },
147 { X86::SAR64r1, X86::SAR64m1 },
148 { X86::SAR64rCL, X86::SAR64mCL },
149 { X86::SAR64ri, X86::SAR64mi },
150 { X86::SAR8r1, X86::SAR8m1 },
151 { X86::SAR8rCL, X86::SAR8mCL },
152 { X86::SAR8ri, X86::SAR8mi },
153 { X86::SBB32ri, X86::SBB32mi },
154 { X86::SBB32ri8, X86::SBB32mi8 },
155 { X86::SBB32rr, X86::SBB32mr },
156 { X86::SBB64ri32, X86::SBB64mi32 },
157 { X86::SBB64ri8, X86::SBB64mi8 },
158 { X86::SBB64rr, X86::SBB64mr },
159 { X86::SHL16rCL, X86::SHL16mCL },
160 { X86::SHL16ri, X86::SHL16mi },
161 { X86::SHL32rCL, X86::SHL32mCL },
162 { X86::SHL32ri, X86::SHL32mi },
163 { X86::SHL64rCL, X86::SHL64mCL },
164 { X86::SHL64ri, X86::SHL64mi },
165 { X86::SHL8rCL, X86::SHL8mCL },
166 { X86::SHL8ri, X86::SHL8mi },
167 { X86::SHLD16rrCL, X86::SHLD16mrCL },
168 { X86::SHLD16rri8, X86::SHLD16mri8 },
169 { X86::SHLD32rrCL, X86::SHLD32mrCL },
170 { X86::SHLD32rri8, X86::SHLD32mri8 },
171 { X86::SHLD64rrCL, X86::SHLD64mrCL },
172 { X86::SHLD64rri8, X86::SHLD64mri8 },
173 { X86::SHR16r1, X86::SHR16m1 },
174 { X86::SHR16rCL, X86::SHR16mCL },
175 { X86::SHR16ri, X86::SHR16mi },
176 { X86::SHR32r1, X86::SHR32m1 },
177 { X86::SHR32rCL, X86::SHR32mCL },
178 { X86::SHR32ri, X86::SHR32mi },
179 { X86::SHR64r1, X86::SHR64m1 },
180 { X86::SHR64rCL, X86::SHR64mCL },
181 { X86::SHR64ri, X86::SHR64mi },
182 { X86::SHR8r1, X86::SHR8m1 },
183 { X86::SHR8rCL, X86::SHR8mCL },
184 { X86::SHR8ri, X86::SHR8mi },
185 { X86::SHRD16rrCL, X86::SHRD16mrCL },
186 { X86::SHRD16rri8, X86::SHRD16mri8 },
187 { X86::SHRD32rrCL, X86::SHRD32mrCL },
188 { X86::SHRD32rri8, X86::SHRD32mri8 },
189 { X86::SHRD64rrCL, X86::SHRD64mrCL },
190 { X86::SHRD64rri8, X86::SHRD64mri8 },
191 { X86::SUB16ri, X86::SUB16mi },
192 { X86::SUB16ri8, X86::SUB16mi8 },
193 { X86::SUB16rr, X86::SUB16mr },
194 { X86::SUB32ri, X86::SUB32mi },
195 { X86::SUB32ri8, X86::SUB32mi8 },
196 { X86::SUB32rr, X86::SUB32mr },
197 { X86::SUB64ri32, X86::SUB64mi32 },
198 { X86::SUB64ri8, X86::SUB64mi8 },
199 { X86::SUB64rr, X86::SUB64mr },
200 { X86::SUB8ri, X86::SUB8mi },
201 { X86::SUB8rr, X86::SUB8mr },
202 { X86::XOR16ri, X86::XOR16mi },
203 { X86::XOR16ri8, X86::XOR16mi8 },
204 { X86::XOR16rr, X86::XOR16mr },
205 { X86::XOR32ri, X86::XOR32mi },
206 { X86::XOR32ri8, X86::XOR32mi8 },
207 { X86::XOR32rr, X86::XOR32mr },
208 { X86::XOR64ri32, X86::XOR64mi32 },
209 { X86::XOR64ri8, X86::XOR64mi8 },
210 { X86::XOR64rr, X86::XOR64mr },
211 { X86::XOR8ri, X86::XOR8mi },
212 { X86::XOR8rr, X86::XOR8mr }
215 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
216 unsigned RegOp = OpTbl2Addr[i][0];
217 unsigned MemOp = OpTbl2Addr[i][1];
218 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
219 std::make_pair(MemOp,0))).second)
220 assert(false && "Duplicated entries?");
221 // Index 0, folded load and store, no alignment requirement.
222 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
223 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
224 std::make_pair(RegOp,
226 AmbEntries.push_back(MemOp);
229 // If the third value is 1, then it's folding either a load or a store.
230 static const unsigned OpTbl0[][4] = {
231 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
232 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
233 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
234 { X86::CALL32r, X86::CALL32m, 1, 0 },
235 { X86::CALL64r, X86::CALL64m, 1, 0 },
236 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
237 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
238 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
239 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
240 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
241 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
242 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
243 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
244 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
245 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
246 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
247 { X86::DIV16r, X86::DIV16m, 1, 0 },
248 { X86::DIV32r, X86::DIV32m, 1, 0 },
249 { X86::DIV64r, X86::DIV64m, 1, 0 },
250 { X86::DIV8r, X86::DIV8m, 1, 0 },
251 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
252 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
253 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
254 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
255 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
256 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
257 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
258 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
259 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
260 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
261 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
262 { X86::JMP32r, X86::JMP32m, 1, 0 },
263 { X86::JMP64r, X86::JMP64m, 1, 0 },
264 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
265 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
266 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
267 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
268 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
269 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
270 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
271 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
272 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
273 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
274 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
275 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
276 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
277 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
278 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 },
279 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 },
280 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
281 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
282 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 },
283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
285 { X86::MUL16r, X86::MUL16m, 1, 0 },
286 { X86::MUL32r, X86::MUL32m, 1, 0 },
287 { X86::MUL64r, X86::MUL64m, 1, 0 },
288 { X86::MUL8r, X86::MUL8m, 1, 0 },
289 { X86::SETAEr, X86::SETAEm, 0, 0 },
290 { X86::SETAr, X86::SETAm, 0, 0 },
291 { X86::SETBEr, X86::SETBEm, 0, 0 },
292 { X86::SETBr, X86::SETBm, 0, 0 },
293 { X86::SETEr, X86::SETEm, 0, 0 },
294 { X86::SETGEr, X86::SETGEm, 0, 0 },
295 { X86::SETGr, X86::SETGm, 0, 0 },
296 { X86::SETLEr, X86::SETLEm, 0, 0 },
297 { X86::SETLr, X86::SETLm, 0, 0 },
298 { X86::SETNEr, X86::SETNEm, 0, 0 },
299 { X86::SETNOr, X86::SETNOm, 0, 0 },
300 { X86::SETNPr, X86::SETNPm, 0, 0 },
301 { X86::SETNSr, X86::SETNSm, 0, 0 },
302 { X86::SETOr, X86::SETOm, 0, 0 },
303 { X86::SETPr, X86::SETPm, 0, 0 },
304 { X86::SETSr, X86::SETSm, 0, 0 },
305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
306 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
307 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
308 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
309 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
312 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
313 unsigned RegOp = OpTbl0[i][0];
314 unsigned MemOp = OpTbl0[i][1];
315 unsigned Align = OpTbl0[i][3];
316 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
317 std::make_pair(MemOp,Align))).second)
318 assert(false && "Duplicated entries?");
319 unsigned FoldedLoad = OpTbl0[i][2];
320 // Index 0, folded load or store.
321 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
322 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
323 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
324 std::make_pair(RegOp, AuxInfo))).second)
325 AmbEntries.push_back(MemOp);
328 static const unsigned OpTbl1[][3] = {
329 { X86::CMP16rr, X86::CMP16rm, 0 },
330 { X86::CMP32rr, X86::CMP32rm, 0 },
331 { X86::CMP64rr, X86::CMP64rm, 0 },
332 { X86::CMP8rr, X86::CMP8rm, 0 },
333 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
334 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
335 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
336 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
337 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
338 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
339 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
340 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
341 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
342 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
343 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
344 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
345 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
346 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
347 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
348 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
349 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
350 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
351 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
352 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
353 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
354 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
355 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
356 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
357 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
358 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
359 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
360 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
361 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
362 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
363 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
364 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
365 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
366 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
367 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
368 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
369 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
370 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
371 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
372 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
373 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
374 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
375 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
376 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
377 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
378 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
379 { X86::MOV16rr, X86::MOV16rm, 0 },
380 { X86::MOV32rr, X86::MOV32rm, 0 },
381 { X86::MOV64rr, X86::MOV64rm, 0 },
382 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
383 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
384 { X86::MOV8rr, X86::MOV8rm, 0 },
385 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
386 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
387 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
388 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
389 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
390 { X86::MOVDQArr, X86::MOVDQArm, 16 },
391 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 },
392 { X86::MOVSDrr, X86::MOVSDrm, 0 },
393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
395 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 },
396 { X86::MOVSSrr, X86::MOVSSrm, 0 },
397 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
398 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
399 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
400 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
401 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
402 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
403 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
404 { X86::MOVUPSrr, X86::MOVUPSrm, 16 },
405 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
406 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
407 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
408 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
409 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
410 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
411 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
412 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
413 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
414 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
415 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
416 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
417 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
418 { X86::RCPPSr, X86::RCPPSm, 16 },
419 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
420 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
421 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
422 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
423 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
424 { X86::SQRTPDr, X86::SQRTPDm, 16 },
425 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
426 { X86::SQRTPSr, X86::SQRTPSm, 16 },
427 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
428 { X86::SQRTSDr, X86::SQRTSDm, 0 },
429 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
430 { X86::SQRTSSr, X86::SQRTSSm, 0 },
431 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
432 { X86::TEST16rr, X86::TEST16rm, 0 },
433 { X86::TEST32rr, X86::TEST32rm, 0 },
434 { X86::TEST64rr, X86::TEST64rm, 0 },
435 { X86::TEST8rr, X86::TEST8rm, 0 },
436 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
437 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
438 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
441 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
442 unsigned RegOp = OpTbl1[i][0];
443 unsigned MemOp = OpTbl1[i][1];
444 unsigned Align = OpTbl1[i][2];
445 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
446 std::make_pair(MemOp,Align))).second)
447 assert(false && "Duplicated entries?");
448 // Index 1, folded load
449 unsigned AuxInfo = 1 | (1 << 4);
450 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
451 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
452 std::make_pair(RegOp, AuxInfo))).second)
453 AmbEntries.push_back(MemOp);
456 static const unsigned OpTbl2[][3] = {
457 { X86::ADC32rr, X86::ADC32rm, 0 },
458 { X86::ADC64rr, X86::ADC64rm, 0 },
459 { X86::ADD16rr, X86::ADD16rm, 0 },
460 { X86::ADD32rr, X86::ADD32rm, 0 },
461 { X86::ADD64rr, X86::ADD64rm, 0 },
462 { X86::ADD8rr, X86::ADD8rm, 0 },
463 { X86::ADDPDrr, X86::ADDPDrm, 16 },
464 { X86::ADDPSrr, X86::ADDPSrm, 16 },
465 { X86::ADDSDrr, X86::ADDSDrm, 0 },
466 { X86::ADDSSrr, X86::ADDSSrm, 0 },
467 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
468 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
469 { X86::AND16rr, X86::AND16rm, 0 },
470 { X86::AND32rr, X86::AND32rm, 0 },
471 { X86::AND64rr, X86::AND64rm, 0 },
472 { X86::AND8rr, X86::AND8rm, 0 },
473 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
474 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
475 { X86::ANDPDrr, X86::ANDPDrm, 16 },
476 { X86::ANDPSrr, X86::ANDPSrm, 16 },
477 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
478 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
479 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
480 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
481 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
482 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
483 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
484 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
485 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
486 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
487 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
488 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
489 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
490 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
491 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
492 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
493 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
494 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
495 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
496 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
497 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
498 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
499 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
500 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
501 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
502 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
503 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
504 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
505 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
506 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
507 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
508 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
509 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
510 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
511 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
512 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
513 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
514 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
515 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
516 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
517 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
518 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
519 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
520 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
521 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
522 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
523 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
524 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
525 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
526 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
527 { X86::CMPSDrr, X86::CMPSDrm, 0 },
528 { X86::CMPSSrr, X86::CMPSSrm, 0 },
529 { X86::DIVPDrr, X86::DIVPDrm, 16 },
530 { X86::DIVPSrr, X86::DIVPSrm, 16 },
531 { X86::DIVSDrr, X86::DIVSDrm, 0 },
532 { X86::DIVSSrr, X86::DIVSSrm, 0 },
533 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
534 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
535 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
536 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
537 { X86::FsORPDrr, X86::FsORPDrm, 16 },
538 { X86::FsORPSrr, X86::FsORPSrm, 16 },
539 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
540 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
541 { X86::HADDPDrr, X86::HADDPDrm, 16 },
542 { X86::HADDPSrr, X86::HADDPSrm, 16 },
543 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
544 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
545 { X86::IMUL16rr, X86::IMUL16rm, 0 },
546 { X86::IMUL32rr, X86::IMUL32rm, 0 },
547 { X86::IMUL64rr, X86::IMUL64rm, 0 },
548 { X86::MAXPDrr, X86::MAXPDrm, 16 },
549 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
550 { X86::MAXPSrr, X86::MAXPSrm, 16 },
551 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
552 { X86::MAXSDrr, X86::MAXSDrm, 0 },
553 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
554 { X86::MAXSSrr, X86::MAXSSrm, 0 },
555 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
556 { X86::MINPDrr, X86::MINPDrm, 16 },
557 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
558 { X86::MINPSrr, X86::MINPSrm, 16 },
559 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
560 { X86::MINSDrr, X86::MINSDrm, 0 },
561 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
562 { X86::MINSSrr, X86::MINSSrm, 0 },
563 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
564 { X86::MULPDrr, X86::MULPDrm, 16 },
565 { X86::MULPSrr, X86::MULPSrm, 16 },
566 { X86::MULSDrr, X86::MULSDrm, 0 },
567 { X86::MULSSrr, X86::MULSSrm, 0 },
568 { X86::OR16rr, X86::OR16rm, 0 },
569 { X86::OR32rr, X86::OR32rm, 0 },
570 { X86::OR64rr, X86::OR64rm, 0 },
571 { X86::OR8rr, X86::OR8rm, 0 },
572 { X86::ORPDrr, X86::ORPDrm, 16 },
573 { X86::ORPSrr, X86::ORPSrm, 16 },
574 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
575 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
576 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
577 { X86::PADDBrr, X86::PADDBrm, 16 },
578 { X86::PADDDrr, X86::PADDDrm, 16 },
579 { X86::PADDQrr, X86::PADDQrm, 16 },
580 { X86::PADDSBrr, X86::PADDSBrm, 16 },
581 { X86::PADDSWrr, X86::PADDSWrm, 16 },
582 { X86::PADDWrr, X86::PADDWrm, 16 },
583 { X86::PANDNrr, X86::PANDNrm, 16 },
584 { X86::PANDrr, X86::PANDrm, 16 },
585 { X86::PAVGBrr, X86::PAVGBrm, 16 },
586 { X86::PAVGWrr, X86::PAVGWrm, 16 },
587 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
588 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
589 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
590 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
591 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
592 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
593 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
594 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
595 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
596 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
597 { X86::PMINSWrr, X86::PMINSWrm, 16 },
598 { X86::PMINUBrr, X86::PMINUBrm, 16 },
599 { X86::PMULDQrr, X86::PMULDQrm, 16 },
600 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
601 { X86::PMULHWrr, X86::PMULHWrm, 16 },
602 { X86::PMULLDrr, X86::PMULLDrm, 16 },
603 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
604 { X86::PMULLWrr, X86::PMULLWrm, 16 },
605 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
606 { X86::PORrr, X86::PORrm, 16 },
607 { X86::PSADBWrr, X86::PSADBWrm, 16 },
608 { X86::PSLLDrr, X86::PSLLDrm, 16 },
609 { X86::PSLLQrr, X86::PSLLQrm, 16 },
610 { X86::PSLLWrr, X86::PSLLWrm, 16 },
611 { X86::PSRADrr, X86::PSRADrm, 16 },
612 { X86::PSRAWrr, X86::PSRAWrm, 16 },
613 { X86::PSRLDrr, X86::PSRLDrm, 16 },
614 { X86::PSRLQrr, X86::PSRLQrm, 16 },
615 { X86::PSRLWrr, X86::PSRLWrm, 16 },
616 { X86::PSUBBrr, X86::PSUBBrm, 16 },
617 { X86::PSUBDrr, X86::PSUBDrm, 16 },
618 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
619 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
620 { X86::PSUBWrr, X86::PSUBWrm, 16 },
621 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
622 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
623 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
624 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
625 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
626 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
627 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
628 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
629 { X86::PXORrr, X86::PXORrm, 16 },
630 { X86::SBB32rr, X86::SBB32rm, 0 },
631 { X86::SBB64rr, X86::SBB64rm, 0 },
632 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
633 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
634 { X86::SUB16rr, X86::SUB16rm, 0 },
635 { X86::SUB32rr, X86::SUB32rm, 0 },
636 { X86::SUB64rr, X86::SUB64rm, 0 },
637 { X86::SUB8rr, X86::SUB8rm, 0 },
638 { X86::SUBPDrr, X86::SUBPDrm, 16 },
639 { X86::SUBPSrr, X86::SUBPSrm, 16 },
640 { X86::SUBSDrr, X86::SUBSDrm, 0 },
641 { X86::SUBSSrr, X86::SUBSSrm, 0 },
642 // FIXME: TEST*rr -> swapped operand of TEST*mr.
643 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
644 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
645 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
646 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
647 { X86::XOR16rr, X86::XOR16rm, 0 },
648 { X86::XOR32rr, X86::XOR32rm, 0 },
649 { X86::XOR64rr, X86::XOR64rm, 0 },
650 { X86::XOR8rr, X86::XOR8rm, 0 },
651 { X86::XORPDrr, X86::XORPDrm, 16 },
652 { X86::XORPSrr, X86::XORPSrm, 16 }
655 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
656 unsigned RegOp = OpTbl2[i][0];
657 unsigned MemOp = OpTbl2[i][1];
658 unsigned Align = OpTbl2[i][2];
659 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
660 std::make_pair(MemOp,Align))).second)
661 assert(false && "Duplicated entries?");
662 // Index 2, folded load
663 unsigned AuxInfo = 2 | (1 << 4);
664 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
665 std::make_pair(RegOp, AuxInfo))).second)
666 AmbEntries.push_back(MemOp);
669 // Remove ambiguous entries.
670 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
673 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
674 unsigned &SrcReg, unsigned &DstReg,
675 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
676 switch (MI.getOpcode()) {
680 case X86::MOV8rr_NOREX:
687 // FP Stack register class copies
688 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
689 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
690 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
692 case X86::FsMOVAPSrr:
693 case X86::FsMOVAPDrr:
697 case X86::MOVSS2PSrr:
698 case X86::MOVSD2PDrr:
699 case X86::MOVPS2SSrr:
700 case X86::MOVPD2SDrr:
701 case X86::MMX_MOVQ64rr:
702 assert(MI.getNumOperands() >= 2 &&
703 MI.getOperand(0).isReg() &&
704 MI.getOperand(1).isReg() &&
705 "invalid register-register move instruction");
706 SrcReg = MI.getOperand(1).getReg();
707 DstReg = MI.getOperand(0).getReg();
708 SrcSubIdx = MI.getOperand(1).getSubReg();
709 DstSubIdx = MI.getOperand(0).getSubReg();
714 /// isFrameOperand - Return true and the FrameIndex if the specified
715 /// operand and follow operands form a reference to the stack frame.
716 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
717 int &FrameIndex) const {
718 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
719 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
720 MI->getOperand(Op+1).getImm() == 1 &&
721 MI->getOperand(Op+2).getReg() == 0 &&
722 MI->getOperand(Op+3).getImm() == 0) {
723 FrameIndex = MI->getOperand(Op).getIndex();
729 static bool isFrameLoadOpcode(int Opcode) {
742 case X86::MMX_MOVD64rm:
743 case X86::MMX_MOVQ64rm:
750 static bool isFrameStoreOpcode(int Opcode) {
763 case X86::MMX_MOVD64mr:
764 case X86::MMX_MOVQ64mr:
765 case X86::MMX_MOVNTQmr:
771 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
772 int &FrameIndex) const {
773 if (isFrameLoadOpcode(MI->getOpcode()))
774 if (isFrameOperand(MI, 1, FrameIndex))
775 return MI->getOperand(0).getReg();
779 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
780 int &FrameIndex) const {
781 if (isFrameLoadOpcode(MI->getOpcode())) {
783 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
785 // Check for post-frame index elimination operations
786 const MachineMemOperand *Dummy;
787 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
792 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
793 const MachineMemOperand *&MMO,
794 int &FrameIndex) const {
795 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
796 oe = MI->memoperands_end();
799 if ((*o)->isLoad() && (*o)->getValue())
800 if (const FixedStackPseudoSourceValue *Value =
801 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
802 FrameIndex = Value->getFrameIndex();
810 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
811 int &FrameIndex) const {
812 if (isFrameStoreOpcode(MI->getOpcode()))
813 if (isFrameOperand(MI, 0, FrameIndex))
814 return MI->getOperand(X86AddrNumOperands).getReg();
818 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
819 int &FrameIndex) const {
820 if (isFrameStoreOpcode(MI->getOpcode())) {
822 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
824 // Check for post-frame index elimination operations
825 const MachineMemOperand *Dummy;
826 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
831 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
832 const MachineMemOperand *&MMO,
833 int &FrameIndex) const {
834 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
835 oe = MI->memoperands_end();
838 if ((*o)->isStore() && (*o)->getValue())
839 if (const FixedStackPseudoSourceValue *Value =
840 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
841 FrameIndex = Value->getFrameIndex();
849 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
851 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
852 bool isPICBase = false;
853 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
854 E = MRI.def_end(); I != E; ++I) {
855 MachineInstr *DefMI = I.getOperand().getParent();
856 if (DefMI->getOpcode() != X86::MOVPC32r)
858 assert(!isPICBase && "More than one PIC base?");
865 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
866 AliasAnalysis *AA) const {
867 switch (MI->getOpcode()) {
878 case X86::MOVUPSrm_Int:
881 case X86::MMX_MOVD64rm:
882 case X86::MMX_MOVQ64rm:
883 case X86::FsMOVAPSrm:
884 case X86::FsMOVAPDrm: {
885 // Loads from constant pools are trivially rematerializable.
886 if (MI->getOperand(1).isReg() &&
887 MI->getOperand(2).isImm() &&
888 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
889 MI->isInvariantLoad(AA)) {
890 unsigned BaseReg = MI->getOperand(1).getReg();
891 if (BaseReg == 0 || BaseReg == X86::RIP)
893 // Allow re-materialization of PIC load.
894 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
896 const MachineFunction &MF = *MI->getParent()->getParent();
897 const MachineRegisterInfo &MRI = MF.getRegInfo();
898 bool isPICBase = false;
899 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
900 E = MRI.def_end(); I != E; ++I) {
901 MachineInstr *DefMI = I.getOperand().getParent();
902 if (DefMI->getOpcode() != X86::MOVPC32r)
904 assert(!isPICBase && "More than one PIC base?");
914 if (MI->getOperand(2).isImm() &&
915 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
916 !MI->getOperand(4).isReg()) {
917 // lea fi#, lea GV, etc. are all rematerializable.
918 if (!MI->getOperand(1).isReg())
920 unsigned BaseReg = MI->getOperand(1).getReg();
923 // Allow re-materialization of lea PICBase + x.
924 const MachineFunction &MF = *MI->getParent()->getParent();
925 const MachineRegisterInfo &MRI = MF.getRegInfo();
926 return regIsPICBase(BaseReg, MRI);
932 // All other instructions marked M_REMATERIALIZABLE are always trivially
937 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
938 /// would clobber the EFLAGS condition register. Note the result may be
939 /// conservative. If it cannot definitely determine the safety after visiting
940 /// a few instructions in each direction it assumes it's not safe.
941 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
942 MachineBasicBlock::iterator I) {
943 // It's always safe to clobber EFLAGS at the end of a block.
947 // For compile time consideration, if we are not able to determine the
948 // safety after visiting 4 instructions in each direction, we will assume
950 MachineBasicBlock::iterator Iter = I;
951 for (unsigned i = 0; i < 4; ++i) {
952 bool SeenDef = false;
953 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
954 MachineOperand &MO = Iter->getOperand(j);
957 if (MO.getReg() == X86::EFLAGS) {
965 // This instruction defines EFLAGS, no need to look any further.
969 // If we make it to the end of the block, it's safe to clobber EFLAGS.
970 if (Iter == MBB.end())
975 for (unsigned i = 0; i < 4; ++i) {
976 // If we make it to the beginning of the block, it's safe to clobber
977 // EFLAGS iff EFLAGS is not live-in.
978 if (Iter == MBB.begin())
979 return !MBB.isLiveIn(X86::EFLAGS);
982 bool SawKill = false;
983 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
984 MachineOperand &MO = Iter->getOperand(j);
985 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
986 if (MO.isDef()) return MO.isDead();
987 if (MO.isKill()) SawKill = true;
992 // This instruction kills EFLAGS and doesn't redefine it, so
993 // there's no need to look further.
997 // Conservative answer.
1001 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1002 MachineBasicBlock::iterator I,
1003 unsigned DestReg, unsigned SubIdx,
1004 const MachineInstr *Orig,
1005 const TargetRegisterInfo *TRI) const {
1006 DebugLoc DL = DebugLoc::getUnknownLoc();
1007 if (I != MBB.end()) DL = I->getDebugLoc();
1009 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1010 DestReg = TRI->getSubReg(DestReg, SubIdx);
1014 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1015 // Re-materialize them as movri instructions to avoid side effects.
1017 unsigned Opc = Orig->getOpcode();
1022 case X86::MOV32r0: {
1023 if (!isSafeToClobberEFLAGS(MBB, I)) {
1026 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1027 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1028 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1037 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1038 MI->getOperand(0).setReg(DestReg);
1041 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1044 MachineInstr *NewMI = prior(I);
1045 NewMI->getOperand(0).setSubReg(SubIdx);
1048 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1049 /// is not marked dead.
1050 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1051 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1052 MachineOperand &MO = MI->getOperand(i);
1053 if (MO.isReg() && MO.isDef() &&
1054 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1061 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1062 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1063 /// to a 32-bit superregister and then truncating back down to a 16-bit
1066 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1067 MachineFunction::iterator &MFI,
1068 MachineBasicBlock::iterator &MBBI,
1069 LiveVariables *LV) const {
1070 MachineInstr *MI = MBBI;
1071 unsigned Dest = MI->getOperand(0).getReg();
1072 unsigned Src = MI->getOperand(1).getReg();
1073 bool isDead = MI->getOperand(0).isDead();
1074 bool isKill = MI->getOperand(1).isKill();
1076 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1077 ? X86::LEA64_32r : X86::LEA32r;
1078 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1079 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1080 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1082 // Build and insert into an implicit UNDEF value. This is OK because
1083 // well be shifting and then extracting the lower 16-bits.
1084 // This has the potential to cause partial register stall. e.g.
1085 // movw (%rbp,%rcx,2), %dx
1086 // leal -65(%rdx), %esi
1087 // But testing has shown this *does* help performance in 64-bit mode (at
1088 // least on modern x86 machines).
1089 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1090 MachineInstr *InsMI =
1091 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1093 .addReg(Src, getKillRegState(isKill))
1094 .addImm(X86::SUBREG_16BIT);
1096 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1097 get(Opc), leaOutReg);
1100 llvm_unreachable(0);
1102 case X86::SHL16ri: {
1103 unsigned ShAmt = MI->getOperand(2).getImm();
1104 MIB.addReg(0).addImm(1 << ShAmt)
1105 .addReg(leaInReg, RegState::Kill).addImm(0);
1109 case X86::INC64_16r:
1110 addLeaRegOffset(MIB, leaInReg, true, 1);
1113 case X86::DEC64_16r:
1114 addLeaRegOffset(MIB, leaInReg, true, -1);
1118 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1120 case X86::ADD16rr: {
1121 unsigned Src2 = MI->getOperand(2).getReg();
1122 bool isKill2 = MI->getOperand(2).isKill();
1123 unsigned leaInReg2 = 0;
1124 MachineInstr *InsMI2 = 0;
1126 // ADD16rr %reg1028<kill>, %reg1028
1127 // just a single insert_subreg.
1128 addRegReg(MIB, leaInReg, true, leaInReg, false);
1130 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1131 // Build and insert into an implicit UNDEF value. This is OK because
1132 // well be shifting and then extracting the lower 16-bits.
1133 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1135 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1137 .addReg(Src2, getKillRegState(isKill2))
1138 .addImm(X86::SUBREG_16BIT);
1139 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1141 if (LV && isKill2 && InsMI2)
1142 LV->replaceKillInstruction(Src2, MI, InsMI2);
1147 MachineInstr *NewMI = MIB;
1148 MachineInstr *ExtMI =
1149 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1150 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1151 .addReg(leaOutReg, RegState::Kill)
1152 .addImm(X86::SUBREG_16BIT);
1155 // Update live variables
1156 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1157 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1159 LV->replaceKillInstruction(Src, MI, InsMI);
1161 LV->replaceKillInstruction(Dest, MI, ExtMI);
1167 /// convertToThreeAddress - This method must be implemented by targets that
1168 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1169 /// may be able to convert a two-address instruction into a true
1170 /// three-address instruction on demand. This allows the X86 target (for
1171 /// example) to convert ADD and SHL instructions into LEA instructions if they
1172 /// would require register copies due to two-addressness.
1174 /// This method returns a null pointer if the transformation cannot be
1175 /// performed, otherwise it returns the new instruction.
1178 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1179 MachineBasicBlock::iterator &MBBI,
1180 LiveVariables *LV) const {
1181 MachineInstr *MI = MBBI;
1182 MachineFunction &MF = *MI->getParent()->getParent();
1183 // All instructions input are two-addr instructions. Get the known operands.
1184 unsigned Dest = MI->getOperand(0).getReg();
1185 unsigned Src = MI->getOperand(1).getReg();
1186 bool isDead = MI->getOperand(0).isDead();
1187 bool isKill = MI->getOperand(1).isKill();
1189 MachineInstr *NewMI = NULL;
1190 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1191 // we have better subtarget support, enable the 16-bit LEA generation here.
1192 // 16-bit LEA is also slow on Core2.
1193 bool DisableLEA16 = true;
1194 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1196 unsigned MIOpc = MI->getOpcode();
1198 case X86::SHUFPSrri: {
1199 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1200 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1202 unsigned B = MI->getOperand(1).getReg();
1203 unsigned C = MI->getOperand(2).getReg();
1204 if (B != C) return 0;
1205 unsigned A = MI->getOperand(0).getReg();
1206 unsigned M = MI->getOperand(3).getImm();
1207 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1208 .addReg(A, RegState::Define | getDeadRegState(isDead))
1209 .addReg(B, getKillRegState(isKill)).addImm(M);
1212 case X86::SHL64ri: {
1213 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1214 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1215 // the flags produced by a shift yet, so this is safe.
1216 unsigned ShAmt = MI->getOperand(2).getImm();
1217 if (ShAmt == 0 || ShAmt >= 4) return 0;
1219 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1220 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1221 .addReg(0).addImm(1 << ShAmt)
1222 .addReg(Src, getKillRegState(isKill))
1226 case X86::SHL32ri: {
1227 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1228 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1229 // the flags produced by a shift yet, so this is safe.
1230 unsigned ShAmt = MI->getOperand(2).getImm();
1231 if (ShAmt == 0 || ShAmt >= 4) return 0;
1233 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1234 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1235 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1236 .addReg(0).addImm(1 << ShAmt)
1237 .addReg(Src, getKillRegState(isKill)).addImm(0);
1240 case X86::SHL16ri: {
1241 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1242 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1243 // the flags produced by a shift yet, so this is safe.
1244 unsigned ShAmt = MI->getOperand(2).getImm();
1245 if (ShAmt == 0 || ShAmt >= 4) return 0;
1248 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1249 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1250 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1251 .addReg(0).addImm(1 << ShAmt)
1252 .addReg(Src, getKillRegState(isKill))
1257 // The following opcodes also sets the condition code register(s). Only
1258 // convert them to equivalent lea if the condition code register def's
1260 if (hasLiveCondCodeDef(MI))
1267 case X86::INC64_32r: {
1268 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1269 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1270 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1271 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1272 .addReg(Dest, RegState::Define |
1273 getDeadRegState(isDead)),
1278 case X86::INC64_16r:
1280 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1281 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1282 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1283 .addReg(Dest, RegState::Define |
1284 getDeadRegState(isDead)),
1289 case X86::DEC64_32r: {
1290 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1291 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1292 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1293 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1294 .addReg(Dest, RegState::Define |
1295 getDeadRegState(isDead)),
1300 case X86::DEC64_16r:
1302 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1303 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1304 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1305 .addReg(Dest, RegState::Define |
1306 getDeadRegState(isDead)),
1310 case X86::ADD32rr: {
1311 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1312 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1313 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1314 unsigned Src2 = MI->getOperand(2).getReg();
1315 bool isKill2 = MI->getOperand(2).isKill();
1316 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1317 .addReg(Dest, RegState::Define |
1318 getDeadRegState(isDead)),
1319 Src, isKill, Src2, isKill2);
1321 LV->replaceKillInstruction(Src2, MI, NewMI);
1324 case X86::ADD16rr: {
1326 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1327 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1328 unsigned Src2 = MI->getOperand(2).getReg();
1329 bool isKill2 = MI->getOperand(2).isKill();
1330 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1331 .addReg(Dest, RegState::Define |
1332 getDeadRegState(isDead)),
1333 Src, isKill, Src2, isKill2);
1335 LV->replaceKillInstruction(Src2, MI, NewMI);
1338 case X86::ADD64ri32:
1340 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1341 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1342 .addReg(Dest, RegState::Define |
1343 getDeadRegState(isDead)),
1344 Src, isKill, MI->getOperand(2).getImm());
1347 case X86::ADD32ri8: {
1348 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1349 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1350 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1351 .addReg(Dest, RegState::Define |
1352 getDeadRegState(isDead)),
1353 Src, isKill, MI->getOperand(2).getImm());
1359 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1360 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1361 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1362 .addReg(Dest, RegState::Define |
1363 getDeadRegState(isDead)),
1364 Src, isKill, MI->getOperand(2).getImm());
1370 if (!NewMI) return 0;
1372 if (LV) { // Update live variables
1374 LV->replaceKillInstruction(Src, MI, NewMI);
1376 LV->replaceKillInstruction(Dest, MI, NewMI);
1379 MFI->insert(MBBI, NewMI); // Insert the new inst
1383 /// commuteInstruction - We have a few instructions that must be hacked on to
1387 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1388 switch (MI->getOpcode()) {
1389 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1390 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1391 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1392 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1393 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1394 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1397 switch (MI->getOpcode()) {
1398 default: llvm_unreachable("Unreachable!");
1399 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1400 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1401 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1402 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1403 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1404 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1406 unsigned Amt = MI->getOperand(3).getImm();
1408 MachineFunction &MF = *MI->getParent()->getParent();
1409 MI = MF.CloneMachineInstr(MI);
1412 MI->setDesc(get(Opc));
1413 MI->getOperand(3).setImm(Size-Amt);
1414 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1416 case X86::CMOVB16rr:
1417 case X86::CMOVB32rr:
1418 case X86::CMOVB64rr:
1419 case X86::CMOVAE16rr:
1420 case X86::CMOVAE32rr:
1421 case X86::CMOVAE64rr:
1422 case X86::CMOVE16rr:
1423 case X86::CMOVE32rr:
1424 case X86::CMOVE64rr:
1425 case X86::CMOVNE16rr:
1426 case X86::CMOVNE32rr:
1427 case X86::CMOVNE64rr:
1428 case X86::CMOVBE16rr:
1429 case X86::CMOVBE32rr:
1430 case X86::CMOVBE64rr:
1431 case X86::CMOVA16rr:
1432 case X86::CMOVA32rr:
1433 case X86::CMOVA64rr:
1434 case X86::CMOVL16rr:
1435 case X86::CMOVL32rr:
1436 case X86::CMOVL64rr:
1437 case X86::CMOVGE16rr:
1438 case X86::CMOVGE32rr:
1439 case X86::CMOVGE64rr:
1440 case X86::CMOVLE16rr:
1441 case X86::CMOVLE32rr:
1442 case X86::CMOVLE64rr:
1443 case X86::CMOVG16rr:
1444 case X86::CMOVG32rr:
1445 case X86::CMOVG64rr:
1446 case X86::CMOVS16rr:
1447 case X86::CMOVS32rr:
1448 case X86::CMOVS64rr:
1449 case X86::CMOVNS16rr:
1450 case X86::CMOVNS32rr:
1451 case X86::CMOVNS64rr:
1452 case X86::CMOVP16rr:
1453 case X86::CMOVP32rr:
1454 case X86::CMOVP64rr:
1455 case X86::CMOVNP16rr:
1456 case X86::CMOVNP32rr:
1457 case X86::CMOVNP64rr:
1458 case X86::CMOVO16rr:
1459 case X86::CMOVO32rr:
1460 case X86::CMOVO64rr:
1461 case X86::CMOVNO16rr:
1462 case X86::CMOVNO32rr:
1463 case X86::CMOVNO64rr: {
1465 switch (MI->getOpcode()) {
1467 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1468 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1469 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1470 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1471 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1472 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1473 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1474 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1475 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1476 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1477 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1478 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1479 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1480 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1481 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1482 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1483 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1484 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1485 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1486 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1487 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1488 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1489 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1490 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1491 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1492 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1493 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1494 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1495 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1496 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1497 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1498 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1499 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1500 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1501 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1502 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1503 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1504 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1505 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1506 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1507 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1508 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1509 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1510 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1511 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1512 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1513 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1514 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1517 MachineFunction &MF = *MI->getParent()->getParent();
1518 MI = MF.CloneMachineInstr(MI);
1521 MI->setDesc(get(Opc));
1522 // Fallthrough intended.
1525 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1529 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1531 default: return X86::COND_INVALID;
1532 case X86::JE: return X86::COND_E;
1533 case X86::JNE: return X86::COND_NE;
1534 case X86::JL: return X86::COND_L;
1535 case X86::JLE: return X86::COND_LE;
1536 case X86::JG: return X86::COND_G;
1537 case X86::JGE: return X86::COND_GE;
1538 case X86::JB: return X86::COND_B;
1539 case X86::JBE: return X86::COND_BE;
1540 case X86::JA: return X86::COND_A;
1541 case X86::JAE: return X86::COND_AE;
1542 case X86::JS: return X86::COND_S;
1543 case X86::JNS: return X86::COND_NS;
1544 case X86::JP: return X86::COND_P;
1545 case X86::JNP: return X86::COND_NP;
1546 case X86::JO: return X86::COND_O;
1547 case X86::JNO: return X86::COND_NO;
1551 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1553 default: llvm_unreachable("Illegal condition code!");
1554 case X86::COND_E: return X86::JE;
1555 case X86::COND_NE: return X86::JNE;
1556 case X86::COND_L: return X86::JL;
1557 case X86::COND_LE: return X86::JLE;
1558 case X86::COND_G: return X86::JG;
1559 case X86::COND_GE: return X86::JGE;
1560 case X86::COND_B: return X86::JB;
1561 case X86::COND_BE: return X86::JBE;
1562 case X86::COND_A: return X86::JA;
1563 case X86::COND_AE: return X86::JAE;
1564 case X86::COND_S: return X86::JS;
1565 case X86::COND_NS: return X86::JNS;
1566 case X86::COND_P: return X86::JP;
1567 case X86::COND_NP: return X86::JNP;
1568 case X86::COND_O: return X86::JO;
1569 case X86::COND_NO: return X86::JNO;
1573 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1574 /// e.g. turning COND_E to COND_NE.
1575 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1577 default: llvm_unreachable("Illegal condition code!");
1578 case X86::COND_E: return X86::COND_NE;
1579 case X86::COND_NE: return X86::COND_E;
1580 case X86::COND_L: return X86::COND_GE;
1581 case X86::COND_LE: return X86::COND_G;
1582 case X86::COND_G: return X86::COND_LE;
1583 case X86::COND_GE: return X86::COND_L;
1584 case X86::COND_B: return X86::COND_AE;
1585 case X86::COND_BE: return X86::COND_A;
1586 case X86::COND_A: return X86::COND_BE;
1587 case X86::COND_AE: return X86::COND_B;
1588 case X86::COND_S: return X86::COND_NS;
1589 case X86::COND_NS: return X86::COND_S;
1590 case X86::COND_P: return X86::COND_NP;
1591 case X86::COND_NP: return X86::COND_P;
1592 case X86::COND_O: return X86::COND_NO;
1593 case X86::COND_NO: return X86::COND_O;
1597 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1598 const TargetInstrDesc &TID = MI->getDesc();
1599 if (!TID.isTerminator()) return false;
1601 // Conditional branch is a special case.
1602 if (TID.isBranch() && !TID.isBarrier())
1604 if (!TID.isPredicable())
1606 return !isPredicated(MI);
1609 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1610 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1611 const X86InstrInfo &TII) {
1612 if (MI->getOpcode() == X86::FP_REG_KILL)
1614 return TII.isUnpredicatedTerminator(MI);
1617 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1618 MachineBasicBlock *&TBB,
1619 MachineBasicBlock *&FBB,
1620 SmallVectorImpl<MachineOperand> &Cond,
1621 bool AllowModify) const {
1622 // Start from the bottom of the block and work up, examining the
1623 // terminator instructions.
1624 MachineBasicBlock::iterator I = MBB.end();
1625 while (I != MBB.begin()) {
1628 // Working from the bottom, when we see a non-terminator instruction, we're
1630 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1633 // A terminator that isn't a branch can't easily be handled by this
1635 if (!I->getDesc().isBranch())
1638 // Handle unconditional branches.
1639 if (I->getOpcode() == X86::JMP) {
1641 TBB = I->getOperand(0).getMBB();
1645 // If the block has any instructions after a JMP, delete them.
1646 while (llvm::next(I) != MBB.end())
1647 llvm::next(I)->eraseFromParent();
1652 // Delete the JMP if it's equivalent to a fall-through.
1653 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1655 I->eraseFromParent();
1660 // TBB is used to indicate the unconditinal destination.
1661 TBB = I->getOperand(0).getMBB();
1665 // Handle conditional branches.
1666 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1667 if (BranchCode == X86::COND_INVALID)
1668 return true; // Can't handle indirect branch.
1670 // Working from the bottom, handle the first conditional branch.
1673 TBB = I->getOperand(0).getMBB();
1674 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1678 // Handle subsequent conditional branches. Only handle the case where all
1679 // conditional branches branch to the same destination and their condition
1680 // opcodes fit one of the special multi-branch idioms.
1681 assert(Cond.size() == 1);
1684 // Only handle the case where all conditional branches branch to the same
1686 if (TBB != I->getOperand(0).getMBB())
1689 // If the conditions are the same, we can leave them alone.
1690 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1691 if (OldBranchCode == BranchCode)
1694 // If they differ, see if they fit one of the known patterns. Theoretically,
1695 // we could handle more patterns here, but we shouldn't expect to see them
1696 // if instruction selection has done a reasonable job.
1697 if ((OldBranchCode == X86::COND_NP &&
1698 BranchCode == X86::COND_E) ||
1699 (OldBranchCode == X86::COND_E &&
1700 BranchCode == X86::COND_NP))
1701 BranchCode = X86::COND_NP_OR_E;
1702 else if ((OldBranchCode == X86::COND_P &&
1703 BranchCode == X86::COND_NE) ||
1704 (OldBranchCode == X86::COND_NE &&
1705 BranchCode == X86::COND_P))
1706 BranchCode = X86::COND_NE_OR_P;
1710 // Update the MachineOperand.
1711 Cond[0].setImm(BranchCode);
1717 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1718 MachineBasicBlock::iterator I = MBB.end();
1721 while (I != MBB.begin()) {
1723 if (I->getOpcode() != X86::JMP &&
1724 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1726 // Remove the branch.
1727 I->eraseFromParent();
1736 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1737 MachineBasicBlock *FBB,
1738 const SmallVectorImpl<MachineOperand> &Cond) const {
1739 // FIXME this should probably have a DebugLoc operand
1740 DebugLoc dl = DebugLoc::getUnknownLoc();
1741 // Shouldn't be a fall through.
1742 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1743 assert((Cond.size() == 1 || Cond.size() == 0) &&
1744 "X86 branch conditions have one component!");
1747 // Unconditional branch?
1748 assert(!FBB && "Unconditional branch with multiple successors!");
1749 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1753 // Conditional branch.
1755 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1757 case X86::COND_NP_OR_E:
1758 // Synthesize NP_OR_E with two branches.
1759 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1761 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1764 case X86::COND_NE_OR_P:
1765 // Synthesize NE_OR_P with two branches.
1766 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1768 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1772 unsigned Opc = GetCondBranchFromCond(CC);
1773 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1778 // Two-way Conditional branch. Insert the second branch.
1779 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1785 /// isHReg - Test if the given register is a physical h register.
1786 static bool isHReg(unsigned Reg) {
1787 return X86::GR8_ABCD_HRegClass.contains(Reg);
1790 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1791 MachineBasicBlock::iterator MI,
1792 unsigned DestReg, unsigned SrcReg,
1793 const TargetRegisterClass *DestRC,
1794 const TargetRegisterClass *SrcRC) const {
1795 DebugLoc DL = DebugLoc::getUnknownLoc();
1796 if (MI != MBB.end()) DL = MI->getDebugLoc();
1798 // Determine if DstRC and SrcRC have a common superclass in common.
1799 const TargetRegisterClass *CommonRC = DestRC;
1800 if (DestRC == SrcRC)
1801 /* Source and destination have the same register class. */;
1802 else if (CommonRC->hasSuperClass(SrcRC))
1804 else if (!DestRC->hasSubClass(SrcRC)) {
1805 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1806 // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1807 // GR32_NOSP, copy as GR32.
1808 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1809 DestRC->hasSuperClass(&X86::GR64RegClass))
1810 CommonRC = &X86::GR64RegClass;
1811 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1812 DestRC->hasSuperClass(&X86::GR32RegClass))
1813 CommonRC = &X86::GR32RegClass;
1820 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1822 } else if (CommonRC == &X86::GR32RegClass ||
1823 CommonRC == &X86::GR32_NOSPRegClass) {
1825 } else if (CommonRC == &X86::GR16RegClass) {
1827 } else if (CommonRC == &X86::GR8RegClass) {
1828 // Copying to or from a physical H register on x86-64 requires a NOREX
1829 // move. Otherwise use a normal move.
1830 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1831 TM.getSubtarget<X86Subtarget>().is64Bit())
1832 Opc = X86::MOV8rr_NOREX;
1835 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1837 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1839 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1841 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1843 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1844 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1845 Opc = X86::MOV8rr_NOREX;
1848 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1849 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1851 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1853 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1855 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1857 } else if (CommonRC == &X86::RFP32RegClass) {
1858 Opc = X86::MOV_Fp3232;
1859 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1860 Opc = X86::MOV_Fp6464;
1861 } else if (CommonRC == &X86::RFP80RegClass) {
1862 Opc = X86::MOV_Fp8080;
1863 } else if (CommonRC == &X86::FR32RegClass) {
1864 Opc = X86::FsMOVAPSrr;
1865 } else if (CommonRC == &X86::FR64RegClass) {
1866 Opc = X86::FsMOVAPDrr;
1867 } else if (CommonRC == &X86::VR128RegClass) {
1868 Opc = X86::MOVAPSrr;
1869 } else if (CommonRC == &X86::VR64RegClass) {
1870 Opc = X86::MMX_MOVQ64rr;
1874 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1878 // Moving EFLAGS to / from another register requires a push and a pop.
1879 if (SrcRC == &X86::CCRRegClass) {
1880 if (SrcReg != X86::EFLAGS)
1882 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1883 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
1884 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1886 } else if (DestRC == &X86::GR32RegClass ||
1887 DestRC == &X86::GR32_NOSPRegClass) {
1888 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1889 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1892 } else if (DestRC == &X86::CCRRegClass) {
1893 if (DestReg != X86::EFLAGS)
1895 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1896 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1897 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1899 } else if (SrcRC == &X86::GR32RegClass ||
1900 DestRC == &X86::GR32_NOSPRegClass) {
1901 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1902 BuildMI(MBB, MI, DL, get(X86::POPFD));
1907 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1908 if (SrcRC == &X86::RSTRegClass) {
1909 // Copying from ST(0)/ST(1).
1910 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1911 // Can only copy from ST(0)/ST(1) right now
1913 bool isST0 = SrcReg == X86::ST0;
1915 if (DestRC == &X86::RFP32RegClass)
1916 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1917 else if (DestRC == &X86::RFP64RegClass)
1918 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1920 if (DestRC != &X86::RFP80RegClass)
1922 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1924 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1928 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1929 if (DestRC == &X86::RSTRegClass) {
1930 // Copying to ST(0) / ST(1).
1931 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1932 // Can only copy to TOS right now
1934 bool isST0 = DestReg == X86::ST0;
1936 if (SrcRC == &X86::RFP32RegClass)
1937 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1938 else if (SrcRC == &X86::RFP64RegClass)
1939 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1941 if (SrcRC != &X86::RFP80RegClass)
1943 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1945 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1949 // Not yet supported!
1953 static unsigned getStoreRegOpcode(unsigned SrcReg,
1954 const TargetRegisterClass *RC,
1955 bool isStackAligned,
1956 TargetMachine &TM) {
1958 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1960 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1962 } else if (RC == &X86::GR16RegClass) {
1964 } else if (RC == &X86::GR8RegClass) {
1965 // Copying to or from a physical H register on x86-64 requires a NOREX
1966 // move. Otherwise use a normal move.
1967 if (isHReg(SrcReg) &&
1968 TM.getSubtarget<X86Subtarget>().is64Bit())
1969 Opc = X86::MOV8mr_NOREX;
1972 } else if (RC == &X86::GR64_ABCDRegClass) {
1974 } else if (RC == &X86::GR32_ABCDRegClass) {
1976 } else if (RC == &X86::GR16_ABCDRegClass) {
1978 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1980 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1981 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1982 Opc = X86::MOV8mr_NOREX;
1985 } else if (RC == &X86::GR64_NOREXRegClass ||
1986 RC == &X86::GR64_NOREX_NOSPRegClass) {
1988 } else if (RC == &X86::GR32_NOREXRegClass) {
1990 } else if (RC == &X86::GR16_NOREXRegClass) {
1992 } else if (RC == &X86::GR8_NOREXRegClass) {
1994 } else if (RC == &X86::RFP80RegClass) {
1995 Opc = X86::ST_FpP80m; // pops
1996 } else if (RC == &X86::RFP64RegClass) {
1997 Opc = X86::ST_Fp64m;
1998 } else if (RC == &X86::RFP32RegClass) {
1999 Opc = X86::ST_Fp32m;
2000 } else if (RC == &X86::FR32RegClass) {
2002 } else if (RC == &X86::FR64RegClass) {
2004 } else if (RC == &X86::VR128RegClass) {
2005 // If stack is realigned we can use aligned stores.
2006 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
2007 } else if (RC == &X86::VR64RegClass) {
2008 Opc = X86::MMX_MOVQ64mr;
2010 llvm_unreachable("Unknown regclass");
2016 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2017 MachineBasicBlock::iterator MI,
2018 unsigned SrcReg, bool isKill, int FrameIdx,
2019 const TargetRegisterClass *RC) const {
2020 const MachineFunction &MF = *MBB.getParent();
2021 bool isAligned = (RI.getStackAlignment() >= 16) ||
2022 RI.needsStackRealignment(MF);
2023 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2024 DebugLoc DL = DebugLoc::getUnknownLoc();
2025 if (MI != MBB.end()) DL = MI->getDebugLoc();
2026 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2027 .addReg(SrcReg, getKillRegState(isKill));
2030 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2032 SmallVectorImpl<MachineOperand> &Addr,
2033 const TargetRegisterClass *RC,
2034 MachineInstr::mmo_iterator MMOBegin,
2035 MachineInstr::mmo_iterator MMOEnd,
2036 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2037 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2038 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2039 DebugLoc DL = DebugLoc::getUnknownLoc();
2040 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2041 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2042 MIB.addOperand(Addr[i]);
2043 MIB.addReg(SrcReg, getKillRegState(isKill));
2044 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2045 NewMIs.push_back(MIB);
2048 static unsigned getLoadRegOpcode(unsigned DestReg,
2049 const TargetRegisterClass *RC,
2050 bool isStackAligned,
2051 const TargetMachine &TM) {
2053 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2055 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2057 } else if (RC == &X86::GR16RegClass) {
2059 } else if (RC == &X86::GR8RegClass) {
2060 // Copying to or from a physical H register on x86-64 requires a NOREX
2061 // move. Otherwise use a normal move.
2062 if (isHReg(DestReg) &&
2063 TM.getSubtarget<X86Subtarget>().is64Bit())
2064 Opc = X86::MOV8rm_NOREX;
2067 } else if (RC == &X86::GR64_ABCDRegClass) {
2069 } else if (RC == &X86::GR32_ABCDRegClass) {
2071 } else if (RC == &X86::GR16_ABCDRegClass) {
2073 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2075 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2076 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2077 Opc = X86::MOV8rm_NOREX;
2080 } else if (RC == &X86::GR64_NOREXRegClass ||
2081 RC == &X86::GR64_NOREX_NOSPRegClass) {
2083 } else if (RC == &X86::GR32_NOREXRegClass) {
2085 } else if (RC == &X86::GR16_NOREXRegClass) {
2087 } else if (RC == &X86::GR8_NOREXRegClass) {
2089 } else if (RC == &X86::RFP80RegClass) {
2090 Opc = X86::LD_Fp80m;
2091 } else if (RC == &X86::RFP64RegClass) {
2092 Opc = X86::LD_Fp64m;
2093 } else if (RC == &X86::RFP32RegClass) {
2094 Opc = X86::LD_Fp32m;
2095 } else if (RC == &X86::FR32RegClass) {
2097 } else if (RC == &X86::FR64RegClass) {
2099 } else if (RC == &X86::VR128RegClass) {
2100 // If stack is realigned we can use aligned loads.
2101 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2102 } else if (RC == &X86::VR64RegClass) {
2103 Opc = X86::MMX_MOVQ64rm;
2105 llvm_unreachable("Unknown regclass");
2111 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2112 MachineBasicBlock::iterator MI,
2113 unsigned DestReg, int FrameIdx,
2114 const TargetRegisterClass *RC) const{
2115 const MachineFunction &MF = *MBB.getParent();
2116 bool isAligned = (RI.getStackAlignment() >= 16) ||
2117 RI.needsStackRealignment(MF);
2118 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2119 DebugLoc DL = DebugLoc::getUnknownLoc();
2120 if (MI != MBB.end()) DL = MI->getDebugLoc();
2121 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2124 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2125 SmallVectorImpl<MachineOperand> &Addr,
2126 const TargetRegisterClass *RC,
2127 MachineInstr::mmo_iterator MMOBegin,
2128 MachineInstr::mmo_iterator MMOEnd,
2129 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2130 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2131 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2132 DebugLoc DL = DebugLoc::getUnknownLoc();
2133 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2134 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2135 MIB.addOperand(Addr[i]);
2136 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2137 NewMIs.push_back(MIB);
2140 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2141 MachineBasicBlock::iterator MI,
2142 const std::vector<CalleeSavedInfo> &CSI) const {
2146 DebugLoc DL = DebugLoc::getUnknownLoc();
2147 if (MI != MBB.end()) DL = MI->getDebugLoc();
2149 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2150 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2151 unsigned SlotSize = is64Bit ? 8 : 4;
2153 MachineFunction &MF = *MBB.getParent();
2154 unsigned FPReg = RI.getFrameRegister(MF);
2155 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2156 unsigned CalleeFrameSize = 0;
2158 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2159 for (unsigned i = CSI.size(); i != 0; --i) {
2160 unsigned Reg = CSI[i-1].getReg();
2161 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2162 // Add the callee-saved register as live-in. It's killed at the spill.
2165 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2167 if (RegClass != &X86::VR128RegClass && !isWin64) {
2168 CalleeFrameSize += SlotSize;
2169 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2171 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2175 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2179 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2180 MachineBasicBlock::iterator MI,
2181 const std::vector<CalleeSavedInfo> &CSI) const {
2185 DebugLoc DL = DebugLoc::getUnknownLoc();
2186 if (MI != MBB.end()) DL = MI->getDebugLoc();
2188 MachineFunction &MF = *MBB.getParent();
2189 unsigned FPReg = RI.getFrameRegister(MF);
2190 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2191 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2192 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2193 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2194 unsigned Reg = CSI[i].getReg();
2196 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2198 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2199 if (RegClass != &X86::VR128RegClass && !isWin64) {
2200 BuildMI(MBB, MI, DL, get(Opc), Reg);
2202 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2208 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2209 const SmallVectorImpl<MachineOperand> &MOs,
2211 const TargetInstrInfo &TII) {
2212 // Create the base instruction with the memory operand as the first part.
2213 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2214 MI->getDebugLoc(), true);
2215 MachineInstrBuilder MIB(NewMI);
2216 unsigned NumAddrOps = MOs.size();
2217 for (unsigned i = 0; i != NumAddrOps; ++i)
2218 MIB.addOperand(MOs[i]);
2219 if (NumAddrOps < 4) // FrameIndex only
2222 // Loop over the rest of the ri operands, converting them over.
2223 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2224 for (unsigned i = 0; i != NumOps; ++i) {
2225 MachineOperand &MO = MI->getOperand(i+2);
2228 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2229 MachineOperand &MO = MI->getOperand(i);
2235 static MachineInstr *FuseInst(MachineFunction &MF,
2236 unsigned Opcode, unsigned OpNo,
2237 const SmallVectorImpl<MachineOperand> &MOs,
2238 MachineInstr *MI, const TargetInstrInfo &TII) {
2239 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2240 MI->getDebugLoc(), true);
2241 MachineInstrBuilder MIB(NewMI);
2243 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2244 MachineOperand &MO = MI->getOperand(i);
2246 assert(MO.isReg() && "Expected to fold into reg operand!");
2247 unsigned NumAddrOps = MOs.size();
2248 for (unsigned i = 0; i != NumAddrOps; ++i)
2249 MIB.addOperand(MOs[i]);
2250 if (NumAddrOps < 4) // FrameIndex only
2259 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2260 const SmallVectorImpl<MachineOperand> &MOs,
2262 MachineFunction &MF = *MI->getParent()->getParent();
2263 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2265 unsigned NumAddrOps = MOs.size();
2266 for (unsigned i = 0; i != NumAddrOps; ++i)
2267 MIB.addOperand(MOs[i]);
2268 if (NumAddrOps < 4) // FrameIndex only
2270 return MIB.addImm(0);
2274 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2275 MachineInstr *MI, unsigned i,
2276 const SmallVectorImpl<MachineOperand> &MOs,
2277 unsigned Size, unsigned Align) const {
2278 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2279 bool isTwoAddrFold = false;
2280 unsigned NumOps = MI->getDesc().getNumOperands();
2281 bool isTwoAddr = NumOps > 1 &&
2282 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2284 MachineInstr *NewMI = NULL;
2285 // Folding a memory location into the two-address part of a two-address
2286 // instruction is different than folding it other places. It requires
2287 // replacing the *two* registers with the memory location.
2288 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2289 MI->getOperand(0).isReg() &&
2290 MI->getOperand(1).isReg() &&
2291 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2292 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2293 isTwoAddrFold = true;
2294 } else if (i == 0) { // If operand 0
2295 if (MI->getOpcode() == X86::MOV16r0)
2296 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2297 else if (MI->getOpcode() == X86::MOV32r0)
2298 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2299 else if (MI->getOpcode() == X86::MOV8r0)
2300 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2304 OpcodeTablePtr = &RegOp2MemOpTable0;
2305 } else if (i == 1) {
2306 OpcodeTablePtr = &RegOp2MemOpTable1;
2307 } else if (i == 2) {
2308 OpcodeTablePtr = &RegOp2MemOpTable2;
2311 // If table selected...
2312 if (OpcodeTablePtr) {
2313 // Find the Opcode to fuse
2314 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2315 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2316 if (I != OpcodeTablePtr->end()) {
2317 unsigned Opcode = I->second.first;
2318 unsigned MinAlign = I->second.second;
2319 if (Align < MinAlign)
2321 bool NarrowToMOV32rm = false;
2323 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2324 if (Size < RCSize) {
2325 // Check if it's safe to fold the load. If the size of the object is
2326 // narrower than the load width, then it's not.
2327 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2329 // If this is a 64-bit load, but the spill slot is 32, then we can do
2330 // a 32-bit load which is implicitly zero-extended. This likely is due
2331 // to liveintervalanalysis remat'ing a load from stack slot.
2332 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2334 Opcode = X86::MOV32rm;
2335 NarrowToMOV32rm = true;
2340 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2342 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2344 if (NarrowToMOV32rm) {
2345 // If this is the special case where we use a MOV32rm to load a 32-bit
2346 // value and zero-extend the top bits. Change the destination register
2348 unsigned DstReg = NewMI->getOperand(0).getReg();
2349 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2350 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2351 4/*x86_subreg_32bit*/));
2353 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2360 if (PrintFailedFusing)
2361 errs() << "We failed to fuse operand " << i << " in " << *MI;
2366 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2368 const SmallVectorImpl<unsigned> &Ops,
2369 int FrameIndex) const {
2370 // Check switch flag
2371 if (NoFusing) return NULL;
2373 if (TM.getSubtarget<X86Subtarget>().shouldBreakSSEDep())
2374 switch (MI->getOpcode()) {
2375 case X86::CVTSD2SSrr:
2376 case X86::Int_CVTSD2SSrr:
2377 case X86::CVTSS2SDrr:
2378 case X86::Int_CVTSS2SDrr:
2380 case X86::RCPSSr_Int:
2381 case X86::ROUNDSDr_Int:
2382 case X86::ROUNDSSr_Int:
2384 case X86::RSQRTSSr_Int:
2386 case X86::SQRTSSr_Int:
2390 const MachineFrameInfo *MFI = MF.getFrameInfo();
2391 unsigned Size = MFI->getObjectSize(FrameIndex);
2392 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2393 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2394 unsigned NewOpc = 0;
2395 unsigned RCSize = 0;
2396 switch (MI->getOpcode()) {
2397 default: return NULL;
2398 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2399 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2400 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2401 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2403 // Check if it's safe to fold the load. If the size of the object is
2404 // narrower than the load width, then it's not.
2407 // Change to CMPXXri r, 0 first.
2408 MI->setDesc(get(NewOpc));
2409 MI->getOperand(1).ChangeToImmediate(0);
2410 } else if (Ops.size() != 1)
2413 SmallVector<MachineOperand,4> MOs;
2414 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2415 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2418 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2420 const SmallVectorImpl<unsigned> &Ops,
2421 MachineInstr *LoadMI) const {
2422 // Check switch flag
2423 if (NoFusing) return NULL;
2425 if (TM.getSubtarget<X86Subtarget>().shouldBreakSSEDep())
2426 switch (MI->getOpcode()) {
2427 case X86::CVTSD2SSrr:
2428 case X86::Int_CVTSD2SSrr:
2429 case X86::CVTSS2SDrr:
2430 case X86::Int_CVTSS2SDrr:
2432 case X86::RCPSSr_Int:
2433 case X86::ROUNDSDr_Int:
2434 case X86::ROUNDSSr_Int:
2436 case X86::RSQRTSSr_Int:
2438 case X86::SQRTSSr_Int:
2442 // Determine the alignment of the load.
2443 unsigned Alignment = 0;
2444 if (LoadMI->hasOneMemOperand())
2445 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2447 switch (LoadMI->getOpcode()) {
2449 case X86::V_SETALLONES:
2459 llvm_unreachable("Don't know how to fold this instruction!");
2461 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2462 unsigned NewOpc = 0;
2463 switch (MI->getOpcode()) {
2464 default: return NULL;
2465 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2466 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2467 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2468 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2470 // Change to CMPXXri r, 0 first.
2471 MI->setDesc(get(NewOpc));
2472 MI->getOperand(1).ChangeToImmediate(0);
2473 } else if (Ops.size() != 1)
2476 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2477 switch (LoadMI->getOpcode()) {
2479 case X86::V_SETALLONES:
2481 case X86::FsFLD0SS: {
2482 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2483 // Create a constant-pool entry and operands to load from it.
2485 // x86-32 PIC requires a PIC base register for constant pools.
2486 unsigned PICBase = 0;
2487 if (TM.getRelocationModel() == Reloc::PIC_) {
2488 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2491 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2492 // This doesn't work for several reasons.
2493 // 1. GlobalBaseReg may have been spilled.
2494 // 2. It may not be live at MI.
2498 // Create a constant-pool entry.
2499 MachineConstantPool &MCP = *MF.getConstantPool();
2501 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2502 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2503 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2504 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2506 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2507 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2508 Constant::getAllOnesValue(Ty) :
2509 Constant::getNullValue(Ty);
2510 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2512 // Create operands to load from the constant pool entry.
2513 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2514 MOs.push_back(MachineOperand::CreateImm(1));
2515 MOs.push_back(MachineOperand::CreateReg(0, false));
2516 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2517 MOs.push_back(MachineOperand::CreateReg(0, false));
2521 // Folding a normal load. Just copy the load's address operands.
2522 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2523 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2524 MOs.push_back(LoadMI->getOperand(i));
2528 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2532 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2533 const SmallVectorImpl<unsigned> &Ops) const {
2534 // Check switch flag
2535 if (NoFusing) return 0;
2537 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2538 switch (MI->getOpcode()) {
2539 default: return false;
2548 if (Ops.size() != 1)
2551 unsigned OpNum = Ops[0];
2552 unsigned Opc = MI->getOpcode();
2553 unsigned NumOps = MI->getDesc().getNumOperands();
2554 bool isTwoAddr = NumOps > 1 &&
2555 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2557 // Folding a memory location into the two-address part of a two-address
2558 // instruction is different than folding it other places. It requires
2559 // replacing the *two* registers with the memory location.
2560 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2561 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2562 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2563 } else if (OpNum == 0) { // If operand 0
2571 OpcodeTablePtr = &RegOp2MemOpTable0;
2572 } else if (OpNum == 1) {
2573 OpcodeTablePtr = &RegOp2MemOpTable1;
2574 } else if (OpNum == 2) {
2575 OpcodeTablePtr = &RegOp2MemOpTable2;
2578 if (OpcodeTablePtr) {
2579 // Find the Opcode to fuse
2580 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2581 OpcodeTablePtr->find((unsigned*)Opc);
2582 if (I != OpcodeTablePtr->end())
2588 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2589 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2590 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2591 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2592 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2593 if (I == MemOp2RegOpTable.end())
2595 DebugLoc dl = MI->getDebugLoc();
2596 unsigned Opc = I->second.first;
2597 unsigned Index = I->second.second & 0xf;
2598 bool FoldedLoad = I->second.second & (1 << 4);
2599 bool FoldedStore = I->second.second & (1 << 5);
2600 if (UnfoldLoad && !FoldedLoad)
2602 UnfoldLoad &= FoldedLoad;
2603 if (UnfoldStore && !FoldedStore)
2605 UnfoldStore &= FoldedStore;
2607 const TargetInstrDesc &TID = get(Opc);
2608 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2609 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2610 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2611 SmallVector<MachineOperand,2> BeforeOps;
2612 SmallVector<MachineOperand,2> AfterOps;
2613 SmallVector<MachineOperand,4> ImpOps;
2614 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2615 MachineOperand &Op = MI->getOperand(i);
2616 if (i >= Index && i < Index + X86AddrNumOperands)
2617 AddrOps.push_back(Op);
2618 else if (Op.isReg() && Op.isImplicit())
2619 ImpOps.push_back(Op);
2621 BeforeOps.push_back(Op);
2623 AfterOps.push_back(Op);
2626 // Emit the load instruction.
2628 std::pair<MachineInstr::mmo_iterator,
2629 MachineInstr::mmo_iterator> MMOs =
2630 MF.extractLoadMemRefs(MI->memoperands_begin(),
2631 MI->memoperands_end());
2632 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2634 // Address operands cannot be marked isKill.
2635 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2636 MachineOperand &MO = NewMIs[0]->getOperand(i);
2638 MO.setIsKill(false);
2643 // Emit the data processing instruction.
2644 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2645 MachineInstrBuilder MIB(DataMI);
2648 MIB.addReg(Reg, RegState::Define);
2649 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2650 MIB.addOperand(BeforeOps[i]);
2653 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2654 MIB.addOperand(AfterOps[i]);
2655 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2656 MachineOperand &MO = ImpOps[i];
2657 MIB.addReg(MO.getReg(),
2658 getDefRegState(MO.isDef()) |
2659 RegState::Implicit |
2660 getKillRegState(MO.isKill()) |
2661 getDeadRegState(MO.isDead()) |
2662 getUndefRegState(MO.isUndef()));
2664 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2665 unsigned NewOpc = 0;
2666 switch (DataMI->getOpcode()) {
2668 case X86::CMP64ri32:
2672 MachineOperand &MO0 = DataMI->getOperand(0);
2673 MachineOperand &MO1 = DataMI->getOperand(1);
2674 if (MO1.getImm() == 0) {
2675 switch (DataMI->getOpcode()) {
2677 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2678 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2679 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2680 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2682 DataMI->setDesc(get(NewOpc));
2683 MO1.ChangeToRegister(MO0.getReg(), false);
2687 NewMIs.push_back(DataMI);
2689 // Emit the store instruction.
2691 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2692 std::pair<MachineInstr::mmo_iterator,
2693 MachineInstr::mmo_iterator> MMOs =
2694 MF.extractStoreMemRefs(MI->memoperands_begin(),
2695 MI->memoperands_end());
2696 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2703 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2704 SmallVectorImpl<SDNode*> &NewNodes) const {
2705 if (!N->isMachineOpcode())
2708 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2709 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2710 if (I == MemOp2RegOpTable.end())
2712 unsigned Opc = I->second.first;
2713 unsigned Index = I->second.second & 0xf;
2714 bool FoldedLoad = I->second.second & (1 << 4);
2715 bool FoldedStore = I->second.second & (1 << 5);
2716 const TargetInstrDesc &TID = get(Opc);
2717 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2718 unsigned NumDefs = TID.NumDefs;
2719 std::vector<SDValue> AddrOps;
2720 std::vector<SDValue> BeforeOps;
2721 std::vector<SDValue> AfterOps;
2722 DebugLoc dl = N->getDebugLoc();
2723 unsigned NumOps = N->getNumOperands();
2724 for (unsigned i = 0; i != NumOps-1; ++i) {
2725 SDValue Op = N->getOperand(i);
2726 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2727 AddrOps.push_back(Op);
2728 else if (i < Index-NumDefs)
2729 BeforeOps.push_back(Op);
2730 else if (i > Index-NumDefs)
2731 AfterOps.push_back(Op);
2733 SDValue Chain = N->getOperand(NumOps-1);
2734 AddrOps.push_back(Chain);
2736 // Emit the load instruction.
2738 MachineFunction &MF = DAG.getMachineFunction();
2740 EVT VT = *RC->vt_begin();
2741 std::pair<MachineInstr::mmo_iterator,
2742 MachineInstr::mmo_iterator> MMOs =
2743 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2744 cast<MachineSDNode>(N)->memoperands_end());
2745 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2746 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2747 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2748 NewNodes.push_back(Load);
2750 // Preserve memory reference information.
2751 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2754 // Emit the data processing instruction.
2755 std::vector<EVT> VTs;
2756 const TargetRegisterClass *DstRC = 0;
2757 if (TID.getNumDefs() > 0) {
2758 DstRC = TID.OpInfo[0].getRegClass(&RI);
2759 VTs.push_back(*DstRC->vt_begin());
2761 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2762 EVT VT = N->getValueType(i);
2763 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2767 BeforeOps.push_back(SDValue(Load, 0));
2768 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2769 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2771 NewNodes.push_back(NewNode);
2773 // Emit the store instruction.
2776 AddrOps.push_back(SDValue(NewNode, 0));
2777 AddrOps.push_back(Chain);
2778 std::pair<MachineInstr::mmo_iterator,
2779 MachineInstr::mmo_iterator> MMOs =
2780 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2781 cast<MachineSDNode>(N)->memoperands_end());
2782 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2783 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2786 &AddrOps[0], AddrOps.size());
2787 NewNodes.push_back(Store);
2789 // Preserve memory reference information.
2790 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2796 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2797 bool UnfoldLoad, bool UnfoldStore,
2798 unsigned *LoadRegIndex) const {
2799 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2800 MemOp2RegOpTable.find((unsigned*)Opc);
2801 if (I == MemOp2RegOpTable.end())
2803 bool FoldedLoad = I->second.second & (1 << 4);
2804 bool FoldedStore = I->second.second & (1 << 5);
2805 if (UnfoldLoad && !FoldedLoad)
2807 if (UnfoldStore && !FoldedStore)
2810 *LoadRegIndex = I->second.second & 0xf;
2811 return I->second.first;
2815 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2816 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2817 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2818 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2820 Cond[0].setImm(GetOppositeBranchCondition(CC));
2825 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2826 // FIXME: Return false for x87 stack register classes for now. We can't
2827 // allow any loads of these registers before FpGet_ST0_80.
2828 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2829 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2832 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2833 switch (Desc->TSFlags & X86II::ImmMask) {
2834 case X86II::Imm8: return 1;
2835 case X86II::Imm16: return 2;
2836 case X86II::Imm32: return 4;
2837 case X86II::Imm64: return 8;
2838 default: llvm_unreachable("Immediate size not set!");
2843 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2844 /// e.g. r8, xmm8, etc.
2845 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2846 if (!MO.isReg()) return false;
2847 switch (MO.getReg()) {
2849 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2850 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2851 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2852 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2853 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2854 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2855 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2856 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2857 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2858 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2865 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2866 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2867 /// size, and 3) use of X86-64 extended registers.
2868 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2870 const TargetInstrDesc &Desc = MI.getDesc();
2872 // Pseudo instructions do not need REX prefix byte.
2873 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2875 if (Desc.TSFlags & X86II::REX_W)
2878 unsigned NumOps = Desc.getNumOperands();
2880 bool isTwoAddr = NumOps > 1 &&
2881 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2883 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2884 unsigned i = isTwoAddr ? 1 : 0;
2885 for (unsigned e = NumOps; i != e; ++i) {
2886 const MachineOperand& MO = MI.getOperand(i);
2888 unsigned Reg = MO.getReg();
2889 if (isX86_64NonExtLowByteReg(Reg))
2894 switch (Desc.TSFlags & X86II::FormMask) {
2895 case X86II::MRMInitReg:
2896 if (isX86_64ExtendedReg(MI.getOperand(0)))
2897 REX |= (1 << 0) | (1 << 2);
2899 case X86II::MRMSrcReg: {
2900 if (isX86_64ExtendedReg(MI.getOperand(0)))
2902 i = isTwoAddr ? 2 : 1;
2903 for (unsigned e = NumOps; i != e; ++i) {
2904 const MachineOperand& MO = MI.getOperand(i);
2905 if (isX86_64ExtendedReg(MO))
2910 case X86II::MRMSrcMem: {
2911 if (isX86_64ExtendedReg(MI.getOperand(0)))
2914 i = isTwoAddr ? 2 : 1;
2915 for (; i != NumOps; ++i) {
2916 const MachineOperand& MO = MI.getOperand(i);
2918 if (isX86_64ExtendedReg(MO))
2925 case X86II::MRM0m: case X86II::MRM1m:
2926 case X86II::MRM2m: case X86II::MRM3m:
2927 case X86II::MRM4m: case X86II::MRM5m:
2928 case X86II::MRM6m: case X86II::MRM7m:
2929 case X86II::MRMDestMem: {
2930 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2931 i = isTwoAddr ? 1 : 0;
2932 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2935 for (; i != e; ++i) {
2936 const MachineOperand& MO = MI.getOperand(i);
2938 if (isX86_64ExtendedReg(MO))
2946 if (isX86_64ExtendedReg(MI.getOperand(0)))
2948 i = isTwoAddr ? 2 : 1;
2949 for (unsigned e = NumOps; i != e; ++i) {
2950 const MachineOperand& MO = MI.getOperand(i);
2951 if (isX86_64ExtendedReg(MO))
2961 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2962 /// relative block address instruction
2964 static unsigned sizePCRelativeBlockAddress() {
2968 /// sizeGlobalAddress - Give the size of the emission of this global address
2970 static unsigned sizeGlobalAddress(bool dword) {
2971 return dword ? 8 : 4;
2974 /// sizeConstPoolAddress - Give the size of the emission of this constant
2977 static unsigned sizeConstPoolAddress(bool dword) {
2978 return dword ? 8 : 4;
2981 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2984 static unsigned sizeExternalSymbolAddress(bool dword) {
2985 return dword ? 8 : 4;
2988 /// sizeJumpTableAddress - Give the size of the emission of this jump
2991 static unsigned sizeJumpTableAddress(bool dword) {
2992 return dword ? 8 : 4;
2995 static unsigned sizeConstant(unsigned Size) {
2999 static unsigned sizeRegModRMByte(){
3003 static unsigned sizeSIBByte(){
3007 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3008 unsigned FinalSize = 0;
3009 // If this is a simple integer displacement that doesn't require a relocation.
3011 FinalSize += sizeConstant(4);
3015 // Otherwise, this is something that requires a relocation.
3016 if (RelocOp->isGlobal()) {
3017 FinalSize += sizeGlobalAddress(false);
3018 } else if (RelocOp->isCPI()) {
3019 FinalSize += sizeConstPoolAddress(false);
3020 } else if (RelocOp->isJTI()) {
3021 FinalSize += sizeJumpTableAddress(false);
3023 llvm_unreachable("Unknown value to relocate!");
3028 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3029 bool IsPIC, bool Is64BitMode) {
3030 const MachineOperand &Op3 = MI.getOperand(Op+3);
3032 const MachineOperand *DispForReloc = 0;
3033 unsigned FinalSize = 0;
3035 // Figure out what sort of displacement we have to handle here.
3036 if (Op3.isGlobal()) {
3037 DispForReloc = &Op3;
3038 } else if (Op3.isCPI()) {
3039 if (Is64BitMode || IsPIC) {
3040 DispForReloc = &Op3;
3044 } else if (Op3.isJTI()) {
3045 if (Is64BitMode || IsPIC) {
3046 DispForReloc = &Op3;
3054 const MachineOperand &Base = MI.getOperand(Op);
3055 const MachineOperand &IndexReg = MI.getOperand(Op+2);
3057 unsigned BaseReg = Base.getReg();
3059 // Is a SIB byte needed?
3060 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3061 IndexReg.getReg() == 0 &&
3062 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3063 if (BaseReg == 0) { // Just a displacement?
3064 // Emit special case [disp32] encoding
3066 FinalSize += getDisplacementFieldSize(DispForReloc);
3068 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3069 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3070 // Emit simple indirect register encoding... [EAX] f.e.
3072 // Be pessimistic and assume it's a disp32, not a disp8
3074 // Emit the most general non-SIB encoding: [REG+disp32]
3076 FinalSize += getDisplacementFieldSize(DispForReloc);
3080 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
3081 assert(IndexReg.getReg() != X86::ESP &&
3082 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3084 bool ForceDisp32 = false;
3085 if (BaseReg == 0 || DispForReloc) {
3086 // Emit the normal disp32 encoding.
3093 FinalSize += sizeSIBByte();
3095 // Do we need to output a displacement?
3096 if (DispVal != 0 || ForceDisp32) {
3097 FinalSize += getDisplacementFieldSize(DispForReloc);
3104 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3105 const TargetInstrDesc *Desc,
3106 bool IsPIC, bool Is64BitMode) {
3108 unsigned Opcode = Desc->Opcode;
3109 unsigned FinalSize = 0;
3111 // Emit the lock opcode prefix as needed.
3112 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3114 // Emit segment override opcode prefix as needed.
3115 switch (Desc->TSFlags & X86II::SegOvrMask) {
3120 default: llvm_unreachable("Invalid segment!");
3121 case 0: break; // No segment override!
3124 // Emit the repeat opcode prefix as needed.
3125 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3127 // Emit the operand size opcode prefix as needed.
3128 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3130 // Emit the address size opcode prefix as needed.
3131 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3133 bool Need0FPrefix = false;
3134 switch (Desc->TSFlags & X86II::Op0Mask) {
3135 case X86II::TB: // Two-byte opcode prefix
3136 case X86II::T8: // 0F 38
3137 case X86II::TA: // 0F 3A
3138 Need0FPrefix = true;
3140 case X86II::TF: // F2 0F 38
3142 Need0FPrefix = true;
3144 case X86II::REP: break; // already handled.
3145 case X86II::XS: // F3 0F
3147 Need0FPrefix = true;
3149 case X86II::XD: // F2 0F
3151 Need0FPrefix = true;
3153 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3154 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3156 break; // Two-byte opcode prefix
3157 default: llvm_unreachable("Invalid prefix!");
3158 case 0: break; // No prefix!
3163 unsigned REX = X86InstrInfo::determineREX(MI);
3168 // 0x0F escape code must be emitted just before the opcode.
3172 switch (Desc->TSFlags & X86II::Op0Mask) {
3173 case X86II::T8: // 0F 38
3176 case X86II::TA: // 0F 3A
3179 case X86II::TF: // F2 0F 38
3184 // If this is a two-address instruction, skip one of the register operands.
3185 unsigned NumOps = Desc->getNumOperands();
3187 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3189 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3190 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3193 switch (Desc->TSFlags & X86II::FormMask) {
3194 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3196 // Remember the current PC offset, this is the PIC relocation
3201 case TargetInstrInfo::INLINEASM: {
3202 const MachineFunction *MF = MI.getParent()->getParent();
3203 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3204 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3205 *MF->getTarget().getMCAsmInfo());
3208 case TargetInstrInfo::DBG_LABEL:
3209 case TargetInstrInfo::EH_LABEL:
3211 case TargetInstrInfo::IMPLICIT_DEF:
3212 case TargetInstrInfo::KILL:
3213 case X86::FP_REG_KILL:
3215 case X86::MOVPC32r: {
3216 // This emits the "call" portion of this pseudo instruction.
3218 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3227 if (CurOp != NumOps) {
3228 const MachineOperand &MO = MI.getOperand(CurOp++);
3230 FinalSize += sizePCRelativeBlockAddress();
3231 } else if (MO.isGlobal()) {
3232 FinalSize += sizeGlobalAddress(false);
3233 } else if (MO.isSymbol()) {
3234 FinalSize += sizeExternalSymbolAddress(false);
3235 } else if (MO.isImm()) {
3236 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3238 llvm_unreachable("Unknown RawFrm operand!");
3243 case X86II::AddRegFrm:
3247 if (CurOp != NumOps) {
3248 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3249 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3251 FinalSize += sizeConstant(Size);
3254 if (Opcode == X86::MOV64ri)
3256 if (MO1.isGlobal()) {
3257 FinalSize += sizeGlobalAddress(dword);
3258 } else if (MO1.isSymbol())
3259 FinalSize += sizeExternalSymbolAddress(dword);
3260 else if (MO1.isCPI())
3261 FinalSize += sizeConstPoolAddress(dword);
3262 else if (MO1.isJTI())
3263 FinalSize += sizeJumpTableAddress(dword);
3268 case X86II::MRMDestReg: {
3270 FinalSize += sizeRegModRMByte();
3272 if (CurOp != NumOps) {
3274 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3278 case X86II::MRMDestMem: {
3280 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3281 CurOp += X86AddrNumOperands + 1;
3282 if (CurOp != NumOps) {
3284 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3289 case X86II::MRMSrcReg:
3291 FinalSize += sizeRegModRMByte();
3293 if (CurOp != NumOps) {
3295 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3299 case X86II::MRMSrcMem: {
3301 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3302 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3303 AddrOperands = X86AddrNumOperands - 1; // No segment register
3305 AddrOperands = X86AddrNumOperands;
3308 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3309 CurOp += AddrOperands + 1;
3310 if (CurOp != NumOps) {
3312 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3317 case X86II::MRM0r: case X86II::MRM1r:
3318 case X86II::MRM2r: case X86II::MRM3r:
3319 case X86II::MRM4r: case X86II::MRM5r:
3320 case X86II::MRM6r: case X86II::MRM7r:
3322 if (Desc->getOpcode() == X86::LFENCE ||
3323 Desc->getOpcode() == X86::MFENCE) {
3324 // Special handling of lfence and mfence;
3325 FinalSize += sizeRegModRMByte();
3326 } else if (Desc->getOpcode() == X86::MONITOR ||
3327 Desc->getOpcode() == X86::MWAIT) {
3328 // Special handling of monitor and mwait.
3329 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3332 FinalSize += sizeRegModRMByte();
3335 if (CurOp != NumOps) {
3336 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3337 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3339 FinalSize += sizeConstant(Size);
3342 if (Opcode == X86::MOV64ri32)
3344 if (MO1.isGlobal()) {
3345 FinalSize += sizeGlobalAddress(dword);
3346 } else if (MO1.isSymbol())
3347 FinalSize += sizeExternalSymbolAddress(dword);
3348 else if (MO1.isCPI())
3349 FinalSize += sizeConstPoolAddress(dword);
3350 else if (MO1.isJTI())
3351 FinalSize += sizeJumpTableAddress(dword);
3356 case X86II::MRM0m: case X86II::MRM1m:
3357 case X86II::MRM2m: case X86II::MRM3m:
3358 case X86II::MRM4m: case X86II::MRM5m:
3359 case X86II::MRM6m: case X86II::MRM7m: {
3362 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3363 CurOp += X86AddrNumOperands;
3365 if (CurOp != NumOps) {
3366 const MachineOperand &MO = MI.getOperand(CurOp++);
3367 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3369 FinalSize += sizeConstant(Size);
3372 if (Opcode == X86::MOV64mi32)
3374 if (MO.isGlobal()) {
3375 FinalSize += sizeGlobalAddress(dword);
3376 } else if (MO.isSymbol())
3377 FinalSize += sizeExternalSymbolAddress(dword);
3378 else if (MO.isCPI())
3379 FinalSize += sizeConstPoolAddress(dword);
3380 else if (MO.isJTI())
3381 FinalSize += sizeJumpTableAddress(dword);
3387 case X86II::MRMInitReg:
3389 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3390 FinalSize += sizeRegModRMByte();
3395 if (!Desc->isVariadic() && CurOp != NumOps) {
3397 raw_string_ostream Msg(msg);
3398 Msg << "Cannot determine size: " << MI;
3399 llvm_report_error(Msg.str());
3407 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3408 const TargetInstrDesc &Desc = MI->getDesc();
3409 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3410 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3411 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3412 if (Desc.getOpcode() == X86::MOVPC32r)
3413 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3417 /// getGlobalBaseReg - Return a virtual register initialized with the
3418 /// the global base register value. Output instructions required to
3419 /// initialize the register in the function entry block, if necessary.
3421 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3422 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3423 "X86-64 PIC uses RIP relative addressing");
3425 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3426 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3427 if (GlobalBaseReg != 0)
3428 return GlobalBaseReg;
3430 // Insert the set of GlobalBaseReg into the first MBB of the function
3431 MachineBasicBlock &FirstMBB = MF->front();
3432 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3433 DebugLoc DL = DebugLoc::getUnknownLoc();
3434 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3435 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3436 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3438 const TargetInstrInfo *TII = TM.getInstrInfo();
3439 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3440 // only used in JIT code emission as displacement to pc.
3441 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3443 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3444 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3445 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3446 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3447 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3448 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3449 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3450 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3455 X86FI->setGlobalBaseReg(GlobalBaseReg);
3456 return GlobalBaseReg;