1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/MC/MCAsmInfo.h"
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
50 ReMatPICStubLoad("remat-pic-stub-load",
51 cl::desc("Re-materialize load from stub in PIC mode"),
52 cl::init(false), cl::Hidden);
54 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
56 TM(tm), RI(tm, *this) {
57 SmallVector<unsigned,16> AmbEntries;
58 static const unsigned OpTbl2Addr[][2] = {
59 { X86::ADC32ri, X86::ADC32mi },
60 { X86::ADC32ri8, X86::ADC32mi8 },
61 { X86::ADC32rr, X86::ADC32mr },
62 { X86::ADC64ri32, X86::ADC64mi32 },
63 { X86::ADC64ri8, X86::ADC64mi8 },
64 { X86::ADC64rr, X86::ADC64mr },
65 { X86::ADD16ri, X86::ADD16mi },
66 { X86::ADD16ri8, X86::ADD16mi8 },
67 { X86::ADD16rr, X86::ADD16mr },
68 { X86::ADD32ri, X86::ADD32mi },
69 { X86::ADD32ri8, X86::ADD32mi8 },
70 { X86::ADD32rr, X86::ADD32mr },
71 { X86::ADD64ri32, X86::ADD64mi32 },
72 { X86::ADD64ri8, X86::ADD64mi8 },
73 { X86::ADD64rr, X86::ADD64mr },
74 { X86::ADD8ri, X86::ADD8mi },
75 { X86::ADD8rr, X86::ADD8mr },
76 { X86::AND16ri, X86::AND16mi },
77 { X86::AND16ri8, X86::AND16mi8 },
78 { X86::AND16rr, X86::AND16mr },
79 { X86::AND32ri, X86::AND32mi },
80 { X86::AND32ri8, X86::AND32mi8 },
81 { X86::AND32rr, X86::AND32mr },
82 { X86::AND64ri32, X86::AND64mi32 },
83 { X86::AND64ri8, X86::AND64mi8 },
84 { X86::AND64rr, X86::AND64mr },
85 { X86::AND8ri, X86::AND8mi },
86 { X86::AND8rr, X86::AND8mr },
87 { X86::DEC16r, X86::DEC16m },
88 { X86::DEC32r, X86::DEC32m },
89 { X86::DEC64_16r, X86::DEC64_16m },
90 { X86::DEC64_32r, X86::DEC64_32m },
91 { X86::DEC64r, X86::DEC64m },
92 { X86::DEC8r, X86::DEC8m },
93 { X86::INC16r, X86::INC16m },
94 { X86::INC32r, X86::INC32m },
95 { X86::INC64_16r, X86::INC64_16m },
96 { X86::INC64_32r, X86::INC64_32m },
97 { X86::INC64r, X86::INC64m },
98 { X86::INC8r, X86::INC8m },
99 { X86::NEG16r, X86::NEG16m },
100 { X86::NEG32r, X86::NEG32m },
101 { X86::NEG64r, X86::NEG64m },
102 { X86::NEG8r, X86::NEG8m },
103 { X86::NOT16r, X86::NOT16m },
104 { X86::NOT32r, X86::NOT32m },
105 { X86::NOT64r, X86::NOT64m },
106 { X86::NOT8r, X86::NOT8m },
107 { X86::OR16ri, X86::OR16mi },
108 { X86::OR16ri8, X86::OR16mi8 },
109 { X86::OR16rr, X86::OR16mr },
110 { X86::OR32ri, X86::OR32mi },
111 { X86::OR32ri8, X86::OR32mi8 },
112 { X86::OR32rr, X86::OR32mr },
113 { X86::OR64ri32, X86::OR64mi32 },
114 { X86::OR64ri8, X86::OR64mi8 },
115 { X86::OR64rr, X86::OR64mr },
116 { X86::OR8ri, X86::OR8mi },
117 { X86::OR8rr, X86::OR8mr },
118 { X86::ROL16r1, X86::ROL16m1 },
119 { X86::ROL16rCL, X86::ROL16mCL },
120 { X86::ROL16ri, X86::ROL16mi },
121 { X86::ROL32r1, X86::ROL32m1 },
122 { X86::ROL32rCL, X86::ROL32mCL },
123 { X86::ROL32ri, X86::ROL32mi },
124 { X86::ROL64r1, X86::ROL64m1 },
125 { X86::ROL64rCL, X86::ROL64mCL },
126 { X86::ROL64ri, X86::ROL64mi },
127 { X86::ROL8r1, X86::ROL8m1 },
128 { X86::ROL8rCL, X86::ROL8mCL },
129 { X86::ROL8ri, X86::ROL8mi },
130 { X86::ROR16r1, X86::ROR16m1 },
131 { X86::ROR16rCL, X86::ROR16mCL },
132 { X86::ROR16ri, X86::ROR16mi },
133 { X86::ROR32r1, X86::ROR32m1 },
134 { X86::ROR32rCL, X86::ROR32mCL },
135 { X86::ROR32ri, X86::ROR32mi },
136 { X86::ROR64r1, X86::ROR64m1 },
137 { X86::ROR64rCL, X86::ROR64mCL },
138 { X86::ROR64ri, X86::ROR64mi },
139 { X86::ROR8r1, X86::ROR8m1 },
140 { X86::ROR8rCL, X86::ROR8mCL },
141 { X86::ROR8ri, X86::ROR8mi },
142 { X86::SAR16r1, X86::SAR16m1 },
143 { X86::SAR16rCL, X86::SAR16mCL },
144 { X86::SAR16ri, X86::SAR16mi },
145 { X86::SAR32r1, X86::SAR32m1 },
146 { X86::SAR32rCL, X86::SAR32mCL },
147 { X86::SAR32ri, X86::SAR32mi },
148 { X86::SAR64r1, X86::SAR64m1 },
149 { X86::SAR64rCL, X86::SAR64mCL },
150 { X86::SAR64ri, X86::SAR64mi },
151 { X86::SAR8r1, X86::SAR8m1 },
152 { X86::SAR8rCL, X86::SAR8mCL },
153 { X86::SAR8ri, X86::SAR8mi },
154 { X86::SBB32ri, X86::SBB32mi },
155 { X86::SBB32ri8, X86::SBB32mi8 },
156 { X86::SBB32rr, X86::SBB32mr },
157 { X86::SBB64ri32, X86::SBB64mi32 },
158 { X86::SBB64ri8, X86::SBB64mi8 },
159 { X86::SBB64rr, X86::SBB64mr },
160 { X86::SHL16rCL, X86::SHL16mCL },
161 { X86::SHL16ri, X86::SHL16mi },
162 { X86::SHL32rCL, X86::SHL32mCL },
163 { X86::SHL32ri, X86::SHL32mi },
164 { X86::SHL64rCL, X86::SHL64mCL },
165 { X86::SHL64ri, X86::SHL64mi },
166 { X86::SHL8rCL, X86::SHL8mCL },
167 { X86::SHL8ri, X86::SHL8mi },
168 { X86::SHLD16rrCL, X86::SHLD16mrCL },
169 { X86::SHLD16rri8, X86::SHLD16mri8 },
170 { X86::SHLD32rrCL, X86::SHLD32mrCL },
171 { X86::SHLD32rri8, X86::SHLD32mri8 },
172 { X86::SHLD64rrCL, X86::SHLD64mrCL },
173 { X86::SHLD64rri8, X86::SHLD64mri8 },
174 { X86::SHR16r1, X86::SHR16m1 },
175 { X86::SHR16rCL, X86::SHR16mCL },
176 { X86::SHR16ri, X86::SHR16mi },
177 { X86::SHR32r1, X86::SHR32m1 },
178 { X86::SHR32rCL, X86::SHR32mCL },
179 { X86::SHR32ri, X86::SHR32mi },
180 { X86::SHR64r1, X86::SHR64m1 },
181 { X86::SHR64rCL, X86::SHR64mCL },
182 { X86::SHR64ri, X86::SHR64mi },
183 { X86::SHR8r1, X86::SHR8m1 },
184 { X86::SHR8rCL, X86::SHR8mCL },
185 { X86::SHR8ri, X86::SHR8mi },
186 { X86::SHRD16rrCL, X86::SHRD16mrCL },
187 { X86::SHRD16rri8, X86::SHRD16mri8 },
188 { X86::SHRD32rrCL, X86::SHRD32mrCL },
189 { X86::SHRD32rri8, X86::SHRD32mri8 },
190 { X86::SHRD64rrCL, X86::SHRD64mrCL },
191 { X86::SHRD64rri8, X86::SHRD64mri8 },
192 { X86::SUB16ri, X86::SUB16mi },
193 { X86::SUB16ri8, X86::SUB16mi8 },
194 { X86::SUB16rr, X86::SUB16mr },
195 { X86::SUB32ri, X86::SUB32mi },
196 { X86::SUB32ri8, X86::SUB32mi8 },
197 { X86::SUB32rr, X86::SUB32mr },
198 { X86::SUB64ri32, X86::SUB64mi32 },
199 { X86::SUB64ri8, X86::SUB64mi8 },
200 { X86::SUB64rr, X86::SUB64mr },
201 { X86::SUB8ri, X86::SUB8mi },
202 { X86::SUB8rr, X86::SUB8mr },
203 { X86::XOR16ri, X86::XOR16mi },
204 { X86::XOR16ri8, X86::XOR16mi8 },
205 { X86::XOR16rr, X86::XOR16mr },
206 { X86::XOR32ri, X86::XOR32mi },
207 { X86::XOR32ri8, X86::XOR32mi8 },
208 { X86::XOR32rr, X86::XOR32mr },
209 { X86::XOR64ri32, X86::XOR64mi32 },
210 { X86::XOR64ri8, X86::XOR64mi8 },
211 { X86::XOR64rr, X86::XOR64mr },
212 { X86::XOR8ri, X86::XOR8mi },
213 { X86::XOR8rr, X86::XOR8mr }
216 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
217 unsigned RegOp = OpTbl2Addr[i][0];
218 unsigned MemOp = OpTbl2Addr[i][1];
219 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
220 std::make_pair(MemOp,0))).second)
221 assert(false && "Duplicated entries?");
222 // Index 0, folded load and store, no alignment requirement.
223 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
224 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
225 std::make_pair(RegOp,
227 AmbEntries.push_back(MemOp);
230 // If the third value is 1, then it's folding either a load or a store.
231 static const unsigned OpTbl0[][4] = {
232 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
233 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
234 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
235 { X86::CALL32r, X86::CALL32m, 1, 0 },
236 { X86::CALL64r, X86::CALL64m, 1, 0 },
237 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
238 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
239 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
240 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
241 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
242 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
243 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
244 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
245 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
246 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
247 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
248 { X86::DIV16r, X86::DIV16m, 1, 0 },
249 { X86::DIV32r, X86::DIV32m, 1, 0 },
250 { X86::DIV64r, X86::DIV64m, 1, 0 },
251 { X86::DIV8r, X86::DIV8m, 1, 0 },
252 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
253 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
254 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
255 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
256 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
257 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
258 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
259 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
260 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
261 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
262 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
263 { X86::JMP32r, X86::JMP32m, 1, 0 },
264 { X86::JMP64r, X86::JMP64m, 1, 0 },
265 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
266 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
267 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
268 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
269 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 },
270 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
271 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
272 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
273 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
274 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
275 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
276 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
277 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
278 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
279 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
280 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
281 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
282 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
283 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
284 { X86::MUL16r, X86::MUL16m, 1, 0 },
285 { X86::MUL32r, X86::MUL32m, 1, 0 },
286 { X86::MUL64r, X86::MUL64m, 1, 0 },
287 { X86::MUL8r, X86::MUL8m, 1, 0 },
288 { X86::SETAEr, X86::SETAEm, 0, 0 },
289 { X86::SETAr, X86::SETAm, 0, 0 },
290 { X86::SETBEr, X86::SETBEm, 0, 0 },
291 { X86::SETBr, X86::SETBm, 0, 0 },
292 { X86::SETEr, X86::SETEm, 0, 0 },
293 { X86::SETGEr, X86::SETGEm, 0, 0 },
294 { X86::SETGr, X86::SETGm, 0, 0 },
295 { X86::SETLEr, X86::SETLEm, 0, 0 },
296 { X86::SETLr, X86::SETLm, 0, 0 },
297 { X86::SETNEr, X86::SETNEm, 0, 0 },
298 { X86::SETNOr, X86::SETNOm, 0, 0 },
299 { X86::SETNPr, X86::SETNPm, 0, 0 },
300 { X86::SETNSr, X86::SETNSm, 0, 0 },
301 { X86::SETOr, X86::SETOm, 0, 0 },
302 { X86::SETPr, X86::SETPm, 0, 0 },
303 { X86::SETSr, X86::SETSm, 0, 0 },
304 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
305 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
306 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
307 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
308 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
309 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
312 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
313 unsigned RegOp = OpTbl0[i][0];
314 unsigned MemOp = OpTbl0[i][1];
315 unsigned Align = OpTbl0[i][3];
316 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
317 std::make_pair(MemOp,Align))).second)
318 assert(false && "Duplicated entries?");
319 unsigned FoldedLoad = OpTbl0[i][2];
320 // Index 0, folded load or store.
321 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
322 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
323 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
324 std::make_pair(RegOp, AuxInfo))).second)
325 AmbEntries.push_back(MemOp);
328 static const unsigned OpTbl1[][3] = {
329 { X86::CMP16rr, X86::CMP16rm, 0 },
330 { X86::CMP32rr, X86::CMP32rm, 0 },
331 { X86::CMP64rr, X86::CMP64rm, 0 },
332 { X86::CMP8rr, X86::CMP8rm, 0 },
333 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
334 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
335 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
336 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
337 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
338 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
339 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
340 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
341 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
342 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
343 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
344 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
345 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
346 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
347 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
348 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
349 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
350 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
351 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
352 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
353 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
354 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
355 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
356 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
357 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
358 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
359 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
360 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
361 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
362 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
363 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
364 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
365 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
366 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
367 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
368 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
369 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
370 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
371 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
372 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
373 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
374 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
375 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
376 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
377 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
378 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
379 { X86::MOV16rr, X86::MOV16rm, 0 },
380 { X86::MOV32rr, X86::MOV32rm, 0 },
381 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 },
382 { X86::MOV64rr, X86::MOV64rm, 0 },
383 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
384 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
385 { X86::MOV8rr, X86::MOV8rm, 0 },
386 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
387 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
388 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
389 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
390 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
391 { X86::MOVDQArr, X86::MOVDQArm, 16 },
392 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
393 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
394 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
395 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
396 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
397 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
398 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
399 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
400 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
401 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
402 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
403 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
404 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
405 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
406 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
407 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
408 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
409 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
410 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
411 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
412 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
413 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
414 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
415 { X86::RCPPSr, X86::RCPPSm, 16 },
416 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
417 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
418 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
419 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
420 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
421 { X86::SQRTPDr, X86::SQRTPDm, 16 },
422 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
423 { X86::SQRTPSr, X86::SQRTPSm, 16 },
424 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
425 { X86::SQRTSDr, X86::SQRTSDm, 0 },
426 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
427 { X86::SQRTSSr, X86::SQRTSSm, 0 },
428 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
429 { X86::TEST16rr, X86::TEST16rm, 0 },
430 { X86::TEST32rr, X86::TEST32rm, 0 },
431 { X86::TEST64rr, X86::TEST64rm, 0 },
432 { X86::TEST8rr, X86::TEST8rm, 0 },
433 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
434 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
435 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
438 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
439 unsigned RegOp = OpTbl1[i][0];
440 unsigned MemOp = OpTbl1[i][1];
441 unsigned Align = OpTbl1[i][2];
442 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
443 std::make_pair(MemOp,Align))).second)
444 assert(false && "Duplicated entries?");
445 // Index 1, folded load
446 unsigned AuxInfo = 1 | (1 << 4);
447 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
448 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
449 std::make_pair(RegOp, AuxInfo))).second)
450 AmbEntries.push_back(MemOp);
453 static const unsigned OpTbl2[][3] = {
454 { X86::ADC32rr, X86::ADC32rm, 0 },
455 { X86::ADC64rr, X86::ADC64rm, 0 },
456 { X86::ADD16rr, X86::ADD16rm, 0 },
457 { X86::ADD32rr, X86::ADD32rm, 0 },
458 { X86::ADD64rr, X86::ADD64rm, 0 },
459 { X86::ADD8rr, X86::ADD8rm, 0 },
460 { X86::ADDPDrr, X86::ADDPDrm, 16 },
461 { X86::ADDPSrr, X86::ADDPSrm, 16 },
462 { X86::ADDSDrr, X86::ADDSDrm, 0 },
463 { X86::ADDSSrr, X86::ADDSSrm, 0 },
464 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
465 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
466 { X86::AND16rr, X86::AND16rm, 0 },
467 { X86::AND32rr, X86::AND32rm, 0 },
468 { X86::AND64rr, X86::AND64rm, 0 },
469 { X86::AND8rr, X86::AND8rm, 0 },
470 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
471 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
472 { X86::ANDPDrr, X86::ANDPDrm, 16 },
473 { X86::ANDPSrr, X86::ANDPSrm, 16 },
474 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
475 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
476 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
477 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
478 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
479 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
480 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
481 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
482 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
483 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
484 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
485 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
486 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
487 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
488 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
489 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
490 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
491 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
492 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
493 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
494 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
495 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
496 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
497 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
498 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
499 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
500 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
501 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
502 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
503 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
504 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
505 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
506 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
507 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
508 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
509 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
510 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
511 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
512 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
513 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
514 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
515 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
516 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
517 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
518 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
519 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
520 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
521 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
522 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
523 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
524 { X86::CMPSDrr, X86::CMPSDrm, 0 },
525 { X86::CMPSSrr, X86::CMPSSrm, 0 },
526 { X86::DIVPDrr, X86::DIVPDrm, 16 },
527 { X86::DIVPSrr, X86::DIVPSrm, 16 },
528 { X86::DIVSDrr, X86::DIVSDrm, 0 },
529 { X86::DIVSSrr, X86::DIVSSrm, 0 },
530 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
531 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
532 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
533 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
534 { X86::FsORPDrr, X86::FsORPDrm, 16 },
535 { X86::FsORPSrr, X86::FsORPSrm, 16 },
536 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
537 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
538 { X86::HADDPDrr, X86::HADDPDrm, 16 },
539 { X86::HADDPSrr, X86::HADDPSrm, 16 },
540 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
541 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
542 { X86::IMUL16rr, X86::IMUL16rm, 0 },
543 { X86::IMUL32rr, X86::IMUL32rm, 0 },
544 { X86::IMUL64rr, X86::IMUL64rm, 0 },
545 { X86::MAXPDrr, X86::MAXPDrm, 16 },
546 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
547 { X86::MAXPSrr, X86::MAXPSrm, 16 },
548 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
549 { X86::MAXSDrr, X86::MAXSDrm, 0 },
550 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
551 { X86::MAXSSrr, X86::MAXSSrm, 0 },
552 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
553 { X86::MINPDrr, X86::MINPDrm, 16 },
554 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
555 { X86::MINPSrr, X86::MINPSrm, 16 },
556 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
557 { X86::MINSDrr, X86::MINSDrm, 0 },
558 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
559 { X86::MINSSrr, X86::MINSSrm, 0 },
560 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
561 { X86::MULPDrr, X86::MULPDrm, 16 },
562 { X86::MULPSrr, X86::MULPSrm, 16 },
563 { X86::MULSDrr, X86::MULSDrm, 0 },
564 { X86::MULSSrr, X86::MULSSrm, 0 },
565 { X86::OR16rr, X86::OR16rm, 0 },
566 { X86::OR32rr, X86::OR32rm, 0 },
567 { X86::OR64rr, X86::OR64rm, 0 },
568 { X86::OR8rr, X86::OR8rm, 0 },
569 { X86::ORPDrr, X86::ORPDrm, 16 },
570 { X86::ORPSrr, X86::ORPSrm, 16 },
571 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
572 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
573 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
574 { X86::PADDBrr, X86::PADDBrm, 16 },
575 { X86::PADDDrr, X86::PADDDrm, 16 },
576 { X86::PADDQrr, X86::PADDQrm, 16 },
577 { X86::PADDSBrr, X86::PADDSBrm, 16 },
578 { X86::PADDSWrr, X86::PADDSWrm, 16 },
579 { X86::PADDWrr, X86::PADDWrm, 16 },
580 { X86::PANDNrr, X86::PANDNrm, 16 },
581 { X86::PANDrr, X86::PANDrm, 16 },
582 { X86::PAVGBrr, X86::PAVGBrm, 16 },
583 { X86::PAVGWrr, X86::PAVGWrm, 16 },
584 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
585 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
586 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
587 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
588 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
589 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
590 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
591 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
592 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
593 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
594 { X86::PMINSWrr, X86::PMINSWrm, 16 },
595 { X86::PMINUBrr, X86::PMINUBrm, 16 },
596 { X86::PMULDQrr, X86::PMULDQrm, 16 },
597 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
598 { X86::PMULHWrr, X86::PMULHWrm, 16 },
599 { X86::PMULLDrr, X86::PMULLDrm, 16 },
600 { X86::PMULLWrr, X86::PMULLWrm, 16 },
601 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
602 { X86::PORrr, X86::PORrm, 16 },
603 { X86::PSADBWrr, X86::PSADBWrm, 16 },
604 { X86::PSLLDrr, X86::PSLLDrm, 16 },
605 { X86::PSLLQrr, X86::PSLLQrm, 16 },
606 { X86::PSLLWrr, X86::PSLLWrm, 16 },
607 { X86::PSRADrr, X86::PSRADrm, 16 },
608 { X86::PSRAWrr, X86::PSRAWrm, 16 },
609 { X86::PSRLDrr, X86::PSRLDrm, 16 },
610 { X86::PSRLQrr, X86::PSRLQrm, 16 },
611 { X86::PSRLWrr, X86::PSRLWrm, 16 },
612 { X86::PSUBBrr, X86::PSUBBrm, 16 },
613 { X86::PSUBDrr, X86::PSUBDrm, 16 },
614 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
615 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
616 { X86::PSUBWrr, X86::PSUBWrm, 16 },
617 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
618 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
619 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
620 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
621 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
622 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
623 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
624 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
625 { X86::PXORrr, X86::PXORrm, 16 },
626 { X86::SBB32rr, X86::SBB32rm, 0 },
627 { X86::SBB64rr, X86::SBB64rm, 0 },
628 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
629 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
630 { X86::SUB16rr, X86::SUB16rm, 0 },
631 { X86::SUB32rr, X86::SUB32rm, 0 },
632 { X86::SUB64rr, X86::SUB64rm, 0 },
633 { X86::SUB8rr, X86::SUB8rm, 0 },
634 { X86::SUBPDrr, X86::SUBPDrm, 16 },
635 { X86::SUBPSrr, X86::SUBPSrm, 16 },
636 { X86::SUBSDrr, X86::SUBSDrm, 0 },
637 { X86::SUBSSrr, X86::SUBSSrm, 0 },
638 // FIXME: TEST*rr -> swapped operand of TEST*mr.
639 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
640 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
641 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
642 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
643 { X86::XOR16rr, X86::XOR16rm, 0 },
644 { X86::XOR32rr, X86::XOR32rm, 0 },
645 { X86::XOR64rr, X86::XOR64rm, 0 },
646 { X86::XOR8rr, X86::XOR8rm, 0 },
647 { X86::XORPDrr, X86::XORPDrm, 16 },
648 { X86::XORPSrr, X86::XORPSrm, 16 }
651 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
652 unsigned RegOp = OpTbl2[i][0];
653 unsigned MemOp = OpTbl2[i][1];
654 unsigned Align = OpTbl2[i][2];
655 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
656 std::make_pair(MemOp,Align))).second)
657 assert(false && "Duplicated entries?");
658 // Index 2, folded load
659 unsigned AuxInfo = 2 | (1 << 4);
660 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
661 std::make_pair(RegOp, AuxInfo))).second)
662 AmbEntries.push_back(MemOp);
665 // Remove ambiguous entries.
666 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
669 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
670 unsigned &SrcReg, unsigned &DstReg,
671 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
672 switch (MI.getOpcode()) {
676 case X86::MOV8rr_NOREX:
680 case X86::MOV32rr_TC:
681 case X86::MOV64rr_TC:
683 // FP Stack register class copies
684 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
685 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
686 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
688 // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
689 // copies are done with FsMOVAPSrr and FsMOVAPDrr.
691 case X86::FsMOVAPSrr:
692 case X86::FsMOVAPDrr:
696 case X86::MMX_MOVQ64rr:
697 assert(MI.getNumOperands() >= 2 &&
698 MI.getOperand(0).isReg() &&
699 MI.getOperand(1).isReg() &&
700 "invalid register-register move instruction");
701 SrcReg = MI.getOperand(1).getReg();
702 DstReg = MI.getOperand(0).getReg();
703 SrcSubIdx = MI.getOperand(1).getSubReg();
704 DstSubIdx = MI.getOperand(0).getSubReg();
710 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
711 unsigned &SrcReg, unsigned &DstReg,
712 unsigned &SubIdx) const {
713 switch (MI.getOpcode()) {
715 case X86::MOVSX16rr8:
716 case X86::MOVZX16rr8:
717 case X86::MOVSX32rr8:
718 case X86::MOVZX32rr8:
719 case X86::MOVSX64rr8:
720 case X86::MOVZX64rr8:
721 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
722 // It's not always legal to reference the low 8-bit of the larger
723 // register in 32-bit mode.
725 case X86::MOVSX32rr16:
726 case X86::MOVZX32rr16:
727 case X86::MOVSX64rr16:
728 case X86::MOVZX64rr16:
729 case X86::MOVSX64rr32:
730 case X86::MOVZX64rr32: {
731 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
734 SrcReg = MI.getOperand(1).getReg();
735 DstReg = MI.getOperand(0).getReg();
736 switch (MI.getOpcode()) {
740 case X86::MOVSX16rr8:
741 case X86::MOVZX16rr8:
742 case X86::MOVSX32rr8:
743 case X86::MOVZX32rr8:
744 case X86::MOVSX64rr8:
745 case X86::MOVZX64rr8:
748 case X86::MOVSX32rr16:
749 case X86::MOVZX32rr16:
750 case X86::MOVSX64rr16:
751 case X86::MOVZX64rr16:
754 case X86::MOVSX64rr32:
755 case X86::MOVZX64rr32:
765 /// isFrameOperand - Return true and the FrameIndex if the specified
766 /// operand and follow operands form a reference to the stack frame.
767 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
768 int &FrameIndex) const {
769 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
770 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
771 MI->getOperand(Op+1).getImm() == 1 &&
772 MI->getOperand(Op+2).getReg() == 0 &&
773 MI->getOperand(Op+3).getImm() == 0) {
774 FrameIndex = MI->getOperand(Op).getIndex();
780 static bool isFrameLoadOpcode(int Opcode) {
793 case X86::MMX_MOVD64rm:
794 case X86::MMX_MOVQ64rm:
801 static bool isFrameStoreOpcode(int Opcode) {
814 case X86::MMX_MOVD64mr:
815 case X86::MMX_MOVQ64mr:
816 case X86::MMX_MOVNTQmr:
822 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
823 int &FrameIndex) const {
824 if (isFrameLoadOpcode(MI->getOpcode()))
825 if (isFrameOperand(MI, 1, FrameIndex))
826 return MI->getOperand(0).getReg();
830 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
831 int &FrameIndex) const {
832 if (isFrameLoadOpcode(MI->getOpcode())) {
834 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
836 // Check for post-frame index elimination operations
837 const MachineMemOperand *Dummy;
838 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
843 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
844 const MachineMemOperand *&MMO,
845 int &FrameIndex) const {
846 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
847 oe = MI->memoperands_end();
850 if ((*o)->isLoad() && (*o)->getValue())
851 if (const FixedStackPseudoSourceValue *Value =
852 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
853 FrameIndex = Value->getFrameIndex();
861 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
862 int &FrameIndex) const {
863 if (isFrameStoreOpcode(MI->getOpcode()))
864 if (isFrameOperand(MI, 0, FrameIndex))
865 return MI->getOperand(X86AddrNumOperands).getReg();
869 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
870 int &FrameIndex) const {
871 if (isFrameStoreOpcode(MI->getOpcode())) {
873 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
875 // Check for post-frame index elimination operations
876 const MachineMemOperand *Dummy;
877 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
882 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
883 const MachineMemOperand *&MMO,
884 int &FrameIndex) const {
885 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
886 oe = MI->memoperands_end();
889 if ((*o)->isStore() && (*o)->getValue())
890 if (const FixedStackPseudoSourceValue *Value =
891 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
892 FrameIndex = Value->getFrameIndex();
900 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
902 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
903 bool isPICBase = false;
904 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
905 E = MRI.def_end(); I != E; ++I) {
906 MachineInstr *DefMI = I.getOperand().getParent();
907 if (DefMI->getOpcode() != X86::MOVPC32r)
909 assert(!isPICBase && "More than one PIC base?");
916 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
917 AliasAnalysis *AA) const {
918 switch (MI->getOpcode()) {
929 case X86::MOVUPSrm_Int:
932 case X86::MMX_MOVD64rm:
933 case X86::MMX_MOVQ64rm:
934 case X86::FsMOVAPSrm:
935 case X86::FsMOVAPDrm: {
936 // Loads from constant pools are trivially rematerializable.
937 if (MI->getOperand(1).isReg() &&
938 MI->getOperand(2).isImm() &&
939 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
940 MI->isInvariantLoad(AA)) {
941 unsigned BaseReg = MI->getOperand(1).getReg();
942 if (BaseReg == 0 || BaseReg == X86::RIP)
944 // Allow re-materialization of PIC load.
945 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
947 const MachineFunction &MF = *MI->getParent()->getParent();
948 const MachineRegisterInfo &MRI = MF.getRegInfo();
949 bool isPICBase = false;
950 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
951 E = MRI.def_end(); I != E; ++I) {
952 MachineInstr *DefMI = I.getOperand().getParent();
953 if (DefMI->getOpcode() != X86::MOVPC32r)
955 assert(!isPICBase && "More than one PIC base?");
965 if (MI->getOperand(2).isImm() &&
966 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
967 !MI->getOperand(4).isReg()) {
968 // lea fi#, lea GV, etc. are all rematerializable.
969 if (!MI->getOperand(1).isReg())
971 unsigned BaseReg = MI->getOperand(1).getReg();
974 // Allow re-materialization of lea PICBase + x.
975 const MachineFunction &MF = *MI->getParent()->getParent();
976 const MachineRegisterInfo &MRI = MF.getRegInfo();
977 return regIsPICBase(BaseReg, MRI);
983 // All other instructions marked M_REMATERIALIZABLE are always trivially
988 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
989 /// would clobber the EFLAGS condition register. Note the result may be
990 /// conservative. If it cannot definitely determine the safety after visiting
991 /// a few instructions in each direction it assumes it's not safe.
992 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
993 MachineBasicBlock::iterator I) {
994 MachineBasicBlock::iterator E = MBB.end();
996 // It's always safe to clobber EFLAGS at the end of a block.
1000 // For compile time consideration, if we are not able to determine the
1001 // safety after visiting 4 instructions in each direction, we will assume
1003 MachineBasicBlock::iterator Iter = I;
1004 for (unsigned i = 0; i < 4; ++i) {
1005 bool SeenDef = false;
1006 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1007 MachineOperand &MO = Iter->getOperand(j);
1010 if (MO.getReg() == X86::EFLAGS) {
1018 // This instruction defines EFLAGS, no need to look any further.
1021 // Skip over DBG_VALUE.
1022 while (Iter != E && Iter->isDebugValue())
1025 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1030 MachineBasicBlock::iterator B = MBB.begin();
1032 for (unsigned i = 0; i < 4; ++i) {
1033 // If we make it to the beginning of the block, it's safe to clobber
1034 // EFLAGS iff EFLAGS is not live-in.
1036 return !MBB.isLiveIn(X86::EFLAGS);
1039 // Skip over DBG_VALUE.
1040 while (Iter != B && Iter->isDebugValue())
1043 bool SawKill = false;
1044 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1045 MachineOperand &MO = Iter->getOperand(j);
1046 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1047 if (MO.isDef()) return MO.isDead();
1048 if (MO.isKill()) SawKill = true;
1053 // This instruction kills EFLAGS and doesn't redefine it, so
1054 // there's no need to look further.
1058 // Conservative answer.
1062 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1063 MachineBasicBlock::iterator I,
1064 unsigned DestReg, unsigned SubIdx,
1065 const MachineInstr *Orig,
1066 const TargetRegisterInfo *TRI) const {
1067 DebugLoc DL = MBB.findDebugLoc(I);
1069 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1070 DestReg = TRI->getSubReg(DestReg, SubIdx);
1074 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1075 // Re-materialize them as movri instructions to avoid side effects.
1077 unsigned Opc = Orig->getOpcode();
1083 case X86::MOV64r0: {
1084 if (!isSafeToClobberEFLAGS(MBB, I)) {
1087 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1088 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1089 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1090 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1099 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1100 MI->getOperand(0).setReg(DestReg);
1103 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1106 MachineInstr *NewMI = prior(I);
1107 NewMI->getOperand(0).setSubReg(SubIdx);
1110 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1111 /// is not marked dead.
1112 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1113 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1114 MachineOperand &MO = MI->getOperand(i);
1115 if (MO.isReg() && MO.isDef() &&
1116 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1123 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1124 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1125 /// to a 32-bit superregister and then truncating back down to a 16-bit
1128 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1129 MachineFunction::iterator &MFI,
1130 MachineBasicBlock::iterator &MBBI,
1131 LiveVariables *LV) const {
1132 MachineInstr *MI = MBBI;
1133 unsigned Dest = MI->getOperand(0).getReg();
1134 unsigned Src = MI->getOperand(1).getReg();
1135 bool isDead = MI->getOperand(0).isDead();
1136 bool isKill = MI->getOperand(1).isKill();
1138 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1139 ? X86::LEA64_32r : X86::LEA32r;
1140 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1141 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1142 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1144 // Build and insert into an implicit UNDEF value. This is OK because
1145 // well be shifting and then extracting the lower 16-bits.
1146 // This has the potential to cause partial register stall. e.g.
1147 // movw (%rbp,%rcx,2), %dx
1148 // leal -65(%rdx), %esi
1149 // But testing has shown this *does* help performance in 64-bit mode (at
1150 // least on modern x86 machines).
1151 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1152 MachineInstr *InsMI =
1153 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1155 .addReg(Src, getKillRegState(isKill))
1156 .addImm(X86::SUBREG_16BIT);
1158 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1159 get(Opc), leaOutReg);
1162 llvm_unreachable(0);
1164 case X86::SHL16ri: {
1165 unsigned ShAmt = MI->getOperand(2).getImm();
1166 MIB.addReg(0).addImm(1 << ShAmt)
1167 .addReg(leaInReg, RegState::Kill).addImm(0);
1171 case X86::INC64_16r:
1172 addLeaRegOffset(MIB, leaInReg, true, 1);
1175 case X86::DEC64_16r:
1176 addLeaRegOffset(MIB, leaInReg, true, -1);
1180 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1182 case X86::ADD16rr: {
1183 unsigned Src2 = MI->getOperand(2).getReg();
1184 bool isKill2 = MI->getOperand(2).isKill();
1185 unsigned leaInReg2 = 0;
1186 MachineInstr *InsMI2 = 0;
1188 // ADD16rr %reg1028<kill>, %reg1028
1189 // just a single insert_subreg.
1190 addRegReg(MIB, leaInReg, true, leaInReg, false);
1192 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1193 // Build and insert into an implicit UNDEF value. This is OK because
1194 // well be shifting and then extracting the lower 16-bits.
1195 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1197 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1199 .addReg(Src2, getKillRegState(isKill2))
1200 .addImm(X86::SUBREG_16BIT);
1201 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1203 if (LV && isKill2 && InsMI2)
1204 LV->replaceKillInstruction(Src2, MI, InsMI2);
1209 MachineInstr *NewMI = MIB;
1210 MachineInstr *ExtMI =
1211 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1212 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1213 .addReg(leaOutReg, RegState::Kill)
1214 .addImm(X86::SUBREG_16BIT);
1217 // Update live variables
1218 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1219 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1221 LV->replaceKillInstruction(Src, MI, InsMI);
1223 LV->replaceKillInstruction(Dest, MI, ExtMI);
1229 /// convertToThreeAddress - This method must be implemented by targets that
1230 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1231 /// may be able to convert a two-address instruction into a true
1232 /// three-address instruction on demand. This allows the X86 target (for
1233 /// example) to convert ADD and SHL instructions into LEA instructions if they
1234 /// would require register copies due to two-addressness.
1236 /// This method returns a null pointer if the transformation cannot be
1237 /// performed, otherwise it returns the new instruction.
1240 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1241 MachineBasicBlock::iterator &MBBI,
1242 LiveVariables *LV) const {
1243 MachineInstr *MI = MBBI;
1244 MachineFunction &MF = *MI->getParent()->getParent();
1245 // All instructions input are two-addr instructions. Get the known operands.
1246 unsigned Dest = MI->getOperand(0).getReg();
1247 unsigned Src = MI->getOperand(1).getReg();
1248 bool isDead = MI->getOperand(0).isDead();
1249 bool isKill = MI->getOperand(1).isKill();
1251 MachineInstr *NewMI = NULL;
1252 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1253 // we have better subtarget support, enable the 16-bit LEA generation here.
1254 // 16-bit LEA is also slow on Core2.
1255 bool DisableLEA16 = true;
1256 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1258 unsigned MIOpc = MI->getOpcode();
1260 case X86::SHUFPSrri: {
1261 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1262 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1264 unsigned B = MI->getOperand(1).getReg();
1265 unsigned C = MI->getOperand(2).getReg();
1266 if (B != C) return 0;
1267 unsigned A = MI->getOperand(0).getReg();
1268 unsigned M = MI->getOperand(3).getImm();
1269 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1270 .addReg(A, RegState::Define | getDeadRegState(isDead))
1271 .addReg(B, getKillRegState(isKill)).addImm(M);
1274 case X86::SHL64ri: {
1275 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1276 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1277 // the flags produced by a shift yet, so this is safe.
1278 unsigned ShAmt = MI->getOperand(2).getImm();
1279 if (ShAmt == 0 || ShAmt >= 4) return 0;
1281 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1282 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1283 .addReg(0).addImm(1 << ShAmt)
1284 .addReg(Src, getKillRegState(isKill))
1288 case X86::SHL32ri: {
1289 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1290 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1291 // the flags produced by a shift yet, so this is safe.
1292 unsigned ShAmt = MI->getOperand(2).getImm();
1293 if (ShAmt == 0 || ShAmt >= 4) return 0;
1295 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1296 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1297 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1298 .addReg(0).addImm(1 << ShAmt)
1299 .addReg(Src, getKillRegState(isKill)).addImm(0);
1302 case X86::SHL16ri: {
1303 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1304 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1305 // the flags produced by a shift yet, so this is safe.
1306 unsigned ShAmt = MI->getOperand(2).getImm();
1307 if (ShAmt == 0 || ShAmt >= 4) return 0;
1310 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1311 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1312 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1313 .addReg(0).addImm(1 << ShAmt)
1314 .addReg(Src, getKillRegState(isKill))
1319 // The following opcodes also sets the condition code register(s). Only
1320 // convert them to equivalent lea if the condition code register def's
1322 if (hasLiveCondCodeDef(MI))
1329 case X86::INC64_32r: {
1330 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1331 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1332 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1333 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1334 .addReg(Dest, RegState::Define |
1335 getDeadRegState(isDead)),
1340 case X86::INC64_16r:
1342 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1343 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1344 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1345 .addReg(Dest, RegState::Define |
1346 getDeadRegState(isDead)),
1351 case X86::DEC64_32r: {
1352 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1353 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1354 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1355 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1356 .addReg(Dest, RegState::Define |
1357 getDeadRegState(isDead)),
1362 case X86::DEC64_16r:
1364 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1365 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1366 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1367 .addReg(Dest, RegState::Define |
1368 getDeadRegState(isDead)),
1372 case X86::ADD32rr: {
1373 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1374 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1375 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1376 unsigned Src2 = MI->getOperand(2).getReg();
1377 bool isKill2 = MI->getOperand(2).isKill();
1378 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1379 .addReg(Dest, RegState::Define |
1380 getDeadRegState(isDead)),
1381 Src, isKill, Src2, isKill2);
1383 LV->replaceKillInstruction(Src2, MI, NewMI);
1386 case X86::ADD16rr: {
1388 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1389 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1390 unsigned Src2 = MI->getOperand(2).getReg();
1391 bool isKill2 = MI->getOperand(2).isKill();
1392 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1393 .addReg(Dest, RegState::Define |
1394 getDeadRegState(isDead)),
1395 Src, isKill, Src2, isKill2);
1397 LV->replaceKillInstruction(Src2, MI, NewMI);
1400 case X86::ADD64ri32:
1402 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1403 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1404 .addReg(Dest, RegState::Define |
1405 getDeadRegState(isDead)),
1406 Src, isKill, MI->getOperand(2).getImm());
1409 case X86::ADD32ri8: {
1410 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1411 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1412 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1413 .addReg(Dest, RegState::Define |
1414 getDeadRegState(isDead)),
1415 Src, isKill, MI->getOperand(2).getImm());
1421 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1422 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1423 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1424 .addReg(Dest, RegState::Define |
1425 getDeadRegState(isDead)),
1426 Src, isKill, MI->getOperand(2).getImm());
1432 if (!NewMI) return 0;
1434 if (LV) { // Update live variables
1436 LV->replaceKillInstruction(Src, MI, NewMI);
1438 LV->replaceKillInstruction(Dest, MI, NewMI);
1441 MFI->insert(MBBI, NewMI); // Insert the new inst
1445 /// commuteInstruction - We have a few instructions that must be hacked on to
1449 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1450 switch (MI->getOpcode()) {
1451 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1452 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1453 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1454 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1455 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1456 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1459 switch (MI->getOpcode()) {
1460 default: llvm_unreachable("Unreachable!");
1461 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1462 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1463 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1464 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1465 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1466 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1468 unsigned Amt = MI->getOperand(3).getImm();
1470 MachineFunction &MF = *MI->getParent()->getParent();
1471 MI = MF.CloneMachineInstr(MI);
1474 MI->setDesc(get(Opc));
1475 MI->getOperand(3).setImm(Size-Amt);
1476 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1478 case X86::CMOVB16rr:
1479 case X86::CMOVB32rr:
1480 case X86::CMOVB64rr:
1481 case X86::CMOVAE16rr:
1482 case X86::CMOVAE32rr:
1483 case X86::CMOVAE64rr:
1484 case X86::CMOVE16rr:
1485 case X86::CMOVE32rr:
1486 case X86::CMOVE64rr:
1487 case X86::CMOVNE16rr:
1488 case X86::CMOVNE32rr:
1489 case X86::CMOVNE64rr:
1490 case X86::CMOVBE16rr:
1491 case X86::CMOVBE32rr:
1492 case X86::CMOVBE64rr:
1493 case X86::CMOVA16rr:
1494 case X86::CMOVA32rr:
1495 case X86::CMOVA64rr:
1496 case X86::CMOVL16rr:
1497 case X86::CMOVL32rr:
1498 case X86::CMOVL64rr:
1499 case X86::CMOVGE16rr:
1500 case X86::CMOVGE32rr:
1501 case X86::CMOVGE64rr:
1502 case X86::CMOVLE16rr:
1503 case X86::CMOVLE32rr:
1504 case X86::CMOVLE64rr:
1505 case X86::CMOVG16rr:
1506 case X86::CMOVG32rr:
1507 case X86::CMOVG64rr:
1508 case X86::CMOVS16rr:
1509 case X86::CMOVS32rr:
1510 case X86::CMOVS64rr:
1511 case X86::CMOVNS16rr:
1512 case X86::CMOVNS32rr:
1513 case X86::CMOVNS64rr:
1514 case X86::CMOVP16rr:
1515 case X86::CMOVP32rr:
1516 case X86::CMOVP64rr:
1517 case X86::CMOVNP16rr:
1518 case X86::CMOVNP32rr:
1519 case X86::CMOVNP64rr:
1520 case X86::CMOVO16rr:
1521 case X86::CMOVO32rr:
1522 case X86::CMOVO64rr:
1523 case X86::CMOVNO16rr:
1524 case X86::CMOVNO32rr:
1525 case X86::CMOVNO64rr: {
1527 switch (MI->getOpcode()) {
1529 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1530 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1531 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1532 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1533 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1534 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1535 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1536 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1537 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1538 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1539 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1540 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1541 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1542 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1543 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1544 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1545 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1546 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1547 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1548 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1549 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1550 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1551 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1552 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1553 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1554 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1555 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1556 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1557 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1558 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1559 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1560 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1561 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1562 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1563 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1564 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1565 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1566 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1567 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1568 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1569 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1570 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1571 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1572 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1573 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1574 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1575 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1576 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1579 MachineFunction &MF = *MI->getParent()->getParent();
1580 MI = MF.CloneMachineInstr(MI);
1583 MI->setDesc(get(Opc));
1584 // Fallthrough intended.
1587 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1591 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1593 default: return X86::COND_INVALID;
1594 case X86::JE_4: return X86::COND_E;
1595 case X86::JNE_4: return X86::COND_NE;
1596 case X86::JL_4: return X86::COND_L;
1597 case X86::JLE_4: return X86::COND_LE;
1598 case X86::JG_4: return X86::COND_G;
1599 case X86::JGE_4: return X86::COND_GE;
1600 case X86::JB_4: return X86::COND_B;
1601 case X86::JBE_4: return X86::COND_BE;
1602 case X86::JA_4: return X86::COND_A;
1603 case X86::JAE_4: return X86::COND_AE;
1604 case X86::JS_4: return X86::COND_S;
1605 case X86::JNS_4: return X86::COND_NS;
1606 case X86::JP_4: return X86::COND_P;
1607 case X86::JNP_4: return X86::COND_NP;
1608 case X86::JO_4: return X86::COND_O;
1609 case X86::JNO_4: return X86::COND_NO;
1613 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1615 default: llvm_unreachable("Illegal condition code!");
1616 case X86::COND_E: return X86::JE_4;
1617 case X86::COND_NE: return X86::JNE_4;
1618 case X86::COND_L: return X86::JL_4;
1619 case X86::COND_LE: return X86::JLE_4;
1620 case X86::COND_G: return X86::JG_4;
1621 case X86::COND_GE: return X86::JGE_4;
1622 case X86::COND_B: return X86::JB_4;
1623 case X86::COND_BE: return X86::JBE_4;
1624 case X86::COND_A: return X86::JA_4;
1625 case X86::COND_AE: return X86::JAE_4;
1626 case X86::COND_S: return X86::JS_4;
1627 case X86::COND_NS: return X86::JNS_4;
1628 case X86::COND_P: return X86::JP_4;
1629 case X86::COND_NP: return X86::JNP_4;
1630 case X86::COND_O: return X86::JO_4;
1631 case X86::COND_NO: return X86::JNO_4;
1635 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1636 /// e.g. turning COND_E to COND_NE.
1637 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1639 default: llvm_unreachable("Illegal condition code!");
1640 case X86::COND_E: return X86::COND_NE;
1641 case X86::COND_NE: return X86::COND_E;
1642 case X86::COND_L: return X86::COND_GE;
1643 case X86::COND_LE: return X86::COND_G;
1644 case X86::COND_G: return X86::COND_LE;
1645 case X86::COND_GE: return X86::COND_L;
1646 case X86::COND_B: return X86::COND_AE;
1647 case X86::COND_BE: return X86::COND_A;
1648 case X86::COND_A: return X86::COND_BE;
1649 case X86::COND_AE: return X86::COND_B;
1650 case X86::COND_S: return X86::COND_NS;
1651 case X86::COND_NS: return X86::COND_S;
1652 case X86::COND_P: return X86::COND_NP;
1653 case X86::COND_NP: return X86::COND_P;
1654 case X86::COND_O: return X86::COND_NO;
1655 case X86::COND_NO: return X86::COND_O;
1659 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1660 const TargetInstrDesc &TID = MI->getDesc();
1661 if (!TID.isTerminator()) return false;
1663 // Conditional branch is a special case.
1664 if (TID.isBranch() && !TID.isBarrier())
1666 if (!TID.isPredicable())
1668 return !isPredicated(MI);
1671 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1672 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1673 const X86InstrInfo &TII) {
1674 if (MI->getOpcode() == X86::FP_REG_KILL)
1676 return TII.isUnpredicatedTerminator(MI);
1679 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1680 MachineBasicBlock *&TBB,
1681 MachineBasicBlock *&FBB,
1682 SmallVectorImpl<MachineOperand> &Cond,
1683 bool AllowModify) const {
1684 // Start from the bottom of the block and work up, examining the
1685 // terminator instructions.
1686 MachineBasicBlock::iterator I = MBB.end();
1687 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1688 while (I != MBB.begin()) {
1690 if (I->isDebugValue())
1693 // Working from the bottom, when we see a non-terminator instruction, we're
1695 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1698 // A terminator that isn't a branch can't easily be handled by this
1700 if (!I->getDesc().isBranch())
1703 // Handle unconditional branches.
1704 if (I->getOpcode() == X86::JMP_4) {
1708 TBB = I->getOperand(0).getMBB();
1712 // If the block has any instructions after a JMP, delete them.
1713 while (llvm::next(I) != MBB.end())
1714 llvm::next(I)->eraseFromParent();
1719 // Delete the JMP if it's equivalent to a fall-through.
1720 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1722 I->eraseFromParent();
1724 UnCondBrIter = MBB.end();
1728 // TBB is used to indicate the unconditional destination.
1729 TBB = I->getOperand(0).getMBB();
1733 // Handle conditional branches.
1734 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1735 if (BranchCode == X86::COND_INVALID)
1736 return true; // Can't handle indirect branch.
1738 // Working from the bottom, handle the first conditional branch.
1740 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1741 if (AllowModify && UnCondBrIter != MBB.end() &&
1742 MBB.isLayoutSuccessor(TargetBB)) {
1743 // If we can modify the code and it ends in something like:
1751 // Then we can change this to:
1758 // Which is a bit more efficient.
1759 // We conditionally jump to the fall-through block.
1760 BranchCode = GetOppositeBranchCondition(BranchCode);
1761 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1762 MachineBasicBlock::iterator OldInst = I;
1764 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1765 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1766 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1768 MBB.addSuccessor(TargetBB);
1770 OldInst->eraseFromParent();
1771 UnCondBrIter->eraseFromParent();
1773 // Restart the analysis.
1774 UnCondBrIter = MBB.end();
1780 TBB = I->getOperand(0).getMBB();
1781 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1785 // Handle subsequent conditional branches. Only handle the case where all
1786 // conditional branches branch to the same destination and their condition
1787 // opcodes fit one of the special multi-branch idioms.
1788 assert(Cond.size() == 1);
1791 // Only handle the case where all conditional branches branch to the same
1793 if (TBB != I->getOperand(0).getMBB())
1796 // If the conditions are the same, we can leave them alone.
1797 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1798 if (OldBranchCode == BranchCode)
1801 // If they differ, see if they fit one of the known patterns. Theoretically,
1802 // we could handle more patterns here, but we shouldn't expect to see them
1803 // if instruction selection has done a reasonable job.
1804 if ((OldBranchCode == X86::COND_NP &&
1805 BranchCode == X86::COND_E) ||
1806 (OldBranchCode == X86::COND_E &&
1807 BranchCode == X86::COND_NP))
1808 BranchCode = X86::COND_NP_OR_E;
1809 else if ((OldBranchCode == X86::COND_P &&
1810 BranchCode == X86::COND_NE) ||
1811 (OldBranchCode == X86::COND_NE &&
1812 BranchCode == X86::COND_P))
1813 BranchCode = X86::COND_NE_OR_P;
1817 // Update the MachineOperand.
1818 Cond[0].setImm(BranchCode);
1824 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1825 MachineBasicBlock::iterator I = MBB.end();
1828 while (I != MBB.begin()) {
1830 if (I->isDebugValue())
1832 if (I->getOpcode() != X86::JMP_4 &&
1833 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1835 // Remove the branch.
1836 I->eraseFromParent();
1845 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1846 MachineBasicBlock *FBB,
1847 const SmallVectorImpl<MachineOperand> &Cond) const {
1848 // FIXME this should probably have a DebugLoc operand
1850 // Shouldn't be a fall through.
1851 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1852 assert((Cond.size() == 1 || Cond.size() == 0) &&
1853 "X86 branch conditions have one component!");
1856 // Unconditional branch?
1857 assert(!FBB && "Unconditional branch with multiple successors!");
1858 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
1862 // Conditional branch.
1864 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1866 case X86::COND_NP_OR_E:
1867 // Synthesize NP_OR_E with two branches.
1868 BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
1870 BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
1873 case X86::COND_NE_OR_P:
1874 // Synthesize NE_OR_P with two branches.
1875 BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
1877 BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
1881 unsigned Opc = GetCondBranchFromCond(CC);
1882 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1887 // Two-way Conditional branch. Insert the second branch.
1888 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
1894 /// isHReg - Test if the given register is a physical h register.
1895 static bool isHReg(unsigned Reg) {
1896 return X86::GR8_ABCD_HRegClass.contains(Reg);
1899 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1900 MachineBasicBlock::iterator MI,
1901 unsigned DestReg, unsigned SrcReg,
1902 const TargetRegisterClass *DestRC,
1903 const TargetRegisterClass *SrcRC) const {
1904 DebugLoc DL = MBB.findDebugLoc(MI);
1906 // Determine if DstRC and SrcRC have a common superclass in common.
1907 const TargetRegisterClass *CommonRC = DestRC;
1908 if (DestRC == SrcRC)
1909 /* Source and destination have the same register class. */;
1910 else if (CommonRC->hasSuperClass(SrcRC))
1912 else if (!DestRC->hasSubClass(SrcRC)) {
1913 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1914 // but we want to copy them as GR64. Similarly, for GR32_NOREX and
1915 // GR32_NOSP, copy as GR32.
1916 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1917 DestRC->hasSuperClass(&X86::GR64RegClass))
1918 CommonRC = &X86::GR64RegClass;
1919 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1920 DestRC->hasSuperClass(&X86::GR32RegClass))
1921 CommonRC = &X86::GR32RegClass;
1928 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1930 } else if (CommonRC == &X86::GR32RegClass ||
1931 CommonRC == &X86::GR32_NOSPRegClass) {
1933 } else if (CommonRC == &X86::GR16RegClass) {
1935 } else if (CommonRC == &X86::GR8RegClass) {
1936 // Copying to or from a physical H register on x86-64 requires a NOREX
1937 // move. Otherwise use a normal move.
1938 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1939 TM.getSubtarget<X86Subtarget>().is64Bit())
1940 Opc = X86::MOV8rr_NOREX;
1943 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1945 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1947 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1949 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1951 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1952 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1953 Opc = X86::MOV8rr_NOREX;
1956 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1957 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1959 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1961 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1963 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1965 } else if (CommonRC == &X86::GR64_TCRegClass) {
1966 Opc = X86::MOV64rr_TC;
1967 } else if (CommonRC == &X86::GR32_TCRegClass) {
1968 Opc = X86::MOV32rr_TC;
1969 } else if (CommonRC == &X86::RFP32RegClass) {
1970 Opc = X86::MOV_Fp3232;
1971 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1972 Opc = X86::MOV_Fp6464;
1973 } else if (CommonRC == &X86::RFP80RegClass) {
1974 Opc = X86::MOV_Fp8080;
1975 } else if (CommonRC == &X86::FR32RegClass) {
1976 Opc = X86::FsMOVAPSrr;
1977 } else if (CommonRC == &X86::FR64RegClass) {
1978 Opc = X86::FsMOVAPDrr;
1979 } else if (CommonRC == &X86::VR128RegClass) {
1980 Opc = X86::MOVAPSrr;
1981 } else if (CommonRC == &X86::VR64RegClass) {
1982 Opc = X86::MMX_MOVQ64rr;
1986 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1990 // Moving EFLAGS to / from another register requires a push and a pop.
1991 if (SrcRC == &X86::CCRRegClass) {
1992 if (SrcReg != X86::EFLAGS)
1994 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1995 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
1996 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1998 } else if (DestRC == &X86::GR32RegClass ||
1999 DestRC == &X86::GR32_NOSPRegClass) {
2000 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
2001 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2004 } else if (DestRC == &X86::CCRRegClass) {
2005 if (DestReg != X86::EFLAGS)
2007 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
2008 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
2009 BuildMI(MBB, MI, DL, get(X86::POPFQ));
2011 } else if (SrcRC == &X86::GR32RegClass ||
2012 DestRC == &X86::GR32_NOSPRegClass) {
2013 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
2014 BuildMI(MBB, MI, DL, get(X86::POPFD));
2019 // Moving from ST(0) turns into FpGET_ST0_32 etc.
2020 if (SrcRC == &X86::RSTRegClass) {
2021 // Copying from ST(0)/ST(1).
2022 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
2023 // Can only copy from ST(0)/ST(1) right now
2025 bool isST0 = SrcReg == X86::ST0;
2027 if (DestRC == &X86::RFP32RegClass)
2028 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
2029 else if (DestRC == &X86::RFP64RegClass)
2030 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
2032 if (DestRC != &X86::RFP80RegClass)
2034 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
2036 BuildMI(MBB, MI, DL, get(Opc), DestReg);
2040 // Moving to ST(0) turns into FpSET_ST0_32 etc.
2041 if (DestRC == &X86::RSTRegClass) {
2042 // Copying to ST(0) / ST(1).
2043 if (DestReg != X86::ST0 && DestReg != X86::ST1)
2044 // Can only copy to TOS right now
2046 bool isST0 = DestReg == X86::ST0;
2048 if (SrcRC == &X86::RFP32RegClass)
2049 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
2050 else if (SrcRC == &X86::RFP64RegClass)
2051 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
2053 if (SrcRC != &X86::RFP80RegClass)
2055 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
2057 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
2061 // Not yet supported!
2065 static unsigned getStoreRegOpcode(unsigned SrcReg,
2066 const TargetRegisterClass *RC,
2067 bool isStackAligned,
2068 TargetMachine &TM) {
2070 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2072 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2074 } else if (RC == &X86::GR16RegClass) {
2076 } else if (RC == &X86::GR8RegClass) {
2077 // Copying to or from a physical H register on x86-64 requires a NOREX
2078 // move. Otherwise use a normal move.
2079 if (isHReg(SrcReg) &&
2080 TM.getSubtarget<X86Subtarget>().is64Bit())
2081 Opc = X86::MOV8mr_NOREX;
2084 } else if (RC == &X86::GR64_ABCDRegClass) {
2086 } else if (RC == &X86::GR32_ABCDRegClass) {
2088 } else if (RC == &X86::GR16_ABCDRegClass) {
2090 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2092 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2093 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2094 Opc = X86::MOV8mr_NOREX;
2097 } else if (RC == &X86::GR64_NOREXRegClass ||
2098 RC == &X86::GR64_NOREX_NOSPRegClass) {
2100 } else if (RC == &X86::GR32_NOREXRegClass) {
2102 } else if (RC == &X86::GR16_NOREXRegClass) {
2104 } else if (RC == &X86::GR8_NOREXRegClass) {
2106 } else if (RC == &X86::GR64_TCRegClass) {
2107 Opc = X86::MOV64mr_TC;
2108 } else if (RC == &X86::GR32_TCRegClass) {
2109 Opc = X86::MOV32mr_TC;
2110 } else if (RC == &X86::RFP80RegClass) {
2111 Opc = X86::ST_FpP80m; // pops
2112 } else if (RC == &X86::RFP64RegClass) {
2113 Opc = X86::ST_Fp64m;
2114 } else if (RC == &X86::RFP32RegClass) {
2115 Opc = X86::ST_Fp32m;
2116 } else if (RC == &X86::FR32RegClass) {
2118 } else if (RC == &X86::FR64RegClass) {
2120 } else if (RC == &X86::VR128RegClass) {
2121 // If stack is realigned we can use aligned stores.
2122 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
2123 } else if (RC == &X86::VR64RegClass) {
2124 Opc = X86::MMX_MOVQ64mr;
2126 llvm_unreachable("Unknown regclass");
2132 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2133 MachineBasicBlock::iterator MI,
2134 unsigned SrcReg, bool isKill, int FrameIdx,
2135 const TargetRegisterClass *RC) const {
2136 const MachineFunction &MF = *MBB.getParent();
2137 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2138 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2139 DebugLoc DL = MBB.findDebugLoc(MI);
2140 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2141 .addReg(SrcReg, getKillRegState(isKill));
2144 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2146 SmallVectorImpl<MachineOperand> &Addr,
2147 const TargetRegisterClass *RC,
2148 MachineInstr::mmo_iterator MMOBegin,
2149 MachineInstr::mmo_iterator MMOEnd,
2150 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2151 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2152 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2154 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2155 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2156 MIB.addOperand(Addr[i]);
2157 MIB.addReg(SrcReg, getKillRegState(isKill));
2158 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2159 NewMIs.push_back(MIB);
2162 static unsigned getLoadRegOpcode(unsigned DestReg,
2163 const TargetRegisterClass *RC,
2164 bool isStackAligned,
2165 const TargetMachine &TM) {
2167 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2169 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2171 } else if (RC == &X86::GR16RegClass) {
2173 } else if (RC == &X86::GR8RegClass) {
2174 // Copying to or from a physical H register on x86-64 requires a NOREX
2175 // move. Otherwise use a normal move.
2176 if (isHReg(DestReg) &&
2177 TM.getSubtarget<X86Subtarget>().is64Bit())
2178 Opc = X86::MOV8rm_NOREX;
2181 } else if (RC == &X86::GR64_ABCDRegClass) {
2183 } else if (RC == &X86::GR32_ABCDRegClass) {
2185 } else if (RC == &X86::GR16_ABCDRegClass) {
2187 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2189 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2190 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2191 Opc = X86::MOV8rm_NOREX;
2194 } else if (RC == &X86::GR64_NOREXRegClass ||
2195 RC == &X86::GR64_NOREX_NOSPRegClass) {
2197 } else if (RC == &X86::GR32_NOREXRegClass) {
2199 } else if (RC == &X86::GR16_NOREXRegClass) {
2201 } else if (RC == &X86::GR8_NOREXRegClass) {
2203 } else if (RC == &X86::GR64_TCRegClass) {
2204 Opc = X86::MOV64rm_TC;
2205 } else if (RC == &X86::GR32_TCRegClass) {
2206 Opc = X86::MOV32rm_TC;
2207 } else if (RC == &X86::RFP80RegClass) {
2208 Opc = X86::LD_Fp80m;
2209 } else if (RC == &X86::RFP64RegClass) {
2210 Opc = X86::LD_Fp64m;
2211 } else if (RC == &X86::RFP32RegClass) {
2212 Opc = X86::LD_Fp32m;
2213 } else if (RC == &X86::FR32RegClass) {
2215 } else if (RC == &X86::FR64RegClass) {
2217 } else if (RC == &X86::VR128RegClass) {
2218 // If stack is realigned we can use aligned loads.
2219 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2220 } else if (RC == &X86::VR64RegClass) {
2221 Opc = X86::MMX_MOVQ64rm;
2223 llvm_unreachable("Unknown regclass");
2229 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2230 MachineBasicBlock::iterator MI,
2231 unsigned DestReg, int FrameIdx,
2232 const TargetRegisterClass *RC) const{
2233 const MachineFunction &MF = *MBB.getParent();
2234 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2235 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2236 DebugLoc DL = MBB.findDebugLoc(MI);
2237 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2240 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2241 SmallVectorImpl<MachineOperand> &Addr,
2242 const TargetRegisterClass *RC,
2243 MachineInstr::mmo_iterator MMOBegin,
2244 MachineInstr::mmo_iterator MMOEnd,
2245 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2246 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2247 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2249 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2250 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2251 MIB.addOperand(Addr[i]);
2252 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2253 NewMIs.push_back(MIB);
2256 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2257 MachineBasicBlock::iterator MI,
2258 const std::vector<CalleeSavedInfo> &CSI) const {
2262 DebugLoc DL = MBB.findDebugLoc(MI);
2264 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2265 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2266 unsigned SlotSize = is64Bit ? 8 : 4;
2268 MachineFunction &MF = *MBB.getParent();
2269 unsigned FPReg = RI.getFrameRegister(MF);
2270 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2271 unsigned CalleeFrameSize = 0;
2273 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2274 for (unsigned i = CSI.size(); i != 0; --i) {
2275 unsigned Reg = CSI[i-1].getReg();
2276 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2277 // Add the callee-saved register as live-in. It's killed at the spill.
2280 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2282 if (RegClass != &X86::VR128RegClass && !isWin64) {
2283 CalleeFrameSize += SlotSize;
2284 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2286 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2290 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2294 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2295 MachineBasicBlock::iterator MI,
2296 const std::vector<CalleeSavedInfo> &CSI) const {
2300 DebugLoc DL = MBB.findDebugLoc(MI);
2302 MachineFunction &MF = *MBB.getParent();
2303 unsigned FPReg = RI.getFrameRegister(MF);
2304 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2305 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2306 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2307 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2308 unsigned Reg = CSI[i].getReg();
2310 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2312 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2313 if (RegClass != &X86::VR128RegClass && !isWin64) {
2314 BuildMI(MBB, MI, DL, get(Opc), Reg);
2316 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2322 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2323 const SmallVectorImpl<MachineOperand> &MOs,
2325 const TargetInstrInfo &TII) {
2326 // Create the base instruction with the memory operand as the first part.
2327 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2328 MI->getDebugLoc(), true);
2329 MachineInstrBuilder MIB(NewMI);
2330 unsigned NumAddrOps = MOs.size();
2331 for (unsigned i = 0; i != NumAddrOps; ++i)
2332 MIB.addOperand(MOs[i]);
2333 if (NumAddrOps < 4) // FrameIndex only
2336 // Loop over the rest of the ri operands, converting them over.
2337 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2338 for (unsigned i = 0; i != NumOps; ++i) {
2339 MachineOperand &MO = MI->getOperand(i+2);
2342 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2343 MachineOperand &MO = MI->getOperand(i);
2349 static MachineInstr *FuseInst(MachineFunction &MF,
2350 unsigned Opcode, unsigned OpNo,
2351 const SmallVectorImpl<MachineOperand> &MOs,
2352 MachineInstr *MI, const TargetInstrInfo &TII) {
2353 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2354 MI->getDebugLoc(), true);
2355 MachineInstrBuilder MIB(NewMI);
2357 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2358 MachineOperand &MO = MI->getOperand(i);
2360 assert(MO.isReg() && "Expected to fold into reg operand!");
2361 unsigned NumAddrOps = MOs.size();
2362 for (unsigned i = 0; i != NumAddrOps; ++i)
2363 MIB.addOperand(MOs[i]);
2364 if (NumAddrOps < 4) // FrameIndex only
2373 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2374 const SmallVectorImpl<MachineOperand> &MOs,
2376 MachineFunction &MF = *MI->getParent()->getParent();
2377 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2379 unsigned NumAddrOps = MOs.size();
2380 for (unsigned i = 0; i != NumAddrOps; ++i)
2381 MIB.addOperand(MOs[i]);
2382 if (NumAddrOps < 4) // FrameIndex only
2384 return MIB.addImm(0);
2388 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2389 MachineInstr *MI, unsigned i,
2390 const SmallVectorImpl<MachineOperand> &MOs,
2391 unsigned Size, unsigned Align) const {
2392 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2393 bool isTwoAddrFold = false;
2394 unsigned NumOps = MI->getDesc().getNumOperands();
2395 bool isTwoAddr = NumOps > 1 &&
2396 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2398 MachineInstr *NewMI = NULL;
2399 // Folding a memory location into the two-address part of a two-address
2400 // instruction is different than folding it other places. It requires
2401 // replacing the *two* registers with the memory location.
2402 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2403 MI->getOperand(0).isReg() &&
2404 MI->getOperand(1).isReg() &&
2405 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2406 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2407 isTwoAddrFold = true;
2408 } else if (i == 0) { // If operand 0
2409 if (MI->getOpcode() == X86::MOV64r0)
2410 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2411 else if (MI->getOpcode() == X86::MOV32r0)
2412 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2413 else if (MI->getOpcode() == X86::MOV16r0)
2414 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2415 else if (MI->getOpcode() == X86::MOV8r0)
2416 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2420 OpcodeTablePtr = &RegOp2MemOpTable0;
2421 } else if (i == 1) {
2422 OpcodeTablePtr = &RegOp2MemOpTable1;
2423 } else if (i == 2) {
2424 OpcodeTablePtr = &RegOp2MemOpTable2;
2427 // If table selected...
2428 if (OpcodeTablePtr) {
2429 // Find the Opcode to fuse
2430 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2431 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2432 if (I != OpcodeTablePtr->end()) {
2433 unsigned Opcode = I->second.first;
2434 unsigned MinAlign = I->second.second;
2435 if (Align < MinAlign)
2437 bool NarrowToMOV32rm = false;
2439 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2440 if (Size < RCSize) {
2441 // Check if it's safe to fold the load. If the size of the object is
2442 // narrower than the load width, then it's not.
2443 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2445 // If this is a 64-bit load, but the spill slot is 32, then we can do
2446 // a 32-bit load which is implicitly zero-extended. This likely is due
2447 // to liveintervalanalysis remat'ing a load from stack slot.
2448 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2450 Opcode = X86::MOV32rm;
2451 NarrowToMOV32rm = true;
2456 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2458 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2460 if (NarrowToMOV32rm) {
2461 // If this is the special case where we use a MOV32rm to load a 32-bit
2462 // value and zero-extend the top bits. Change the destination register
2464 unsigned DstReg = NewMI->getOperand(0).getReg();
2465 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2466 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2467 4/*x86_subreg_32bit*/));
2469 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2476 if (PrintFailedFusing)
2477 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2482 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2484 const SmallVectorImpl<unsigned> &Ops,
2485 int FrameIndex) const {
2486 // Check switch flag
2487 if (NoFusing) return NULL;
2489 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2490 switch (MI->getOpcode()) {
2491 case X86::CVTSD2SSrr:
2492 case X86::Int_CVTSD2SSrr:
2493 case X86::CVTSS2SDrr:
2494 case X86::Int_CVTSS2SDrr:
2496 case X86::RCPSSr_Int:
2497 case X86::ROUNDSDr_Int:
2498 case X86::ROUNDSSr_Int:
2500 case X86::RSQRTSSr_Int:
2502 case X86::SQRTSSr_Int:
2506 const MachineFrameInfo *MFI = MF.getFrameInfo();
2507 unsigned Size = MFI->getObjectSize(FrameIndex);
2508 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2509 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2510 unsigned NewOpc = 0;
2511 unsigned RCSize = 0;
2512 switch (MI->getOpcode()) {
2513 default: return NULL;
2514 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2515 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2516 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2517 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2519 // Check if it's safe to fold the load. If the size of the object is
2520 // narrower than the load width, then it's not.
2523 // Change to CMPXXri r, 0 first.
2524 MI->setDesc(get(NewOpc));
2525 MI->getOperand(1).ChangeToImmediate(0);
2526 } else if (Ops.size() != 1)
2529 SmallVector<MachineOperand,4> MOs;
2530 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2531 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2534 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2536 const SmallVectorImpl<unsigned> &Ops,
2537 MachineInstr *LoadMI) const {
2538 // Check switch flag
2539 if (NoFusing) return NULL;
2541 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2542 switch (MI->getOpcode()) {
2543 case X86::CVTSD2SSrr:
2544 case X86::Int_CVTSD2SSrr:
2545 case X86::CVTSS2SDrr:
2546 case X86::Int_CVTSS2SDrr:
2548 case X86::RCPSSr_Int:
2549 case X86::ROUNDSDr_Int:
2550 case X86::ROUNDSSr_Int:
2552 case X86::RSQRTSSr_Int:
2554 case X86::SQRTSSr_Int:
2558 // Determine the alignment of the load.
2559 unsigned Alignment = 0;
2560 if (LoadMI->hasOneMemOperand())
2561 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2563 switch (LoadMI->getOpcode()) {
2567 case X86::V_SETALLONES:
2577 llvm_unreachable("Don't know how to fold this instruction!");
2579 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2580 unsigned NewOpc = 0;
2581 switch (MI->getOpcode()) {
2582 default: return NULL;
2583 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2584 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2585 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2586 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2588 // Change to CMPXXri r, 0 first.
2589 MI->setDesc(get(NewOpc));
2590 MI->getOperand(1).ChangeToImmediate(0);
2591 } else if (Ops.size() != 1)
2594 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2595 switch (LoadMI->getOpcode()) {
2599 case X86::V_SETALLONES:
2601 case X86::FsFLD0SS: {
2602 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2603 // Create a constant-pool entry and operands to load from it.
2605 // Medium and large mode can't fold loads this way.
2606 if (TM.getCodeModel() != CodeModel::Small &&
2607 TM.getCodeModel() != CodeModel::Kernel)
2610 // x86-32 PIC requires a PIC base register for constant pools.
2611 unsigned PICBase = 0;
2612 if (TM.getRelocationModel() == Reloc::PIC_) {
2613 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2616 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2617 // This doesn't work for several reasons.
2618 // 1. GlobalBaseReg may have been spilled.
2619 // 2. It may not be live at MI.
2623 // Create a constant-pool entry.
2624 MachineConstantPool &MCP = *MF.getConstantPool();
2626 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2627 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2628 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2629 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2631 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2632 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2633 Constant::getAllOnesValue(Ty) :
2634 Constant::getNullValue(Ty);
2635 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2637 // Create operands to load from the constant pool entry.
2638 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2639 MOs.push_back(MachineOperand::CreateImm(1));
2640 MOs.push_back(MachineOperand::CreateReg(0, false));
2641 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2642 MOs.push_back(MachineOperand::CreateReg(0, false));
2646 // Folding a normal load. Just copy the load's address operands.
2647 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2648 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2649 MOs.push_back(LoadMI->getOperand(i));
2653 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2657 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2658 const SmallVectorImpl<unsigned> &Ops) const {
2659 // Check switch flag
2660 if (NoFusing) return 0;
2662 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2663 switch (MI->getOpcode()) {
2664 default: return false;
2673 if (Ops.size() != 1)
2676 unsigned OpNum = Ops[0];
2677 unsigned Opc = MI->getOpcode();
2678 unsigned NumOps = MI->getDesc().getNumOperands();
2679 bool isTwoAddr = NumOps > 1 &&
2680 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2682 // Folding a memory location into the two-address part of a two-address
2683 // instruction is different than folding it other places. It requires
2684 // replacing the *two* registers with the memory location.
2685 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2686 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2687 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2688 } else if (OpNum == 0) { // If operand 0
2697 OpcodeTablePtr = &RegOp2MemOpTable0;
2698 } else if (OpNum == 1) {
2699 OpcodeTablePtr = &RegOp2MemOpTable1;
2700 } else if (OpNum == 2) {
2701 OpcodeTablePtr = &RegOp2MemOpTable2;
2704 if (OpcodeTablePtr) {
2705 // Find the Opcode to fuse
2706 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2707 OpcodeTablePtr->find((unsigned*)Opc);
2708 if (I != OpcodeTablePtr->end())
2714 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2715 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2716 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2717 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2718 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2719 if (I == MemOp2RegOpTable.end())
2721 unsigned Opc = I->second.first;
2722 unsigned Index = I->second.second & 0xf;
2723 bool FoldedLoad = I->second.second & (1 << 4);
2724 bool FoldedStore = I->second.second & (1 << 5);
2725 if (UnfoldLoad && !FoldedLoad)
2727 UnfoldLoad &= FoldedLoad;
2728 if (UnfoldStore && !FoldedStore)
2730 UnfoldStore &= FoldedStore;
2732 const TargetInstrDesc &TID = get(Opc);
2733 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2734 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2735 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2736 SmallVector<MachineOperand,2> BeforeOps;
2737 SmallVector<MachineOperand,2> AfterOps;
2738 SmallVector<MachineOperand,4> ImpOps;
2739 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2740 MachineOperand &Op = MI->getOperand(i);
2741 if (i >= Index && i < Index + X86AddrNumOperands)
2742 AddrOps.push_back(Op);
2743 else if (Op.isReg() && Op.isImplicit())
2744 ImpOps.push_back(Op);
2746 BeforeOps.push_back(Op);
2748 AfterOps.push_back(Op);
2751 // Emit the load instruction.
2753 std::pair<MachineInstr::mmo_iterator,
2754 MachineInstr::mmo_iterator> MMOs =
2755 MF.extractLoadMemRefs(MI->memoperands_begin(),
2756 MI->memoperands_end());
2757 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2759 // Address operands cannot be marked isKill.
2760 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2761 MachineOperand &MO = NewMIs[0]->getOperand(i);
2763 MO.setIsKill(false);
2768 // Emit the data processing instruction.
2769 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2770 MachineInstrBuilder MIB(DataMI);
2773 MIB.addReg(Reg, RegState::Define);
2774 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2775 MIB.addOperand(BeforeOps[i]);
2778 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2779 MIB.addOperand(AfterOps[i]);
2780 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2781 MachineOperand &MO = ImpOps[i];
2782 MIB.addReg(MO.getReg(),
2783 getDefRegState(MO.isDef()) |
2784 RegState::Implicit |
2785 getKillRegState(MO.isKill()) |
2786 getDeadRegState(MO.isDead()) |
2787 getUndefRegState(MO.isUndef()));
2789 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2790 unsigned NewOpc = 0;
2791 switch (DataMI->getOpcode()) {
2793 case X86::CMP64ri32:
2797 MachineOperand &MO0 = DataMI->getOperand(0);
2798 MachineOperand &MO1 = DataMI->getOperand(1);
2799 if (MO1.getImm() == 0) {
2800 switch (DataMI->getOpcode()) {
2802 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2803 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2804 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2805 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2807 DataMI->setDesc(get(NewOpc));
2808 MO1.ChangeToRegister(MO0.getReg(), false);
2812 NewMIs.push_back(DataMI);
2814 // Emit the store instruction.
2816 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2817 std::pair<MachineInstr::mmo_iterator,
2818 MachineInstr::mmo_iterator> MMOs =
2819 MF.extractStoreMemRefs(MI->memoperands_begin(),
2820 MI->memoperands_end());
2821 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2828 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2829 SmallVectorImpl<SDNode*> &NewNodes) const {
2830 if (!N->isMachineOpcode())
2833 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2834 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2835 if (I == MemOp2RegOpTable.end())
2837 unsigned Opc = I->second.first;
2838 unsigned Index = I->second.second & 0xf;
2839 bool FoldedLoad = I->second.second & (1 << 4);
2840 bool FoldedStore = I->second.second & (1 << 5);
2841 const TargetInstrDesc &TID = get(Opc);
2842 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2843 unsigned NumDefs = TID.NumDefs;
2844 std::vector<SDValue> AddrOps;
2845 std::vector<SDValue> BeforeOps;
2846 std::vector<SDValue> AfterOps;
2847 DebugLoc dl = N->getDebugLoc();
2848 unsigned NumOps = N->getNumOperands();
2849 for (unsigned i = 0; i != NumOps-1; ++i) {
2850 SDValue Op = N->getOperand(i);
2851 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2852 AddrOps.push_back(Op);
2853 else if (i < Index-NumDefs)
2854 BeforeOps.push_back(Op);
2855 else if (i > Index-NumDefs)
2856 AfterOps.push_back(Op);
2858 SDValue Chain = N->getOperand(NumOps-1);
2859 AddrOps.push_back(Chain);
2861 // Emit the load instruction.
2863 MachineFunction &MF = DAG.getMachineFunction();
2865 EVT VT = *RC->vt_begin();
2866 std::pair<MachineInstr::mmo_iterator,
2867 MachineInstr::mmo_iterator> MMOs =
2868 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2869 cast<MachineSDNode>(N)->memoperands_end());
2870 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2871 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2872 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2873 NewNodes.push_back(Load);
2875 // Preserve memory reference information.
2876 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2879 // Emit the data processing instruction.
2880 std::vector<EVT> VTs;
2881 const TargetRegisterClass *DstRC = 0;
2882 if (TID.getNumDefs() > 0) {
2883 DstRC = TID.OpInfo[0].getRegClass(&RI);
2884 VTs.push_back(*DstRC->vt_begin());
2886 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2887 EVT VT = N->getValueType(i);
2888 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2892 BeforeOps.push_back(SDValue(Load, 0));
2893 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2894 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2896 NewNodes.push_back(NewNode);
2898 // Emit the store instruction.
2901 AddrOps.push_back(SDValue(NewNode, 0));
2902 AddrOps.push_back(Chain);
2903 std::pair<MachineInstr::mmo_iterator,
2904 MachineInstr::mmo_iterator> MMOs =
2905 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2906 cast<MachineSDNode>(N)->memoperands_end());
2907 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2908 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2911 &AddrOps[0], AddrOps.size());
2912 NewNodes.push_back(Store);
2914 // Preserve memory reference information.
2915 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2921 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2922 bool UnfoldLoad, bool UnfoldStore,
2923 unsigned *LoadRegIndex) const {
2924 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2925 MemOp2RegOpTable.find((unsigned*)Opc);
2926 if (I == MemOp2RegOpTable.end())
2928 bool FoldedLoad = I->second.second & (1 << 4);
2929 bool FoldedStore = I->second.second & (1 << 5);
2930 if (UnfoldLoad && !FoldedLoad)
2932 if (UnfoldStore && !FoldedStore)
2935 *LoadRegIndex = I->second.second & 0xf;
2936 return I->second.first;
2940 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2941 int64_t &Offset1, int64_t &Offset2) const {
2942 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2944 unsigned Opc1 = Load1->getMachineOpcode();
2945 unsigned Opc2 = Load2->getMachineOpcode();
2947 default: return false;
2957 case X86::MMX_MOVD64rm:
2958 case X86::MMX_MOVQ64rm:
2959 case X86::FsMOVAPSrm:
2960 case X86::FsMOVAPDrm:
2963 case X86::MOVUPSrm_Int:
2967 case X86::MOVDQUrm_Int:
2971 default: return false;
2981 case X86::MMX_MOVD64rm:
2982 case X86::MMX_MOVQ64rm:
2983 case X86::FsMOVAPSrm:
2984 case X86::FsMOVAPDrm:
2987 case X86::MOVUPSrm_Int:
2991 case X86::MOVDQUrm_Int:
2995 // Check if chain operands and base addresses match.
2996 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2997 Load1->getOperand(5) != Load2->getOperand(5))
2999 // Segment operands should match as well.
3000 if (Load1->getOperand(4) != Load2->getOperand(4))
3002 // Scale should be 1, Index should be Reg0.
3003 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3004 Load1->getOperand(2) == Load2->getOperand(2)) {
3005 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3008 // Now let's examine the displacements.
3009 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3010 isa<ConstantSDNode>(Load2->getOperand(3))) {
3011 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3012 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3019 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3020 int64_t Offset1, int64_t Offset2,
3021 unsigned NumLoads) const {
3022 assert(Offset2 > Offset1);
3023 if ((Offset2 - Offset1) / 8 > 64)
3026 unsigned Opc1 = Load1->getMachineOpcode();
3027 unsigned Opc2 = Load2->getMachineOpcode();
3029 return false; // FIXME: overly conservative?
3036 case X86::MMX_MOVD64rm:
3037 case X86::MMX_MOVQ64rm:
3041 EVT VT = Load1->getValueType(0);
3042 switch (VT.getSimpleVT().SimpleTy) {
3044 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3045 // have 16 of them to play with.
3046 if (TM.getSubtargetImpl()->is64Bit()) {
3049 } else if (NumLoads)
3068 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3069 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3070 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3071 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3073 Cond[0].setImm(GetOppositeBranchCondition(CC));
3078 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3079 // FIXME: Return false for x87 stack register classes for now. We can't
3080 // allow any loads of these registers before FpGet_ST0_80.
3081 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3082 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3086 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3087 /// register? e.g. r8, xmm8, xmm13, etc.
3088 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3091 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3092 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3093 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3094 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3095 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3096 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3097 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3098 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3099 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3100 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3107 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
3108 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
3109 /// size, and 3) use of X86-64 extended registers.
3110 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
3112 const TargetInstrDesc &Desc = MI.getDesc();
3114 // Pseudo instructions do not need REX prefix byte.
3115 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
3117 if (Desc.TSFlags & X86II::REX_W)
3120 unsigned NumOps = Desc.getNumOperands();
3122 bool isTwoAddr = NumOps > 1 &&
3123 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
3125 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
3126 unsigned i = isTwoAddr ? 1 : 0;
3127 for (unsigned e = NumOps; i != e; ++i) {
3128 const MachineOperand& MO = MI.getOperand(i);
3130 unsigned Reg = MO.getReg();
3131 if (isX86_64NonExtLowByteReg(Reg))
3136 switch (Desc.TSFlags & X86II::FormMask) {
3137 case X86II::MRMInitReg:
3138 if (isX86_64ExtendedReg(MI.getOperand(0)))
3139 REX |= (1 << 0) | (1 << 2);
3141 case X86II::MRMSrcReg: {
3142 if (isX86_64ExtendedReg(MI.getOperand(0)))
3144 i = isTwoAddr ? 2 : 1;
3145 for (unsigned e = NumOps; i != e; ++i) {
3146 const MachineOperand& MO = MI.getOperand(i);
3147 if (isX86_64ExtendedReg(MO))
3152 case X86II::MRMSrcMem: {
3153 if (isX86_64ExtendedReg(MI.getOperand(0)))
3156 i = isTwoAddr ? 2 : 1;
3157 for (; i != NumOps; ++i) {
3158 const MachineOperand& MO = MI.getOperand(i);
3160 if (isX86_64ExtendedReg(MO))
3167 case X86II::MRM0m: case X86II::MRM1m:
3168 case X86II::MRM2m: case X86II::MRM3m:
3169 case X86II::MRM4m: case X86II::MRM5m:
3170 case X86II::MRM6m: case X86II::MRM7m:
3171 case X86II::MRMDestMem: {
3172 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
3173 i = isTwoAddr ? 1 : 0;
3174 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
3177 for (; i != e; ++i) {
3178 const MachineOperand& MO = MI.getOperand(i);
3180 if (isX86_64ExtendedReg(MO))
3188 if (isX86_64ExtendedReg(MI.getOperand(0)))
3190 i = isTwoAddr ? 2 : 1;
3191 for (unsigned e = NumOps; i != e; ++i) {
3192 const MachineOperand& MO = MI.getOperand(i);
3193 if (isX86_64ExtendedReg(MO))
3203 /// sizePCRelativeBlockAddress - This method returns the size of a PC
3204 /// relative block address instruction
3206 static unsigned sizePCRelativeBlockAddress() {
3210 /// sizeGlobalAddress - Give the size of the emission of this global address
3212 static unsigned sizeGlobalAddress(bool dword) {
3213 return dword ? 8 : 4;
3216 /// sizeConstPoolAddress - Give the size of the emission of this constant
3219 static unsigned sizeConstPoolAddress(bool dword) {
3220 return dword ? 8 : 4;
3223 /// sizeExternalSymbolAddress - Give the size of the emission of this external
3226 static unsigned sizeExternalSymbolAddress(bool dword) {
3227 return dword ? 8 : 4;
3230 /// sizeJumpTableAddress - Give the size of the emission of this jump
3233 static unsigned sizeJumpTableAddress(bool dword) {
3234 return dword ? 8 : 4;
3237 static unsigned sizeConstant(unsigned Size) {
3241 static unsigned sizeRegModRMByte(){
3245 static unsigned sizeSIBByte(){
3249 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3250 unsigned FinalSize = 0;
3251 // If this is a simple integer displacement that doesn't require a relocation.
3253 FinalSize += sizeConstant(4);
3257 // Otherwise, this is something that requires a relocation.
3258 if (RelocOp->isGlobal()) {
3259 FinalSize += sizeGlobalAddress(false);
3260 } else if (RelocOp->isCPI()) {
3261 FinalSize += sizeConstPoolAddress(false);
3262 } else if (RelocOp->isJTI()) {
3263 FinalSize += sizeJumpTableAddress(false);
3265 llvm_unreachable("Unknown value to relocate!");
3270 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3271 bool IsPIC, bool Is64BitMode) {
3272 const MachineOperand &Op3 = MI.getOperand(Op+3);
3274 const MachineOperand *DispForReloc = 0;
3275 unsigned FinalSize = 0;
3277 // Figure out what sort of displacement we have to handle here.
3278 if (Op3.isGlobal()) {
3279 DispForReloc = &Op3;
3280 } else if (Op3.isCPI()) {
3281 if (Is64BitMode || IsPIC) {
3282 DispForReloc = &Op3;
3286 } else if (Op3.isJTI()) {
3287 if (Is64BitMode || IsPIC) {
3288 DispForReloc = &Op3;
3296 const MachineOperand &Base = MI.getOperand(Op);
3297 const MachineOperand &IndexReg = MI.getOperand(Op+2);
3299 unsigned BaseReg = Base.getReg();
3301 // Is a SIB byte needed?
3302 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3303 IndexReg.getReg() == 0 &&
3304 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3305 if (BaseReg == 0) { // Just a displacement?
3306 // Emit special case [disp32] encoding
3308 FinalSize += getDisplacementFieldSize(DispForReloc);
3310 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3311 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3312 // Emit simple indirect register encoding... [EAX] f.e.
3314 // Be pessimistic and assume it's a disp32, not a disp8
3316 // Emit the most general non-SIB encoding: [REG+disp32]
3318 FinalSize += getDisplacementFieldSize(DispForReloc);
3322 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
3323 assert(IndexReg.getReg() != X86::ESP &&
3324 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3326 bool ForceDisp32 = false;
3327 if (BaseReg == 0 || DispForReloc) {
3328 // Emit the normal disp32 encoding.
3335 FinalSize += sizeSIBByte();
3337 // Do we need to output a displacement?
3338 if (DispVal != 0 || ForceDisp32) {
3339 FinalSize += getDisplacementFieldSize(DispForReloc);
3346 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3347 const TargetInstrDesc *Desc,
3348 bool IsPIC, bool Is64BitMode) {
3350 unsigned Opcode = Desc->Opcode;
3351 unsigned FinalSize = 0;
3353 // Emit the lock opcode prefix as needed.
3354 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3356 // Emit segment override opcode prefix as needed.
3357 switch (Desc->TSFlags & X86II::SegOvrMask) {
3362 default: llvm_unreachable("Invalid segment!");
3363 case 0: break; // No segment override!
3366 // Emit the repeat opcode prefix as needed.
3367 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3369 // Emit the operand size opcode prefix as needed.
3370 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3372 // Emit the address size opcode prefix as needed.
3373 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3375 bool Need0FPrefix = false;
3376 switch (Desc->TSFlags & X86II::Op0Mask) {
3377 case X86II::TB: // Two-byte opcode prefix
3378 case X86II::T8: // 0F 38
3379 case X86II::TA: // 0F 3A
3380 Need0FPrefix = true;
3382 case X86II::TF: // F2 0F 38
3384 Need0FPrefix = true;
3386 case X86II::REP: break; // already handled.
3387 case X86II::XS: // F3 0F
3389 Need0FPrefix = true;
3391 case X86II::XD: // F2 0F
3393 Need0FPrefix = true;
3395 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3396 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3398 break; // Two-byte opcode prefix
3399 default: llvm_unreachable("Invalid prefix!");
3400 case 0: break; // No prefix!
3405 unsigned REX = X86InstrInfo::determineREX(MI);
3410 // 0x0F escape code must be emitted just before the opcode.
3414 switch (Desc->TSFlags & X86II::Op0Mask) {
3415 case X86II::T8: // 0F 38
3418 case X86II::TA: // 0F 3A
3421 case X86II::TF: // F2 0F 38
3426 // If this is a two-address instruction, skip one of the register operands.
3427 unsigned NumOps = Desc->getNumOperands();
3429 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3431 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3432 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3435 switch (Desc->TSFlags & X86II::FormMask) {
3436 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3438 // Remember the current PC offset, this is the PIC relocation
3443 case TargetOpcode::INLINEASM: {
3444 const MachineFunction *MF = MI.getParent()->getParent();
3445 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3446 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3447 *MF->getTarget().getMCAsmInfo());
3450 case TargetOpcode::DBG_LABEL:
3451 case TargetOpcode::EH_LABEL:
3452 case TargetOpcode::DBG_VALUE:
3454 case TargetOpcode::IMPLICIT_DEF:
3455 case TargetOpcode::KILL:
3456 case X86::FP_REG_KILL:
3458 case X86::MOVPC32r: {
3459 // This emits the "call" portion of this pseudo instruction.
3461 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3470 if (CurOp != NumOps) {
3471 const MachineOperand &MO = MI.getOperand(CurOp++);
3473 FinalSize += sizePCRelativeBlockAddress();
3474 } else if (MO.isGlobal()) {
3475 FinalSize += sizeGlobalAddress(false);
3476 } else if (MO.isSymbol()) {
3477 FinalSize += sizeExternalSymbolAddress(false);
3478 } else if (MO.isImm()) {
3479 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3481 llvm_unreachable("Unknown RawFrm operand!");
3486 case X86II::AddRegFrm:
3490 if (CurOp != NumOps) {
3491 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3492 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3494 FinalSize += sizeConstant(Size);
3497 if (Opcode == X86::MOV64ri)
3499 if (MO1.isGlobal()) {
3500 FinalSize += sizeGlobalAddress(dword);
3501 } else if (MO1.isSymbol())
3502 FinalSize += sizeExternalSymbolAddress(dword);
3503 else if (MO1.isCPI())
3504 FinalSize += sizeConstPoolAddress(dword);
3505 else if (MO1.isJTI())
3506 FinalSize += sizeJumpTableAddress(dword);
3511 case X86II::MRMDestReg: {
3513 FinalSize += sizeRegModRMByte();
3515 if (CurOp != NumOps) {
3517 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3521 case X86II::MRMDestMem: {
3523 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3524 CurOp += X86AddrNumOperands + 1;
3525 if (CurOp != NumOps) {
3527 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3532 case X86II::MRMSrcReg:
3534 FinalSize += sizeRegModRMByte();
3536 if (CurOp != NumOps) {
3538 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3542 case X86II::MRMSrcMem: {
3544 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3545 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3546 AddrOperands = X86AddrNumOperands - 1; // No segment register
3548 AddrOperands = X86AddrNumOperands;
3551 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3552 CurOp += AddrOperands + 1;
3553 if (CurOp != NumOps) {
3555 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3560 case X86II::MRM0r: case X86II::MRM1r:
3561 case X86II::MRM2r: case X86II::MRM3r:
3562 case X86II::MRM4r: case X86II::MRM5r:
3563 case X86II::MRM6r: case X86II::MRM7r:
3565 if (Desc->getOpcode() == X86::LFENCE ||
3566 Desc->getOpcode() == X86::MFENCE) {
3567 // Special handling of lfence and mfence;
3568 FinalSize += sizeRegModRMByte();
3569 } else if (Desc->getOpcode() == X86::MONITOR ||
3570 Desc->getOpcode() == X86::MWAIT) {
3571 // Special handling of monitor and mwait.
3572 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3575 FinalSize += sizeRegModRMByte();
3578 if (CurOp != NumOps) {
3579 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3580 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3582 FinalSize += sizeConstant(Size);
3585 if (Opcode == X86::MOV64ri32)
3587 if (MO1.isGlobal()) {
3588 FinalSize += sizeGlobalAddress(dword);
3589 } else if (MO1.isSymbol())
3590 FinalSize += sizeExternalSymbolAddress(dword);
3591 else if (MO1.isCPI())
3592 FinalSize += sizeConstPoolAddress(dword);
3593 else if (MO1.isJTI())
3594 FinalSize += sizeJumpTableAddress(dword);
3599 case X86II::MRM0m: case X86II::MRM1m:
3600 case X86II::MRM2m: case X86II::MRM3m:
3601 case X86II::MRM4m: case X86II::MRM5m:
3602 case X86II::MRM6m: case X86II::MRM7m: {
3605 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3606 CurOp += X86AddrNumOperands;
3608 if (CurOp != NumOps) {
3609 const MachineOperand &MO = MI.getOperand(CurOp++);
3610 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3612 FinalSize += sizeConstant(Size);
3615 if (Opcode == X86::MOV64mi32)
3617 if (MO.isGlobal()) {
3618 FinalSize += sizeGlobalAddress(dword);
3619 } else if (MO.isSymbol())
3620 FinalSize += sizeExternalSymbolAddress(dword);
3621 else if (MO.isCPI())
3622 FinalSize += sizeConstPoolAddress(dword);
3623 else if (MO.isJTI())
3624 FinalSize += sizeJumpTableAddress(dword);
3638 case X86II::MRMInitReg:
3640 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3641 FinalSize += sizeRegModRMByte();
3646 if (!Desc->isVariadic() && CurOp != NumOps) {
3648 raw_string_ostream Msg(msg);
3649 Msg << "Cannot determine size: " << MI;
3650 report_fatal_error(Msg.str());
3658 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3659 const TargetInstrDesc &Desc = MI->getDesc();
3660 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3661 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3662 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3663 if (Desc.getOpcode() == X86::MOVPC32r)
3664 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3668 /// getGlobalBaseReg - Return a virtual register initialized with the
3669 /// the global base register value. Output instructions required to
3670 /// initialize the register in the function entry block, if necessary.
3672 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3673 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3674 "X86-64 PIC uses RIP relative addressing");
3676 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3677 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3678 if (GlobalBaseReg != 0)
3679 return GlobalBaseReg;
3681 // Insert the set of GlobalBaseReg into the first MBB of the function
3682 MachineBasicBlock &FirstMBB = MF->front();
3683 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3684 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3685 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3686 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3688 const TargetInstrInfo *TII = TM.getInstrInfo();
3689 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3690 // only used in JIT code emission as displacement to pc.
3691 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3693 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3694 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3695 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3696 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3697 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3698 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3699 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3700 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3705 X86FI->setGlobalBaseReg(GlobalBaseReg);
3706 return GlobalBaseReg;
3709 // These are the replaceable SSE instructions. Some of these have Int variants
3710 // that we don't include here. We don't want to replace instructions selected
3712 static const unsigned ReplaceableInstrs[][3] = {
3713 //PackedInt PackedSingle PackedDouble
3714 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3715 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3716 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3717 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3718 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3719 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3720 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3721 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3722 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3723 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3724 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3725 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3726 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3727 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3728 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3731 // FIXME: Some shuffle and unpack instructions have equivalents in different
3732 // domains, but they require a bit more work than just switching opcodes.
3734 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3735 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3736 if (ReplaceableInstrs[i][domain-1] == opcode)
3737 return ReplaceableInstrs[i];
3741 std::pair<uint16_t, uint16_t>
3742 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3743 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3744 return std::make_pair(domain,
3745 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3748 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3749 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3750 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3751 assert(dom && "Not an SSE instruction");
3752 const unsigned *table = lookup(MI->getOpcode(), dom);
3753 assert(table && "Cannot change domain");
3754 MI->setDesc(get(table[Domain-1]));