1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetAsmInfo.h"
34 // FIXME: This should be some header
35 static const int X86AddrNumOperands = 4;
39 NoFusing("disable-spill-fusing",
40 cl::desc("Disable fusing of spill code into instructions"));
42 PrintFailedFusing("print-failed-fuse-candidates",
43 cl::desc("Print instructions that the allocator wants to"
44 " fuse, but the X86 backend currently can't"),
47 ReMatPICStubLoad("remat-pic-stub-load",
48 cl::desc("Re-materialize load from stub in PIC mode"),
49 cl::init(false), cl::Hidden);
52 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
53 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
54 TM(tm), RI(tm, *this) {
55 SmallVector<unsigned,16> AmbEntries;
56 static const unsigned OpTbl2Addr[][2] = {
57 { X86::ADC32ri, X86::ADC32mi },
58 { X86::ADC32ri8, X86::ADC32mi8 },
59 { X86::ADC32rr, X86::ADC32mr },
60 { X86::ADC64ri32, X86::ADC64mi32 },
61 { X86::ADC64ri8, X86::ADC64mi8 },
62 { X86::ADC64rr, X86::ADC64mr },
63 { X86::ADD16ri, X86::ADD16mi },
64 { X86::ADD16ri8, X86::ADD16mi8 },
65 { X86::ADD16rr, X86::ADD16mr },
66 { X86::ADD32ri, X86::ADD32mi },
67 { X86::ADD32ri8, X86::ADD32mi8 },
68 { X86::ADD32rr, X86::ADD32mr },
69 { X86::ADD64ri32, X86::ADD64mi32 },
70 { X86::ADD64ri8, X86::ADD64mi8 },
71 { X86::ADD64rr, X86::ADD64mr },
72 { X86::ADD8ri, X86::ADD8mi },
73 { X86::ADD8rr, X86::ADD8mr },
74 { X86::AND16ri, X86::AND16mi },
75 { X86::AND16ri8, X86::AND16mi8 },
76 { X86::AND16rr, X86::AND16mr },
77 { X86::AND32ri, X86::AND32mi },
78 { X86::AND32ri8, X86::AND32mi8 },
79 { X86::AND32rr, X86::AND32mr },
80 { X86::AND64ri32, X86::AND64mi32 },
81 { X86::AND64ri8, X86::AND64mi8 },
82 { X86::AND64rr, X86::AND64mr },
83 { X86::AND8ri, X86::AND8mi },
84 { X86::AND8rr, X86::AND8mr },
85 { X86::DEC16r, X86::DEC16m },
86 { X86::DEC32r, X86::DEC32m },
87 { X86::DEC64_16r, X86::DEC64_16m },
88 { X86::DEC64_32r, X86::DEC64_32m },
89 { X86::DEC64r, X86::DEC64m },
90 { X86::DEC8r, X86::DEC8m },
91 { X86::INC16r, X86::INC16m },
92 { X86::INC32r, X86::INC32m },
93 { X86::INC64_16r, X86::INC64_16m },
94 { X86::INC64_32r, X86::INC64_32m },
95 { X86::INC64r, X86::INC64m },
96 { X86::INC8r, X86::INC8m },
97 { X86::NEG16r, X86::NEG16m },
98 { X86::NEG32r, X86::NEG32m },
99 { X86::NEG64r, X86::NEG64m },
100 { X86::NEG8r, X86::NEG8m },
101 { X86::NOT16r, X86::NOT16m },
102 { X86::NOT32r, X86::NOT32m },
103 { X86::NOT64r, X86::NOT64m },
104 { X86::NOT8r, X86::NOT8m },
105 { X86::OR16ri, X86::OR16mi },
106 { X86::OR16ri8, X86::OR16mi8 },
107 { X86::OR16rr, X86::OR16mr },
108 { X86::OR32ri, X86::OR32mi },
109 { X86::OR32ri8, X86::OR32mi8 },
110 { X86::OR32rr, X86::OR32mr },
111 { X86::OR64ri32, X86::OR64mi32 },
112 { X86::OR64ri8, X86::OR64mi8 },
113 { X86::OR64rr, X86::OR64mr },
114 { X86::OR8ri, X86::OR8mi },
115 { X86::OR8rr, X86::OR8mr },
116 { X86::ROL16r1, X86::ROL16m1 },
117 { X86::ROL16rCL, X86::ROL16mCL },
118 { X86::ROL16ri, X86::ROL16mi },
119 { X86::ROL32r1, X86::ROL32m1 },
120 { X86::ROL32rCL, X86::ROL32mCL },
121 { X86::ROL32ri, X86::ROL32mi },
122 { X86::ROL64r1, X86::ROL64m1 },
123 { X86::ROL64rCL, X86::ROL64mCL },
124 { X86::ROL64ri, X86::ROL64mi },
125 { X86::ROL8r1, X86::ROL8m1 },
126 { X86::ROL8rCL, X86::ROL8mCL },
127 { X86::ROL8ri, X86::ROL8mi },
128 { X86::ROR16r1, X86::ROR16m1 },
129 { X86::ROR16rCL, X86::ROR16mCL },
130 { X86::ROR16ri, X86::ROR16mi },
131 { X86::ROR32r1, X86::ROR32m1 },
132 { X86::ROR32rCL, X86::ROR32mCL },
133 { X86::ROR32ri, X86::ROR32mi },
134 { X86::ROR64r1, X86::ROR64m1 },
135 { X86::ROR64rCL, X86::ROR64mCL },
136 { X86::ROR64ri, X86::ROR64mi },
137 { X86::ROR8r1, X86::ROR8m1 },
138 { X86::ROR8rCL, X86::ROR8mCL },
139 { X86::ROR8ri, X86::ROR8mi },
140 { X86::SAR16r1, X86::SAR16m1 },
141 { X86::SAR16rCL, X86::SAR16mCL },
142 { X86::SAR16ri, X86::SAR16mi },
143 { X86::SAR32r1, X86::SAR32m1 },
144 { X86::SAR32rCL, X86::SAR32mCL },
145 { X86::SAR32ri, X86::SAR32mi },
146 { X86::SAR64r1, X86::SAR64m1 },
147 { X86::SAR64rCL, X86::SAR64mCL },
148 { X86::SAR64ri, X86::SAR64mi },
149 { X86::SAR8r1, X86::SAR8m1 },
150 { X86::SAR8rCL, X86::SAR8mCL },
151 { X86::SAR8ri, X86::SAR8mi },
152 { X86::SBB32ri, X86::SBB32mi },
153 { X86::SBB32ri8, X86::SBB32mi8 },
154 { X86::SBB32rr, X86::SBB32mr },
155 { X86::SBB64ri32, X86::SBB64mi32 },
156 { X86::SBB64ri8, X86::SBB64mi8 },
157 { X86::SBB64rr, X86::SBB64mr },
158 { X86::SHL16rCL, X86::SHL16mCL },
159 { X86::SHL16ri, X86::SHL16mi },
160 { X86::SHL32rCL, X86::SHL32mCL },
161 { X86::SHL32ri, X86::SHL32mi },
162 { X86::SHL64rCL, X86::SHL64mCL },
163 { X86::SHL64ri, X86::SHL64mi },
164 { X86::SHL8rCL, X86::SHL8mCL },
165 { X86::SHL8ri, X86::SHL8mi },
166 { X86::SHLD16rrCL, X86::SHLD16mrCL },
167 { X86::SHLD16rri8, X86::SHLD16mri8 },
168 { X86::SHLD32rrCL, X86::SHLD32mrCL },
169 { X86::SHLD32rri8, X86::SHLD32mri8 },
170 { X86::SHLD64rrCL, X86::SHLD64mrCL },
171 { X86::SHLD64rri8, X86::SHLD64mri8 },
172 { X86::SHR16r1, X86::SHR16m1 },
173 { X86::SHR16rCL, X86::SHR16mCL },
174 { X86::SHR16ri, X86::SHR16mi },
175 { X86::SHR32r1, X86::SHR32m1 },
176 { X86::SHR32rCL, X86::SHR32mCL },
177 { X86::SHR32ri, X86::SHR32mi },
178 { X86::SHR64r1, X86::SHR64m1 },
179 { X86::SHR64rCL, X86::SHR64mCL },
180 { X86::SHR64ri, X86::SHR64mi },
181 { X86::SHR8r1, X86::SHR8m1 },
182 { X86::SHR8rCL, X86::SHR8mCL },
183 { X86::SHR8ri, X86::SHR8mi },
184 { X86::SHRD16rrCL, X86::SHRD16mrCL },
185 { X86::SHRD16rri8, X86::SHRD16mri8 },
186 { X86::SHRD32rrCL, X86::SHRD32mrCL },
187 { X86::SHRD32rri8, X86::SHRD32mri8 },
188 { X86::SHRD64rrCL, X86::SHRD64mrCL },
189 { X86::SHRD64rri8, X86::SHRD64mri8 },
190 { X86::SUB16ri, X86::SUB16mi },
191 { X86::SUB16ri8, X86::SUB16mi8 },
192 { X86::SUB16rr, X86::SUB16mr },
193 { X86::SUB32ri, X86::SUB32mi },
194 { X86::SUB32ri8, X86::SUB32mi8 },
195 { X86::SUB32rr, X86::SUB32mr },
196 { X86::SUB64ri32, X86::SUB64mi32 },
197 { X86::SUB64ri8, X86::SUB64mi8 },
198 { X86::SUB64rr, X86::SUB64mr },
199 { X86::SUB8ri, X86::SUB8mi },
200 { X86::SUB8rr, X86::SUB8mr },
201 { X86::XOR16ri, X86::XOR16mi },
202 { X86::XOR16ri8, X86::XOR16mi8 },
203 { X86::XOR16rr, X86::XOR16mr },
204 { X86::XOR32ri, X86::XOR32mi },
205 { X86::XOR32ri8, X86::XOR32mi8 },
206 { X86::XOR32rr, X86::XOR32mr },
207 { X86::XOR64ri32, X86::XOR64mi32 },
208 { X86::XOR64ri8, X86::XOR64mi8 },
209 { X86::XOR64rr, X86::XOR64mr },
210 { X86::XOR8ri, X86::XOR8mi },
211 { X86::XOR8rr, X86::XOR8mr }
214 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
215 unsigned RegOp = OpTbl2Addr[i][0];
216 unsigned MemOp = OpTbl2Addr[i][1];
217 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
219 assert(false && "Duplicated entries?");
220 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
221 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
222 std::make_pair(RegOp,
224 AmbEntries.push_back(MemOp);
227 // If the third value is 1, then it's folding either a load or a store.
228 static const unsigned OpTbl0[][3] = {
229 { X86::BT16ri8, X86::BT16mi8, 1 },
230 { X86::BT32ri8, X86::BT32mi8, 1 },
231 { X86::BT64ri8, X86::BT64mi8, 1 },
232 { X86::CALL32r, X86::CALL32m, 1 },
233 { X86::CALL64r, X86::CALL64m, 1 },
234 { X86::CMP16ri, X86::CMP16mi, 1 },
235 { X86::CMP16ri8, X86::CMP16mi8, 1 },
236 { X86::CMP16rr, X86::CMP16mr, 1 },
237 { X86::CMP32ri, X86::CMP32mi, 1 },
238 { X86::CMP32ri8, X86::CMP32mi8, 1 },
239 { X86::CMP32rr, X86::CMP32mr, 1 },
240 { X86::CMP64ri32, X86::CMP64mi32, 1 },
241 { X86::CMP64ri8, X86::CMP64mi8, 1 },
242 { X86::CMP64rr, X86::CMP64mr, 1 },
243 { X86::CMP8ri, X86::CMP8mi, 1 },
244 { X86::CMP8rr, X86::CMP8mr, 1 },
245 { X86::DIV16r, X86::DIV16m, 1 },
246 { X86::DIV32r, X86::DIV32m, 1 },
247 { X86::DIV64r, X86::DIV64m, 1 },
248 { X86::DIV8r, X86::DIV8m, 1 },
249 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 },
250 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
251 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
252 { X86::IDIV16r, X86::IDIV16m, 1 },
253 { X86::IDIV32r, X86::IDIV32m, 1 },
254 { X86::IDIV64r, X86::IDIV64m, 1 },
255 { X86::IDIV8r, X86::IDIV8m, 1 },
256 { X86::IMUL16r, X86::IMUL16m, 1 },
257 { X86::IMUL32r, X86::IMUL32m, 1 },
258 { X86::IMUL64r, X86::IMUL64m, 1 },
259 { X86::IMUL8r, X86::IMUL8m, 1 },
260 { X86::JMP32r, X86::JMP32m, 1 },
261 { X86::JMP64r, X86::JMP64m, 1 },
262 { X86::MOV16ri, X86::MOV16mi, 0 },
263 { X86::MOV16rr, X86::MOV16mr, 0 },
264 { X86::MOV16to16_, X86::MOV16_mr, 0 },
265 { X86::MOV32ri, X86::MOV32mi, 0 },
266 { X86::MOV32rr, X86::MOV32mr, 0 },
267 { X86::MOV32to32_, X86::MOV32_mr, 0 },
268 { X86::MOV64ri32, X86::MOV64mi32, 0 },
269 { X86::MOV64rr, X86::MOV64mr, 0 },
270 { X86::MOV8ri, X86::MOV8mi, 0 },
271 { X86::MOV8rr, X86::MOV8mr, 0 },
272 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
273 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
274 { X86::MOVDQArr, X86::MOVDQAmr, 0 },
275 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
276 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
277 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
278 { X86::MOVSDrr, X86::MOVSDmr, 0 },
279 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
280 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
281 { X86::MOVSSrr, X86::MOVSSmr, 0 },
282 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
283 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
284 { X86::MUL16r, X86::MUL16m, 1 },
285 { X86::MUL32r, X86::MUL32m, 1 },
286 { X86::MUL64r, X86::MUL64m, 1 },
287 { X86::MUL8r, X86::MUL8m, 1 },
288 { X86::SETAEr, X86::SETAEm, 0 },
289 { X86::SETAr, X86::SETAm, 0 },
290 { X86::SETBEr, X86::SETBEm, 0 },
291 { X86::SETBr, X86::SETBm, 0 },
292 { X86::SETEr, X86::SETEm, 0 },
293 { X86::SETGEr, X86::SETGEm, 0 },
294 { X86::SETGr, X86::SETGm, 0 },
295 { X86::SETLEr, X86::SETLEm, 0 },
296 { X86::SETLr, X86::SETLm, 0 },
297 { X86::SETNEr, X86::SETNEm, 0 },
298 { X86::SETNOr, X86::SETNOm, 0 },
299 { X86::SETNPr, X86::SETNPm, 0 },
300 { X86::SETNSr, X86::SETNSm, 0 },
301 { X86::SETOr, X86::SETOm, 0 },
302 { X86::SETPr, X86::SETPm, 0 },
303 { X86::SETSr, X86::SETSm, 0 },
304 { X86::TAILJMPr, X86::TAILJMPm, 1 },
305 { X86::TEST16ri, X86::TEST16mi, 1 },
306 { X86::TEST32ri, X86::TEST32mi, 1 },
307 { X86::TEST64ri32, X86::TEST64mi32, 1 },
308 { X86::TEST8ri, X86::TEST8mi, 1 }
311 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
312 unsigned RegOp = OpTbl0[i][0];
313 unsigned MemOp = OpTbl0[i][1];
314 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
316 assert(false && "Duplicated entries?");
317 unsigned FoldedLoad = OpTbl0[i][2];
318 // Index 0, folded load or store.
319 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
320 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
321 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
322 std::make_pair(RegOp, AuxInfo))).second)
323 AmbEntries.push_back(MemOp);
326 static const unsigned OpTbl1[][2] = {
327 { X86::CMP16rr, X86::CMP16rm },
328 { X86::CMP32rr, X86::CMP32rm },
329 { X86::CMP64rr, X86::CMP64rm },
330 { X86::CMP8rr, X86::CMP8rm },
331 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
332 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
333 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
334 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
335 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
336 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
337 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
338 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
339 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
340 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
341 { X86::FsMOVAPDrr, X86::MOVSDrm },
342 { X86::FsMOVAPSrr, X86::MOVSSrm },
343 { X86::IMUL16rri, X86::IMUL16rmi },
344 { X86::IMUL16rri8, X86::IMUL16rmi8 },
345 { X86::IMUL32rri, X86::IMUL32rmi },
346 { X86::IMUL32rri8, X86::IMUL32rmi8 },
347 { X86::IMUL64rri32, X86::IMUL64rmi32 },
348 { X86::IMUL64rri8, X86::IMUL64rmi8 },
349 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
350 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
351 { X86::Int_COMISDrr, X86::Int_COMISDrm },
352 { X86::Int_COMISSrr, X86::Int_COMISSrm },
353 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
354 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
355 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
356 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
357 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
358 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
359 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
360 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
361 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
362 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
363 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
364 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
365 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
366 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
367 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
368 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
369 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
370 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
371 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
372 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
373 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
374 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
375 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
376 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
377 { X86::MOV16rr, X86::MOV16rm },
378 { X86::MOV16to16_, X86::MOV16_rm },
379 { X86::MOV32rr, X86::MOV32rm },
380 { X86::MOV32to32_, X86::MOV32_rm },
381 { X86::MOV64rr, X86::MOV64rm },
382 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
383 { X86::MOV64toSDrr, X86::MOV64toSDrm },
384 { X86::MOV8rr, X86::MOV8rm },
385 { X86::MOVAPDrr, X86::MOVAPDrm },
386 { X86::MOVAPSrr, X86::MOVAPSrm },
387 { X86::MOVDDUPrr, X86::MOVDDUPrm },
388 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
389 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
390 { X86::MOVDQArr, X86::MOVDQArm },
391 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
392 { X86::MOVSDrr, X86::MOVSDrm },
393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
395 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
396 { X86::MOVSSrr, X86::MOVSSrm },
397 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
398 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
399 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
400 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
401 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
402 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
403 { X86::MOVUPDrr, X86::MOVUPDrm },
404 { X86::MOVUPSrr, X86::MOVUPSrm },
405 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
406 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
407 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
408 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
409 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
410 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
411 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
412 { X86::MOVZX64rr32, X86::MOVZX64rm32 },
413 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
414 { X86::PSHUFDri, X86::PSHUFDmi },
415 { X86::PSHUFHWri, X86::PSHUFHWmi },
416 { X86::PSHUFLWri, X86::PSHUFLWmi },
417 { X86::RCPPSr, X86::RCPPSm },
418 { X86::RCPPSr_Int, X86::RCPPSm_Int },
419 { X86::RSQRTPSr, X86::RSQRTPSm },
420 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
421 { X86::RSQRTSSr, X86::RSQRTSSm },
422 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
423 { X86::SQRTPDr, X86::SQRTPDm },
424 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
425 { X86::SQRTPSr, X86::SQRTPSm },
426 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
427 { X86::SQRTSDr, X86::SQRTSDm },
428 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
429 { X86::SQRTSSr, X86::SQRTSSm },
430 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
431 { X86::TEST16rr, X86::TEST16rm },
432 { X86::TEST32rr, X86::TEST32rm },
433 { X86::TEST64rr, X86::TEST64rm },
434 { X86::TEST8rr, X86::TEST8rm },
435 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
436 { X86::UCOMISDrr, X86::UCOMISDrm },
437 { X86::UCOMISSrr, X86::UCOMISSrm }
440 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
441 unsigned RegOp = OpTbl1[i][0];
442 unsigned MemOp = OpTbl1[i][1];
443 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
445 assert(false && "Duplicated entries?");
446 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
447 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
448 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
449 std::make_pair(RegOp, AuxInfo))).second)
450 AmbEntries.push_back(MemOp);
453 static const unsigned OpTbl2[][2] = {
454 { X86::ADC32rr, X86::ADC32rm },
455 { X86::ADC64rr, X86::ADC64rm },
456 { X86::ADD16rr, X86::ADD16rm },
457 { X86::ADD32rr, X86::ADD32rm },
458 { X86::ADD64rr, X86::ADD64rm },
459 { X86::ADD8rr, X86::ADD8rm },
460 { X86::ADDPDrr, X86::ADDPDrm },
461 { X86::ADDPSrr, X86::ADDPSrm },
462 { X86::ADDSDrr, X86::ADDSDrm },
463 { X86::ADDSSrr, X86::ADDSSrm },
464 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
465 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
466 { X86::AND16rr, X86::AND16rm },
467 { X86::AND32rr, X86::AND32rm },
468 { X86::AND64rr, X86::AND64rm },
469 { X86::AND8rr, X86::AND8rm },
470 { X86::ANDNPDrr, X86::ANDNPDrm },
471 { X86::ANDNPSrr, X86::ANDNPSrm },
472 { X86::ANDPDrr, X86::ANDPDrm },
473 { X86::ANDPSrr, X86::ANDPSrm },
474 { X86::CMOVA16rr, X86::CMOVA16rm },
475 { X86::CMOVA32rr, X86::CMOVA32rm },
476 { X86::CMOVA64rr, X86::CMOVA64rm },
477 { X86::CMOVAE16rr, X86::CMOVAE16rm },
478 { X86::CMOVAE32rr, X86::CMOVAE32rm },
479 { X86::CMOVAE64rr, X86::CMOVAE64rm },
480 { X86::CMOVB16rr, X86::CMOVB16rm },
481 { X86::CMOVB32rr, X86::CMOVB32rm },
482 { X86::CMOVB64rr, X86::CMOVB64rm },
483 { X86::CMOVBE16rr, X86::CMOVBE16rm },
484 { X86::CMOVBE32rr, X86::CMOVBE32rm },
485 { X86::CMOVBE64rr, X86::CMOVBE64rm },
486 { X86::CMOVE16rr, X86::CMOVE16rm },
487 { X86::CMOVE32rr, X86::CMOVE32rm },
488 { X86::CMOVE64rr, X86::CMOVE64rm },
489 { X86::CMOVG16rr, X86::CMOVG16rm },
490 { X86::CMOVG32rr, X86::CMOVG32rm },
491 { X86::CMOVG64rr, X86::CMOVG64rm },
492 { X86::CMOVGE16rr, X86::CMOVGE16rm },
493 { X86::CMOVGE32rr, X86::CMOVGE32rm },
494 { X86::CMOVGE64rr, X86::CMOVGE64rm },
495 { X86::CMOVL16rr, X86::CMOVL16rm },
496 { X86::CMOVL32rr, X86::CMOVL32rm },
497 { X86::CMOVL64rr, X86::CMOVL64rm },
498 { X86::CMOVLE16rr, X86::CMOVLE16rm },
499 { X86::CMOVLE32rr, X86::CMOVLE32rm },
500 { X86::CMOVLE64rr, X86::CMOVLE64rm },
501 { X86::CMOVNE16rr, X86::CMOVNE16rm },
502 { X86::CMOVNE32rr, X86::CMOVNE32rm },
503 { X86::CMOVNE64rr, X86::CMOVNE64rm },
504 { X86::CMOVNO16rr, X86::CMOVNO16rm },
505 { X86::CMOVNO32rr, X86::CMOVNO32rm },
506 { X86::CMOVNO64rr, X86::CMOVNO64rm },
507 { X86::CMOVNP16rr, X86::CMOVNP16rm },
508 { X86::CMOVNP32rr, X86::CMOVNP32rm },
509 { X86::CMOVNP64rr, X86::CMOVNP64rm },
510 { X86::CMOVNS16rr, X86::CMOVNS16rm },
511 { X86::CMOVNS32rr, X86::CMOVNS32rm },
512 { X86::CMOVNS64rr, X86::CMOVNS64rm },
513 { X86::CMOVO16rr, X86::CMOVO16rm },
514 { X86::CMOVO32rr, X86::CMOVO32rm },
515 { X86::CMOVO64rr, X86::CMOVO64rm },
516 { X86::CMOVP16rr, X86::CMOVP16rm },
517 { X86::CMOVP32rr, X86::CMOVP32rm },
518 { X86::CMOVP64rr, X86::CMOVP64rm },
519 { X86::CMOVS16rr, X86::CMOVS16rm },
520 { X86::CMOVS32rr, X86::CMOVS32rm },
521 { X86::CMOVS64rr, X86::CMOVS64rm },
522 { X86::CMPPDrri, X86::CMPPDrmi },
523 { X86::CMPPSrri, X86::CMPPSrmi },
524 { X86::CMPSDrr, X86::CMPSDrm },
525 { X86::CMPSSrr, X86::CMPSSrm },
526 { X86::DIVPDrr, X86::DIVPDrm },
527 { X86::DIVPSrr, X86::DIVPSrm },
528 { X86::DIVSDrr, X86::DIVSDrm },
529 { X86::DIVSSrr, X86::DIVSSrm },
530 { X86::FsANDNPDrr, X86::FsANDNPDrm },
531 { X86::FsANDNPSrr, X86::FsANDNPSrm },
532 { X86::FsANDPDrr, X86::FsANDPDrm },
533 { X86::FsANDPSrr, X86::FsANDPSrm },
534 { X86::FsORPDrr, X86::FsORPDrm },
535 { X86::FsORPSrr, X86::FsORPSrm },
536 { X86::FsXORPDrr, X86::FsXORPDrm },
537 { X86::FsXORPSrr, X86::FsXORPSrm },
538 { X86::HADDPDrr, X86::HADDPDrm },
539 { X86::HADDPSrr, X86::HADDPSrm },
540 { X86::HSUBPDrr, X86::HSUBPDrm },
541 { X86::HSUBPSrr, X86::HSUBPSrm },
542 { X86::IMUL16rr, X86::IMUL16rm },
543 { X86::IMUL32rr, X86::IMUL32rm },
544 { X86::IMUL64rr, X86::IMUL64rm },
545 { X86::MAXPDrr, X86::MAXPDrm },
546 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
547 { X86::MAXPSrr, X86::MAXPSrm },
548 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
549 { X86::MAXSDrr, X86::MAXSDrm },
550 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
551 { X86::MAXSSrr, X86::MAXSSrm },
552 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
553 { X86::MINPDrr, X86::MINPDrm },
554 { X86::MINPDrr_Int, X86::MINPDrm_Int },
555 { X86::MINPSrr, X86::MINPSrm },
556 { X86::MINPSrr_Int, X86::MINPSrm_Int },
557 { X86::MINSDrr, X86::MINSDrm },
558 { X86::MINSDrr_Int, X86::MINSDrm_Int },
559 { X86::MINSSrr, X86::MINSSrm },
560 { X86::MINSSrr_Int, X86::MINSSrm_Int },
561 { X86::MULPDrr, X86::MULPDrm },
562 { X86::MULPSrr, X86::MULPSrm },
563 { X86::MULSDrr, X86::MULSDrm },
564 { X86::MULSSrr, X86::MULSSrm },
565 { X86::OR16rr, X86::OR16rm },
566 { X86::OR32rr, X86::OR32rm },
567 { X86::OR64rr, X86::OR64rm },
568 { X86::OR8rr, X86::OR8rm },
569 { X86::ORPDrr, X86::ORPDrm },
570 { X86::ORPSrr, X86::ORPSrm },
571 { X86::PACKSSDWrr, X86::PACKSSDWrm },
572 { X86::PACKSSWBrr, X86::PACKSSWBrm },
573 { X86::PACKUSWBrr, X86::PACKUSWBrm },
574 { X86::PADDBrr, X86::PADDBrm },
575 { X86::PADDDrr, X86::PADDDrm },
576 { X86::PADDQrr, X86::PADDQrm },
577 { X86::PADDSBrr, X86::PADDSBrm },
578 { X86::PADDSWrr, X86::PADDSWrm },
579 { X86::PADDWrr, X86::PADDWrm },
580 { X86::PANDNrr, X86::PANDNrm },
581 { X86::PANDrr, X86::PANDrm },
582 { X86::PAVGBrr, X86::PAVGBrm },
583 { X86::PAVGWrr, X86::PAVGWrm },
584 { X86::PCMPEQBrr, X86::PCMPEQBrm },
585 { X86::PCMPEQDrr, X86::PCMPEQDrm },
586 { X86::PCMPEQWrr, X86::PCMPEQWrm },
587 { X86::PCMPGTBrr, X86::PCMPGTBrm },
588 { X86::PCMPGTDrr, X86::PCMPGTDrm },
589 { X86::PCMPGTWrr, X86::PCMPGTWrm },
590 { X86::PINSRWrri, X86::PINSRWrmi },
591 { X86::PMADDWDrr, X86::PMADDWDrm },
592 { X86::PMAXSWrr, X86::PMAXSWrm },
593 { X86::PMAXUBrr, X86::PMAXUBrm },
594 { X86::PMINSWrr, X86::PMINSWrm },
595 { X86::PMINUBrr, X86::PMINUBrm },
596 { X86::PMULDQrr, X86::PMULDQrm },
597 { X86::PMULHUWrr, X86::PMULHUWrm },
598 { X86::PMULHWrr, X86::PMULHWrm },
599 { X86::PMULLDrr, X86::PMULLDrm },
600 { X86::PMULLDrr_int, X86::PMULLDrm_int },
601 { X86::PMULLWrr, X86::PMULLWrm },
602 { X86::PMULUDQrr, X86::PMULUDQrm },
603 { X86::PORrr, X86::PORrm },
604 { X86::PSADBWrr, X86::PSADBWrm },
605 { X86::PSLLDrr, X86::PSLLDrm },
606 { X86::PSLLQrr, X86::PSLLQrm },
607 { X86::PSLLWrr, X86::PSLLWrm },
608 { X86::PSRADrr, X86::PSRADrm },
609 { X86::PSRAWrr, X86::PSRAWrm },
610 { X86::PSRLDrr, X86::PSRLDrm },
611 { X86::PSRLQrr, X86::PSRLQrm },
612 { X86::PSRLWrr, X86::PSRLWrm },
613 { X86::PSUBBrr, X86::PSUBBrm },
614 { X86::PSUBDrr, X86::PSUBDrm },
615 { X86::PSUBSBrr, X86::PSUBSBrm },
616 { X86::PSUBSWrr, X86::PSUBSWrm },
617 { X86::PSUBWrr, X86::PSUBWrm },
618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
626 { X86::PXORrr, X86::PXORrm },
627 { X86::SBB32rr, X86::SBB32rm },
628 { X86::SBB64rr, X86::SBB64rm },
629 { X86::SHUFPDrri, X86::SHUFPDrmi },
630 { X86::SHUFPSrri, X86::SHUFPSrmi },
631 { X86::SUB16rr, X86::SUB16rm },
632 { X86::SUB32rr, X86::SUB32rm },
633 { X86::SUB64rr, X86::SUB64rm },
634 { X86::SUB8rr, X86::SUB8rm },
635 { X86::SUBPDrr, X86::SUBPDrm },
636 { X86::SUBPSrr, X86::SUBPSrm },
637 { X86::SUBSDrr, X86::SUBSDrm },
638 { X86::SUBSSrr, X86::SUBSSrm },
639 // FIXME: TEST*rr -> swapped operand of TEST*mr.
640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
644 { X86::XOR16rr, X86::XOR16rm },
645 { X86::XOR32rr, X86::XOR32rm },
646 { X86::XOR64rr, X86::XOR64rm },
647 { X86::XOR8rr, X86::XOR8rm },
648 { X86::XORPDrr, X86::XORPDrm },
649 { X86::XORPSrr, X86::XORPSrm }
652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
653 unsigned RegOp = OpTbl2[i][0];
654 unsigned MemOp = OpTbl2[i][1];
655 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
657 assert(false && "Duplicated entries?");
658 unsigned AuxInfo = 2 | (1 << 4); // Index 2, folded load
659 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
660 std::make_pair(RegOp, AuxInfo))).second)
661 AmbEntries.push_back(MemOp);
664 // Remove ambiguous entries.
665 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
668 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
669 unsigned &SrcReg, unsigned &DstReg,
670 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
671 switch (MI.getOpcode()) {
678 case X86::MOV16to16_:
679 case X86::MOV32to32_:
683 // FP Stack register class copies
684 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
685 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
686 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
688 case X86::FsMOVAPSrr:
689 case X86::FsMOVAPDrr:
693 case X86::MOVSS2PSrr:
694 case X86::MOVSD2PDrr:
695 case X86::MOVPS2SSrr:
696 case X86::MOVPD2SDrr:
697 case X86::MMX_MOVQ64rr:
698 assert(MI.getNumOperands() >= 2 &&
699 MI.getOperand(0).isReg() &&
700 MI.getOperand(1).isReg() &&
701 "invalid register-register move instruction");
702 SrcReg = MI.getOperand(1).getReg();
703 DstReg = MI.getOperand(0).getReg();
704 SrcSubIdx = MI.getOperand(1).getSubReg();
705 DstSubIdx = MI.getOperand(0).getSubReg();
710 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
711 int &FrameIndex) const {
712 switch (MI->getOpcode()) {
726 case X86::MMX_MOVD64rm:
727 case X86::MMX_MOVQ64rm:
728 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
729 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
730 MI->getOperand(2).getImm() == 1 &&
731 MI->getOperand(3).getReg() == 0 &&
732 MI->getOperand(4).getImm() == 0) {
733 FrameIndex = MI->getOperand(1).getIndex();
734 return MI->getOperand(0).getReg();
741 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
742 int &FrameIndex) const {
743 switch (MI->getOpcode()) {
757 case X86::MMX_MOVD64mr:
758 case X86::MMX_MOVQ64mr:
759 case X86::MMX_MOVNTQmr:
760 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
761 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
762 MI->getOperand(1).getImm() == 1 &&
763 MI->getOperand(2).getReg() == 0 &&
764 MI->getOperand(3).getImm() == 0) {
765 FrameIndex = MI->getOperand(0).getIndex();
766 return MI->getOperand(4).getReg();
774 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
776 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
777 bool isPICBase = false;
778 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
779 E = MRI.def_end(); I != E; ++I) {
780 MachineInstr *DefMI = I.getOperand().getParent();
781 if (DefMI->getOpcode() != X86::MOVPC32r)
783 assert(!isPICBase && "More than one PIC base?");
789 /// isGVStub - Return true if the GV requires an extra load to get the
791 static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
792 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
796 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
797 switch (MI->getOpcode()) {
811 case X86::MMX_MOVD64rm:
812 case X86::MMX_MOVQ64rm: {
813 // Loads from constant pools are trivially rematerializable.
814 if (MI->getOperand(1).isReg() &&
815 MI->getOperand(2).isImm() &&
816 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
817 (MI->getOperand(4).isCPI() ||
818 (MI->getOperand(4).isGlobal() &&
819 isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
820 unsigned BaseReg = MI->getOperand(1).getReg();
823 // Allow re-materialization of PIC load.
824 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
826 const MachineFunction &MF = *MI->getParent()->getParent();
827 const MachineRegisterInfo &MRI = MF.getRegInfo();
828 bool isPICBase = false;
829 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
830 E = MRI.def_end(); I != E; ++I) {
831 MachineInstr *DefMI = I.getOperand().getParent();
832 if (DefMI->getOpcode() != X86::MOVPC32r)
834 assert(!isPICBase && "More than one PIC base?");
844 if (MI->getOperand(2).isImm() &&
845 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
846 !MI->getOperand(4).isReg()) {
847 // lea fi#, lea GV, etc. are all rematerializable.
848 if (!MI->getOperand(1).isReg())
850 unsigned BaseReg = MI->getOperand(1).getReg();
853 // Allow re-materialization of lea PICBase + x.
854 const MachineFunction &MF = *MI->getParent()->getParent();
855 const MachineRegisterInfo &MRI = MF.getRegInfo();
856 return regIsPICBase(BaseReg, MRI);
862 // All other instructions marked M_REMATERIALIZABLE are always trivially
867 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
868 /// would clobber the EFLAGS condition register. Note the result may be
869 /// conservative. If it cannot definitely determine the safety after visiting
870 /// two instructions it assumes it's not safe.
871 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
872 MachineBasicBlock::iterator I) {
873 // It's always safe to clobber EFLAGS at the end of a block.
877 // For compile time consideration, if we are not able to determine the
878 // safety after visiting 2 instructions, we will assume it's not safe.
879 for (unsigned i = 0; i < 2; ++i) {
880 bool SeenDef = false;
881 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
882 MachineOperand &MO = I->getOperand(j);
885 if (MO.getReg() == X86::EFLAGS) {
893 // This instruction defines EFLAGS, no need to look any further.
897 // If we make it to the end of the block, it's safe to clobber EFLAGS.
902 // Conservative answer.
906 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
907 MachineBasicBlock::iterator I,
909 const MachineInstr *Orig) const {
910 DebugLoc DL = DebugLoc::getUnknownLoc();
911 if (I != MBB.end()) DL = I->getDebugLoc();
913 unsigned SubIdx = Orig->getOperand(0).isReg()
914 ? Orig->getOperand(0).getSubReg() : 0;
915 bool ChangeSubIdx = SubIdx != 0;
916 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
917 DestReg = RI.getSubReg(DestReg, SubIdx);
921 // MOV32r0 etc. are implemented with xor which clobbers condition code.
922 // Re-materialize them as movri instructions to avoid side effects.
923 bool Emitted = false;
924 switch (Orig->getOpcode()) {
930 if (!isSafeToClobberEFLAGS(MBB, I)) {
932 switch (Orig->getOpcode()) {
934 case X86::MOV8r0: Opc = X86::MOV8ri; break;
935 case X86::MOV16r0: Opc = X86::MOV16ri; break;
936 case X86::MOV32r0: Opc = X86::MOV32ri; break;
937 case X86::MOV64r0: Opc = X86::MOV64ri32; break;
939 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
947 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
948 MI->getOperand(0).setReg(DestReg);
953 MachineInstr *NewMI = prior(I);
954 NewMI->getOperand(0).setSubReg(SubIdx);
958 /// isInvariantLoad - Return true if the specified instruction (which is marked
959 /// mayLoad) is loading from a location whose value is invariant across the
960 /// function. For example, loading a value from the constant pool or from
961 /// from the argument area of a function if it does not change. This should
962 /// only return true of *all* loads the instruction does are invariant (if it
963 /// does multiple loads).
964 bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
965 // This code cares about loads from three cases: constant pool entries,
966 // invariant argument slots, and global stubs. In order to handle these cases
967 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
968 // operand and base our analysis on it. This is safe because the address of
969 // none of these three cases is ever used as anything other than a load base
970 // and X86 doesn't have any instructions that load from multiple places.
972 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
973 const MachineOperand &MO = MI->getOperand(i);
974 // Loads from constant pools are trivially invariant.
979 return isGVStub(MO.getGlobal(), TM);
981 // If this is a load from an invariant stack slot, the load is a constant.
983 const MachineFrameInfo &MFI =
984 *MI->getParent()->getParent()->getFrameInfo();
985 int Idx = MO.getIndex();
986 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
990 // All other instances of these instructions are presumed to have other
995 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
996 /// is not marked dead.
997 static bool hasLiveCondCodeDef(MachineInstr *MI) {
998 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
999 MachineOperand &MO = MI->getOperand(i);
1000 if (MO.isReg() && MO.isDef() &&
1001 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1008 /// convertToThreeAddress - This method must be implemented by targets that
1009 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1010 /// may be able to convert a two-address instruction into a true
1011 /// three-address instruction on demand. This allows the X86 target (for
1012 /// example) to convert ADD and SHL instructions into LEA instructions if they
1013 /// would require register copies due to two-addressness.
1015 /// This method returns a null pointer if the transformation cannot be
1016 /// performed, otherwise it returns the new instruction.
1019 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1020 MachineBasicBlock::iterator &MBBI,
1021 LiveVariables *LV) const {
1022 MachineInstr *MI = MBBI;
1023 MachineFunction &MF = *MI->getParent()->getParent();
1024 // All instructions input are two-addr instructions. Get the known operands.
1025 unsigned Dest = MI->getOperand(0).getReg();
1026 unsigned Src = MI->getOperand(1).getReg();
1027 bool isDead = MI->getOperand(0).isDead();
1028 bool isKill = MI->getOperand(1).isKill();
1030 MachineInstr *NewMI = NULL;
1031 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1032 // we have better subtarget support, enable the 16-bit LEA generation here.
1033 bool DisableLEA16 = true;
1035 unsigned MIOpc = MI->getOpcode();
1037 case X86::SHUFPSrri: {
1038 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1039 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1041 unsigned B = MI->getOperand(1).getReg();
1042 unsigned C = MI->getOperand(2).getReg();
1043 if (B != C) return 0;
1044 unsigned A = MI->getOperand(0).getReg();
1045 unsigned M = MI->getOperand(3).getImm();
1046 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1047 .addReg(A, true, false, false, isDead)
1048 .addReg(B, false, false, isKill).addImm(M);
1051 case X86::SHL64ri: {
1052 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1053 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1054 // the flags produced by a shift yet, so this is safe.
1055 unsigned ShAmt = MI->getOperand(2).getImm();
1056 if (ShAmt == 0 || ShAmt >= 4) return 0;
1058 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1059 .addReg(Dest, true, false, false, isDead)
1060 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
1063 case X86::SHL32ri: {
1064 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1065 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1066 // the flags produced by a shift yet, so this is safe.
1067 unsigned ShAmt = MI->getOperand(2).getImm();
1068 if (ShAmt == 0 || ShAmt >= 4) return 0;
1070 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1071 X86::LEA64_32r : X86::LEA32r;
1072 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1073 .addReg(Dest, true, false, false, isDead)
1074 .addReg(0).addImm(1 << ShAmt)
1075 .addReg(Src, false, false, isKill).addImm(0);
1078 case X86::SHL16ri: {
1079 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1080 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1081 // the flags produced by a shift yet, so this is safe.
1082 unsigned ShAmt = MI->getOperand(2).getImm();
1083 if (ShAmt == 0 || ShAmt >= 4) return 0;
1086 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1087 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1088 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1089 ? X86::LEA64_32r : X86::LEA32r;
1090 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1091 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1093 // Build and insert into an implicit UNDEF value. This is OK because
1094 // well be shifting and then extracting the lower 16-bits.
1095 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1096 MachineInstr *InsMI =
1097 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1098 .addReg(leaInReg).addReg(Src, false, false, isKill)
1099 .addImm(X86::SUBREG_16BIT);
1101 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1102 .addReg(0).addImm(1 << ShAmt)
1103 .addReg(leaInReg, false, false, true).addImm(0);
1105 MachineInstr *ExtMI =
1106 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1107 .addReg(Dest, true, false, false, isDead)
1108 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
1111 // Update live variables
1112 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1113 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1115 LV->replaceKillInstruction(Src, MI, InsMI);
1117 LV->replaceKillInstruction(Dest, MI, ExtMI);
1121 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1122 .addReg(Dest, true, false, false, isDead)
1123 .addReg(0).addImm(1 << ShAmt)
1124 .addReg(Src, false, false, isKill).addImm(0);
1129 // The following opcodes also sets the condition code register(s). Only
1130 // convert them to equivalent lea if the condition code register def's
1132 if (hasLiveCondCodeDef(MI))
1135 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1140 case X86::INC64_32r: {
1141 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1142 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1143 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1144 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1145 .addReg(Dest, true, false, false, isDead),
1150 case X86::INC64_16r:
1151 if (DisableLEA16) return 0;
1152 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1153 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1154 .addReg(Dest, true, false, false, isDead),
1159 case X86::DEC64_32r: {
1160 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1161 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1162 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1163 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1164 .addReg(Dest, true, false, false, isDead),
1169 case X86::DEC64_16r:
1170 if (DisableLEA16) return 0;
1171 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1172 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1173 .addReg(Dest, true, false, false, isDead),
1177 case X86::ADD32rr: {
1178 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1179 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1180 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1181 unsigned Src2 = MI->getOperand(2).getReg();
1182 bool isKill2 = MI->getOperand(2).isKill();
1183 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1184 .addReg(Dest, true, false, false, isDead),
1185 Src, isKill, Src2, isKill2);
1187 LV->replaceKillInstruction(Src2, MI, NewMI);
1190 case X86::ADD16rr: {
1191 if (DisableLEA16) return 0;
1192 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1193 unsigned Src2 = MI->getOperand(2).getReg();
1194 bool isKill2 = MI->getOperand(2).isKill();
1195 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1196 .addReg(Dest, true, false, false, isDead),
1197 Src, isKill, Src2, isKill2);
1199 LV->replaceKillInstruction(Src2, MI, NewMI);
1202 case X86::ADD64ri32:
1204 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1205 if (MI->getOperand(2).isImm())
1206 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1207 .addReg(Dest, true, false, false, isDead),
1208 Src, isKill, MI->getOperand(2).getImm());
1212 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1213 if (MI->getOperand(2).isImm()) {
1214 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1215 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1216 .addReg(Dest, true, false, false, isDead),
1217 Src, isKill, MI->getOperand(2).getImm());
1222 if (DisableLEA16) return 0;
1223 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1224 if (MI->getOperand(2).isImm())
1225 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1226 .addReg(Dest, true, false, false, isDead),
1227 Src, isKill, MI->getOperand(2).getImm());
1230 if (DisableLEA16) return 0;
1232 case X86::SHL64ri: {
1233 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1234 "Unknown shl instruction!");
1235 unsigned ShAmt = MI->getOperand(2).getImm();
1236 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1238 AM.Scale = 1 << ShAmt;
1240 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1241 : (MIOpc == X86::SHL32ri
1242 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1243 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1244 .addReg(Dest, true, false, false, isDead), AM);
1246 NewMI->getOperand(3).setIsKill(true);
1254 if (!NewMI) return 0;
1256 if (LV) { // Update live variables
1258 LV->replaceKillInstruction(Src, MI, NewMI);
1260 LV->replaceKillInstruction(Dest, MI, NewMI);
1263 MFI->insert(MBBI, NewMI); // Insert the new inst
1267 /// commuteInstruction - We have a few instructions that must be hacked on to
1271 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1272 switch (MI->getOpcode()) {
1273 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1274 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1275 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1276 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1277 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1278 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1281 switch (MI->getOpcode()) {
1282 default: assert(0 && "Unreachable!");
1283 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1284 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1285 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1286 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1287 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1288 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1290 unsigned Amt = MI->getOperand(3).getImm();
1292 MachineFunction &MF = *MI->getParent()->getParent();
1293 MI = MF.CloneMachineInstr(MI);
1296 MI->setDesc(get(Opc));
1297 MI->getOperand(3).setImm(Size-Amt);
1298 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1300 case X86::CMOVB16rr:
1301 case X86::CMOVB32rr:
1302 case X86::CMOVB64rr:
1303 case X86::CMOVAE16rr:
1304 case X86::CMOVAE32rr:
1305 case X86::CMOVAE64rr:
1306 case X86::CMOVE16rr:
1307 case X86::CMOVE32rr:
1308 case X86::CMOVE64rr:
1309 case X86::CMOVNE16rr:
1310 case X86::CMOVNE32rr:
1311 case X86::CMOVNE64rr:
1312 case X86::CMOVBE16rr:
1313 case X86::CMOVBE32rr:
1314 case X86::CMOVBE64rr:
1315 case X86::CMOVA16rr:
1316 case X86::CMOVA32rr:
1317 case X86::CMOVA64rr:
1318 case X86::CMOVL16rr:
1319 case X86::CMOVL32rr:
1320 case X86::CMOVL64rr:
1321 case X86::CMOVGE16rr:
1322 case X86::CMOVGE32rr:
1323 case X86::CMOVGE64rr:
1324 case X86::CMOVLE16rr:
1325 case X86::CMOVLE32rr:
1326 case X86::CMOVLE64rr:
1327 case X86::CMOVG16rr:
1328 case X86::CMOVG32rr:
1329 case X86::CMOVG64rr:
1330 case X86::CMOVS16rr:
1331 case X86::CMOVS32rr:
1332 case X86::CMOVS64rr:
1333 case X86::CMOVNS16rr:
1334 case X86::CMOVNS32rr:
1335 case X86::CMOVNS64rr:
1336 case X86::CMOVP16rr:
1337 case X86::CMOVP32rr:
1338 case X86::CMOVP64rr:
1339 case X86::CMOVNP16rr:
1340 case X86::CMOVNP32rr:
1341 case X86::CMOVNP64rr:
1342 case X86::CMOVO16rr:
1343 case X86::CMOVO32rr:
1344 case X86::CMOVO64rr:
1345 case X86::CMOVNO16rr:
1346 case X86::CMOVNO32rr:
1347 case X86::CMOVNO64rr: {
1349 switch (MI->getOpcode()) {
1351 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1352 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1353 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1354 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1355 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1356 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1357 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1358 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1359 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1360 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1361 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1362 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1363 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1364 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1365 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1366 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1367 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1368 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1369 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1370 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1371 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1372 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1373 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1374 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1375 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1376 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1377 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1378 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1379 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1380 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1381 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1382 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1383 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
1384 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1385 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1386 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1387 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1388 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1389 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
1390 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1391 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1392 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1393 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1394 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1395 case X86::CMOVO64rr: Opc = X86::CMOVNO32rr; break;
1396 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1397 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1398 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1401 MachineFunction &MF = *MI->getParent()->getParent();
1402 MI = MF.CloneMachineInstr(MI);
1405 MI->setDesc(get(Opc));
1406 // Fallthrough intended.
1409 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1413 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1415 default: return X86::COND_INVALID;
1416 case X86::JE: return X86::COND_E;
1417 case X86::JNE: return X86::COND_NE;
1418 case X86::JL: return X86::COND_L;
1419 case X86::JLE: return X86::COND_LE;
1420 case X86::JG: return X86::COND_G;
1421 case X86::JGE: return X86::COND_GE;
1422 case X86::JB: return X86::COND_B;
1423 case X86::JBE: return X86::COND_BE;
1424 case X86::JA: return X86::COND_A;
1425 case X86::JAE: return X86::COND_AE;
1426 case X86::JS: return X86::COND_S;
1427 case X86::JNS: return X86::COND_NS;
1428 case X86::JP: return X86::COND_P;
1429 case X86::JNP: return X86::COND_NP;
1430 case X86::JO: return X86::COND_O;
1431 case X86::JNO: return X86::COND_NO;
1435 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1437 default: assert(0 && "Illegal condition code!");
1438 case X86::COND_E: return X86::JE;
1439 case X86::COND_NE: return X86::JNE;
1440 case X86::COND_L: return X86::JL;
1441 case X86::COND_LE: return X86::JLE;
1442 case X86::COND_G: return X86::JG;
1443 case X86::COND_GE: return X86::JGE;
1444 case X86::COND_B: return X86::JB;
1445 case X86::COND_BE: return X86::JBE;
1446 case X86::COND_A: return X86::JA;
1447 case X86::COND_AE: return X86::JAE;
1448 case X86::COND_S: return X86::JS;
1449 case X86::COND_NS: return X86::JNS;
1450 case X86::COND_P: return X86::JP;
1451 case X86::COND_NP: return X86::JNP;
1452 case X86::COND_O: return X86::JO;
1453 case X86::COND_NO: return X86::JNO;
1457 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1458 /// e.g. turning COND_E to COND_NE.
1459 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1461 default: assert(0 && "Illegal condition code!");
1462 case X86::COND_E: return X86::COND_NE;
1463 case X86::COND_NE: return X86::COND_E;
1464 case X86::COND_L: return X86::COND_GE;
1465 case X86::COND_LE: return X86::COND_G;
1466 case X86::COND_G: return X86::COND_LE;
1467 case X86::COND_GE: return X86::COND_L;
1468 case X86::COND_B: return X86::COND_AE;
1469 case X86::COND_BE: return X86::COND_A;
1470 case X86::COND_A: return X86::COND_BE;
1471 case X86::COND_AE: return X86::COND_B;
1472 case X86::COND_S: return X86::COND_NS;
1473 case X86::COND_NS: return X86::COND_S;
1474 case X86::COND_P: return X86::COND_NP;
1475 case X86::COND_NP: return X86::COND_P;
1476 case X86::COND_O: return X86::COND_NO;
1477 case X86::COND_NO: return X86::COND_O;
1481 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1482 const TargetInstrDesc &TID = MI->getDesc();
1483 if (!TID.isTerminator()) return false;
1485 // Conditional branch is a special case.
1486 if (TID.isBranch() && !TID.isBarrier())
1488 if (!TID.isPredicable())
1490 return !isPredicated(MI);
1493 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1494 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1495 const X86InstrInfo &TII) {
1496 if (MI->getOpcode() == X86::FP_REG_KILL)
1498 return TII.isUnpredicatedTerminator(MI);
1501 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1502 MachineBasicBlock *&TBB,
1503 MachineBasicBlock *&FBB,
1504 SmallVectorImpl<MachineOperand> &Cond,
1505 bool AllowModify) const {
1506 // Start from the bottom of the block and work up, examining the
1507 // terminator instructions.
1508 MachineBasicBlock::iterator I = MBB.end();
1509 while (I != MBB.begin()) {
1511 // Working from the bottom, when we see a non-terminator
1512 // instruction, we're done.
1513 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1515 // A terminator that isn't a branch can't easily be handled
1516 // by this analysis.
1517 if (!I->getDesc().isBranch())
1519 // Handle unconditional branches.
1520 if (I->getOpcode() == X86::JMP) {
1522 TBB = I->getOperand(0).getMBB();
1526 // If the block has any instructions after a JMP, delete them.
1527 while (next(I) != MBB.end())
1528 next(I)->eraseFromParent();
1531 // Delete the JMP if it's equivalent to a fall-through.
1532 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1534 I->eraseFromParent();
1538 // TBB is used to indicate the unconditinal destination.
1539 TBB = I->getOperand(0).getMBB();
1542 // Handle conditional branches.
1543 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1544 if (BranchCode == X86::COND_INVALID)
1545 return true; // Can't handle indirect branch.
1546 // Working from the bottom, handle the first conditional branch.
1549 TBB = I->getOperand(0).getMBB();
1550 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1553 // Handle subsequent conditional branches. Only handle the case
1554 // where all conditional branches branch to the same destination
1555 // and their condition opcodes fit one of the special
1556 // multi-branch idioms.
1557 assert(Cond.size() == 1);
1559 // Only handle the case where all conditional branches branch to
1560 // the same destination.
1561 if (TBB != I->getOperand(0).getMBB())
1563 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1564 // If the conditions are the same, we can leave them alone.
1565 if (OldBranchCode == BranchCode)
1567 // If they differ, see if they fit one of the known patterns.
1568 // Theoretically we could handle more patterns here, but
1569 // we shouldn't expect to see them if instruction selection
1570 // has done a reasonable job.
1571 if ((OldBranchCode == X86::COND_NP &&
1572 BranchCode == X86::COND_E) ||
1573 (OldBranchCode == X86::COND_E &&
1574 BranchCode == X86::COND_NP))
1575 BranchCode = X86::COND_NP_OR_E;
1576 else if ((OldBranchCode == X86::COND_P &&
1577 BranchCode == X86::COND_NE) ||
1578 (OldBranchCode == X86::COND_NE &&
1579 BranchCode == X86::COND_P))
1580 BranchCode = X86::COND_NE_OR_P;
1583 // Update the MachineOperand.
1584 Cond[0].setImm(BranchCode);
1590 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1591 MachineBasicBlock::iterator I = MBB.end();
1594 while (I != MBB.begin()) {
1596 if (I->getOpcode() != X86::JMP &&
1597 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1599 // Remove the branch.
1600 I->eraseFromParent();
1609 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1610 MachineBasicBlock *FBB,
1611 const SmallVectorImpl<MachineOperand> &Cond) const {
1612 // FIXME this should probably have a DebugLoc operand
1613 DebugLoc dl = DebugLoc::getUnknownLoc();
1614 // Shouldn't be a fall through.
1615 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1616 assert((Cond.size() == 1 || Cond.size() == 0) &&
1617 "X86 branch conditions have one component!");
1620 // Unconditional branch?
1621 assert(!FBB && "Unconditional branch with multiple successors!");
1622 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1626 // Conditional branch.
1628 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1630 case X86::COND_NP_OR_E:
1631 // Synthesize NP_OR_E with two branches.
1632 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1634 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1637 case X86::COND_NE_OR_P:
1638 // Synthesize NE_OR_P with two branches.
1639 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1641 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1645 unsigned Opc = GetCondBranchFromCond(CC);
1646 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1651 // Two-way Conditional branch. Insert the second branch.
1652 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1658 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1659 MachineBasicBlock::iterator MI,
1660 unsigned DestReg, unsigned SrcReg,
1661 const TargetRegisterClass *DestRC,
1662 const TargetRegisterClass *SrcRC) const {
1663 DebugLoc DL = DebugLoc::getUnknownLoc();
1664 if (MI != MBB.end()) DL = MI->getDebugLoc();
1666 if (DestRC == SrcRC) {
1668 if (DestRC == &X86::GR64RegClass) {
1670 } else if (DestRC == &X86::GR32RegClass) {
1672 } else if (DestRC == &X86::GR16RegClass) {
1674 } else if (DestRC == &X86::GR8RegClass) {
1676 } else if (DestRC == &X86::GR32_RegClass) {
1677 Opc = X86::MOV32_rr;
1678 } else if (DestRC == &X86::GR16_RegClass) {
1679 Opc = X86::MOV16_rr;
1680 } else if (DestRC == &X86::RFP32RegClass) {
1681 Opc = X86::MOV_Fp3232;
1682 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
1683 Opc = X86::MOV_Fp6464;
1684 } else if (DestRC == &X86::RFP80RegClass) {
1685 Opc = X86::MOV_Fp8080;
1686 } else if (DestRC == &X86::FR32RegClass) {
1687 Opc = X86::FsMOVAPSrr;
1688 } else if (DestRC == &X86::FR64RegClass) {
1689 Opc = X86::FsMOVAPDrr;
1690 } else if (DestRC == &X86::VR128RegClass) {
1691 Opc = X86::MOVAPSrr;
1692 } else if (DestRC == &X86::VR64RegClass) {
1693 Opc = X86::MMX_MOVQ64rr;
1697 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1701 // Moving EFLAGS to / from another register requires a push and a pop.
1702 if (SrcRC == &X86::CCRRegClass) {
1703 if (SrcReg != X86::EFLAGS)
1705 if (DestRC == &X86::GR64RegClass) {
1706 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1707 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1709 } else if (DestRC == &X86::GR32RegClass) {
1710 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1711 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1714 } else if (DestRC == &X86::CCRRegClass) {
1715 if (DestReg != X86::EFLAGS)
1717 if (SrcRC == &X86::GR64RegClass) {
1718 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1719 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1721 } else if (SrcRC == &X86::GR32RegClass) {
1722 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1723 BuildMI(MBB, MI, DL, get(X86::POPFD));
1728 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1729 if (SrcRC == &X86::RSTRegClass) {
1730 // Copying from ST(0)/ST(1).
1731 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1732 // Can only copy from ST(0)/ST(1) right now
1734 bool isST0 = SrcReg == X86::ST0;
1736 if (DestRC == &X86::RFP32RegClass)
1737 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1738 else if (DestRC == &X86::RFP64RegClass)
1739 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1741 if (DestRC != &X86::RFP80RegClass)
1743 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1745 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1749 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1750 if (DestRC == &X86::RSTRegClass) {
1751 // Copying to ST(0) / ST(1).
1752 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1753 // Can only copy to TOS right now
1755 bool isST0 = DestReg == X86::ST0;
1757 if (SrcRC == &X86::RFP32RegClass)
1758 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1759 else if (SrcRC == &X86::RFP64RegClass)
1760 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1762 if (SrcRC != &X86::RFP80RegClass)
1764 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1766 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1770 // Not yet supported!
1774 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
1775 bool isStackAligned) {
1777 if (RC == &X86::GR64RegClass) {
1779 } else if (RC == &X86::GR32RegClass) {
1781 } else if (RC == &X86::GR16RegClass) {
1783 } else if (RC == &X86::GR8RegClass) {
1785 } else if (RC == &X86::GR32_RegClass) {
1786 Opc = X86::MOV32_mr;
1787 } else if (RC == &X86::GR16_RegClass) {
1788 Opc = X86::MOV16_mr;
1789 } else if (RC == &X86::RFP80RegClass) {
1790 Opc = X86::ST_FpP80m; // pops
1791 } else if (RC == &X86::RFP64RegClass) {
1792 Opc = X86::ST_Fp64m;
1793 } else if (RC == &X86::RFP32RegClass) {
1794 Opc = X86::ST_Fp32m;
1795 } else if (RC == &X86::FR32RegClass) {
1797 } else if (RC == &X86::FR64RegClass) {
1799 } else if (RC == &X86::VR128RegClass) {
1800 // If stack is realigned we can use aligned stores.
1801 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1802 } else if (RC == &X86::VR64RegClass) {
1803 Opc = X86::MMX_MOVQ64mr;
1805 assert(0 && "Unknown regclass");
1812 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1813 MachineBasicBlock::iterator MI,
1814 unsigned SrcReg, bool isKill, int FrameIdx,
1815 const TargetRegisterClass *RC) const {
1816 const MachineFunction &MF = *MBB.getParent();
1817 bool isAligned = (RI.getStackAlignment() >= 16) ||
1818 RI.needsStackRealignment(MF);
1819 unsigned Opc = getStoreRegOpcode(RC, isAligned);
1820 DebugLoc DL = DebugLoc::getUnknownLoc();
1821 if (MI != MBB.end()) DL = MI->getDebugLoc();
1822 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1823 .addReg(SrcReg, false, false, isKill);
1826 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1828 SmallVectorImpl<MachineOperand> &Addr,
1829 const TargetRegisterClass *RC,
1830 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1831 bool isAligned = (RI.getStackAlignment() >= 16) ||
1832 RI.needsStackRealignment(MF);
1833 unsigned Opc = getStoreRegOpcode(RC, isAligned);
1834 DebugLoc DL = DebugLoc::getUnknownLoc();
1835 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1836 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1837 MIB.addOperand(Addr[i]);
1838 MIB.addReg(SrcReg, false, false, isKill);
1839 NewMIs.push_back(MIB);
1842 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
1843 bool isStackAligned) {
1845 if (RC == &X86::GR64RegClass) {
1847 } else if (RC == &X86::GR32RegClass) {
1849 } else if (RC == &X86::GR16RegClass) {
1851 } else if (RC == &X86::GR8RegClass) {
1853 } else if (RC == &X86::GR32_RegClass) {
1854 Opc = X86::MOV32_rm;
1855 } else if (RC == &X86::GR16_RegClass) {
1856 Opc = X86::MOV16_rm;
1857 } else if (RC == &X86::RFP80RegClass) {
1858 Opc = X86::LD_Fp80m;
1859 } else if (RC == &X86::RFP64RegClass) {
1860 Opc = X86::LD_Fp64m;
1861 } else if (RC == &X86::RFP32RegClass) {
1862 Opc = X86::LD_Fp32m;
1863 } else if (RC == &X86::FR32RegClass) {
1865 } else if (RC == &X86::FR64RegClass) {
1867 } else if (RC == &X86::VR128RegClass) {
1868 // If stack is realigned we can use aligned loads.
1869 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1870 } else if (RC == &X86::VR64RegClass) {
1871 Opc = X86::MMX_MOVQ64rm;
1873 assert(0 && "Unknown regclass");
1880 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1881 MachineBasicBlock::iterator MI,
1882 unsigned DestReg, int FrameIdx,
1883 const TargetRegisterClass *RC) const{
1884 const MachineFunction &MF = *MBB.getParent();
1885 bool isAligned = (RI.getStackAlignment() >= 16) ||
1886 RI.needsStackRealignment(MF);
1887 unsigned Opc = getLoadRegOpcode(RC, isAligned);
1888 DebugLoc DL = DebugLoc::getUnknownLoc();
1889 if (MI != MBB.end()) DL = MI->getDebugLoc();
1890 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
1893 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1894 SmallVectorImpl<MachineOperand> &Addr,
1895 const TargetRegisterClass *RC,
1896 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1897 bool isAligned = (RI.getStackAlignment() >= 16) ||
1898 RI.needsStackRealignment(MF);
1899 unsigned Opc = getLoadRegOpcode(RC, isAligned);
1900 DebugLoc DL = DebugLoc::getUnknownLoc();
1901 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
1902 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1903 MIB.addOperand(Addr[i]);
1904 NewMIs.push_back(MIB);
1907 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1908 MachineBasicBlock::iterator MI,
1909 const std::vector<CalleeSavedInfo> &CSI) const {
1913 DebugLoc DL = DebugLoc::getUnknownLoc();
1914 if (MI != MBB.end()) DL = MI->getDebugLoc();
1916 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1917 unsigned SlotSize = is64Bit ? 8 : 4;
1919 MachineFunction &MF = *MBB.getParent();
1920 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1921 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1923 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1924 for (unsigned i = CSI.size(); i != 0; --i) {
1925 unsigned Reg = CSI[i-1].getReg();
1926 // Add the callee-saved register as live-in. It's killed at the spill.
1928 BuildMI(MBB, MI, DL, get(Opc))
1929 .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
1934 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1935 MachineBasicBlock::iterator MI,
1936 const std::vector<CalleeSavedInfo> &CSI) const {
1940 DebugLoc DL = DebugLoc::getUnknownLoc();
1941 if (MI != MBB.end()) DL = MI->getDebugLoc();
1943 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1945 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1946 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1947 unsigned Reg = CSI[i].getReg();
1948 BuildMI(MBB, MI, DL, get(Opc), Reg);
1953 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
1954 const SmallVectorImpl<MachineOperand> &MOs,
1956 const TargetInstrInfo &TII) {
1957 // Create the base instruction with the memory operand as the first part.
1958 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
1959 MI->getDebugLoc(), true);
1960 MachineInstrBuilder MIB(NewMI);
1961 unsigned NumAddrOps = MOs.size();
1962 for (unsigned i = 0; i != NumAddrOps; ++i)
1963 MIB.addOperand(MOs[i]);
1964 if (NumAddrOps < 4) // FrameIndex only
1965 MIB.addImm(1).addReg(0).addImm(0);
1967 // Loop over the rest of the ri operands, converting them over.
1968 unsigned NumOps = MI->getDesc().getNumOperands()-2;
1969 for (unsigned i = 0; i != NumOps; ++i) {
1970 MachineOperand &MO = MI->getOperand(i+2);
1973 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1974 MachineOperand &MO = MI->getOperand(i);
1980 static MachineInstr *FuseInst(MachineFunction &MF,
1981 unsigned Opcode, unsigned OpNo,
1982 const SmallVectorImpl<MachineOperand> &MOs,
1983 MachineInstr *MI, const TargetInstrInfo &TII) {
1984 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
1985 MI->getDebugLoc(), true);
1986 MachineInstrBuilder MIB(NewMI);
1988 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1989 MachineOperand &MO = MI->getOperand(i);
1991 assert(MO.isReg() && "Expected to fold into reg operand!");
1992 unsigned NumAddrOps = MOs.size();
1993 for (unsigned i = 0; i != NumAddrOps; ++i)
1994 MIB.addOperand(MOs[i]);
1995 if (NumAddrOps < 4) // FrameIndex only
1996 MIB.addImm(1).addReg(0).addImm(0);
2004 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2005 const SmallVectorImpl<MachineOperand> &MOs,
2007 MachineFunction &MF = *MI->getParent()->getParent();
2008 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2010 unsigned NumAddrOps = MOs.size();
2011 for (unsigned i = 0; i != NumAddrOps; ++i)
2012 MIB.addOperand(MOs[i]);
2013 if (NumAddrOps < 4) // FrameIndex only
2014 MIB.addImm(1).addReg(0).addImm(0);
2015 return MIB.addImm(0);
2019 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2020 MachineInstr *MI, unsigned i,
2021 const SmallVectorImpl<MachineOperand> &MOs) const{
2022 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2023 bool isTwoAddrFold = false;
2024 unsigned NumOps = MI->getDesc().getNumOperands();
2025 bool isTwoAddr = NumOps > 1 &&
2026 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2028 MachineInstr *NewMI = NULL;
2029 // Folding a memory location into the two-address part of a two-address
2030 // instruction is different than folding it other places. It requires
2031 // replacing the *two* registers with the memory location.
2032 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2033 MI->getOperand(0).isReg() &&
2034 MI->getOperand(1).isReg() &&
2035 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2036 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2037 isTwoAddrFold = true;
2038 } else if (i == 0) { // If operand 0
2039 if (MI->getOpcode() == X86::MOV16r0)
2040 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2041 else if (MI->getOpcode() == X86::MOV32r0)
2042 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2043 else if (MI->getOpcode() == X86::MOV64r0)
2044 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2045 else if (MI->getOpcode() == X86::MOV8r0)
2046 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2050 OpcodeTablePtr = &RegOp2MemOpTable0;
2051 } else if (i == 1) {
2052 OpcodeTablePtr = &RegOp2MemOpTable1;
2053 } else if (i == 2) {
2054 OpcodeTablePtr = &RegOp2MemOpTable2;
2057 // If table selected...
2058 if (OpcodeTablePtr) {
2059 // Find the Opcode to fuse
2060 DenseMap<unsigned*, unsigned>::iterator I =
2061 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2062 if (I != OpcodeTablePtr->end()) {
2064 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
2066 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
2072 if (PrintFailedFusing)
2073 cerr << "We failed to fuse operand " << i << " in " << *MI;
2078 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2080 const SmallVectorImpl<unsigned> &Ops,
2081 int FrameIndex) const {
2082 // Check switch flag
2083 if (NoFusing) return NULL;
2085 const MachineFrameInfo *MFI = MF.getFrameInfo();
2086 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2087 // FIXME: Move alignment requirement into tables?
2088 if (Alignment < 16) {
2089 switch (MI->getOpcode()) {
2091 // Not always safe to fold movsd into these instructions since their load
2092 // folding variants expects the address to be 16 byte aligned.
2093 case X86::FsANDNPDrr:
2094 case X86::FsANDNPSrr:
2095 case X86::FsANDPDrr:
2096 case X86::FsANDPSrr:
2099 case X86::FsXORPDrr:
2100 case X86::FsXORPSrr:
2105 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2106 unsigned NewOpc = 0;
2107 switch (MI->getOpcode()) {
2108 default: return NULL;
2109 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2110 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2111 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2112 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2114 // Change to CMPXXri r, 0 first.
2115 MI->setDesc(get(NewOpc));
2116 MI->getOperand(1).ChangeToImmediate(0);
2117 } else if (Ops.size() != 1)
2120 SmallVector<MachineOperand,4> MOs;
2121 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2122 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2125 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2127 const SmallVectorImpl<unsigned> &Ops,
2128 MachineInstr *LoadMI) const {
2129 // Check switch flag
2130 if (NoFusing) return NULL;
2132 // Determine the alignment of the load.
2133 unsigned Alignment = 0;
2134 if (LoadMI->hasOneMemOperand())
2135 Alignment = LoadMI->memoperands_begin()->getAlignment();
2137 // FIXME: Move alignment requirement into tables?
2138 if (Alignment < 16) {
2139 switch (MI->getOpcode()) {
2141 // Not always safe to fold movsd into these instructions since their load
2142 // folding variants expects the address to be 16 byte aligned.
2143 case X86::FsANDNPDrr:
2144 case X86::FsANDNPSrr:
2145 case X86::FsANDPDrr:
2146 case X86::FsANDPSrr:
2149 case X86::FsXORPDrr:
2150 case X86::FsXORPSrr:
2155 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2156 unsigned NewOpc = 0;
2157 switch (MI->getOpcode()) {
2158 default: return NULL;
2159 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2160 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2161 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2162 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2164 // Change to CMPXXri r, 0 first.
2165 MI->setDesc(get(NewOpc));
2166 MI->getOperand(1).ChangeToImmediate(0);
2167 } else if (Ops.size() != 1)
2170 SmallVector<MachineOperand,4> MOs;
2171 if (LoadMI->getOpcode() == X86::V_SET0 ||
2172 LoadMI->getOpcode() == X86::V_SETALLONES) {
2173 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2174 // Create a constant-pool entry and operands to load from it.
2176 // x86-32 PIC requires a PIC base register for constant pools.
2177 unsigned PICBase = 0;
2178 if (TM.getRelocationModel() == Reloc::PIC_ &&
2179 !TM.getSubtarget<X86Subtarget>().is64Bit())
2180 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2181 // This doesn't work for several reasons.
2182 // 1. GlobalBaseReg may have been spilled.
2183 // 2. It may not be live at MI.
2186 // Create a v4i32 constant-pool entry.
2187 MachineConstantPool &MCP = *MF.getConstantPool();
2188 const VectorType *Ty = VectorType::get(Type::Int32Ty, 4);
2189 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2190 ConstantVector::getNullValue(Ty) :
2191 ConstantVector::getAllOnesValue(Ty);
2192 unsigned CPI = MCP.getConstantPoolIndex(C, 16);
2194 // Create operands to load from the constant pool entry.
2195 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2196 MOs.push_back(MachineOperand::CreateImm(1));
2197 MOs.push_back(MachineOperand::CreateReg(0, false));
2198 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2200 // Folding a normal load. Just copy the load's address operands.
2201 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2202 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2203 MOs.push_back(LoadMI->getOperand(i));
2205 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2209 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2210 const SmallVectorImpl<unsigned> &Ops) const {
2211 // Check switch flag
2212 if (NoFusing) return 0;
2214 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2215 switch (MI->getOpcode()) {
2216 default: return false;
2225 if (Ops.size() != 1)
2228 unsigned OpNum = Ops[0];
2229 unsigned Opc = MI->getOpcode();
2230 unsigned NumOps = MI->getDesc().getNumOperands();
2231 bool isTwoAddr = NumOps > 1 &&
2232 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2234 // Folding a memory location into the two-address part of a two-address
2235 // instruction is different than folding it other places. It requires
2236 // replacing the *two* registers with the memory location.
2237 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2238 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2239 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2240 } else if (OpNum == 0) { // If operand 0
2249 OpcodeTablePtr = &RegOp2MemOpTable0;
2250 } else if (OpNum == 1) {
2251 OpcodeTablePtr = &RegOp2MemOpTable1;
2252 } else if (OpNum == 2) {
2253 OpcodeTablePtr = &RegOp2MemOpTable2;
2256 if (OpcodeTablePtr) {
2257 // Find the Opcode to fuse
2258 DenseMap<unsigned*, unsigned>::iterator I =
2259 OpcodeTablePtr->find((unsigned*)Opc);
2260 if (I != OpcodeTablePtr->end())
2266 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2267 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2268 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2269 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2270 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2271 if (I == MemOp2RegOpTable.end())
2273 DebugLoc dl = MI->getDebugLoc();
2274 unsigned Opc = I->second.first;
2275 unsigned Index = I->second.second & 0xf;
2276 bool FoldedLoad = I->second.second & (1 << 4);
2277 bool FoldedStore = I->second.second & (1 << 5);
2278 if (UnfoldLoad && !FoldedLoad)
2280 UnfoldLoad &= FoldedLoad;
2281 if (UnfoldStore && !FoldedStore)
2283 UnfoldStore &= FoldedStore;
2285 const TargetInstrDesc &TID = get(Opc);
2286 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2287 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2288 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2289 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2290 SmallVector<MachineOperand,2> BeforeOps;
2291 SmallVector<MachineOperand,2> AfterOps;
2292 SmallVector<MachineOperand,4> ImpOps;
2293 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2294 MachineOperand &Op = MI->getOperand(i);
2295 if (i >= Index && i < Index + X86AddrNumOperands)
2296 AddrOps.push_back(Op);
2297 else if (Op.isReg() && Op.isImplicit())
2298 ImpOps.push_back(Op);
2300 BeforeOps.push_back(Op);
2302 AfterOps.push_back(Op);
2305 // Emit the load instruction.
2307 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2309 // Address operands cannot be marked isKill.
2310 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2311 MachineOperand &MO = NewMIs[0]->getOperand(i);
2313 MO.setIsKill(false);
2318 // Emit the data processing instruction.
2319 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2320 MachineInstrBuilder MIB(DataMI);
2323 MIB.addReg(Reg, true);
2324 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2325 MIB.addOperand(BeforeOps[i]);
2328 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2329 MIB.addOperand(AfterOps[i]);
2330 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2331 MachineOperand &MO = ImpOps[i];
2332 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
2334 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2335 unsigned NewOpc = 0;
2336 switch (DataMI->getOpcode()) {
2338 case X86::CMP64ri32:
2342 MachineOperand &MO0 = DataMI->getOperand(0);
2343 MachineOperand &MO1 = DataMI->getOperand(1);
2344 if (MO1.getImm() == 0) {
2345 switch (DataMI->getOpcode()) {
2347 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2348 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2349 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2350 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2352 DataMI->setDesc(get(NewOpc));
2353 MO1.ChangeToRegister(MO0.getReg(), false);
2357 NewMIs.push_back(DataMI);
2359 // Emit the store instruction.
2361 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2362 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2363 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2364 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2371 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2372 SmallVectorImpl<SDNode*> &NewNodes) const {
2373 if (!N->isMachineOpcode())
2376 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2377 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2378 if (I == MemOp2RegOpTable.end())
2380 unsigned Opc = I->second.first;
2381 unsigned Index = I->second.second & 0xf;
2382 bool FoldedLoad = I->second.second & (1 << 4);
2383 bool FoldedStore = I->second.second & (1 << 5);
2384 const TargetInstrDesc &TID = get(Opc);
2385 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2386 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2387 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2388 unsigned NumDefs = TID.NumDefs;
2389 std::vector<SDValue> AddrOps;
2390 std::vector<SDValue> BeforeOps;
2391 std::vector<SDValue> AfterOps;
2392 DebugLoc dl = N->getDebugLoc();
2393 unsigned NumOps = N->getNumOperands();
2394 for (unsigned i = 0; i != NumOps-1; ++i) {
2395 SDValue Op = N->getOperand(i);
2396 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2397 AddrOps.push_back(Op);
2398 else if (i < Index-NumDefs)
2399 BeforeOps.push_back(Op);
2400 else if (i > Index-NumDefs)
2401 AfterOps.push_back(Op);
2403 SDValue Chain = N->getOperand(NumOps-1);
2404 AddrOps.push_back(Chain);
2406 // Emit the load instruction.
2408 const MachineFunction &MF = DAG.getMachineFunction();
2410 MVT VT = *RC->vt_begin();
2411 bool isAligned = (RI.getStackAlignment() >= 16) ||
2412 RI.needsStackRealignment(MF);
2413 Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), dl,
2415 &AddrOps[0], AddrOps.size());
2416 NewNodes.push_back(Load);
2419 // Emit the data processing instruction.
2420 std::vector<MVT> VTs;
2421 const TargetRegisterClass *DstRC = 0;
2422 if (TID.getNumDefs() > 0) {
2423 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2424 DstRC = DstTOI.isLookupPtrRegClass()
2425 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2426 VTs.push_back(*DstRC->vt_begin());
2428 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2429 MVT VT = N->getValueType(i);
2430 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2434 BeforeOps.push_back(SDValue(Load, 0));
2435 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2436 SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
2438 NewNodes.push_back(NewNode);
2440 // Emit the store instruction.
2443 AddrOps.push_back(SDValue(NewNode, 0));
2444 AddrOps.push_back(Chain);
2445 bool isAligned = (RI.getStackAlignment() >= 16) ||
2446 RI.needsStackRealignment(MF);
2447 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), dl,
2448 MVT::Other, &AddrOps[0], AddrOps.size());
2449 NewNodes.push_back(Store);
2455 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2456 bool UnfoldLoad, bool UnfoldStore) const {
2457 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2458 MemOp2RegOpTable.find((unsigned*)Opc);
2459 if (I == MemOp2RegOpTable.end())
2461 bool FoldedLoad = I->second.second & (1 << 4);
2462 bool FoldedStore = I->second.second & (1 << 5);
2463 if (UnfoldLoad && !FoldedLoad)
2465 if (UnfoldStore && !FoldedStore)
2467 return I->second.first;
2470 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2471 if (MBB.empty()) return false;
2473 switch (MBB.back().getOpcode()) {
2474 case X86::TCRETURNri:
2475 case X86::TCRETURNdi:
2476 case X86::RET: // Return.
2481 case X86::JMP: // Uncond branch.
2482 case X86::JMP32r: // Indirect branch.
2483 case X86::JMP64r: // Indirect branch (64-bit).
2484 case X86::JMP32m: // Indirect branch through mem.
2485 case X86::JMP64m: // Indirect branch through mem (64-bit).
2487 default: return false;
2492 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2493 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2494 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2495 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2497 Cond[0].setImm(GetOppositeBranchCondition(CC));
2502 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2503 // FIXME: Return false for x87 stack register classes for now. We can't
2504 // allow any loads of these registers before FpGet_ST0_80.
2505 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2506 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2509 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2510 switch (Desc->TSFlags & X86II::ImmMask) {
2511 case X86II::Imm8: return 1;
2512 case X86II::Imm16: return 2;
2513 case X86II::Imm32: return 4;
2514 case X86II::Imm64: return 8;
2515 default: assert(0 && "Immediate size not set!");
2520 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2521 /// e.g. r8, xmm8, etc.
2522 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2523 if (!MO.isReg()) return false;
2524 switch (MO.getReg()) {
2526 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2527 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2528 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2529 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2530 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2531 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2532 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2533 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2534 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2535 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2542 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2543 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2544 /// size, and 3) use of X86-64 extended registers.
2545 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2547 const TargetInstrDesc &Desc = MI.getDesc();
2549 // Pseudo instructions do not need REX prefix byte.
2550 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2552 if (Desc.TSFlags & X86II::REX_W)
2555 unsigned NumOps = Desc.getNumOperands();
2557 bool isTwoAddr = NumOps > 1 &&
2558 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2560 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2561 unsigned i = isTwoAddr ? 1 : 0;
2562 for (unsigned e = NumOps; i != e; ++i) {
2563 const MachineOperand& MO = MI.getOperand(i);
2565 unsigned Reg = MO.getReg();
2566 if (isX86_64NonExtLowByteReg(Reg))
2571 switch (Desc.TSFlags & X86II::FormMask) {
2572 case X86II::MRMInitReg:
2573 if (isX86_64ExtendedReg(MI.getOperand(0)))
2574 REX |= (1 << 0) | (1 << 2);
2576 case X86II::MRMSrcReg: {
2577 if (isX86_64ExtendedReg(MI.getOperand(0)))
2579 i = isTwoAddr ? 2 : 1;
2580 for (unsigned e = NumOps; i != e; ++i) {
2581 const MachineOperand& MO = MI.getOperand(i);
2582 if (isX86_64ExtendedReg(MO))
2587 case X86II::MRMSrcMem: {
2588 if (isX86_64ExtendedReg(MI.getOperand(0)))
2591 i = isTwoAddr ? 2 : 1;
2592 for (; i != NumOps; ++i) {
2593 const MachineOperand& MO = MI.getOperand(i);
2595 if (isX86_64ExtendedReg(MO))
2602 case X86II::MRM0m: case X86II::MRM1m:
2603 case X86II::MRM2m: case X86II::MRM3m:
2604 case X86II::MRM4m: case X86II::MRM5m:
2605 case X86II::MRM6m: case X86II::MRM7m:
2606 case X86II::MRMDestMem: {
2607 unsigned e = isTwoAddr ? 5 : 4;
2608 i = isTwoAddr ? 1 : 0;
2609 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2612 for (; i != e; ++i) {
2613 const MachineOperand& MO = MI.getOperand(i);
2615 if (isX86_64ExtendedReg(MO))
2623 if (isX86_64ExtendedReg(MI.getOperand(0)))
2625 i = isTwoAddr ? 2 : 1;
2626 for (unsigned e = NumOps; i != e; ++i) {
2627 const MachineOperand& MO = MI.getOperand(i);
2628 if (isX86_64ExtendedReg(MO))
2638 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2639 /// relative block address instruction
2641 static unsigned sizePCRelativeBlockAddress() {
2645 /// sizeGlobalAddress - Give the size of the emission of this global address
2647 static unsigned sizeGlobalAddress(bool dword) {
2648 return dword ? 8 : 4;
2651 /// sizeConstPoolAddress - Give the size of the emission of this constant
2654 static unsigned sizeConstPoolAddress(bool dword) {
2655 return dword ? 8 : 4;
2658 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2661 static unsigned sizeExternalSymbolAddress(bool dword) {
2662 return dword ? 8 : 4;
2665 /// sizeJumpTableAddress - Give the size of the emission of this jump
2668 static unsigned sizeJumpTableAddress(bool dword) {
2669 return dword ? 8 : 4;
2672 static unsigned sizeConstant(unsigned Size) {
2676 static unsigned sizeRegModRMByte(){
2680 static unsigned sizeSIBByte(){
2684 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2685 unsigned FinalSize = 0;
2686 // If this is a simple integer displacement that doesn't require a relocation.
2688 FinalSize += sizeConstant(4);
2692 // Otherwise, this is something that requires a relocation.
2693 if (RelocOp->isGlobal()) {
2694 FinalSize += sizeGlobalAddress(false);
2695 } else if (RelocOp->isCPI()) {
2696 FinalSize += sizeConstPoolAddress(false);
2697 } else if (RelocOp->isJTI()) {
2698 FinalSize += sizeJumpTableAddress(false);
2700 assert(0 && "Unknown value to relocate!");
2705 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2706 bool IsPIC, bool Is64BitMode) {
2707 const MachineOperand &Op3 = MI.getOperand(Op+3);
2709 const MachineOperand *DispForReloc = 0;
2710 unsigned FinalSize = 0;
2712 // Figure out what sort of displacement we have to handle here.
2713 if (Op3.isGlobal()) {
2714 DispForReloc = &Op3;
2715 } else if (Op3.isCPI()) {
2716 if (Is64BitMode || IsPIC) {
2717 DispForReloc = &Op3;
2721 } else if (Op3.isJTI()) {
2722 if (Is64BitMode || IsPIC) {
2723 DispForReloc = &Op3;
2731 const MachineOperand &Base = MI.getOperand(Op);
2732 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2734 unsigned BaseReg = Base.getReg();
2736 // Is a SIB byte needed?
2737 if (IndexReg.getReg() == 0 &&
2738 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2739 if (BaseReg == 0) { // Just a displacement?
2740 // Emit special case [disp32] encoding
2742 FinalSize += getDisplacementFieldSize(DispForReloc);
2744 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2745 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2746 // Emit simple indirect register encoding... [EAX] f.e.
2748 // Be pessimistic and assume it's a disp32, not a disp8
2750 // Emit the most general non-SIB encoding: [REG+disp32]
2752 FinalSize += getDisplacementFieldSize(DispForReloc);
2756 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2757 assert(IndexReg.getReg() != X86::ESP &&
2758 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2760 bool ForceDisp32 = false;
2761 if (BaseReg == 0 || DispForReloc) {
2762 // Emit the normal disp32 encoding.
2769 FinalSize += sizeSIBByte();
2771 // Do we need to output a displacement?
2772 if (DispVal != 0 || ForceDisp32) {
2773 FinalSize += getDisplacementFieldSize(DispForReloc);
2780 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2781 const TargetInstrDesc *Desc,
2782 bool IsPIC, bool Is64BitMode) {
2784 unsigned Opcode = Desc->Opcode;
2785 unsigned FinalSize = 0;
2787 // Emit the lock opcode prefix as needed.
2788 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2790 // Emit segment overrid opcode prefix as needed.
2791 switch (Desc->TSFlags & X86II::SegOvrMask) {
2796 default: assert(0 && "Invalid segment!");
2797 case 0: break; // No segment override!
2800 // Emit the repeat opcode prefix as needed.
2801 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2803 // Emit the operand size opcode prefix as needed.
2804 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2806 // Emit the address size opcode prefix as needed.
2807 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2809 bool Need0FPrefix = false;
2810 switch (Desc->TSFlags & X86II::Op0Mask) {
2811 case X86II::TB: // Two-byte opcode prefix
2812 case X86II::T8: // 0F 38
2813 case X86II::TA: // 0F 3A
2814 Need0FPrefix = true;
2816 case X86II::REP: break; // already handled.
2817 case X86II::XS: // F3 0F
2819 Need0FPrefix = true;
2821 case X86II::XD: // F2 0F
2823 Need0FPrefix = true;
2825 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2826 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2828 break; // Two-byte opcode prefix
2829 default: assert(0 && "Invalid prefix!");
2830 case 0: break; // No prefix!
2835 unsigned REX = X86InstrInfo::determineREX(MI);
2840 // 0x0F escape code must be emitted just before the opcode.
2844 switch (Desc->TSFlags & X86II::Op0Mask) {
2845 case X86II::T8: // 0F 38
2848 case X86II::TA: // 0F 3A
2853 // If this is a two-address instruction, skip one of the register operands.
2854 unsigned NumOps = Desc->getNumOperands();
2856 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2859 switch (Desc->TSFlags & X86II::FormMask) {
2860 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
2862 // Remember the current PC offset, this is the PIC relocation
2867 case TargetInstrInfo::INLINEASM: {
2868 const MachineFunction *MF = MI.getParent()->getParent();
2869 const char *AsmStr = MI.getOperand(0).getSymbolName();
2870 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
2871 FinalSize += AI->getInlineAsmLength(AsmStr);
2874 case TargetInstrInfo::DBG_LABEL:
2875 case TargetInstrInfo::EH_LABEL:
2877 case TargetInstrInfo::IMPLICIT_DEF:
2878 case TargetInstrInfo::DECLARE:
2879 case X86::DWARF_LOC:
2880 case X86::FP_REG_KILL:
2882 case X86::MOVPC32r: {
2883 // This emits the "call" portion of this pseudo instruction.
2885 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2889 case X86::TLS_gs_ri:
2891 FinalSize += sizeGlobalAddress(false);
2899 if (CurOp != NumOps) {
2900 const MachineOperand &MO = MI.getOperand(CurOp++);
2902 FinalSize += sizePCRelativeBlockAddress();
2903 } else if (MO.isGlobal()) {
2904 FinalSize += sizeGlobalAddress(false);
2905 } else if (MO.isSymbol()) {
2906 FinalSize += sizeExternalSymbolAddress(false);
2907 } else if (MO.isImm()) {
2908 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2910 assert(0 && "Unknown RawFrm operand!");
2915 case X86II::AddRegFrm:
2919 if (CurOp != NumOps) {
2920 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2921 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2923 FinalSize += sizeConstant(Size);
2926 if (Opcode == X86::MOV64ri)
2928 if (MO1.isGlobal()) {
2929 FinalSize += sizeGlobalAddress(dword);
2930 } else if (MO1.isSymbol())
2931 FinalSize += sizeExternalSymbolAddress(dword);
2932 else if (MO1.isCPI())
2933 FinalSize += sizeConstPoolAddress(dword);
2934 else if (MO1.isJTI())
2935 FinalSize += sizeJumpTableAddress(dword);
2940 case X86II::MRMDestReg: {
2942 FinalSize += sizeRegModRMByte();
2944 if (CurOp != NumOps) {
2946 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2950 case X86II::MRMDestMem: {
2952 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2954 if (CurOp != NumOps) {
2956 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2961 case X86II::MRMSrcReg:
2963 FinalSize += sizeRegModRMByte();
2965 if (CurOp != NumOps) {
2967 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2971 case X86II::MRMSrcMem: {
2974 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
2976 if (CurOp != NumOps) {
2978 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2983 case X86II::MRM0r: case X86II::MRM1r:
2984 case X86II::MRM2r: case X86II::MRM3r:
2985 case X86II::MRM4r: case X86II::MRM5r:
2986 case X86II::MRM6r: case X86II::MRM7r:
2989 FinalSize += sizeRegModRMByte();
2991 if (CurOp != NumOps) {
2992 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2993 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2995 FinalSize += sizeConstant(Size);
2998 if (Opcode == X86::MOV64ri32)
3000 if (MO1.isGlobal()) {
3001 FinalSize += sizeGlobalAddress(dword);
3002 } else if (MO1.isSymbol())
3003 FinalSize += sizeExternalSymbolAddress(dword);
3004 else if (MO1.isCPI())
3005 FinalSize += sizeConstPoolAddress(dword);
3006 else if (MO1.isJTI())
3007 FinalSize += sizeJumpTableAddress(dword);
3012 case X86II::MRM0m: case X86II::MRM1m:
3013 case X86II::MRM2m: case X86II::MRM3m:
3014 case X86II::MRM4m: case X86II::MRM5m:
3015 case X86II::MRM6m: case X86II::MRM7m: {
3018 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3021 if (CurOp != NumOps) {
3022 const MachineOperand &MO = MI.getOperand(CurOp++);
3023 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3025 FinalSize += sizeConstant(Size);
3028 if (Opcode == X86::MOV64mi32)
3030 if (MO.isGlobal()) {
3031 FinalSize += sizeGlobalAddress(dword);
3032 } else if (MO.isSymbol())
3033 FinalSize += sizeExternalSymbolAddress(dword);
3034 else if (MO.isCPI())
3035 FinalSize += sizeConstPoolAddress(dword);
3036 else if (MO.isJTI())
3037 FinalSize += sizeJumpTableAddress(dword);
3043 case X86II::MRMInitReg:
3045 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3046 FinalSize += sizeRegModRMByte();
3051 if (!Desc->isVariadic() && CurOp != NumOps) {
3052 cerr << "Cannot determine size: ";
3063 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3064 const TargetInstrDesc &Desc = MI->getDesc();
3065 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
3066 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3067 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3068 if (Desc.getOpcode() == X86::MOVPC32r) {
3069 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3074 /// getGlobalBaseReg - Return a virtual register initialized with the
3075 /// the global base register value. Output instructions required to
3076 /// initialize the register in the function entry block, if necessary.
3078 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3079 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3080 "X86-64 PIC uses RIP relative addressing");
3082 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3083 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3084 if (GlobalBaseReg != 0)
3085 return GlobalBaseReg;
3087 // Insert the set of GlobalBaseReg into the first MBB of the function
3088 MachineBasicBlock &FirstMBB = MF->front();
3089 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3090 DebugLoc DL = DebugLoc::getUnknownLoc();
3091 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3092 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3093 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3095 const TargetInstrInfo *TII = TM.getInstrInfo();
3096 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3097 // only used in JIT code emission as displacement to pc.
3098 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC)
3101 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3102 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
3103 if (TM.getRelocationModel() == Reloc::PIC_ &&
3104 TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3106 RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3107 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3108 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
3113 X86FI->setGlobalBaseReg(GlobalBaseReg);
3114 return GlobalBaseReg;