1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/MC/MCAsmInfo.h"
41 NoFusing("disable-spill-fusing",
42 cl::desc("Disable fusing of spill code into instructions"));
44 PrintFailedFusing("print-failed-fuse-candidates",
45 cl::desc("Print instructions that the allocator wants to"
46 " fuse, but the X86 backend currently can't"),
49 ReMatPICStubLoad("remat-pic-stub-load",
50 cl::desc("Re-materialize load from stub in PIC mode"),
51 cl::init(false), cl::Hidden);
53 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
54 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
55 TM(tm), RI(tm, *this) {
56 SmallVector<unsigned,16> AmbEntries;
57 static const unsigned OpTbl2Addr[][2] = {
58 { X86::ADC32ri, X86::ADC32mi },
59 { X86::ADC32ri8, X86::ADC32mi8 },
60 { X86::ADC32rr, X86::ADC32mr },
61 { X86::ADC64ri32, X86::ADC64mi32 },
62 { X86::ADC64ri8, X86::ADC64mi8 },
63 { X86::ADC64rr, X86::ADC64mr },
64 { X86::ADD16ri, X86::ADD16mi },
65 { X86::ADD16ri8, X86::ADD16mi8 },
66 { X86::ADD16rr, X86::ADD16mr },
67 { X86::ADD32ri, X86::ADD32mi },
68 { X86::ADD32ri8, X86::ADD32mi8 },
69 { X86::ADD32rr, X86::ADD32mr },
70 { X86::ADD64ri32, X86::ADD64mi32 },
71 { X86::ADD64ri8, X86::ADD64mi8 },
72 { X86::ADD64rr, X86::ADD64mr },
73 { X86::ADD8ri, X86::ADD8mi },
74 { X86::ADD8rr, X86::ADD8mr },
75 { X86::AND16ri, X86::AND16mi },
76 { X86::AND16ri8, X86::AND16mi8 },
77 { X86::AND16rr, X86::AND16mr },
78 { X86::AND32ri, X86::AND32mi },
79 { X86::AND32ri8, X86::AND32mi8 },
80 { X86::AND32rr, X86::AND32mr },
81 { X86::AND64ri32, X86::AND64mi32 },
82 { X86::AND64ri8, X86::AND64mi8 },
83 { X86::AND64rr, X86::AND64mr },
84 { X86::AND8ri, X86::AND8mi },
85 { X86::AND8rr, X86::AND8mr },
86 { X86::DEC16r, X86::DEC16m },
87 { X86::DEC32r, X86::DEC32m },
88 { X86::DEC64_16r, X86::DEC64_16m },
89 { X86::DEC64_32r, X86::DEC64_32m },
90 { X86::DEC64r, X86::DEC64m },
91 { X86::DEC8r, X86::DEC8m },
92 { X86::INC16r, X86::INC16m },
93 { X86::INC32r, X86::INC32m },
94 { X86::INC64_16r, X86::INC64_16m },
95 { X86::INC64_32r, X86::INC64_32m },
96 { X86::INC64r, X86::INC64m },
97 { X86::INC8r, X86::INC8m },
98 { X86::NEG16r, X86::NEG16m },
99 { X86::NEG32r, X86::NEG32m },
100 { X86::NEG64r, X86::NEG64m },
101 { X86::NEG8r, X86::NEG8m },
102 { X86::NOT16r, X86::NOT16m },
103 { X86::NOT32r, X86::NOT32m },
104 { X86::NOT64r, X86::NOT64m },
105 { X86::NOT8r, X86::NOT8m },
106 { X86::OR16ri, X86::OR16mi },
107 { X86::OR16ri8, X86::OR16mi8 },
108 { X86::OR16rr, X86::OR16mr },
109 { X86::OR32ri, X86::OR32mi },
110 { X86::OR32ri8, X86::OR32mi8 },
111 { X86::OR32rr, X86::OR32mr },
112 { X86::OR64ri32, X86::OR64mi32 },
113 { X86::OR64ri8, X86::OR64mi8 },
114 { X86::OR64rr, X86::OR64mr },
115 { X86::OR8ri, X86::OR8mi },
116 { X86::OR8rr, X86::OR8mr },
117 { X86::ROL16r1, X86::ROL16m1 },
118 { X86::ROL16rCL, X86::ROL16mCL },
119 { X86::ROL16ri, X86::ROL16mi },
120 { X86::ROL32r1, X86::ROL32m1 },
121 { X86::ROL32rCL, X86::ROL32mCL },
122 { X86::ROL32ri, X86::ROL32mi },
123 { X86::ROL64r1, X86::ROL64m1 },
124 { X86::ROL64rCL, X86::ROL64mCL },
125 { X86::ROL64ri, X86::ROL64mi },
126 { X86::ROL8r1, X86::ROL8m1 },
127 { X86::ROL8rCL, X86::ROL8mCL },
128 { X86::ROL8ri, X86::ROL8mi },
129 { X86::ROR16r1, X86::ROR16m1 },
130 { X86::ROR16rCL, X86::ROR16mCL },
131 { X86::ROR16ri, X86::ROR16mi },
132 { X86::ROR32r1, X86::ROR32m1 },
133 { X86::ROR32rCL, X86::ROR32mCL },
134 { X86::ROR32ri, X86::ROR32mi },
135 { X86::ROR64r1, X86::ROR64m1 },
136 { X86::ROR64rCL, X86::ROR64mCL },
137 { X86::ROR64ri, X86::ROR64mi },
138 { X86::ROR8r1, X86::ROR8m1 },
139 { X86::ROR8rCL, X86::ROR8mCL },
140 { X86::ROR8ri, X86::ROR8mi },
141 { X86::SAR16r1, X86::SAR16m1 },
142 { X86::SAR16rCL, X86::SAR16mCL },
143 { X86::SAR16ri, X86::SAR16mi },
144 { X86::SAR32r1, X86::SAR32m1 },
145 { X86::SAR32rCL, X86::SAR32mCL },
146 { X86::SAR32ri, X86::SAR32mi },
147 { X86::SAR64r1, X86::SAR64m1 },
148 { X86::SAR64rCL, X86::SAR64mCL },
149 { X86::SAR64ri, X86::SAR64mi },
150 { X86::SAR8r1, X86::SAR8m1 },
151 { X86::SAR8rCL, X86::SAR8mCL },
152 { X86::SAR8ri, X86::SAR8mi },
153 { X86::SBB32ri, X86::SBB32mi },
154 { X86::SBB32ri8, X86::SBB32mi8 },
155 { X86::SBB32rr, X86::SBB32mr },
156 { X86::SBB64ri32, X86::SBB64mi32 },
157 { X86::SBB64ri8, X86::SBB64mi8 },
158 { X86::SBB64rr, X86::SBB64mr },
159 { X86::SHL16rCL, X86::SHL16mCL },
160 { X86::SHL16ri, X86::SHL16mi },
161 { X86::SHL32rCL, X86::SHL32mCL },
162 { X86::SHL32ri, X86::SHL32mi },
163 { X86::SHL64rCL, X86::SHL64mCL },
164 { X86::SHL64ri, X86::SHL64mi },
165 { X86::SHL8rCL, X86::SHL8mCL },
166 { X86::SHL8ri, X86::SHL8mi },
167 { X86::SHLD16rrCL, X86::SHLD16mrCL },
168 { X86::SHLD16rri8, X86::SHLD16mri8 },
169 { X86::SHLD32rrCL, X86::SHLD32mrCL },
170 { X86::SHLD32rri8, X86::SHLD32mri8 },
171 { X86::SHLD64rrCL, X86::SHLD64mrCL },
172 { X86::SHLD64rri8, X86::SHLD64mri8 },
173 { X86::SHR16r1, X86::SHR16m1 },
174 { X86::SHR16rCL, X86::SHR16mCL },
175 { X86::SHR16ri, X86::SHR16mi },
176 { X86::SHR32r1, X86::SHR32m1 },
177 { X86::SHR32rCL, X86::SHR32mCL },
178 { X86::SHR32ri, X86::SHR32mi },
179 { X86::SHR64r1, X86::SHR64m1 },
180 { X86::SHR64rCL, X86::SHR64mCL },
181 { X86::SHR64ri, X86::SHR64mi },
182 { X86::SHR8r1, X86::SHR8m1 },
183 { X86::SHR8rCL, X86::SHR8mCL },
184 { X86::SHR8ri, X86::SHR8mi },
185 { X86::SHRD16rrCL, X86::SHRD16mrCL },
186 { X86::SHRD16rri8, X86::SHRD16mri8 },
187 { X86::SHRD32rrCL, X86::SHRD32mrCL },
188 { X86::SHRD32rri8, X86::SHRD32mri8 },
189 { X86::SHRD64rrCL, X86::SHRD64mrCL },
190 { X86::SHRD64rri8, X86::SHRD64mri8 },
191 { X86::SUB16ri, X86::SUB16mi },
192 { X86::SUB16ri8, X86::SUB16mi8 },
193 { X86::SUB16rr, X86::SUB16mr },
194 { X86::SUB32ri, X86::SUB32mi },
195 { X86::SUB32ri8, X86::SUB32mi8 },
196 { X86::SUB32rr, X86::SUB32mr },
197 { X86::SUB64ri32, X86::SUB64mi32 },
198 { X86::SUB64ri8, X86::SUB64mi8 },
199 { X86::SUB64rr, X86::SUB64mr },
200 { X86::SUB8ri, X86::SUB8mi },
201 { X86::SUB8rr, X86::SUB8mr },
202 { X86::XOR16ri, X86::XOR16mi },
203 { X86::XOR16ri8, X86::XOR16mi8 },
204 { X86::XOR16rr, X86::XOR16mr },
205 { X86::XOR32ri, X86::XOR32mi },
206 { X86::XOR32ri8, X86::XOR32mi8 },
207 { X86::XOR32rr, X86::XOR32mr },
208 { X86::XOR64ri32, X86::XOR64mi32 },
209 { X86::XOR64ri8, X86::XOR64mi8 },
210 { X86::XOR64rr, X86::XOR64mr },
211 { X86::XOR8ri, X86::XOR8mi },
212 { X86::XOR8rr, X86::XOR8mr }
215 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
216 unsigned RegOp = OpTbl2Addr[i][0];
217 unsigned MemOp = OpTbl2Addr[i][1];
218 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
219 std::make_pair(MemOp,0))).second)
220 assert(false && "Duplicated entries?");
221 // Index 0, folded load and store, no alignment requirement.
222 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
223 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
224 std::make_pair(RegOp,
226 AmbEntries.push_back(MemOp);
229 // If the third value is 1, then it's folding either a load or a store.
230 static const unsigned OpTbl0[][4] = {
231 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
232 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
233 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
234 { X86::CALL32r, X86::CALL32m, 1, 0 },
235 { X86::CALL64r, X86::CALL64m, 1, 0 },
236 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
237 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
238 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
239 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
240 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
241 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
242 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
243 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
244 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
245 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
246 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
247 { X86::DIV16r, X86::DIV16m, 1, 0 },
248 { X86::DIV32r, X86::DIV32m, 1, 0 },
249 { X86::DIV64r, X86::DIV64m, 1, 0 },
250 { X86::DIV8r, X86::DIV8m, 1, 0 },
251 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
252 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
253 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
254 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
255 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
256 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
257 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
258 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
259 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
260 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
261 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
262 { X86::JMP32r, X86::JMP32m, 1, 0 },
263 { X86::JMP64r, X86::JMP64m, 1, 0 },
264 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
265 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
266 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
267 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
268 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
269 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
270 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
271 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
272 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
273 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
274 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
275 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
276 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
277 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
278 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 },
279 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 },
280 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
281 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
282 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 },
283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
285 { X86::MUL16r, X86::MUL16m, 1, 0 },
286 { X86::MUL32r, X86::MUL32m, 1, 0 },
287 { X86::MUL64r, X86::MUL64m, 1, 0 },
288 { X86::MUL8r, X86::MUL8m, 1, 0 },
289 { X86::SETAEr, X86::SETAEm, 0, 0 },
290 { X86::SETAr, X86::SETAm, 0, 0 },
291 { X86::SETBEr, X86::SETBEm, 0, 0 },
292 { X86::SETBr, X86::SETBm, 0, 0 },
293 { X86::SETEr, X86::SETEm, 0, 0 },
294 { X86::SETGEr, X86::SETGEm, 0, 0 },
295 { X86::SETGr, X86::SETGm, 0, 0 },
296 { X86::SETLEr, X86::SETLEm, 0, 0 },
297 { X86::SETLr, X86::SETLm, 0, 0 },
298 { X86::SETNEr, X86::SETNEm, 0, 0 },
299 { X86::SETNOr, X86::SETNOm, 0, 0 },
300 { X86::SETNPr, X86::SETNPm, 0, 0 },
301 { X86::SETNSr, X86::SETNSm, 0, 0 },
302 { X86::SETOr, X86::SETOm, 0, 0 },
303 { X86::SETPr, X86::SETPm, 0, 0 },
304 { X86::SETSr, X86::SETSm, 0, 0 },
305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
306 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
307 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
308 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
309 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
312 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
313 unsigned RegOp = OpTbl0[i][0];
314 unsigned MemOp = OpTbl0[i][1];
315 unsigned Align = OpTbl0[i][3];
316 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
317 std::make_pair(MemOp,Align))).second)
318 assert(false && "Duplicated entries?");
319 unsigned FoldedLoad = OpTbl0[i][2];
320 // Index 0, folded load or store.
321 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
322 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
323 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
324 std::make_pair(RegOp, AuxInfo))).second)
325 AmbEntries.push_back(MemOp);
328 static const unsigned OpTbl1[][3] = {
329 { X86::CMP16rr, X86::CMP16rm, 0 },
330 { X86::CMP32rr, X86::CMP32rm, 0 },
331 { X86::CMP64rr, X86::CMP64rm, 0 },
332 { X86::CMP8rr, X86::CMP8rm, 0 },
333 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
334 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
335 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
336 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
337 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
338 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
339 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
340 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
341 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
342 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
343 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
344 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
345 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
346 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
347 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
348 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
349 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
350 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
351 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
352 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
353 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
354 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
355 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
356 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
357 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
358 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
359 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
360 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
361 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
362 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
363 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
364 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
365 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
366 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
367 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
368 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
369 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
370 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
371 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
372 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
373 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
374 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
375 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
376 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
377 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
378 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
379 { X86::MOV16rr, X86::MOV16rm, 0 },
380 { X86::MOV32rr, X86::MOV32rm, 0 },
381 { X86::MOV64rr, X86::MOV64rm, 0 },
382 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
383 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
384 { X86::MOV8rr, X86::MOV8rm, 0 },
385 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
386 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
387 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
388 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
389 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
390 { X86::MOVDQArr, X86::MOVDQArm, 16 },
391 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 },
392 { X86::MOVSDrr, X86::MOVSDrm, 0 },
393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
395 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 },
396 { X86::MOVSSrr, X86::MOVSSrm, 0 },
397 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
398 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
399 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
400 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
401 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
402 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
403 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
404 { X86::MOVUPSrr, X86::MOVUPSrm, 16 },
405 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
406 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
407 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
408 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
409 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
410 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
411 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
412 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
413 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
414 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
415 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
416 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
417 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
418 { X86::RCPPSr, X86::RCPPSm, 16 },
419 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
420 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
421 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
422 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
423 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
424 { X86::SQRTPDr, X86::SQRTPDm, 16 },
425 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
426 { X86::SQRTPSr, X86::SQRTPSm, 16 },
427 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
428 { X86::SQRTSDr, X86::SQRTSDm, 0 },
429 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
430 { X86::SQRTSSr, X86::SQRTSSm, 0 },
431 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
432 { X86::TEST16rr, X86::TEST16rm, 0 },
433 { X86::TEST32rr, X86::TEST32rm, 0 },
434 { X86::TEST64rr, X86::TEST64rm, 0 },
435 { X86::TEST8rr, X86::TEST8rm, 0 },
436 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
437 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
438 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
441 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
442 unsigned RegOp = OpTbl1[i][0];
443 unsigned MemOp = OpTbl1[i][1];
444 unsigned Align = OpTbl1[i][2];
445 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
446 std::make_pair(MemOp,Align))).second)
447 assert(false && "Duplicated entries?");
448 // Index 1, folded load
449 unsigned AuxInfo = 1 | (1 << 4);
450 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
451 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
452 std::make_pair(RegOp, AuxInfo))).second)
453 AmbEntries.push_back(MemOp);
456 static const unsigned OpTbl2[][3] = {
457 { X86::ADC32rr, X86::ADC32rm, 0 },
458 { X86::ADC64rr, X86::ADC64rm, 0 },
459 { X86::ADD16rr, X86::ADD16rm, 0 },
460 { X86::ADD32rr, X86::ADD32rm, 0 },
461 { X86::ADD64rr, X86::ADD64rm, 0 },
462 { X86::ADD8rr, X86::ADD8rm, 0 },
463 { X86::ADDPDrr, X86::ADDPDrm, 16 },
464 { X86::ADDPSrr, X86::ADDPSrm, 16 },
465 { X86::ADDSDrr, X86::ADDSDrm, 0 },
466 { X86::ADDSSrr, X86::ADDSSrm, 0 },
467 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
468 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
469 { X86::AND16rr, X86::AND16rm, 0 },
470 { X86::AND32rr, X86::AND32rm, 0 },
471 { X86::AND64rr, X86::AND64rm, 0 },
472 { X86::AND8rr, X86::AND8rm, 0 },
473 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
474 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
475 { X86::ANDPDrr, X86::ANDPDrm, 16 },
476 { X86::ANDPSrr, X86::ANDPSrm, 16 },
477 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
478 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
479 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
480 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
481 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
482 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
483 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
484 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
485 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
486 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
487 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
488 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
489 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
490 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
491 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
492 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
493 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
494 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
495 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
496 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
497 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
498 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
499 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
500 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
501 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
502 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
503 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
504 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
505 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
506 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
507 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
508 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
509 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
510 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
511 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
512 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
513 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
514 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
515 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
516 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
517 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
518 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
519 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
520 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
521 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
522 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
523 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
524 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
525 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
526 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
527 { X86::CMPSDrr, X86::CMPSDrm, 0 },
528 { X86::CMPSSrr, X86::CMPSSrm, 0 },
529 { X86::DIVPDrr, X86::DIVPDrm, 16 },
530 { X86::DIVPSrr, X86::DIVPSrm, 16 },
531 { X86::DIVSDrr, X86::DIVSDrm, 0 },
532 { X86::DIVSSrr, X86::DIVSSrm, 0 },
533 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
534 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
535 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
536 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
537 { X86::FsORPDrr, X86::FsORPDrm, 16 },
538 { X86::FsORPSrr, X86::FsORPSrm, 16 },
539 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
540 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
541 { X86::HADDPDrr, X86::HADDPDrm, 16 },
542 { X86::HADDPSrr, X86::HADDPSrm, 16 },
543 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
544 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
545 { X86::IMUL16rr, X86::IMUL16rm, 0 },
546 { X86::IMUL32rr, X86::IMUL32rm, 0 },
547 { X86::IMUL64rr, X86::IMUL64rm, 0 },
548 { X86::MAXPDrr, X86::MAXPDrm, 16 },
549 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
550 { X86::MAXPSrr, X86::MAXPSrm, 16 },
551 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
552 { X86::MAXSDrr, X86::MAXSDrm, 0 },
553 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
554 { X86::MAXSSrr, X86::MAXSSrm, 0 },
555 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
556 { X86::MINPDrr, X86::MINPDrm, 16 },
557 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
558 { X86::MINPSrr, X86::MINPSrm, 16 },
559 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
560 { X86::MINSDrr, X86::MINSDrm, 0 },
561 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
562 { X86::MINSSrr, X86::MINSSrm, 0 },
563 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
564 { X86::MULPDrr, X86::MULPDrm, 16 },
565 { X86::MULPSrr, X86::MULPSrm, 16 },
566 { X86::MULSDrr, X86::MULSDrm, 0 },
567 { X86::MULSSrr, X86::MULSSrm, 0 },
568 { X86::OR16rr, X86::OR16rm, 0 },
569 { X86::OR32rr, X86::OR32rm, 0 },
570 { X86::OR64rr, X86::OR64rm, 0 },
571 { X86::OR8rr, X86::OR8rm, 0 },
572 { X86::ORPDrr, X86::ORPDrm, 16 },
573 { X86::ORPSrr, X86::ORPSrm, 16 },
574 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
575 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
576 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
577 { X86::PADDBrr, X86::PADDBrm, 16 },
578 { X86::PADDDrr, X86::PADDDrm, 16 },
579 { X86::PADDQrr, X86::PADDQrm, 16 },
580 { X86::PADDSBrr, X86::PADDSBrm, 16 },
581 { X86::PADDSWrr, X86::PADDSWrm, 16 },
582 { X86::PADDWrr, X86::PADDWrm, 16 },
583 { X86::PANDNrr, X86::PANDNrm, 16 },
584 { X86::PANDrr, X86::PANDrm, 16 },
585 { X86::PAVGBrr, X86::PAVGBrm, 16 },
586 { X86::PAVGWrr, X86::PAVGWrm, 16 },
587 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
588 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
589 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
590 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
591 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
592 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
593 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
594 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
595 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
596 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
597 { X86::PMINSWrr, X86::PMINSWrm, 16 },
598 { X86::PMINUBrr, X86::PMINUBrm, 16 },
599 { X86::PMULDQrr, X86::PMULDQrm, 16 },
600 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
601 { X86::PMULHWrr, X86::PMULHWrm, 16 },
602 { X86::PMULLDrr, X86::PMULLDrm, 16 },
603 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
604 { X86::PMULLWrr, X86::PMULLWrm, 16 },
605 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
606 { X86::PORrr, X86::PORrm, 16 },
607 { X86::PSADBWrr, X86::PSADBWrm, 16 },
608 { X86::PSLLDrr, X86::PSLLDrm, 16 },
609 { X86::PSLLQrr, X86::PSLLQrm, 16 },
610 { X86::PSLLWrr, X86::PSLLWrm, 16 },
611 { X86::PSRADrr, X86::PSRADrm, 16 },
612 { X86::PSRAWrr, X86::PSRAWrm, 16 },
613 { X86::PSRLDrr, X86::PSRLDrm, 16 },
614 { X86::PSRLQrr, X86::PSRLQrm, 16 },
615 { X86::PSRLWrr, X86::PSRLWrm, 16 },
616 { X86::PSUBBrr, X86::PSUBBrm, 16 },
617 { X86::PSUBDrr, X86::PSUBDrm, 16 },
618 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
619 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
620 { X86::PSUBWrr, X86::PSUBWrm, 16 },
621 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
622 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
623 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
624 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
625 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
626 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
627 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
628 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
629 { X86::PXORrr, X86::PXORrm, 16 },
630 { X86::SBB32rr, X86::SBB32rm, 0 },
631 { X86::SBB64rr, X86::SBB64rm, 0 },
632 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
633 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
634 { X86::SUB16rr, X86::SUB16rm, 0 },
635 { X86::SUB32rr, X86::SUB32rm, 0 },
636 { X86::SUB64rr, X86::SUB64rm, 0 },
637 { X86::SUB8rr, X86::SUB8rm, 0 },
638 { X86::SUBPDrr, X86::SUBPDrm, 16 },
639 { X86::SUBPSrr, X86::SUBPSrm, 16 },
640 { X86::SUBSDrr, X86::SUBSDrm, 0 },
641 { X86::SUBSSrr, X86::SUBSSrm, 0 },
642 // FIXME: TEST*rr -> swapped operand of TEST*mr.
643 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
644 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
645 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
646 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
647 { X86::XOR16rr, X86::XOR16rm, 0 },
648 { X86::XOR32rr, X86::XOR32rm, 0 },
649 { X86::XOR64rr, X86::XOR64rm, 0 },
650 { X86::XOR8rr, X86::XOR8rm, 0 },
651 { X86::XORPDrr, X86::XORPDrm, 16 },
652 { X86::XORPSrr, X86::XORPSrm, 16 }
655 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
656 unsigned RegOp = OpTbl2[i][0];
657 unsigned MemOp = OpTbl2[i][1];
658 unsigned Align = OpTbl2[i][2];
659 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
660 std::make_pair(MemOp,Align))).second)
661 assert(false && "Duplicated entries?");
662 // Index 2, folded load
663 unsigned AuxInfo = 2 | (1 << 4);
664 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
665 std::make_pair(RegOp, AuxInfo))).second)
666 AmbEntries.push_back(MemOp);
669 // Remove ambiguous entries.
670 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
673 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
674 unsigned &SrcReg, unsigned &DstReg,
675 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
676 switch (MI.getOpcode()) {
680 case X86::MOV8rr_NOREX:
687 // FP Stack register class copies
688 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
689 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
690 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
692 case X86::FsMOVAPSrr:
693 case X86::FsMOVAPDrr:
697 case X86::MOVSS2PSrr:
698 case X86::MOVSD2PDrr:
699 case X86::MOVPS2SSrr:
700 case X86::MOVPD2SDrr:
701 case X86::MMX_MOVQ64rr:
702 assert(MI.getNumOperands() >= 2 &&
703 MI.getOperand(0).isReg() &&
704 MI.getOperand(1).isReg() &&
705 "invalid register-register move instruction");
706 SrcReg = MI.getOperand(1).getReg();
707 DstReg = MI.getOperand(0).getReg();
708 SrcSubIdx = MI.getOperand(1).getSubReg();
709 DstSubIdx = MI.getOperand(0).getSubReg();
714 /// isFrameOperand - Return true and the FrameIndex if the specified
715 /// operand and follow operands form a reference to the stack frame.
716 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
717 int &FrameIndex) const {
718 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
719 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
720 MI->getOperand(Op+1).getImm() == 1 &&
721 MI->getOperand(Op+2).getReg() == 0 &&
722 MI->getOperand(Op+3).getImm() == 0) {
723 FrameIndex = MI->getOperand(Op).getIndex();
729 static bool isFrameLoadOpcode(int Opcode) {
742 case X86::MMX_MOVD64rm:
743 case X86::MMX_MOVQ64rm:
750 static bool isFrameStoreOpcode(int Opcode) {
763 case X86::MMX_MOVD64mr:
764 case X86::MMX_MOVQ64mr:
765 case X86::MMX_MOVNTQmr:
771 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
772 int &FrameIndex) const {
773 if (isFrameLoadOpcode(MI->getOpcode()))
774 if (isFrameOperand(MI, 1, FrameIndex))
775 return MI->getOperand(0).getReg();
779 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
780 int &FrameIndex) const {
781 if (isFrameLoadOpcode(MI->getOpcode())) {
783 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
785 // Check for post-frame index elimination operations
786 const MachineMemOperand *Dummy;
787 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
792 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
793 const MachineMemOperand *&MMO,
794 int &FrameIndex) const {
795 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
796 oe = MI->memoperands_end();
799 if ((*o)->isLoad() && (*o)->getValue())
800 if (const FixedStackPseudoSourceValue *Value =
801 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
802 FrameIndex = Value->getFrameIndex();
810 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
811 int &FrameIndex) const {
812 if (isFrameStoreOpcode(MI->getOpcode()))
813 if (isFrameOperand(MI, 0, FrameIndex))
814 return MI->getOperand(X86AddrNumOperands).getReg();
818 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
819 int &FrameIndex) const {
820 if (isFrameStoreOpcode(MI->getOpcode())) {
822 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
824 // Check for post-frame index elimination operations
825 const MachineMemOperand *Dummy;
826 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
831 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
832 const MachineMemOperand *&MMO,
833 int &FrameIndex) const {
834 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
835 oe = MI->memoperands_end();
838 if ((*o)->isStore() && (*o)->getValue())
839 if (const FixedStackPseudoSourceValue *Value =
840 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
841 FrameIndex = Value->getFrameIndex();
849 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
851 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
852 bool isPICBase = false;
853 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
854 E = MRI.def_end(); I != E; ++I) {
855 MachineInstr *DefMI = I.getOperand().getParent();
856 if (DefMI->getOpcode() != X86::MOVPC32r)
858 assert(!isPICBase && "More than one PIC base?");
865 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
866 AliasAnalysis *AA) const {
867 switch (MI->getOpcode()) {
878 case X86::MOVUPSrm_Int:
881 case X86::MMX_MOVD64rm:
882 case X86::MMX_MOVQ64rm:
883 case X86::FsMOVAPSrm:
884 case X86::FsMOVAPDrm: {
885 // Loads from constant pools are trivially rematerializable.
886 if (MI->getOperand(1).isReg() &&
887 MI->getOperand(2).isImm() &&
888 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
889 MI->isInvariantLoad(AA)) {
890 unsigned BaseReg = MI->getOperand(1).getReg();
891 if (BaseReg == 0 || BaseReg == X86::RIP)
893 // Allow re-materialization of PIC load.
894 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
896 const MachineFunction &MF = *MI->getParent()->getParent();
897 const MachineRegisterInfo &MRI = MF.getRegInfo();
898 bool isPICBase = false;
899 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
900 E = MRI.def_end(); I != E; ++I) {
901 MachineInstr *DefMI = I.getOperand().getParent();
902 if (DefMI->getOpcode() != X86::MOVPC32r)
904 assert(!isPICBase && "More than one PIC base?");
914 if (MI->getOperand(2).isImm() &&
915 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
916 !MI->getOperand(4).isReg()) {
917 // lea fi#, lea GV, etc. are all rematerializable.
918 if (!MI->getOperand(1).isReg())
920 unsigned BaseReg = MI->getOperand(1).getReg();
923 // Allow re-materialization of lea PICBase + x.
924 const MachineFunction &MF = *MI->getParent()->getParent();
925 const MachineRegisterInfo &MRI = MF.getRegInfo();
926 return regIsPICBase(BaseReg, MRI);
932 // All other instructions marked M_REMATERIALIZABLE are always trivially
937 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
938 /// would clobber the EFLAGS condition register. Note the result may be
939 /// conservative. If it cannot definitely determine the safety after visiting
940 /// a few instructions in each direction it assumes it's not safe.
941 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
942 MachineBasicBlock::iterator I) {
943 // It's always safe to clobber EFLAGS at the end of a block.
947 // For compile time consideration, if we are not able to determine the
948 // safety after visiting 4 instructions in each direction, we will assume
950 MachineBasicBlock::iterator Iter = I;
951 for (unsigned i = 0; i < 4; ++i) {
952 bool SeenDef = false;
953 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
954 MachineOperand &MO = Iter->getOperand(j);
957 if (MO.getReg() == X86::EFLAGS) {
965 // This instruction defines EFLAGS, no need to look any further.
969 // If we make it to the end of the block, it's safe to clobber EFLAGS.
970 if (Iter == MBB.end())
975 for (unsigned i = 0; i < 4; ++i) {
976 // If we make it to the beginning of the block, it's safe to clobber
977 // EFLAGS iff EFLAGS is not live-in.
978 if (Iter == MBB.begin())
979 return !MBB.isLiveIn(X86::EFLAGS);
982 bool SawKill = false;
983 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
984 MachineOperand &MO = Iter->getOperand(j);
985 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
986 if (MO.isDef()) return MO.isDead();
987 if (MO.isKill()) SawKill = true;
992 // This instruction kills EFLAGS and doesn't redefine it, so
993 // there's no need to look further.
997 // Conservative answer.
1001 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1002 MachineBasicBlock::iterator I,
1003 unsigned DestReg, unsigned SubIdx,
1004 const MachineInstr *Orig,
1005 const TargetRegisterInfo *TRI) const {
1006 DebugLoc DL = DebugLoc::getUnknownLoc();
1007 if (I != MBB.end()) DL = I->getDebugLoc();
1009 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1010 DestReg = TRI->getSubReg(DestReg, SubIdx);
1014 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1015 // Re-materialize them as movri instructions to avoid side effects.
1017 unsigned Opc = Orig->getOpcode();
1022 case X86::MOV32r0: {
1023 if (!isSafeToClobberEFLAGS(MBB, I)) {
1026 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1027 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1028 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1037 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1038 MI->getOperand(0).setReg(DestReg);
1041 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1044 MachineInstr *NewMI = prior(I);
1045 NewMI->getOperand(0).setSubReg(SubIdx);
1048 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1049 /// is not marked dead.
1050 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1051 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1052 MachineOperand &MO = MI->getOperand(i);
1053 if (MO.isReg() && MO.isDef() &&
1054 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1061 /// convertToThreeAddress - This method must be implemented by targets that
1062 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1063 /// may be able to convert a two-address instruction into a true
1064 /// three-address instruction on demand. This allows the X86 target (for
1065 /// example) to convert ADD and SHL instructions into LEA instructions if they
1066 /// would require register copies due to two-addressness.
1068 /// This method returns a null pointer if the transformation cannot be
1069 /// performed, otherwise it returns the new instruction.
1072 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1073 MachineBasicBlock::iterator &MBBI,
1074 LiveVariables *LV) const {
1075 MachineInstr *MI = MBBI;
1076 MachineFunction &MF = *MI->getParent()->getParent();
1077 // All instructions input are two-addr instructions. Get the known operands.
1078 unsigned Dest = MI->getOperand(0).getReg();
1079 unsigned Src = MI->getOperand(1).getReg();
1080 bool isDead = MI->getOperand(0).isDead();
1081 bool isKill = MI->getOperand(1).isKill();
1083 MachineInstr *NewMI = NULL;
1084 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1085 // we have better subtarget support, enable the 16-bit LEA generation here.
1086 bool DisableLEA16 = true;
1088 unsigned MIOpc = MI->getOpcode();
1090 case X86::SHUFPSrri: {
1091 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1092 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1094 unsigned B = MI->getOperand(1).getReg();
1095 unsigned C = MI->getOperand(2).getReg();
1096 if (B != C) return 0;
1097 unsigned A = MI->getOperand(0).getReg();
1098 unsigned M = MI->getOperand(3).getImm();
1099 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1100 .addReg(A, RegState::Define | getDeadRegState(isDead))
1101 .addReg(B, getKillRegState(isKill)).addImm(M);
1104 case X86::SHL64ri: {
1105 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1106 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1107 // the flags produced by a shift yet, so this is safe.
1108 unsigned ShAmt = MI->getOperand(2).getImm();
1109 if (ShAmt == 0 || ShAmt >= 4) return 0;
1111 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1112 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1113 .addReg(0).addImm(1 << ShAmt)
1114 .addReg(Src, getKillRegState(isKill))
1118 case X86::SHL32ri: {
1119 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1120 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1121 // the flags produced by a shift yet, so this is safe.
1122 unsigned ShAmt = MI->getOperand(2).getImm();
1123 if (ShAmt == 0 || ShAmt >= 4) return 0;
1125 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1126 X86::LEA64_32r : X86::LEA32r;
1127 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1128 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1129 .addReg(0).addImm(1 << ShAmt)
1130 .addReg(Src, getKillRegState(isKill)).addImm(0);
1133 case X86::SHL16ri: {
1134 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1135 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1136 // the flags produced by a shift yet, so this is safe.
1137 unsigned ShAmt = MI->getOperand(2).getImm();
1138 if (ShAmt == 0 || ShAmt >= 4) return 0;
1141 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1142 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1143 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1144 ? X86::LEA64_32r : X86::LEA32r;
1145 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1146 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1148 // Build and insert into an implicit UNDEF value. This is OK because
1149 // well be shifting and then extracting the lower 16-bits.
1150 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1151 MachineInstr *InsMI =
1152 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1154 .addReg(Src, getKillRegState(isKill))
1155 .addImm(X86::SUBREG_16BIT);
1157 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1158 .addReg(0).addImm(1 << ShAmt)
1159 .addReg(leaInReg, RegState::Kill)
1162 MachineInstr *ExtMI =
1163 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1164 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1165 .addReg(leaOutReg, RegState::Kill)
1166 .addImm(X86::SUBREG_16BIT);
1169 // Update live variables
1170 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1171 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1173 LV->replaceKillInstruction(Src, MI, InsMI);
1175 LV->replaceKillInstruction(Dest, MI, ExtMI);
1179 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1180 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1181 .addReg(0).addImm(1 << ShAmt)
1182 .addReg(Src, getKillRegState(isKill))
1188 // The following opcodes also sets the condition code register(s). Only
1189 // convert them to equivalent lea if the condition code register def's
1191 if (hasLiveCondCodeDef(MI))
1194 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1199 case X86::INC64_32r: {
1200 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1201 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1202 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1203 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1204 .addReg(Dest, RegState::Define |
1205 getDeadRegState(isDead)),
1210 case X86::INC64_16r:
1211 if (DisableLEA16) return 0;
1212 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1213 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1214 .addReg(Dest, RegState::Define |
1215 getDeadRegState(isDead)),
1220 case X86::DEC64_32r: {
1221 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1222 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1223 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1224 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1225 .addReg(Dest, RegState::Define |
1226 getDeadRegState(isDead)),
1231 case X86::DEC64_16r:
1232 if (DisableLEA16) return 0;
1233 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1234 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1235 .addReg(Dest, RegState::Define |
1236 getDeadRegState(isDead)),
1240 case X86::ADD32rr: {
1241 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1242 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1243 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1244 unsigned Src2 = MI->getOperand(2).getReg();
1245 bool isKill2 = MI->getOperand(2).isKill();
1246 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1247 .addReg(Dest, RegState::Define |
1248 getDeadRegState(isDead)),
1249 Src, isKill, Src2, isKill2);
1251 LV->replaceKillInstruction(Src2, MI, NewMI);
1254 case X86::ADD16rr: {
1255 if (DisableLEA16) return 0;
1256 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1257 unsigned Src2 = MI->getOperand(2).getReg();
1258 bool isKill2 = MI->getOperand(2).isKill();
1259 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1260 .addReg(Dest, RegState::Define |
1261 getDeadRegState(isDead)),
1262 Src, isKill, Src2, isKill2);
1264 LV->replaceKillInstruction(Src2, MI, NewMI);
1267 case X86::ADD64ri32:
1269 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1270 if (MI->getOperand(2).isImm())
1271 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1272 .addReg(Dest, RegState::Define |
1273 getDeadRegState(isDead)),
1274 Src, isKill, MI->getOperand(2).getImm());
1278 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1279 if (MI->getOperand(2).isImm()) {
1280 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1281 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1282 .addReg(Dest, RegState::Define |
1283 getDeadRegState(isDead)),
1284 Src, isKill, MI->getOperand(2).getImm());
1289 if (DisableLEA16) return 0;
1290 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1291 if (MI->getOperand(2).isImm())
1292 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1293 .addReg(Dest, RegState::Define |
1294 getDeadRegState(isDead)),
1295 Src, isKill, MI->getOperand(2).getImm());
1298 if (DisableLEA16) return 0;
1300 case X86::SHL64ri: {
1301 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1302 "Unknown shl instruction!");
1303 unsigned ShAmt = MI->getOperand(2).getImm();
1304 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1306 AM.Scale = 1 << ShAmt;
1308 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1309 : (MIOpc == X86::SHL32ri
1310 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1311 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1312 .addReg(Dest, RegState::Define |
1313 getDeadRegState(isDead)), AM);
1315 NewMI->getOperand(3).setIsKill(true);
1323 if (!NewMI) return 0;
1325 if (LV) { // Update live variables
1327 LV->replaceKillInstruction(Src, MI, NewMI);
1329 LV->replaceKillInstruction(Dest, MI, NewMI);
1332 MFI->insert(MBBI, NewMI); // Insert the new inst
1336 /// commuteInstruction - We have a few instructions that must be hacked on to
1340 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1341 switch (MI->getOpcode()) {
1342 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1343 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1344 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1345 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1346 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1347 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1350 switch (MI->getOpcode()) {
1351 default: llvm_unreachable("Unreachable!");
1352 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1353 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1354 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1355 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1356 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1357 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1359 unsigned Amt = MI->getOperand(3).getImm();
1361 MachineFunction &MF = *MI->getParent()->getParent();
1362 MI = MF.CloneMachineInstr(MI);
1365 MI->setDesc(get(Opc));
1366 MI->getOperand(3).setImm(Size-Amt);
1367 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1369 case X86::CMOVB16rr:
1370 case X86::CMOVB32rr:
1371 case X86::CMOVB64rr:
1372 case X86::CMOVAE16rr:
1373 case X86::CMOVAE32rr:
1374 case X86::CMOVAE64rr:
1375 case X86::CMOVE16rr:
1376 case X86::CMOVE32rr:
1377 case X86::CMOVE64rr:
1378 case X86::CMOVNE16rr:
1379 case X86::CMOVNE32rr:
1380 case X86::CMOVNE64rr:
1381 case X86::CMOVBE16rr:
1382 case X86::CMOVBE32rr:
1383 case X86::CMOVBE64rr:
1384 case X86::CMOVA16rr:
1385 case X86::CMOVA32rr:
1386 case X86::CMOVA64rr:
1387 case X86::CMOVL16rr:
1388 case X86::CMOVL32rr:
1389 case X86::CMOVL64rr:
1390 case X86::CMOVGE16rr:
1391 case X86::CMOVGE32rr:
1392 case X86::CMOVGE64rr:
1393 case X86::CMOVLE16rr:
1394 case X86::CMOVLE32rr:
1395 case X86::CMOVLE64rr:
1396 case X86::CMOVG16rr:
1397 case X86::CMOVG32rr:
1398 case X86::CMOVG64rr:
1399 case X86::CMOVS16rr:
1400 case X86::CMOVS32rr:
1401 case X86::CMOVS64rr:
1402 case X86::CMOVNS16rr:
1403 case X86::CMOVNS32rr:
1404 case X86::CMOVNS64rr:
1405 case X86::CMOVP16rr:
1406 case X86::CMOVP32rr:
1407 case X86::CMOVP64rr:
1408 case X86::CMOVNP16rr:
1409 case X86::CMOVNP32rr:
1410 case X86::CMOVNP64rr:
1411 case X86::CMOVO16rr:
1412 case X86::CMOVO32rr:
1413 case X86::CMOVO64rr:
1414 case X86::CMOVNO16rr:
1415 case X86::CMOVNO32rr:
1416 case X86::CMOVNO64rr: {
1418 switch (MI->getOpcode()) {
1420 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1421 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1422 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1423 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1424 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1425 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1426 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1427 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1428 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1429 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1430 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1431 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1432 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1433 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1434 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1435 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1436 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1437 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1438 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1439 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1440 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1441 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1442 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1443 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1444 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1445 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1446 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1447 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1448 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1449 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1450 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1451 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1452 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1453 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1454 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1455 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1456 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1457 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1458 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1459 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1460 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1461 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1462 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1463 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1464 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1465 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1466 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1467 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1470 MachineFunction &MF = *MI->getParent()->getParent();
1471 MI = MF.CloneMachineInstr(MI);
1474 MI->setDesc(get(Opc));
1475 // Fallthrough intended.
1478 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1482 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1484 default: return X86::COND_INVALID;
1485 case X86::JE: return X86::COND_E;
1486 case X86::JNE: return X86::COND_NE;
1487 case X86::JL: return X86::COND_L;
1488 case X86::JLE: return X86::COND_LE;
1489 case X86::JG: return X86::COND_G;
1490 case X86::JGE: return X86::COND_GE;
1491 case X86::JB: return X86::COND_B;
1492 case X86::JBE: return X86::COND_BE;
1493 case X86::JA: return X86::COND_A;
1494 case X86::JAE: return X86::COND_AE;
1495 case X86::JS: return X86::COND_S;
1496 case X86::JNS: return X86::COND_NS;
1497 case X86::JP: return X86::COND_P;
1498 case X86::JNP: return X86::COND_NP;
1499 case X86::JO: return X86::COND_O;
1500 case X86::JNO: return X86::COND_NO;
1504 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1506 default: llvm_unreachable("Illegal condition code!");
1507 case X86::COND_E: return X86::JE;
1508 case X86::COND_NE: return X86::JNE;
1509 case X86::COND_L: return X86::JL;
1510 case X86::COND_LE: return X86::JLE;
1511 case X86::COND_G: return X86::JG;
1512 case X86::COND_GE: return X86::JGE;
1513 case X86::COND_B: return X86::JB;
1514 case X86::COND_BE: return X86::JBE;
1515 case X86::COND_A: return X86::JA;
1516 case X86::COND_AE: return X86::JAE;
1517 case X86::COND_S: return X86::JS;
1518 case X86::COND_NS: return X86::JNS;
1519 case X86::COND_P: return X86::JP;
1520 case X86::COND_NP: return X86::JNP;
1521 case X86::COND_O: return X86::JO;
1522 case X86::COND_NO: return X86::JNO;
1526 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1527 /// e.g. turning COND_E to COND_NE.
1528 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1530 default: llvm_unreachable("Illegal condition code!");
1531 case X86::COND_E: return X86::COND_NE;
1532 case X86::COND_NE: return X86::COND_E;
1533 case X86::COND_L: return X86::COND_GE;
1534 case X86::COND_LE: return X86::COND_G;
1535 case X86::COND_G: return X86::COND_LE;
1536 case X86::COND_GE: return X86::COND_L;
1537 case X86::COND_B: return X86::COND_AE;
1538 case X86::COND_BE: return X86::COND_A;
1539 case X86::COND_A: return X86::COND_BE;
1540 case X86::COND_AE: return X86::COND_B;
1541 case X86::COND_S: return X86::COND_NS;
1542 case X86::COND_NS: return X86::COND_S;
1543 case X86::COND_P: return X86::COND_NP;
1544 case X86::COND_NP: return X86::COND_P;
1545 case X86::COND_O: return X86::COND_NO;
1546 case X86::COND_NO: return X86::COND_O;
1550 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1551 const TargetInstrDesc &TID = MI->getDesc();
1552 if (!TID.isTerminator()) return false;
1554 // Conditional branch is a special case.
1555 if (TID.isBranch() && !TID.isBarrier())
1557 if (!TID.isPredicable())
1559 return !isPredicated(MI);
1562 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1563 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1564 const X86InstrInfo &TII) {
1565 if (MI->getOpcode() == X86::FP_REG_KILL)
1567 return TII.isUnpredicatedTerminator(MI);
1570 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1571 MachineBasicBlock *&TBB,
1572 MachineBasicBlock *&FBB,
1573 SmallVectorImpl<MachineOperand> &Cond,
1574 bool AllowModify) const {
1575 // Start from the bottom of the block and work up, examining the
1576 // terminator instructions.
1577 MachineBasicBlock::iterator I = MBB.end();
1578 while (I != MBB.begin()) {
1580 // Working from the bottom, when we see a non-terminator
1581 // instruction, we're done.
1582 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1584 // A terminator that isn't a branch can't easily be handled
1585 // by this analysis.
1586 if (!I->getDesc().isBranch())
1588 // Handle unconditional branches.
1589 if (I->getOpcode() == X86::JMP) {
1591 TBB = I->getOperand(0).getMBB();
1595 // If the block has any instructions after a JMP, delete them.
1596 while (llvm::next(I) != MBB.end())
1597 llvm::next(I)->eraseFromParent();
1600 // Delete the JMP if it's equivalent to a fall-through.
1601 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1603 I->eraseFromParent();
1607 // TBB is used to indicate the unconditinal destination.
1608 TBB = I->getOperand(0).getMBB();
1611 // Handle conditional branches.
1612 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1613 if (BranchCode == X86::COND_INVALID)
1614 return true; // Can't handle indirect branch.
1615 // Working from the bottom, handle the first conditional branch.
1618 TBB = I->getOperand(0).getMBB();
1619 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1622 // Handle subsequent conditional branches. Only handle the case
1623 // where all conditional branches branch to the same destination
1624 // and their condition opcodes fit one of the special
1625 // multi-branch idioms.
1626 assert(Cond.size() == 1);
1628 // Only handle the case where all conditional branches branch to
1629 // the same destination.
1630 if (TBB != I->getOperand(0).getMBB())
1632 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1633 // If the conditions are the same, we can leave them alone.
1634 if (OldBranchCode == BranchCode)
1636 // If they differ, see if they fit one of the known patterns.
1637 // Theoretically we could handle more patterns here, but
1638 // we shouldn't expect to see them if instruction selection
1639 // has done a reasonable job.
1640 if ((OldBranchCode == X86::COND_NP &&
1641 BranchCode == X86::COND_E) ||
1642 (OldBranchCode == X86::COND_E &&
1643 BranchCode == X86::COND_NP))
1644 BranchCode = X86::COND_NP_OR_E;
1645 else if ((OldBranchCode == X86::COND_P &&
1646 BranchCode == X86::COND_NE) ||
1647 (OldBranchCode == X86::COND_NE &&
1648 BranchCode == X86::COND_P))
1649 BranchCode = X86::COND_NE_OR_P;
1652 // Update the MachineOperand.
1653 Cond[0].setImm(BranchCode);
1659 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1660 MachineBasicBlock::iterator I = MBB.end();
1663 while (I != MBB.begin()) {
1665 if (I->getOpcode() != X86::JMP &&
1666 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1668 // Remove the branch.
1669 I->eraseFromParent();
1678 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1679 MachineBasicBlock *FBB,
1680 const SmallVectorImpl<MachineOperand> &Cond) const {
1681 // FIXME this should probably have a DebugLoc operand
1682 DebugLoc dl = DebugLoc::getUnknownLoc();
1683 // Shouldn't be a fall through.
1684 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1685 assert((Cond.size() == 1 || Cond.size() == 0) &&
1686 "X86 branch conditions have one component!");
1689 // Unconditional branch?
1690 assert(!FBB && "Unconditional branch with multiple successors!");
1691 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1695 // Conditional branch.
1697 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1699 case X86::COND_NP_OR_E:
1700 // Synthesize NP_OR_E with two branches.
1701 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1703 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1706 case X86::COND_NE_OR_P:
1707 // Synthesize NE_OR_P with two branches.
1708 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1710 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1714 unsigned Opc = GetCondBranchFromCond(CC);
1715 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1720 // Two-way Conditional branch. Insert the second branch.
1721 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1727 /// isHReg - Test if the given register is a physical h register.
1728 static bool isHReg(unsigned Reg) {
1729 return X86::GR8_ABCD_HRegClass.contains(Reg);
1732 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1733 MachineBasicBlock::iterator MI,
1734 unsigned DestReg, unsigned SrcReg,
1735 const TargetRegisterClass *DestRC,
1736 const TargetRegisterClass *SrcRC) const {
1737 DebugLoc DL = DebugLoc::getUnknownLoc();
1738 if (MI != MBB.end()) DL = MI->getDebugLoc();
1740 // Determine if DstRC and SrcRC have a common superclass in common.
1741 const TargetRegisterClass *CommonRC = DestRC;
1742 if (DestRC == SrcRC)
1743 /* Source and destination have the same register class. */;
1744 else if (CommonRC->hasSuperClass(SrcRC))
1746 else if (!DestRC->hasSubClass(SrcRC)) {
1747 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1748 // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1749 // GR32_NOSP, copy as GR32.
1750 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1751 DestRC->hasSuperClass(&X86::GR64RegClass))
1752 CommonRC = &X86::GR64RegClass;
1753 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1754 DestRC->hasSuperClass(&X86::GR32RegClass))
1755 CommonRC = &X86::GR32RegClass;
1762 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1764 } else if (CommonRC == &X86::GR32RegClass ||
1765 CommonRC == &X86::GR32_NOSPRegClass) {
1767 } else if (CommonRC == &X86::GR16RegClass) {
1769 } else if (CommonRC == &X86::GR8RegClass) {
1770 // Copying to or from a physical H register on x86-64 requires a NOREX
1771 // move. Otherwise use a normal move.
1772 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1773 TM.getSubtarget<X86Subtarget>().is64Bit())
1774 Opc = X86::MOV8rr_NOREX;
1777 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1779 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1781 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1783 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1785 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1786 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1787 Opc = X86::MOV8rr_NOREX;
1790 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1791 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1793 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1795 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1797 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1799 } else if (CommonRC == &X86::RFP32RegClass) {
1800 Opc = X86::MOV_Fp3232;
1801 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1802 Opc = X86::MOV_Fp6464;
1803 } else if (CommonRC == &X86::RFP80RegClass) {
1804 Opc = X86::MOV_Fp8080;
1805 } else if (CommonRC == &X86::FR32RegClass) {
1806 Opc = X86::FsMOVAPSrr;
1807 } else if (CommonRC == &X86::FR64RegClass) {
1808 Opc = X86::FsMOVAPDrr;
1809 } else if (CommonRC == &X86::VR128RegClass) {
1810 Opc = X86::MOVAPSrr;
1811 } else if (CommonRC == &X86::VR64RegClass) {
1812 Opc = X86::MMX_MOVQ64rr;
1816 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1820 // Moving EFLAGS to / from another register requires a push and a pop.
1821 if (SrcRC == &X86::CCRRegClass) {
1822 if (SrcReg != X86::EFLAGS)
1824 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1825 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1826 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1828 } else if (DestRC == &X86::GR32RegClass ||
1829 DestRC == &X86::GR32_NOSPRegClass) {
1830 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1831 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1834 } else if (DestRC == &X86::CCRRegClass) {
1835 if (DestReg != X86::EFLAGS)
1837 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1838 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1839 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1841 } else if (SrcRC == &X86::GR32RegClass ||
1842 DestRC == &X86::GR32_NOSPRegClass) {
1843 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1844 BuildMI(MBB, MI, DL, get(X86::POPFD));
1849 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1850 if (SrcRC == &X86::RSTRegClass) {
1851 // Copying from ST(0)/ST(1).
1852 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1853 // Can only copy from ST(0)/ST(1) right now
1855 bool isST0 = SrcReg == X86::ST0;
1857 if (DestRC == &X86::RFP32RegClass)
1858 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1859 else if (DestRC == &X86::RFP64RegClass)
1860 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1862 if (DestRC != &X86::RFP80RegClass)
1864 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1866 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1870 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1871 if (DestRC == &X86::RSTRegClass) {
1872 // Copying to ST(0) / ST(1).
1873 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1874 // Can only copy to TOS right now
1876 bool isST0 = DestReg == X86::ST0;
1878 if (SrcRC == &X86::RFP32RegClass)
1879 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1880 else if (SrcRC == &X86::RFP64RegClass)
1881 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1883 if (SrcRC != &X86::RFP80RegClass)
1885 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1887 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1891 // Not yet supported!
1895 static unsigned getStoreRegOpcode(unsigned SrcReg,
1896 const TargetRegisterClass *RC,
1897 bool isStackAligned,
1898 TargetMachine &TM) {
1900 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1902 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1904 } else if (RC == &X86::GR16RegClass) {
1906 } else if (RC == &X86::GR8RegClass) {
1907 // Copying to or from a physical H register on x86-64 requires a NOREX
1908 // move. Otherwise use a normal move.
1909 if (isHReg(SrcReg) &&
1910 TM.getSubtarget<X86Subtarget>().is64Bit())
1911 Opc = X86::MOV8mr_NOREX;
1914 } else if (RC == &X86::GR64_ABCDRegClass) {
1916 } else if (RC == &X86::GR32_ABCDRegClass) {
1918 } else if (RC == &X86::GR16_ABCDRegClass) {
1920 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1922 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1923 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1924 Opc = X86::MOV8mr_NOREX;
1927 } else if (RC == &X86::GR64_NOREXRegClass ||
1928 RC == &X86::GR64_NOREX_NOSPRegClass) {
1930 } else if (RC == &X86::GR32_NOREXRegClass) {
1932 } else if (RC == &X86::GR16_NOREXRegClass) {
1934 } else if (RC == &X86::GR8_NOREXRegClass) {
1936 } else if (RC == &X86::RFP80RegClass) {
1937 Opc = X86::ST_FpP80m; // pops
1938 } else if (RC == &X86::RFP64RegClass) {
1939 Opc = X86::ST_Fp64m;
1940 } else if (RC == &X86::RFP32RegClass) {
1941 Opc = X86::ST_Fp32m;
1942 } else if (RC == &X86::FR32RegClass) {
1944 } else if (RC == &X86::FR64RegClass) {
1946 } else if (RC == &X86::VR128RegClass) {
1947 // If stack is realigned we can use aligned stores.
1948 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1949 } else if (RC == &X86::VR64RegClass) {
1950 Opc = X86::MMX_MOVQ64mr;
1952 llvm_unreachable("Unknown regclass");
1958 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1959 MachineBasicBlock::iterator MI,
1960 unsigned SrcReg, bool isKill, int FrameIdx,
1961 const TargetRegisterClass *RC) const {
1962 const MachineFunction &MF = *MBB.getParent();
1963 bool isAligned = (RI.getStackAlignment() >= 16) ||
1964 RI.needsStackRealignment(MF);
1965 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1966 DebugLoc DL = DebugLoc::getUnknownLoc();
1967 if (MI != MBB.end()) DL = MI->getDebugLoc();
1968 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1969 .addReg(SrcReg, getKillRegState(isKill));
1972 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1974 SmallVectorImpl<MachineOperand> &Addr,
1975 const TargetRegisterClass *RC,
1976 MachineInstr::mmo_iterator MMOBegin,
1977 MachineInstr::mmo_iterator MMOEnd,
1978 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1979 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
1980 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1981 DebugLoc DL = DebugLoc::getUnknownLoc();
1982 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1983 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1984 MIB.addOperand(Addr[i]);
1985 MIB.addReg(SrcReg, getKillRegState(isKill));
1986 (*MIB).setMemRefs(MMOBegin, MMOEnd);
1987 NewMIs.push_back(MIB);
1990 static unsigned getLoadRegOpcode(unsigned DestReg,
1991 const TargetRegisterClass *RC,
1992 bool isStackAligned,
1993 const TargetMachine &TM) {
1995 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1997 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1999 } else if (RC == &X86::GR16RegClass) {
2001 } else if (RC == &X86::GR8RegClass) {
2002 // Copying to or from a physical H register on x86-64 requires a NOREX
2003 // move. Otherwise use a normal move.
2004 if (isHReg(DestReg) &&
2005 TM.getSubtarget<X86Subtarget>().is64Bit())
2006 Opc = X86::MOV8rm_NOREX;
2009 } else if (RC == &X86::GR64_ABCDRegClass) {
2011 } else if (RC == &X86::GR32_ABCDRegClass) {
2013 } else if (RC == &X86::GR16_ABCDRegClass) {
2015 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2017 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2018 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2019 Opc = X86::MOV8rm_NOREX;
2022 } else if (RC == &X86::GR64_NOREXRegClass ||
2023 RC == &X86::GR64_NOREX_NOSPRegClass) {
2025 } else if (RC == &X86::GR32_NOREXRegClass) {
2027 } else if (RC == &X86::GR16_NOREXRegClass) {
2029 } else if (RC == &X86::GR8_NOREXRegClass) {
2031 } else if (RC == &X86::RFP80RegClass) {
2032 Opc = X86::LD_Fp80m;
2033 } else if (RC == &X86::RFP64RegClass) {
2034 Opc = X86::LD_Fp64m;
2035 } else if (RC == &X86::RFP32RegClass) {
2036 Opc = X86::LD_Fp32m;
2037 } else if (RC == &X86::FR32RegClass) {
2039 } else if (RC == &X86::FR64RegClass) {
2041 } else if (RC == &X86::VR128RegClass) {
2042 // If stack is realigned we can use aligned loads.
2043 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2044 } else if (RC == &X86::VR64RegClass) {
2045 Opc = X86::MMX_MOVQ64rm;
2047 llvm_unreachable("Unknown regclass");
2053 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2054 MachineBasicBlock::iterator MI,
2055 unsigned DestReg, int FrameIdx,
2056 const TargetRegisterClass *RC) const{
2057 const MachineFunction &MF = *MBB.getParent();
2058 bool isAligned = (RI.getStackAlignment() >= 16) ||
2059 RI.needsStackRealignment(MF);
2060 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2061 DebugLoc DL = DebugLoc::getUnknownLoc();
2062 if (MI != MBB.end()) DL = MI->getDebugLoc();
2063 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2066 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2067 SmallVectorImpl<MachineOperand> &Addr,
2068 const TargetRegisterClass *RC,
2069 MachineInstr::mmo_iterator MMOBegin,
2070 MachineInstr::mmo_iterator MMOEnd,
2071 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2072 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2073 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2074 DebugLoc DL = DebugLoc::getUnknownLoc();
2075 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2076 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2077 MIB.addOperand(Addr[i]);
2078 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2079 NewMIs.push_back(MIB);
2082 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2083 MachineBasicBlock::iterator MI,
2084 const std::vector<CalleeSavedInfo> &CSI) const {
2088 DebugLoc DL = DebugLoc::getUnknownLoc();
2089 if (MI != MBB.end()) DL = MI->getDebugLoc();
2091 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2092 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2093 unsigned SlotSize = is64Bit ? 8 : 4;
2095 MachineFunction &MF = *MBB.getParent();
2096 unsigned FPReg = RI.getFrameRegister(MF);
2097 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2098 unsigned CalleeFrameSize = 0;
2100 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2101 for (unsigned i = CSI.size(); i != 0; --i) {
2102 unsigned Reg = CSI[i-1].getReg();
2103 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2104 // Add the callee-saved register as live-in. It's killed at the spill.
2107 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2109 if (RegClass != &X86::VR128RegClass && !isWin64) {
2110 CalleeFrameSize += SlotSize;
2111 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2113 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2117 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2121 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2122 MachineBasicBlock::iterator MI,
2123 const std::vector<CalleeSavedInfo> &CSI) const {
2127 DebugLoc DL = DebugLoc::getUnknownLoc();
2128 if (MI != MBB.end()) DL = MI->getDebugLoc();
2130 MachineFunction &MF = *MBB.getParent();
2131 unsigned FPReg = RI.getFrameRegister(MF);
2132 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2133 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2134 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2135 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2136 unsigned Reg = CSI[i].getReg();
2138 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2140 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2141 if (RegClass != &X86::VR128RegClass && !isWin64) {
2142 BuildMI(MBB, MI, DL, get(Opc), Reg);
2144 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2150 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2151 const SmallVectorImpl<MachineOperand> &MOs,
2153 const TargetInstrInfo &TII) {
2154 // Create the base instruction with the memory operand as the first part.
2155 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2156 MI->getDebugLoc(), true);
2157 MachineInstrBuilder MIB(NewMI);
2158 unsigned NumAddrOps = MOs.size();
2159 for (unsigned i = 0; i != NumAddrOps; ++i)
2160 MIB.addOperand(MOs[i]);
2161 if (NumAddrOps < 4) // FrameIndex only
2164 // Loop over the rest of the ri operands, converting them over.
2165 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2166 for (unsigned i = 0; i != NumOps; ++i) {
2167 MachineOperand &MO = MI->getOperand(i+2);
2170 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2171 MachineOperand &MO = MI->getOperand(i);
2177 static MachineInstr *FuseInst(MachineFunction &MF,
2178 unsigned Opcode, unsigned OpNo,
2179 const SmallVectorImpl<MachineOperand> &MOs,
2180 MachineInstr *MI, const TargetInstrInfo &TII) {
2181 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2182 MI->getDebugLoc(), true);
2183 MachineInstrBuilder MIB(NewMI);
2185 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2186 MachineOperand &MO = MI->getOperand(i);
2188 assert(MO.isReg() && "Expected to fold into reg operand!");
2189 unsigned NumAddrOps = MOs.size();
2190 for (unsigned i = 0; i != NumAddrOps; ++i)
2191 MIB.addOperand(MOs[i]);
2192 if (NumAddrOps < 4) // FrameIndex only
2201 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2202 const SmallVectorImpl<MachineOperand> &MOs,
2204 MachineFunction &MF = *MI->getParent()->getParent();
2205 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2207 unsigned NumAddrOps = MOs.size();
2208 for (unsigned i = 0; i != NumAddrOps; ++i)
2209 MIB.addOperand(MOs[i]);
2210 if (NumAddrOps < 4) // FrameIndex only
2212 return MIB.addImm(0);
2216 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2217 MachineInstr *MI, unsigned i,
2218 const SmallVectorImpl<MachineOperand> &MOs,
2219 unsigned Size, unsigned Align) const {
2220 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2221 bool isTwoAddrFold = false;
2222 unsigned NumOps = MI->getDesc().getNumOperands();
2223 bool isTwoAddr = NumOps > 1 &&
2224 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2226 MachineInstr *NewMI = NULL;
2227 // Folding a memory location into the two-address part of a two-address
2228 // instruction is different than folding it other places. It requires
2229 // replacing the *two* registers with the memory location.
2230 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2231 MI->getOperand(0).isReg() &&
2232 MI->getOperand(1).isReg() &&
2233 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2234 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2235 isTwoAddrFold = true;
2236 } else if (i == 0) { // If operand 0
2237 if (MI->getOpcode() == X86::MOV16r0)
2238 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2239 else if (MI->getOpcode() == X86::MOV32r0)
2240 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2241 else if (MI->getOpcode() == X86::MOV8r0)
2242 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2246 OpcodeTablePtr = &RegOp2MemOpTable0;
2247 } else if (i == 1) {
2248 OpcodeTablePtr = &RegOp2MemOpTable1;
2249 } else if (i == 2) {
2250 OpcodeTablePtr = &RegOp2MemOpTable2;
2253 // If table selected...
2254 if (OpcodeTablePtr) {
2255 // Find the Opcode to fuse
2256 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2257 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2258 if (I != OpcodeTablePtr->end()) {
2259 unsigned Opcode = I->second.first;
2260 unsigned MinAlign = I->second.second;
2261 if (Align < MinAlign)
2263 bool NarrowToMOV32rm = false;
2265 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2266 if (Size < RCSize) {
2267 // Check if it's safe to fold the load. If the size of the object is
2268 // narrower than the load width, then it's not.
2269 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2271 // If this is a 64-bit load, but the spill slot is 32, then we can do
2272 // a 32-bit load which is implicitly zero-extended. This likely is due
2273 // to liveintervalanalysis remat'ing a load from stack slot.
2274 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2276 Opcode = X86::MOV32rm;
2277 NarrowToMOV32rm = true;
2282 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2284 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2286 if (NarrowToMOV32rm) {
2287 // If this is the special case where we use a MOV32rm to load a 32-bit
2288 // value and zero-extend the top bits. Change the destination register
2290 unsigned DstReg = NewMI->getOperand(0).getReg();
2291 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2292 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2293 4/*x86_subreg_32bit*/));
2295 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2302 if (PrintFailedFusing)
2303 errs() << "We failed to fuse operand " << i << " in " << *MI;
2308 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2310 const SmallVectorImpl<unsigned> &Ops,
2311 int FrameIndex) const {
2312 // Check switch flag
2313 if (NoFusing) return NULL;
2315 const MachineFrameInfo *MFI = MF.getFrameInfo();
2316 unsigned Size = MFI->getObjectSize(FrameIndex);
2317 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2318 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2319 unsigned NewOpc = 0;
2320 unsigned RCSize = 0;
2321 switch (MI->getOpcode()) {
2322 default: return NULL;
2323 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2324 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2325 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2326 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2328 // Check if it's safe to fold the load. If the size of the object is
2329 // narrower than the load width, then it's not.
2332 // Change to CMPXXri r, 0 first.
2333 MI->setDesc(get(NewOpc));
2334 MI->getOperand(1).ChangeToImmediate(0);
2335 } else if (Ops.size() != 1)
2338 SmallVector<MachineOperand,4> MOs;
2339 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2340 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2343 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2345 const SmallVectorImpl<unsigned> &Ops,
2346 MachineInstr *LoadMI) const {
2347 // Check switch flag
2348 if (NoFusing) return NULL;
2350 // Determine the alignment of the load.
2351 unsigned Alignment = 0;
2352 if (LoadMI->hasOneMemOperand())
2353 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2355 switch (LoadMI->getOpcode()) {
2357 case X86::V_SETALLONES:
2367 llvm_unreachable("Don't know how to fold this instruction!");
2369 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2370 unsigned NewOpc = 0;
2371 switch (MI->getOpcode()) {
2372 default: return NULL;
2373 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2374 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2375 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2376 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2378 // Change to CMPXXri r, 0 first.
2379 MI->setDesc(get(NewOpc));
2380 MI->getOperand(1).ChangeToImmediate(0);
2381 } else if (Ops.size() != 1)
2384 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2385 switch (LoadMI->getOpcode()) {
2387 case X86::V_SETALLONES:
2389 case X86::FsFLD0SS: {
2390 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2391 // Create a constant-pool entry and operands to load from it.
2393 // x86-32 PIC requires a PIC base register for constant pools.
2394 unsigned PICBase = 0;
2395 if (TM.getRelocationModel() == Reloc::PIC_) {
2396 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2399 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2400 // This doesn't work for several reasons.
2401 // 1. GlobalBaseReg may have been spilled.
2402 // 2. It may not be live at MI.
2406 // Create a constant-pool entry.
2407 MachineConstantPool &MCP = *MF.getConstantPool();
2409 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2410 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2411 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2412 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2414 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2415 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2416 Constant::getAllOnesValue(Ty) :
2417 Constant::getNullValue(Ty);
2418 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2420 // Create operands to load from the constant pool entry.
2421 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2422 MOs.push_back(MachineOperand::CreateImm(1));
2423 MOs.push_back(MachineOperand::CreateReg(0, false));
2424 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2425 MOs.push_back(MachineOperand::CreateReg(0, false));
2429 // Folding a normal load. Just copy the load's address operands.
2430 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2431 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2432 MOs.push_back(LoadMI->getOperand(i));
2436 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2440 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2441 const SmallVectorImpl<unsigned> &Ops) const {
2442 // Check switch flag
2443 if (NoFusing) return 0;
2445 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2446 switch (MI->getOpcode()) {
2447 default: return false;
2456 if (Ops.size() != 1)
2459 unsigned OpNum = Ops[0];
2460 unsigned Opc = MI->getOpcode();
2461 unsigned NumOps = MI->getDesc().getNumOperands();
2462 bool isTwoAddr = NumOps > 1 &&
2463 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2465 // Folding a memory location into the two-address part of a two-address
2466 // instruction is different than folding it other places. It requires
2467 // replacing the *two* registers with the memory location.
2468 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2469 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2470 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2471 } else if (OpNum == 0) { // If operand 0
2479 OpcodeTablePtr = &RegOp2MemOpTable0;
2480 } else if (OpNum == 1) {
2481 OpcodeTablePtr = &RegOp2MemOpTable1;
2482 } else if (OpNum == 2) {
2483 OpcodeTablePtr = &RegOp2MemOpTable2;
2486 if (OpcodeTablePtr) {
2487 // Find the Opcode to fuse
2488 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2489 OpcodeTablePtr->find((unsigned*)Opc);
2490 if (I != OpcodeTablePtr->end())
2496 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2497 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2498 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2499 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2500 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2501 if (I == MemOp2RegOpTable.end())
2503 DebugLoc dl = MI->getDebugLoc();
2504 unsigned Opc = I->second.first;
2505 unsigned Index = I->second.second & 0xf;
2506 bool FoldedLoad = I->second.second & (1 << 4);
2507 bool FoldedStore = I->second.second & (1 << 5);
2508 if (UnfoldLoad && !FoldedLoad)
2510 UnfoldLoad &= FoldedLoad;
2511 if (UnfoldStore && !FoldedStore)
2513 UnfoldStore &= FoldedStore;
2515 const TargetInstrDesc &TID = get(Opc);
2516 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2517 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2518 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2519 SmallVector<MachineOperand,2> BeforeOps;
2520 SmallVector<MachineOperand,2> AfterOps;
2521 SmallVector<MachineOperand,4> ImpOps;
2522 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2523 MachineOperand &Op = MI->getOperand(i);
2524 if (i >= Index && i < Index + X86AddrNumOperands)
2525 AddrOps.push_back(Op);
2526 else if (Op.isReg() && Op.isImplicit())
2527 ImpOps.push_back(Op);
2529 BeforeOps.push_back(Op);
2531 AfterOps.push_back(Op);
2534 // Emit the load instruction.
2536 std::pair<MachineInstr::mmo_iterator,
2537 MachineInstr::mmo_iterator> MMOs =
2538 MF.extractLoadMemRefs(MI->memoperands_begin(),
2539 MI->memoperands_end());
2540 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2542 // Address operands cannot be marked isKill.
2543 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2544 MachineOperand &MO = NewMIs[0]->getOperand(i);
2546 MO.setIsKill(false);
2551 // Emit the data processing instruction.
2552 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2553 MachineInstrBuilder MIB(DataMI);
2556 MIB.addReg(Reg, RegState::Define);
2557 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2558 MIB.addOperand(BeforeOps[i]);
2561 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2562 MIB.addOperand(AfterOps[i]);
2563 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2564 MachineOperand &MO = ImpOps[i];
2565 MIB.addReg(MO.getReg(),
2566 getDefRegState(MO.isDef()) |
2567 RegState::Implicit |
2568 getKillRegState(MO.isKill()) |
2569 getDeadRegState(MO.isDead()) |
2570 getUndefRegState(MO.isUndef()));
2572 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2573 unsigned NewOpc = 0;
2574 switch (DataMI->getOpcode()) {
2576 case X86::CMP64ri32:
2580 MachineOperand &MO0 = DataMI->getOperand(0);
2581 MachineOperand &MO1 = DataMI->getOperand(1);
2582 if (MO1.getImm() == 0) {
2583 switch (DataMI->getOpcode()) {
2585 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2586 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2587 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2588 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2590 DataMI->setDesc(get(NewOpc));
2591 MO1.ChangeToRegister(MO0.getReg(), false);
2595 NewMIs.push_back(DataMI);
2597 // Emit the store instruction.
2599 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2600 std::pair<MachineInstr::mmo_iterator,
2601 MachineInstr::mmo_iterator> MMOs =
2602 MF.extractStoreMemRefs(MI->memoperands_begin(),
2603 MI->memoperands_end());
2604 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2611 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2612 SmallVectorImpl<SDNode*> &NewNodes) const {
2613 if (!N->isMachineOpcode())
2616 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2617 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2618 if (I == MemOp2RegOpTable.end())
2620 unsigned Opc = I->second.first;
2621 unsigned Index = I->second.second & 0xf;
2622 bool FoldedLoad = I->second.second & (1 << 4);
2623 bool FoldedStore = I->second.second & (1 << 5);
2624 const TargetInstrDesc &TID = get(Opc);
2625 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2626 unsigned NumDefs = TID.NumDefs;
2627 std::vector<SDValue> AddrOps;
2628 std::vector<SDValue> BeforeOps;
2629 std::vector<SDValue> AfterOps;
2630 DebugLoc dl = N->getDebugLoc();
2631 unsigned NumOps = N->getNumOperands();
2632 for (unsigned i = 0; i != NumOps-1; ++i) {
2633 SDValue Op = N->getOperand(i);
2634 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2635 AddrOps.push_back(Op);
2636 else if (i < Index-NumDefs)
2637 BeforeOps.push_back(Op);
2638 else if (i > Index-NumDefs)
2639 AfterOps.push_back(Op);
2641 SDValue Chain = N->getOperand(NumOps-1);
2642 AddrOps.push_back(Chain);
2644 // Emit the load instruction.
2646 MachineFunction &MF = DAG.getMachineFunction();
2648 EVT VT = *RC->vt_begin();
2649 std::pair<MachineInstr::mmo_iterator,
2650 MachineInstr::mmo_iterator> MMOs =
2651 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2652 cast<MachineSDNode>(N)->memoperands_end());
2653 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2654 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2655 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2656 NewNodes.push_back(Load);
2658 // Preserve memory reference information.
2659 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2662 // Emit the data processing instruction.
2663 std::vector<EVT> VTs;
2664 const TargetRegisterClass *DstRC = 0;
2665 if (TID.getNumDefs() > 0) {
2666 DstRC = TID.OpInfo[0].getRegClass(&RI);
2667 VTs.push_back(*DstRC->vt_begin());
2669 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2670 EVT VT = N->getValueType(i);
2671 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2675 BeforeOps.push_back(SDValue(Load, 0));
2676 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2677 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2679 NewNodes.push_back(NewNode);
2681 // Emit the store instruction.
2684 AddrOps.push_back(SDValue(NewNode, 0));
2685 AddrOps.push_back(Chain);
2686 std::pair<MachineInstr::mmo_iterator,
2687 MachineInstr::mmo_iterator> MMOs =
2688 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2689 cast<MachineSDNode>(N)->memoperands_end());
2690 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2691 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2694 &AddrOps[0], AddrOps.size());
2695 NewNodes.push_back(Store);
2697 // Preserve memory reference information.
2698 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2704 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2705 bool UnfoldLoad, bool UnfoldStore,
2706 unsigned *LoadRegIndex) const {
2707 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2708 MemOp2RegOpTable.find((unsigned*)Opc);
2709 if (I == MemOp2RegOpTable.end())
2711 bool FoldedLoad = I->second.second & (1 << 4);
2712 bool FoldedStore = I->second.second & (1 << 5);
2713 if (UnfoldLoad && !FoldedLoad)
2715 if (UnfoldStore && !FoldedStore)
2718 *LoadRegIndex = I->second.second & 0xf;
2719 return I->second.first;
2723 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2724 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2725 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2726 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2728 Cond[0].setImm(GetOppositeBranchCondition(CC));
2733 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2734 // FIXME: Return false for x87 stack register classes for now. We can't
2735 // allow any loads of these registers before FpGet_ST0_80.
2736 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2737 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2740 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2741 switch (Desc->TSFlags & X86II::ImmMask) {
2742 case X86II::Imm8: return 1;
2743 case X86II::Imm16: return 2;
2744 case X86II::Imm32: return 4;
2745 case X86II::Imm64: return 8;
2746 default: llvm_unreachable("Immediate size not set!");
2751 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2752 /// e.g. r8, xmm8, etc.
2753 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2754 if (!MO.isReg()) return false;
2755 switch (MO.getReg()) {
2757 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2758 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2759 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2760 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2761 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2762 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2763 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2764 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2765 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2766 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2773 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2774 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2775 /// size, and 3) use of X86-64 extended registers.
2776 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2778 const TargetInstrDesc &Desc = MI.getDesc();
2780 // Pseudo instructions do not need REX prefix byte.
2781 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2783 if (Desc.TSFlags & X86II::REX_W)
2786 unsigned NumOps = Desc.getNumOperands();
2788 bool isTwoAddr = NumOps > 1 &&
2789 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2791 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2792 unsigned i = isTwoAddr ? 1 : 0;
2793 for (unsigned e = NumOps; i != e; ++i) {
2794 const MachineOperand& MO = MI.getOperand(i);
2796 unsigned Reg = MO.getReg();
2797 if (isX86_64NonExtLowByteReg(Reg))
2802 switch (Desc.TSFlags & X86II::FormMask) {
2803 case X86II::MRMInitReg:
2804 if (isX86_64ExtendedReg(MI.getOperand(0)))
2805 REX |= (1 << 0) | (1 << 2);
2807 case X86II::MRMSrcReg: {
2808 if (isX86_64ExtendedReg(MI.getOperand(0)))
2810 i = isTwoAddr ? 2 : 1;
2811 for (unsigned e = NumOps; i != e; ++i) {
2812 const MachineOperand& MO = MI.getOperand(i);
2813 if (isX86_64ExtendedReg(MO))
2818 case X86II::MRMSrcMem: {
2819 if (isX86_64ExtendedReg(MI.getOperand(0)))
2822 i = isTwoAddr ? 2 : 1;
2823 for (; i != NumOps; ++i) {
2824 const MachineOperand& MO = MI.getOperand(i);
2826 if (isX86_64ExtendedReg(MO))
2833 case X86II::MRM0m: case X86II::MRM1m:
2834 case X86II::MRM2m: case X86II::MRM3m:
2835 case X86II::MRM4m: case X86II::MRM5m:
2836 case X86II::MRM6m: case X86II::MRM7m:
2837 case X86II::MRMDestMem: {
2838 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2839 i = isTwoAddr ? 1 : 0;
2840 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2843 for (; i != e; ++i) {
2844 const MachineOperand& MO = MI.getOperand(i);
2846 if (isX86_64ExtendedReg(MO))
2854 if (isX86_64ExtendedReg(MI.getOperand(0)))
2856 i = isTwoAddr ? 2 : 1;
2857 for (unsigned e = NumOps; i != e; ++i) {
2858 const MachineOperand& MO = MI.getOperand(i);
2859 if (isX86_64ExtendedReg(MO))
2869 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2870 /// relative block address instruction
2872 static unsigned sizePCRelativeBlockAddress() {
2876 /// sizeGlobalAddress - Give the size of the emission of this global address
2878 static unsigned sizeGlobalAddress(bool dword) {
2879 return dword ? 8 : 4;
2882 /// sizeConstPoolAddress - Give the size of the emission of this constant
2885 static unsigned sizeConstPoolAddress(bool dword) {
2886 return dword ? 8 : 4;
2889 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2892 static unsigned sizeExternalSymbolAddress(bool dword) {
2893 return dword ? 8 : 4;
2896 /// sizeJumpTableAddress - Give the size of the emission of this jump
2899 static unsigned sizeJumpTableAddress(bool dword) {
2900 return dword ? 8 : 4;
2903 static unsigned sizeConstant(unsigned Size) {
2907 static unsigned sizeRegModRMByte(){
2911 static unsigned sizeSIBByte(){
2915 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2916 unsigned FinalSize = 0;
2917 // If this is a simple integer displacement that doesn't require a relocation.
2919 FinalSize += sizeConstant(4);
2923 // Otherwise, this is something that requires a relocation.
2924 if (RelocOp->isGlobal()) {
2925 FinalSize += sizeGlobalAddress(false);
2926 } else if (RelocOp->isCPI()) {
2927 FinalSize += sizeConstPoolAddress(false);
2928 } else if (RelocOp->isJTI()) {
2929 FinalSize += sizeJumpTableAddress(false);
2931 llvm_unreachable("Unknown value to relocate!");
2936 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2937 bool IsPIC, bool Is64BitMode) {
2938 const MachineOperand &Op3 = MI.getOperand(Op+3);
2940 const MachineOperand *DispForReloc = 0;
2941 unsigned FinalSize = 0;
2943 // Figure out what sort of displacement we have to handle here.
2944 if (Op3.isGlobal()) {
2945 DispForReloc = &Op3;
2946 } else if (Op3.isCPI()) {
2947 if (Is64BitMode || IsPIC) {
2948 DispForReloc = &Op3;
2952 } else if (Op3.isJTI()) {
2953 if (Is64BitMode || IsPIC) {
2954 DispForReloc = &Op3;
2962 const MachineOperand &Base = MI.getOperand(Op);
2963 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2965 unsigned BaseReg = Base.getReg();
2967 // Is a SIB byte needed?
2968 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2969 IndexReg.getReg() == 0 &&
2970 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2971 if (BaseReg == 0) { // Just a displacement?
2972 // Emit special case [disp32] encoding
2974 FinalSize += getDisplacementFieldSize(DispForReloc);
2976 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2977 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2978 // Emit simple indirect register encoding... [EAX] f.e.
2980 // Be pessimistic and assume it's a disp32, not a disp8
2982 // Emit the most general non-SIB encoding: [REG+disp32]
2984 FinalSize += getDisplacementFieldSize(DispForReloc);
2988 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2989 assert(IndexReg.getReg() != X86::ESP &&
2990 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2992 bool ForceDisp32 = false;
2993 if (BaseReg == 0 || DispForReloc) {
2994 // Emit the normal disp32 encoding.
3001 FinalSize += sizeSIBByte();
3003 // Do we need to output a displacement?
3004 if (DispVal != 0 || ForceDisp32) {
3005 FinalSize += getDisplacementFieldSize(DispForReloc);
3012 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3013 const TargetInstrDesc *Desc,
3014 bool IsPIC, bool Is64BitMode) {
3016 unsigned Opcode = Desc->Opcode;
3017 unsigned FinalSize = 0;
3019 // Emit the lock opcode prefix as needed.
3020 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3022 // Emit segment override opcode prefix as needed.
3023 switch (Desc->TSFlags & X86II::SegOvrMask) {
3028 default: llvm_unreachable("Invalid segment!");
3029 case 0: break; // No segment override!
3032 // Emit the repeat opcode prefix as needed.
3033 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3035 // Emit the operand size opcode prefix as needed.
3036 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3038 // Emit the address size opcode prefix as needed.
3039 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3041 bool Need0FPrefix = false;
3042 switch (Desc->TSFlags & X86II::Op0Mask) {
3043 case X86II::TB: // Two-byte opcode prefix
3044 case X86II::T8: // 0F 38
3045 case X86II::TA: // 0F 3A
3046 Need0FPrefix = true;
3048 case X86II::TF: // F2 0F 38
3050 Need0FPrefix = true;
3052 case X86II::REP: break; // already handled.
3053 case X86II::XS: // F3 0F
3055 Need0FPrefix = true;
3057 case X86II::XD: // F2 0F
3059 Need0FPrefix = true;
3061 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3062 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3064 break; // Two-byte opcode prefix
3065 default: llvm_unreachable("Invalid prefix!");
3066 case 0: break; // No prefix!
3071 unsigned REX = X86InstrInfo::determineREX(MI);
3076 // 0x0F escape code must be emitted just before the opcode.
3080 switch (Desc->TSFlags & X86II::Op0Mask) {
3081 case X86II::T8: // 0F 38
3084 case X86II::TA: // 0F 3A
3087 case X86II::TF: // F2 0F 38
3092 // If this is a two-address instruction, skip one of the register operands.
3093 unsigned NumOps = Desc->getNumOperands();
3095 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3097 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3098 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3101 switch (Desc->TSFlags & X86II::FormMask) {
3102 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3104 // Remember the current PC offset, this is the PIC relocation
3109 case TargetInstrInfo::INLINEASM: {
3110 const MachineFunction *MF = MI.getParent()->getParent();
3111 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3112 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3113 *MF->getTarget().getMCAsmInfo());
3116 case TargetInstrInfo::DBG_LABEL:
3117 case TargetInstrInfo::EH_LABEL:
3119 case TargetInstrInfo::IMPLICIT_DEF:
3120 case TargetInstrInfo::KILL:
3121 case X86::FP_REG_KILL:
3123 case X86::MOVPC32r: {
3124 // This emits the "call" portion of this pseudo instruction.
3126 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3135 if (CurOp != NumOps) {
3136 const MachineOperand &MO = MI.getOperand(CurOp++);
3138 FinalSize += sizePCRelativeBlockAddress();
3139 } else if (MO.isGlobal()) {
3140 FinalSize += sizeGlobalAddress(false);
3141 } else if (MO.isSymbol()) {
3142 FinalSize += sizeExternalSymbolAddress(false);
3143 } else if (MO.isImm()) {
3144 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3146 llvm_unreachable("Unknown RawFrm operand!");
3151 case X86II::AddRegFrm:
3155 if (CurOp != NumOps) {
3156 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3157 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3159 FinalSize += sizeConstant(Size);
3162 if (Opcode == X86::MOV64ri)
3164 if (MO1.isGlobal()) {
3165 FinalSize += sizeGlobalAddress(dword);
3166 } else if (MO1.isSymbol())
3167 FinalSize += sizeExternalSymbolAddress(dword);
3168 else if (MO1.isCPI())
3169 FinalSize += sizeConstPoolAddress(dword);
3170 else if (MO1.isJTI())
3171 FinalSize += sizeJumpTableAddress(dword);
3176 case X86II::MRMDestReg: {
3178 FinalSize += sizeRegModRMByte();
3180 if (CurOp != NumOps) {
3182 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3186 case X86II::MRMDestMem: {
3188 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3189 CurOp += X86AddrNumOperands + 1;
3190 if (CurOp != NumOps) {
3192 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3197 case X86II::MRMSrcReg:
3199 FinalSize += sizeRegModRMByte();
3201 if (CurOp != NumOps) {
3203 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3207 case X86II::MRMSrcMem: {
3209 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3210 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3211 AddrOperands = X86AddrNumOperands - 1; // No segment register
3213 AddrOperands = X86AddrNumOperands;
3216 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3217 CurOp += AddrOperands + 1;
3218 if (CurOp != NumOps) {
3220 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3225 case X86II::MRM0r: case X86II::MRM1r:
3226 case X86II::MRM2r: case X86II::MRM3r:
3227 case X86II::MRM4r: case X86II::MRM5r:
3228 case X86II::MRM6r: case X86II::MRM7r:
3230 if (Desc->getOpcode() == X86::LFENCE ||
3231 Desc->getOpcode() == X86::MFENCE) {
3232 // Special handling of lfence and mfence;
3233 FinalSize += sizeRegModRMByte();
3234 } else if (Desc->getOpcode() == X86::MONITOR ||
3235 Desc->getOpcode() == X86::MWAIT) {
3236 // Special handling of monitor and mwait.
3237 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3240 FinalSize += sizeRegModRMByte();
3243 if (CurOp != NumOps) {
3244 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3245 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3247 FinalSize += sizeConstant(Size);
3250 if (Opcode == X86::MOV64ri32)
3252 if (MO1.isGlobal()) {
3253 FinalSize += sizeGlobalAddress(dword);
3254 } else if (MO1.isSymbol())
3255 FinalSize += sizeExternalSymbolAddress(dword);
3256 else if (MO1.isCPI())
3257 FinalSize += sizeConstPoolAddress(dword);
3258 else if (MO1.isJTI())
3259 FinalSize += sizeJumpTableAddress(dword);
3264 case X86II::MRM0m: case X86II::MRM1m:
3265 case X86II::MRM2m: case X86II::MRM3m:
3266 case X86II::MRM4m: case X86II::MRM5m:
3267 case X86II::MRM6m: case X86II::MRM7m: {
3270 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3271 CurOp += X86AddrNumOperands;
3273 if (CurOp != NumOps) {
3274 const MachineOperand &MO = MI.getOperand(CurOp++);
3275 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3277 FinalSize += sizeConstant(Size);
3280 if (Opcode == X86::MOV64mi32)
3282 if (MO.isGlobal()) {
3283 FinalSize += sizeGlobalAddress(dword);
3284 } else if (MO.isSymbol())
3285 FinalSize += sizeExternalSymbolAddress(dword);
3286 else if (MO.isCPI())
3287 FinalSize += sizeConstPoolAddress(dword);
3288 else if (MO.isJTI())
3289 FinalSize += sizeJumpTableAddress(dword);
3295 case X86II::MRMInitReg:
3297 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3298 FinalSize += sizeRegModRMByte();
3303 if (!Desc->isVariadic() && CurOp != NumOps) {
3305 raw_string_ostream Msg(msg);
3306 Msg << "Cannot determine size: " << MI;
3307 llvm_report_error(Msg.str());
3315 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3316 const TargetInstrDesc &Desc = MI->getDesc();
3317 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3318 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3319 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3320 if (Desc.getOpcode() == X86::MOVPC32r)
3321 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3325 /// getGlobalBaseReg - Return a virtual register initialized with the
3326 /// the global base register value. Output instructions required to
3327 /// initialize the register in the function entry block, if necessary.
3329 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3330 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3331 "X86-64 PIC uses RIP relative addressing");
3333 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3334 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3335 if (GlobalBaseReg != 0)
3336 return GlobalBaseReg;
3338 // Insert the set of GlobalBaseReg into the first MBB of the function
3339 MachineBasicBlock &FirstMBB = MF->front();
3340 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3341 DebugLoc DL = DebugLoc::getUnknownLoc();
3342 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3343 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3344 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3346 const TargetInstrInfo *TII = TM.getInstrInfo();
3347 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3348 // only used in JIT code emission as displacement to pc.
3349 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3351 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3352 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3353 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3354 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3355 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3356 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3357 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3358 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3363 X86FI->setGlobalBaseReg(GlobalBaseReg);
3364 return GlobalBaseReg;