1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
24 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
29 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
31 unsigned& destReg) const {
32 MachineOpCode oc = MI.getOpcode();
33 if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
34 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
35 oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
36 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
37 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
38 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
39 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
40 oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
41 oc == X86::MOVPDI2DIrr) {
42 assert(MI.getNumOperands() == 2 &&
43 MI.getOperand(0).isRegister() &&
44 MI.getOperand(1).isRegister() &&
45 "invalid register-register move instruction");
46 sourceReg = MI.getOperand(1).getReg();
47 destReg = MI.getOperand(0).getReg();
53 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
54 int &FrameIndex) const {
55 switch (MI->getOpcode()) {
67 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
68 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
69 MI->getOperand(2).getImmedValue() == 1 &&
70 MI->getOperand(3).getReg() == 0 &&
71 MI->getOperand(4).getImmedValue() == 0) {
72 FrameIndex = MI->getOperand(1).getFrameIndex();
73 return MI->getOperand(0).getReg();
80 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
81 int &FrameIndex) const {
82 switch (MI->getOpcode()) {
94 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
95 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
96 MI->getOperand(1).getImmedValue() == 1 &&
97 MI->getOperand(2).getReg() == 0 &&
98 MI->getOperand(3).getImmedValue() == 0) {
99 FrameIndex = MI->getOperand(0).getFrameIndex();
100 return MI->getOperand(4).getReg();
108 /// convertToThreeAddress - This method must be implemented by targets that
109 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
110 /// may be able to convert a two-address instruction into a true
111 /// three-address instruction on demand. This allows the X86 target (for
112 /// example) to convert ADD and SHL instructions into LEA instructions if they
113 /// would require register copies due to two-addressness.
115 /// This method returns a null pointer if the transformation cannot be
116 /// performed, otherwise it returns the new instruction.
118 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
119 // All instructions input are two-addr instructions. Get the known operands.
120 unsigned Dest = MI->getOperand(0).getReg();
121 unsigned Src = MI->getOperand(1).getReg();
123 switch (MI->getOpcode()) {
125 case X86::SHUFPSrri: {
126 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
127 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
128 unsigned A = MI->getOperand(0).getReg();
129 unsigned B = MI->getOperand(1).getReg();
130 unsigned C = MI->getOperand(2).getReg();
131 unsigned M = MI->getOperand(3).getImmedValue();
132 if (!Subtarget->hasSSE2() || B != C) return 0;
133 return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
137 // FIXME: None of these instructions are promotable to LEAs without
138 // additional information. In particular, LEA doesn't set the flags that
139 // add and inc do. :(
142 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
143 // we have subtarget support, enable the 16-bit LEA generation here.
144 bool DisableLEA16 = true;
146 switch (MI->getOpcode()) {
148 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
149 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
151 if (DisableLEA16) return 0;
152 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
153 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
155 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
156 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
158 if (DisableLEA16) return 0;
159 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
160 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
162 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
163 return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
164 MI->getOperand(2).getReg());
166 if (DisableLEA16) return 0;
167 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
168 return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
169 MI->getOperand(2).getReg());
172 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
173 if (MI->getOperand(2).isImmediate())
174 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
175 MI->getOperand(2).getImmedValue());
179 if (DisableLEA16) return 0;
180 assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
181 if (MI->getOperand(2).isImmediate())
182 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
183 MI->getOperand(2).getImmedValue());
187 if (DisableLEA16) return 0;
189 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
190 "Unknown shl instruction!");
191 unsigned ShAmt = MI->getOperand(2).getImmedValue();
192 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
194 AM.Scale = 1 << ShAmt;
196 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
197 return addFullAddress(BuildMI(Opc, 5, Dest), AM);
205 /// commuteInstruction - We have a few instructions that must be hacked on to
208 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
209 switch (MI->getOpcode()) {
210 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
211 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
212 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
213 case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
216 switch (MI->getOpcode()) {
217 default: assert(0 && "Unreachable!");
218 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
219 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
220 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
221 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
223 unsigned Amt = MI->getOperand(3).getImmedValue();
224 unsigned A = MI->getOperand(0).getReg();
225 unsigned B = MI->getOperand(1).getReg();
226 unsigned C = MI->getOperand(2).getReg();
227 return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
230 return TargetInstrInfo::commuteInstruction(MI);
235 void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
236 MachineBasicBlock& TMBB) const {
237 BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
240 MachineBasicBlock::iterator
241 X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
242 unsigned Opcode = MI->getOpcode();
243 assert(isBranch(Opcode) && "MachineInstr must be a branch");
246 default: assert(0 && "Cannot reverse unconditional branches!");
247 case X86::JB: ROpcode = X86::JAE; break;
248 case X86::JAE: ROpcode = X86::JB; break;
249 case X86::JE: ROpcode = X86::JNE; break;
250 case X86::JNE: ROpcode = X86::JE; break;
251 case X86::JBE: ROpcode = X86::JA; break;
252 case X86::JA: ROpcode = X86::JBE; break;
253 case X86::JS: ROpcode = X86::JNS; break;
254 case X86::JNS: ROpcode = X86::JS; break;
255 case X86::JP: ROpcode = X86::JNP; break;
256 case X86::JNP: ROpcode = X86::JP; break;
257 case X86::JL: ROpcode = X86::JGE; break;
258 case X86::JGE: ROpcode = X86::JL; break;
259 case X86::JLE: ROpcode = X86::JG; break;
260 case X86::JG: ROpcode = X86::JLE; break;
262 MachineBasicBlock* MBB = MI->getParent();
263 MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
264 return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);