1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/MC/MCAsmInfo.h"
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
50 ReMatPICStubLoad("remat-pic-stub-load",
51 cl::desc("Re-materialize load from stub in PIC mode"),
52 cl::init(false), cl::Hidden);
54 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
56 TM(tm), RI(tm, *this) {
58 TB_NOT_REVERSABLE = 1U << 31,
59 TB_FLAGS = TB_NOT_REVERSABLE
62 static const unsigned OpTbl2Addr[][2] = {
63 { X86::ADC32ri, X86::ADC32mi },
64 { X86::ADC32ri8, X86::ADC32mi8 },
65 { X86::ADC32rr, X86::ADC32mr },
66 { X86::ADC64ri32, X86::ADC64mi32 },
67 { X86::ADC64ri8, X86::ADC64mi8 },
68 { X86::ADC64rr, X86::ADC64mr },
69 { X86::ADD16ri, X86::ADD16mi },
70 { X86::ADD16ri8, X86::ADD16mi8 },
71 { X86::ADD16rr, X86::ADD16mr },
72 { X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE },
73 { X86::ADD32ri, X86::ADD32mi },
74 { X86::ADD32ri8, X86::ADD32mi8 },
75 { X86::ADD32rr, X86::ADD32mr },
76 { X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE },
77 { X86::ADD64ri32, X86::ADD64mi32 },
78 { X86::ADD64ri8, X86::ADD64mi8 },
79 { X86::ADD64rr, X86::ADD64mr },
80 { X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE },
81 { X86::ADD8ri, X86::ADD8mi },
82 { X86::ADD8rr, X86::ADD8mr },
83 { X86::AND16ri, X86::AND16mi },
84 { X86::AND16ri8, X86::AND16mi8 },
85 { X86::AND16rr, X86::AND16mr },
86 { X86::AND32ri, X86::AND32mi },
87 { X86::AND32ri8, X86::AND32mi8 },
88 { X86::AND32rr, X86::AND32mr },
89 { X86::AND64ri32, X86::AND64mi32 },
90 { X86::AND64ri8, X86::AND64mi8 },
91 { X86::AND64rr, X86::AND64mr },
92 { X86::AND8ri, X86::AND8mi },
93 { X86::AND8rr, X86::AND8mr },
94 { X86::DEC16r, X86::DEC16m },
95 { X86::DEC32r, X86::DEC32m },
96 { X86::DEC64_16r, X86::DEC64_16m },
97 { X86::DEC64_32r, X86::DEC64_32m },
98 { X86::DEC64r, X86::DEC64m },
99 { X86::DEC8r, X86::DEC8m },
100 { X86::INC16r, X86::INC16m },
101 { X86::INC32r, X86::INC32m },
102 { X86::INC64_16r, X86::INC64_16m },
103 { X86::INC64_32r, X86::INC64_32m },
104 { X86::INC64r, X86::INC64m },
105 { X86::INC8r, X86::INC8m },
106 { X86::NEG16r, X86::NEG16m },
107 { X86::NEG32r, X86::NEG32m },
108 { X86::NEG64r, X86::NEG64m },
109 { X86::NEG8r, X86::NEG8m },
110 { X86::NOT16r, X86::NOT16m },
111 { X86::NOT32r, X86::NOT32m },
112 { X86::NOT64r, X86::NOT64m },
113 { X86::NOT8r, X86::NOT8m },
114 { X86::OR16ri, X86::OR16mi },
115 { X86::OR16ri8, X86::OR16mi8 },
116 { X86::OR16rr, X86::OR16mr },
117 { X86::OR32ri, X86::OR32mi },
118 { X86::OR32ri8, X86::OR32mi8 },
119 { X86::OR32rr, X86::OR32mr },
120 { X86::OR64ri32, X86::OR64mi32 },
121 { X86::OR64ri8, X86::OR64mi8 },
122 { X86::OR64rr, X86::OR64mr },
123 { X86::OR8ri, X86::OR8mi },
124 { X86::OR8rr, X86::OR8mr },
125 { X86::ROL16r1, X86::ROL16m1 },
126 { X86::ROL16rCL, X86::ROL16mCL },
127 { X86::ROL16ri, X86::ROL16mi },
128 { X86::ROL32r1, X86::ROL32m1 },
129 { X86::ROL32rCL, X86::ROL32mCL },
130 { X86::ROL32ri, X86::ROL32mi },
131 { X86::ROL64r1, X86::ROL64m1 },
132 { X86::ROL64rCL, X86::ROL64mCL },
133 { X86::ROL64ri, X86::ROL64mi },
134 { X86::ROL8r1, X86::ROL8m1 },
135 { X86::ROL8rCL, X86::ROL8mCL },
136 { X86::ROL8ri, X86::ROL8mi },
137 { X86::ROR16r1, X86::ROR16m1 },
138 { X86::ROR16rCL, X86::ROR16mCL },
139 { X86::ROR16ri, X86::ROR16mi },
140 { X86::ROR32r1, X86::ROR32m1 },
141 { X86::ROR32rCL, X86::ROR32mCL },
142 { X86::ROR32ri, X86::ROR32mi },
143 { X86::ROR64r1, X86::ROR64m1 },
144 { X86::ROR64rCL, X86::ROR64mCL },
145 { X86::ROR64ri, X86::ROR64mi },
146 { X86::ROR8r1, X86::ROR8m1 },
147 { X86::ROR8rCL, X86::ROR8mCL },
148 { X86::ROR8ri, X86::ROR8mi },
149 { X86::SAR16r1, X86::SAR16m1 },
150 { X86::SAR16rCL, X86::SAR16mCL },
151 { X86::SAR16ri, X86::SAR16mi },
152 { X86::SAR32r1, X86::SAR32m1 },
153 { X86::SAR32rCL, X86::SAR32mCL },
154 { X86::SAR32ri, X86::SAR32mi },
155 { X86::SAR64r1, X86::SAR64m1 },
156 { X86::SAR64rCL, X86::SAR64mCL },
157 { X86::SAR64ri, X86::SAR64mi },
158 { X86::SAR8r1, X86::SAR8m1 },
159 { X86::SAR8rCL, X86::SAR8mCL },
160 { X86::SAR8ri, X86::SAR8mi },
161 { X86::SBB32ri, X86::SBB32mi },
162 { X86::SBB32ri8, X86::SBB32mi8 },
163 { X86::SBB32rr, X86::SBB32mr },
164 { X86::SBB64ri32, X86::SBB64mi32 },
165 { X86::SBB64ri8, X86::SBB64mi8 },
166 { X86::SBB64rr, X86::SBB64mr },
167 { X86::SHL16rCL, X86::SHL16mCL },
168 { X86::SHL16ri, X86::SHL16mi },
169 { X86::SHL32rCL, X86::SHL32mCL },
170 { X86::SHL32ri, X86::SHL32mi },
171 { X86::SHL64rCL, X86::SHL64mCL },
172 { X86::SHL64ri, X86::SHL64mi },
173 { X86::SHL8rCL, X86::SHL8mCL },
174 { X86::SHL8ri, X86::SHL8mi },
175 { X86::SHLD16rrCL, X86::SHLD16mrCL },
176 { X86::SHLD16rri8, X86::SHLD16mri8 },
177 { X86::SHLD32rrCL, X86::SHLD32mrCL },
178 { X86::SHLD32rri8, X86::SHLD32mri8 },
179 { X86::SHLD64rrCL, X86::SHLD64mrCL },
180 { X86::SHLD64rri8, X86::SHLD64mri8 },
181 { X86::SHR16r1, X86::SHR16m1 },
182 { X86::SHR16rCL, X86::SHR16mCL },
183 { X86::SHR16ri, X86::SHR16mi },
184 { X86::SHR32r1, X86::SHR32m1 },
185 { X86::SHR32rCL, X86::SHR32mCL },
186 { X86::SHR32ri, X86::SHR32mi },
187 { X86::SHR64r1, X86::SHR64m1 },
188 { X86::SHR64rCL, X86::SHR64mCL },
189 { X86::SHR64ri, X86::SHR64mi },
190 { X86::SHR8r1, X86::SHR8m1 },
191 { X86::SHR8rCL, X86::SHR8mCL },
192 { X86::SHR8ri, X86::SHR8mi },
193 { X86::SHRD16rrCL, X86::SHRD16mrCL },
194 { X86::SHRD16rri8, X86::SHRD16mri8 },
195 { X86::SHRD32rrCL, X86::SHRD32mrCL },
196 { X86::SHRD32rri8, X86::SHRD32mri8 },
197 { X86::SHRD64rrCL, X86::SHRD64mrCL },
198 { X86::SHRD64rri8, X86::SHRD64mri8 },
199 { X86::SUB16ri, X86::SUB16mi },
200 { X86::SUB16ri8, X86::SUB16mi8 },
201 { X86::SUB16rr, X86::SUB16mr },
202 { X86::SUB32ri, X86::SUB32mi },
203 { X86::SUB32ri8, X86::SUB32mi8 },
204 { X86::SUB32rr, X86::SUB32mr },
205 { X86::SUB64ri32, X86::SUB64mi32 },
206 { X86::SUB64ri8, X86::SUB64mi8 },
207 { X86::SUB64rr, X86::SUB64mr },
208 { X86::SUB8ri, X86::SUB8mi },
209 { X86::SUB8rr, X86::SUB8mr },
210 { X86::XOR16ri, X86::XOR16mi },
211 { X86::XOR16ri8, X86::XOR16mi8 },
212 { X86::XOR16rr, X86::XOR16mr },
213 { X86::XOR32ri, X86::XOR32mi },
214 { X86::XOR32ri8, X86::XOR32mi8 },
215 { X86::XOR32rr, X86::XOR32mr },
216 { X86::XOR64ri32, X86::XOR64mi32 },
217 { X86::XOR64ri8, X86::XOR64mi8 },
218 { X86::XOR64rr, X86::XOR64mr },
219 { X86::XOR8ri, X86::XOR8mi },
220 { X86::XOR8rr, X86::XOR8mr }
223 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
224 unsigned RegOp = OpTbl2Addr[i][0];
225 unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS;
226 assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?");
227 RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U);
229 // If this is not a reversable operation (because there is a many->one)
230 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
231 if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE)
234 // Index 0, folded load and store, no alignment requirement.
235 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
237 assert(!MemOp2RegOpTable.count(MemOp) &&
238 "Duplicated entries in unfolding maps?");
239 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
242 // If the third value is 1, then it's folding either a load or a store.
243 static const unsigned OpTbl0[][4] = {
244 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
245 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
246 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
247 { X86::CALL32r, X86::CALL32m, 1, 0 },
248 { X86::CALL64r, X86::CALL64m, 1, 0 },
249 { X86::WINCALL64r, X86::WINCALL64m, 1, 0 },
250 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
251 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
252 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
253 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
254 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
255 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
256 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
257 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
258 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
259 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
260 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
261 { X86::DIV16r, X86::DIV16m, 1, 0 },
262 { X86::DIV32r, X86::DIV32m, 1, 0 },
263 { X86::DIV64r, X86::DIV64m, 1, 0 },
264 { X86::DIV8r, X86::DIV8m, 1, 0 },
265 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
266 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
267 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
268 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
269 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
270 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
271 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
272 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
273 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
274 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
275 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
276 { X86::JMP32r, X86::JMP32m, 1, 0 },
277 { X86::JMP64r, X86::JMP64m, 1, 0 },
278 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
279 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
280 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
281 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
282 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 },
283 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
284 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
285 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
286 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
287 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
288 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
289 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
290 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
291 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
292 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
293 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
294 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
295 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
296 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
297 { X86::MUL16r, X86::MUL16m, 1, 0 },
298 { X86::MUL32r, X86::MUL32m, 1, 0 },
299 { X86::MUL64r, X86::MUL64m, 1, 0 },
300 { X86::MUL8r, X86::MUL8m, 1, 0 },
301 { X86::SETAEr, X86::SETAEm, 0, 0 },
302 { X86::SETAr, X86::SETAm, 0, 0 },
303 { X86::SETBEr, X86::SETBEm, 0, 0 },
304 { X86::SETBr, X86::SETBm, 0, 0 },
305 { X86::SETEr, X86::SETEm, 0, 0 },
306 { X86::SETGEr, X86::SETGEm, 0, 0 },
307 { X86::SETGr, X86::SETGm, 0, 0 },
308 { X86::SETLEr, X86::SETLEm, 0, 0 },
309 { X86::SETLr, X86::SETLm, 0, 0 },
310 { X86::SETNEr, X86::SETNEm, 0, 0 },
311 { X86::SETNOr, X86::SETNOm, 0, 0 },
312 { X86::SETNPr, X86::SETNPm, 0, 0 },
313 { X86::SETNSr, X86::SETNSm, 0, 0 },
314 { X86::SETOr, X86::SETOm, 0, 0 },
315 { X86::SETPr, X86::SETPm, 0, 0 },
316 { X86::SETSr, X86::SETSm, 0, 0 },
317 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
318 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
319 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
320 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
321 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
322 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
325 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
326 unsigned RegOp = OpTbl0[i][0];
327 unsigned MemOp = OpTbl0[i][1];
328 unsigned Align = OpTbl0[i][3];
329 assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?");
330 RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp,Align);
331 unsigned FoldedLoad = OpTbl0[i][2];
332 // Index 0, folded load or store.
333 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
334 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) {
335 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?");
336 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
340 static const unsigned OpTbl1[][3] = {
341 { X86::CMP16rr, X86::CMP16rm, 0 },
342 { X86::CMP32rr, X86::CMP32rm, 0 },
343 { X86::CMP64rr, X86::CMP64rm, 0 },
344 { X86::CMP8rr, X86::CMP8rm, 0 },
345 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
346 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
347 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
348 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
349 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
350 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
351 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
352 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
353 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
354 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
355 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
356 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
357 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
358 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
359 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
360 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
361 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
362 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
363 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
364 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
365 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
366 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
367 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
368 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
369 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
370 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
371 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
372 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
373 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
374 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
375 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
376 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
377 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
378 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
379 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
380 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
381 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
382 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
383 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, 16 },
384 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, 16 },
385 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
386 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
387 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
388 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
389 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
390 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
391 { X86::MOV16rr, X86::MOV16rm, 0 },
392 { X86::MOV32rr, X86::MOV32rm, 0 },
393 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 },
394 { X86::MOV64rr, X86::MOV64rm, 0 },
395 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
396 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
397 { X86::MOV8rr, X86::MOV8rm, 0 },
398 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
399 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
400 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
401 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
402 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
403 { X86::MOVDQArr, X86::MOVDQArm, 16 },
404 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
405 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
406 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
407 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
408 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
409 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
410 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
411 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
412 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
413 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
414 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
415 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
416 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
417 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
418 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
419 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
420 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
421 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
422 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
423 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
424 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
425 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
426 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
427 { X86::RCPPSr, X86::RCPPSm, 16 },
428 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
429 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
430 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
431 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
432 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
433 { X86::SQRTPDr, X86::SQRTPDm, 16 },
434 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
435 { X86::SQRTPSr, X86::SQRTPSm, 16 },
436 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
437 { X86::SQRTSDr, X86::SQRTSDm, 0 },
438 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
439 { X86::SQRTSSr, X86::SQRTSSm, 0 },
440 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
441 { X86::TEST16rr, X86::TEST16rm, 0 },
442 { X86::TEST32rr, X86::TEST32rm, 0 },
443 { X86::TEST64rr, X86::TEST64rm, 0 },
444 { X86::TEST8rr, X86::TEST8rm, 0 },
445 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
446 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
447 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
450 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
451 unsigned RegOp = OpTbl1[i][0];
452 unsigned MemOp = OpTbl1[i][1];
453 unsigned Align = OpTbl1[i][2];
454 assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries");
455 RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp,Align);
457 // Index 1, folded load
458 unsigned AuxInfo = 1 | (1 << 4);
459 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) {
460 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries");
461 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
465 static const unsigned OpTbl2[][3] = {
466 { X86::ADC32rr, X86::ADC32rm, 0 },
467 { X86::ADC64rr, X86::ADC64rm, 0 },
468 { X86::ADD16rr, X86::ADD16rm, 0 },
469 { X86::ADD16rr_DB, X86::ADD16rm | TB_NOT_REVERSABLE, 0 },
470 { X86::ADD32rr, X86::ADD32rm, 0 },
471 { X86::ADD32rr_DB, X86::ADD32rm | TB_NOT_REVERSABLE, 0 },
472 { X86::ADD64rr, X86::ADD64rm, 0 },
473 { X86::ADD64rr_DB, X86::ADD64rm | TB_NOT_REVERSABLE, 0 },
474 { X86::ADD8rr, X86::ADD8rm, 0 },
475 { X86::ADDPDrr, X86::ADDPDrm, 16 },
476 { X86::ADDPSrr, X86::ADDPSrm, 16 },
477 { X86::ADDSDrr, X86::ADDSDrm, 0 },
478 { X86::ADDSSrr, X86::ADDSSrm, 0 },
479 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
480 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
481 { X86::AND16rr, X86::AND16rm, 0 },
482 { X86::AND32rr, X86::AND32rm, 0 },
483 { X86::AND64rr, X86::AND64rm, 0 },
484 { X86::AND8rr, X86::AND8rm, 0 },
485 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
486 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
487 { X86::ANDPDrr, X86::ANDPDrm, 16 },
488 { X86::ANDPSrr, X86::ANDPSrm, 16 },
489 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
490 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
491 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
492 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
493 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
494 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
495 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
496 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
497 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
498 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
499 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
500 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
501 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
502 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
503 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
504 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
505 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
506 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
507 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
508 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
509 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
510 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
511 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
512 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
513 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
514 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
515 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
516 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
517 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
518 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
519 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
520 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
521 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
522 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
523 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
524 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
525 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
526 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
527 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
528 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
529 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
530 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
531 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
532 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
533 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
534 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
535 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
536 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
537 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
538 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
539 { X86::CMPSDrr, X86::CMPSDrm, 0 },
540 { X86::CMPSSrr, X86::CMPSSrm, 0 },
541 { X86::DIVPDrr, X86::DIVPDrm, 16 },
542 { X86::DIVPSrr, X86::DIVPSrm, 16 },
543 { X86::DIVSDrr, X86::DIVSDrm, 0 },
544 { X86::DIVSSrr, X86::DIVSSrm, 0 },
545 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
546 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
547 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
548 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
549 { X86::FsORPDrr, X86::FsORPDrm, 16 },
550 { X86::FsORPSrr, X86::FsORPSrm, 16 },
551 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
552 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
553 { X86::HADDPDrr, X86::HADDPDrm, 16 },
554 { X86::HADDPSrr, X86::HADDPSrm, 16 },
555 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
556 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
557 { X86::IMUL16rr, X86::IMUL16rm, 0 },
558 { X86::IMUL32rr, X86::IMUL32rm, 0 },
559 { X86::IMUL64rr, X86::IMUL64rm, 0 },
560 { X86::MAXPDrr, X86::MAXPDrm, 16 },
561 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
562 { X86::MAXPSrr, X86::MAXPSrm, 16 },
563 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
564 { X86::MAXSDrr, X86::MAXSDrm, 0 },
565 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
566 { X86::MAXSSrr, X86::MAXSSrm, 0 },
567 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
568 { X86::MINPDrr, X86::MINPDrm, 16 },
569 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
570 { X86::MINPSrr, X86::MINPSrm, 16 },
571 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
572 { X86::MINSDrr, X86::MINSDrm, 0 },
573 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
574 { X86::MINSSrr, X86::MINSSrm, 0 },
575 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
576 { X86::MULPDrr, X86::MULPDrm, 16 },
577 { X86::MULPSrr, X86::MULPSrm, 16 },
578 { X86::MULSDrr, X86::MULSDrm, 0 },
579 { X86::MULSSrr, X86::MULSSrm, 0 },
580 { X86::OR16rr, X86::OR16rm, 0 },
581 { X86::OR32rr, X86::OR32rm, 0 },
582 { X86::OR64rr, X86::OR64rm, 0 },
583 { X86::OR8rr, X86::OR8rm, 0 },
584 { X86::ORPDrr, X86::ORPDrm, 16 },
585 { X86::ORPSrr, X86::ORPSrm, 16 },
586 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
587 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
588 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
589 { X86::PADDBrr, X86::PADDBrm, 16 },
590 { X86::PADDDrr, X86::PADDDrm, 16 },
591 { X86::PADDQrr, X86::PADDQrm, 16 },
592 { X86::PADDSBrr, X86::PADDSBrm, 16 },
593 { X86::PADDSWrr, X86::PADDSWrm, 16 },
594 { X86::PADDWrr, X86::PADDWrm, 16 },
595 { X86::PANDNrr, X86::PANDNrm, 16 },
596 { X86::PANDrr, X86::PANDrm, 16 },
597 { X86::PAVGBrr, X86::PAVGBrm, 16 },
598 { X86::PAVGWrr, X86::PAVGWrm, 16 },
599 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
600 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
601 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
602 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
603 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
604 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
605 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
606 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
607 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
608 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
609 { X86::PMINSWrr, X86::PMINSWrm, 16 },
610 { X86::PMINUBrr, X86::PMINUBrm, 16 },
611 { X86::PMULDQrr, X86::PMULDQrm, 16 },
612 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
613 { X86::PMULHWrr, X86::PMULHWrm, 16 },
614 { X86::PMULLDrr, X86::PMULLDrm, 16 },
615 { X86::PMULLWrr, X86::PMULLWrm, 16 },
616 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
617 { X86::PORrr, X86::PORrm, 16 },
618 { X86::PSADBWrr, X86::PSADBWrm, 16 },
619 { X86::PSLLDrr, X86::PSLLDrm, 16 },
620 { X86::PSLLQrr, X86::PSLLQrm, 16 },
621 { X86::PSLLWrr, X86::PSLLWrm, 16 },
622 { X86::PSRADrr, X86::PSRADrm, 16 },
623 { X86::PSRAWrr, X86::PSRAWrm, 16 },
624 { X86::PSRLDrr, X86::PSRLDrm, 16 },
625 { X86::PSRLQrr, X86::PSRLQrm, 16 },
626 { X86::PSRLWrr, X86::PSRLWrm, 16 },
627 { X86::PSUBBrr, X86::PSUBBrm, 16 },
628 { X86::PSUBDrr, X86::PSUBDrm, 16 },
629 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
630 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
631 { X86::PSUBWrr, X86::PSUBWrm, 16 },
632 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
633 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
634 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
635 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
636 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
637 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
638 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
639 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
640 { X86::PXORrr, X86::PXORrm, 16 },
641 { X86::SBB32rr, X86::SBB32rm, 0 },
642 { X86::SBB64rr, X86::SBB64rm, 0 },
643 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
644 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
645 { X86::SUB16rr, X86::SUB16rm, 0 },
646 { X86::SUB32rr, X86::SUB32rm, 0 },
647 { X86::SUB64rr, X86::SUB64rm, 0 },
648 { X86::SUB8rr, X86::SUB8rm, 0 },
649 { X86::SUBPDrr, X86::SUBPDrm, 16 },
650 { X86::SUBPSrr, X86::SUBPSrm, 16 },
651 { X86::SUBSDrr, X86::SUBSDrm, 0 },
652 { X86::SUBSSrr, X86::SUBSSrm, 0 },
653 // FIXME: TEST*rr -> swapped operand of TEST*mr.
654 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
655 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
656 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
657 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
658 { X86::XOR16rr, X86::XOR16rm, 0 },
659 { X86::XOR32rr, X86::XOR32rm, 0 },
660 { X86::XOR64rr, X86::XOR64rm, 0 },
661 { X86::XOR8rr, X86::XOR8rm, 0 },
662 { X86::XORPDrr, X86::XORPDrm, 16 },
663 { X86::XORPSrr, X86::XORPSrm, 16 }
666 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
667 unsigned RegOp = OpTbl2[i][0];
668 unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS;
669 unsigned Align = OpTbl2[i][2];
671 assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!");
672 RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align);
675 // If this is not a reversable operation (because there is a many->one)
676 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
677 if (OpTbl2[i][1] & TB_NOT_REVERSABLE)
680 // Index 2, folded load
681 unsigned AuxInfo = 2 | (1 << 4);
682 assert(!MemOp2RegOpTable.count(MemOp) &&
683 "Duplicated entries in unfolding maps?");
684 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
689 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
690 unsigned &SrcReg, unsigned &DstReg,
691 unsigned &SubIdx) const {
692 switch (MI.getOpcode()) {
694 case X86::MOVSX16rr8:
695 case X86::MOVZX16rr8:
696 case X86::MOVSX32rr8:
697 case X86::MOVZX32rr8:
698 case X86::MOVSX64rr8:
699 case X86::MOVZX64rr8:
700 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
701 // It's not always legal to reference the low 8-bit of the larger
702 // register in 32-bit mode.
704 case X86::MOVSX32rr16:
705 case X86::MOVZX32rr16:
706 case X86::MOVSX64rr16:
707 case X86::MOVZX64rr16:
708 case X86::MOVSX64rr32:
709 case X86::MOVZX64rr32: {
710 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
713 SrcReg = MI.getOperand(1).getReg();
714 DstReg = MI.getOperand(0).getReg();
715 switch (MI.getOpcode()) {
719 case X86::MOVSX16rr8:
720 case X86::MOVZX16rr8:
721 case X86::MOVSX32rr8:
722 case X86::MOVZX32rr8:
723 case X86::MOVSX64rr8:
724 case X86::MOVZX64rr8:
725 SubIdx = X86::sub_8bit;
727 case X86::MOVSX32rr16:
728 case X86::MOVZX32rr16:
729 case X86::MOVSX64rr16:
730 case X86::MOVZX64rr16:
731 SubIdx = X86::sub_16bit;
733 case X86::MOVSX64rr32:
734 case X86::MOVZX64rr32:
735 SubIdx = X86::sub_32bit;
744 /// isFrameOperand - Return true and the FrameIndex if the specified
745 /// operand and follow operands form a reference to the stack frame.
746 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
747 int &FrameIndex) const {
748 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
749 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
750 MI->getOperand(Op+1).getImm() == 1 &&
751 MI->getOperand(Op+2).getReg() == 0 &&
752 MI->getOperand(Op+3).getImm() == 0) {
753 FrameIndex = MI->getOperand(Op).getIndex();
759 static bool isFrameLoadOpcode(int Opcode) {
765 case X86::MOV32rm_TC:
767 case X86::MOV64rm_TC:
774 case X86::MMX_MOVD64rm:
775 case X86::MMX_MOVQ64rm:
782 static bool isFrameStoreOpcode(int Opcode) {
788 case X86::MOV32mr_TC:
790 case X86::MOV64mr_TC:
797 case X86::MMX_MOVD64mr:
798 case X86::MMX_MOVQ64mr:
799 case X86::MMX_MOVNTQmr:
805 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
806 int &FrameIndex) const {
807 if (isFrameLoadOpcode(MI->getOpcode()))
808 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
809 return MI->getOperand(0).getReg();
813 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
814 int &FrameIndex) const {
815 if (isFrameLoadOpcode(MI->getOpcode())) {
817 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
819 // Check for post-frame index elimination operations
820 const MachineMemOperand *Dummy;
821 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
826 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
827 const MachineMemOperand *&MMO,
828 int &FrameIndex) const {
829 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
830 oe = MI->memoperands_end();
833 if ((*o)->isLoad() && (*o)->getValue())
834 if (const FixedStackPseudoSourceValue *Value =
835 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
836 FrameIndex = Value->getFrameIndex();
844 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
845 int &FrameIndex) const {
846 if (isFrameStoreOpcode(MI->getOpcode()))
847 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
848 isFrameOperand(MI, 0, FrameIndex))
849 return MI->getOperand(X86::AddrNumOperands).getReg();
853 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
854 int &FrameIndex) const {
855 if (isFrameStoreOpcode(MI->getOpcode())) {
857 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
859 // Check for post-frame index elimination operations
860 const MachineMemOperand *Dummy;
861 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
866 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
867 const MachineMemOperand *&MMO,
868 int &FrameIndex) const {
869 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
870 oe = MI->memoperands_end();
873 if ((*o)->isStore() && (*o)->getValue())
874 if (const FixedStackPseudoSourceValue *Value =
875 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
876 FrameIndex = Value->getFrameIndex();
884 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
886 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
887 bool isPICBase = false;
888 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
889 E = MRI.def_end(); I != E; ++I) {
890 MachineInstr *DefMI = I.getOperand().getParent();
891 if (DefMI->getOpcode() != X86::MOVPC32r)
893 assert(!isPICBase && "More than one PIC base?");
900 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
901 AliasAnalysis *AA) const {
902 switch (MI->getOpcode()) {
913 case X86::MOVUPSrm_Int:
916 case X86::MMX_MOVD64rm:
917 case X86::MMX_MOVQ64rm:
918 case X86::FsMOVAPSrm:
919 case X86::FsMOVAPDrm: {
920 // Loads from constant pools are trivially rematerializable.
921 if (MI->getOperand(1).isReg() &&
922 MI->getOperand(2).isImm() &&
923 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
924 MI->isInvariantLoad(AA)) {
925 unsigned BaseReg = MI->getOperand(1).getReg();
926 if (BaseReg == 0 || BaseReg == X86::RIP)
928 // Allow re-materialization of PIC load.
929 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
931 const MachineFunction &MF = *MI->getParent()->getParent();
932 const MachineRegisterInfo &MRI = MF.getRegInfo();
933 bool isPICBase = false;
934 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
935 E = MRI.def_end(); I != E; ++I) {
936 MachineInstr *DefMI = I.getOperand().getParent();
937 if (DefMI->getOpcode() != X86::MOVPC32r)
939 assert(!isPICBase && "More than one PIC base?");
949 if (MI->getOperand(2).isImm() &&
950 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
951 !MI->getOperand(4).isReg()) {
952 // lea fi#, lea GV, etc. are all rematerializable.
953 if (!MI->getOperand(1).isReg())
955 unsigned BaseReg = MI->getOperand(1).getReg();
958 // Allow re-materialization of lea PICBase + x.
959 const MachineFunction &MF = *MI->getParent()->getParent();
960 const MachineRegisterInfo &MRI = MF.getRegInfo();
961 return regIsPICBase(BaseReg, MRI);
967 // All other instructions marked M_REMATERIALIZABLE are always trivially
972 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
973 /// would clobber the EFLAGS condition register. Note the result may be
974 /// conservative. If it cannot definitely determine the safety after visiting
975 /// a few instructions in each direction it assumes it's not safe.
976 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
977 MachineBasicBlock::iterator I) {
978 MachineBasicBlock::iterator E = MBB.end();
980 // It's always safe to clobber EFLAGS at the end of a block.
984 // For compile time consideration, if we are not able to determine the
985 // safety after visiting 4 instructions in each direction, we will assume
987 MachineBasicBlock::iterator Iter = I;
988 for (unsigned i = 0; i < 4; ++i) {
989 bool SeenDef = false;
990 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
991 MachineOperand &MO = Iter->getOperand(j);
994 if (MO.getReg() == X86::EFLAGS) {
1002 // This instruction defines EFLAGS, no need to look any further.
1005 // Skip over DBG_VALUE.
1006 while (Iter != E && Iter->isDebugValue())
1009 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1014 MachineBasicBlock::iterator B = MBB.begin();
1016 for (unsigned i = 0; i < 4; ++i) {
1017 // If we make it to the beginning of the block, it's safe to clobber
1018 // EFLAGS iff EFLAGS is not live-in.
1020 return !MBB.isLiveIn(X86::EFLAGS);
1023 // Skip over DBG_VALUE.
1024 while (Iter != B && Iter->isDebugValue())
1027 bool SawKill = false;
1028 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1029 MachineOperand &MO = Iter->getOperand(j);
1030 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1031 if (MO.isDef()) return MO.isDead();
1032 if (MO.isKill()) SawKill = true;
1037 // This instruction kills EFLAGS and doesn't redefine it, so
1038 // there's no need to look further.
1042 // Conservative answer.
1046 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1047 MachineBasicBlock::iterator I,
1048 unsigned DestReg, unsigned SubIdx,
1049 const MachineInstr *Orig,
1050 const TargetRegisterInfo &TRI) const {
1051 DebugLoc DL = Orig->getDebugLoc();
1053 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1054 // Re-materialize them as movri instructions to avoid side effects.
1056 unsigned Opc = Orig->getOpcode();
1062 case X86::MOV64r0: {
1063 if (!isSafeToClobberEFLAGS(MBB, I)) {
1066 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1067 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1068 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1069 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1078 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1081 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1084 MachineInstr *NewMI = prior(I);
1085 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1088 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1089 /// is not marked dead.
1090 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1091 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1092 MachineOperand &MO = MI->getOperand(i);
1093 if (MO.isReg() && MO.isDef() &&
1094 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1101 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1102 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1103 /// to a 32-bit superregister and then truncating back down to a 16-bit
1106 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1107 MachineFunction::iterator &MFI,
1108 MachineBasicBlock::iterator &MBBI,
1109 LiveVariables *LV) const {
1110 MachineInstr *MI = MBBI;
1111 unsigned Dest = MI->getOperand(0).getReg();
1112 unsigned Src = MI->getOperand(1).getReg();
1113 bool isDead = MI->getOperand(0).isDead();
1114 bool isKill = MI->getOperand(1).isKill();
1116 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1117 ? X86::LEA64_32r : X86::LEA32r;
1118 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1119 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1120 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1122 // Build and insert into an implicit UNDEF value. This is OK because
1123 // well be shifting and then extracting the lower 16-bits.
1124 // This has the potential to cause partial register stall. e.g.
1125 // movw (%rbp,%rcx,2), %dx
1126 // leal -65(%rdx), %esi
1127 // But testing has shown this *does* help performance in 64-bit mode (at
1128 // least on modern x86 machines).
1129 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1130 MachineInstr *InsMI =
1131 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1132 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1133 .addReg(Src, getKillRegState(isKill));
1135 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1136 get(Opc), leaOutReg);
1139 llvm_unreachable(0);
1141 case X86::SHL16ri: {
1142 unsigned ShAmt = MI->getOperand(2).getImm();
1143 MIB.addReg(0).addImm(1 << ShAmt)
1144 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1148 case X86::INC64_16r:
1149 addRegOffset(MIB, leaInReg, true, 1);
1152 case X86::DEC64_16r:
1153 addRegOffset(MIB, leaInReg, true, -1);
1157 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1160 case X86::ADD16rr_DB: {
1161 unsigned Src2 = MI->getOperand(2).getReg();
1162 bool isKill2 = MI->getOperand(2).isKill();
1163 unsigned leaInReg2 = 0;
1164 MachineInstr *InsMI2 = 0;
1166 // ADD16rr %reg1028<kill>, %reg1028
1167 // just a single insert_subreg.
1168 addRegReg(MIB, leaInReg, true, leaInReg, false);
1170 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1171 // Build and insert into an implicit UNDEF value. This is OK because
1172 // well be shifting and then extracting the lower 16-bits.
1173 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1175 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1176 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1177 .addReg(Src2, getKillRegState(isKill2));
1178 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1180 if (LV && isKill2 && InsMI2)
1181 LV->replaceKillInstruction(Src2, MI, InsMI2);
1186 MachineInstr *NewMI = MIB;
1187 MachineInstr *ExtMI =
1188 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1189 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1190 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1193 // Update live variables
1194 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1195 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1197 LV->replaceKillInstruction(Src, MI, InsMI);
1199 LV->replaceKillInstruction(Dest, MI, ExtMI);
1205 /// convertToThreeAddress - This method must be implemented by targets that
1206 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1207 /// may be able to convert a two-address instruction into a true
1208 /// three-address instruction on demand. This allows the X86 target (for
1209 /// example) to convert ADD and SHL instructions into LEA instructions if they
1210 /// would require register copies due to two-addressness.
1212 /// This method returns a null pointer if the transformation cannot be
1213 /// performed, otherwise it returns the new instruction.
1216 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1217 MachineBasicBlock::iterator &MBBI,
1218 LiveVariables *LV) const {
1219 MachineInstr *MI = MBBI;
1220 MachineFunction &MF = *MI->getParent()->getParent();
1221 // All instructions input are two-addr instructions. Get the known operands.
1222 unsigned Dest = MI->getOperand(0).getReg();
1223 unsigned Src = MI->getOperand(1).getReg();
1224 bool isDead = MI->getOperand(0).isDead();
1225 bool isKill = MI->getOperand(1).isKill();
1227 MachineInstr *NewMI = NULL;
1228 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1229 // we have better subtarget support, enable the 16-bit LEA generation here.
1230 // 16-bit LEA is also slow on Core2.
1231 bool DisableLEA16 = true;
1232 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1234 unsigned MIOpc = MI->getOpcode();
1236 case X86::SHUFPSrri: {
1237 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1238 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1240 unsigned B = MI->getOperand(1).getReg();
1241 unsigned C = MI->getOperand(2).getReg();
1242 if (B != C) return 0;
1243 unsigned A = MI->getOperand(0).getReg();
1244 unsigned M = MI->getOperand(3).getImm();
1245 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1246 .addReg(A, RegState::Define | getDeadRegState(isDead))
1247 .addReg(B, getKillRegState(isKill)).addImm(M);
1250 case X86::SHL64ri: {
1251 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1252 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1253 // the flags produced by a shift yet, so this is safe.
1254 unsigned ShAmt = MI->getOperand(2).getImm();
1255 if (ShAmt == 0 || ShAmt >= 4) return 0;
1257 // LEA can't handle RSP.
1258 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1259 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1262 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1263 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1264 .addReg(0).addImm(1 << ShAmt)
1265 .addReg(Src, getKillRegState(isKill))
1266 .addImm(0).addReg(0);
1269 case X86::SHL32ri: {
1270 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1271 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1272 // the flags produced by a shift yet, so this is safe.
1273 unsigned ShAmt = MI->getOperand(2).getImm();
1274 if (ShAmt == 0 || ShAmt >= 4) return 0;
1276 // LEA can't handle ESP.
1277 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1278 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1281 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1282 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1283 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1284 .addReg(0).addImm(1 << ShAmt)
1285 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1288 case X86::SHL16ri: {
1289 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1290 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1291 // the flags produced by a shift yet, so this is safe.
1292 unsigned ShAmt = MI->getOperand(2).getImm();
1293 if (ShAmt == 0 || ShAmt >= 4) return 0;
1296 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1297 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1298 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1299 .addReg(0).addImm(1 << ShAmt)
1300 .addReg(Src, getKillRegState(isKill))
1301 .addImm(0).addReg(0);
1305 // The following opcodes also sets the condition code register(s). Only
1306 // convert them to equivalent lea if the condition code register def's
1308 if (hasLiveCondCodeDef(MI))
1315 case X86::INC64_32r: {
1316 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1317 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1318 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1320 // LEA can't handle RSP.
1321 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1322 !MF.getRegInfo().constrainRegClass(Src,
1323 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1324 X86::GR32_NOSPRegisterClass))
1327 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1328 .addReg(Dest, RegState::Define |
1329 getDeadRegState(isDead)),
1334 case X86::INC64_16r:
1336 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1337 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1338 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1339 .addReg(Dest, RegState::Define |
1340 getDeadRegState(isDead)),
1345 case X86::DEC64_32r: {
1346 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1347 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1348 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1349 // LEA can't handle RSP.
1350 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1351 !MF.getRegInfo().constrainRegClass(Src,
1352 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1353 X86::GR32_NOSPRegisterClass))
1356 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1357 .addReg(Dest, RegState::Define |
1358 getDeadRegState(isDead)),
1363 case X86::DEC64_16r:
1365 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1366 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1367 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1368 .addReg(Dest, RegState::Define |
1369 getDeadRegState(isDead)),
1373 case X86::ADD64rr_DB:
1375 case X86::ADD32rr_DB: {
1376 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1378 TargetRegisterClass *RC;
1379 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1381 RC = X86::GR64_NOSPRegisterClass;
1383 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1384 RC = X86::GR32_NOSPRegisterClass;
1388 unsigned Src2 = MI->getOperand(2).getReg();
1389 bool isKill2 = MI->getOperand(2).isKill();
1391 // LEA can't handle RSP.
1392 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1393 !MF.getRegInfo().constrainRegClass(Src2, RC))
1396 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1397 .addReg(Dest, RegState::Define |
1398 getDeadRegState(isDead)),
1399 Src, isKill, Src2, isKill2);
1401 LV->replaceKillInstruction(Src2, MI, NewMI);
1405 case X86::ADD16rr_DB: {
1407 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1408 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1409 unsigned Src2 = MI->getOperand(2).getReg();
1410 bool isKill2 = MI->getOperand(2).isKill();
1411 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1412 .addReg(Dest, RegState::Define |
1413 getDeadRegState(isDead)),
1414 Src, isKill, Src2, isKill2);
1416 LV->replaceKillInstruction(Src2, MI, NewMI);
1419 case X86::ADD64ri32:
1421 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1422 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1423 .addReg(Dest, RegState::Define |
1424 getDeadRegState(isDead)),
1425 Src, isKill, MI->getOperand(2).getImm());
1428 case X86::ADD32ri8: {
1429 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1430 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1431 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1432 .addReg(Dest, RegState::Define |
1433 getDeadRegState(isDead)),
1434 Src, isKill, MI->getOperand(2).getImm());
1440 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1441 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1442 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1443 .addReg(Dest, RegState::Define |
1444 getDeadRegState(isDead)),
1445 Src, isKill, MI->getOperand(2).getImm());
1451 if (!NewMI) return 0;
1453 if (LV) { // Update live variables
1455 LV->replaceKillInstruction(Src, MI, NewMI);
1457 LV->replaceKillInstruction(Dest, MI, NewMI);
1460 MFI->insert(MBBI, NewMI); // Insert the new inst
1464 /// commuteInstruction - We have a few instructions that must be hacked on to
1468 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1469 switch (MI->getOpcode()) {
1470 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1471 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1472 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1473 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1474 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1475 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1478 switch (MI->getOpcode()) {
1479 default: llvm_unreachable("Unreachable!");
1480 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1481 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1482 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1483 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1484 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1485 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1487 unsigned Amt = MI->getOperand(3).getImm();
1489 MachineFunction &MF = *MI->getParent()->getParent();
1490 MI = MF.CloneMachineInstr(MI);
1493 MI->setDesc(get(Opc));
1494 MI->getOperand(3).setImm(Size-Amt);
1495 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1497 case X86::CMOVB16rr:
1498 case X86::CMOVB32rr:
1499 case X86::CMOVB64rr:
1500 case X86::CMOVAE16rr:
1501 case X86::CMOVAE32rr:
1502 case X86::CMOVAE64rr:
1503 case X86::CMOVE16rr:
1504 case X86::CMOVE32rr:
1505 case X86::CMOVE64rr:
1506 case X86::CMOVNE16rr:
1507 case X86::CMOVNE32rr:
1508 case X86::CMOVNE64rr:
1509 case X86::CMOVBE16rr:
1510 case X86::CMOVBE32rr:
1511 case X86::CMOVBE64rr:
1512 case X86::CMOVA16rr:
1513 case X86::CMOVA32rr:
1514 case X86::CMOVA64rr:
1515 case X86::CMOVL16rr:
1516 case X86::CMOVL32rr:
1517 case X86::CMOVL64rr:
1518 case X86::CMOVGE16rr:
1519 case X86::CMOVGE32rr:
1520 case X86::CMOVGE64rr:
1521 case X86::CMOVLE16rr:
1522 case X86::CMOVLE32rr:
1523 case X86::CMOVLE64rr:
1524 case X86::CMOVG16rr:
1525 case X86::CMOVG32rr:
1526 case X86::CMOVG64rr:
1527 case X86::CMOVS16rr:
1528 case X86::CMOVS32rr:
1529 case X86::CMOVS64rr:
1530 case X86::CMOVNS16rr:
1531 case X86::CMOVNS32rr:
1532 case X86::CMOVNS64rr:
1533 case X86::CMOVP16rr:
1534 case X86::CMOVP32rr:
1535 case X86::CMOVP64rr:
1536 case X86::CMOVNP16rr:
1537 case X86::CMOVNP32rr:
1538 case X86::CMOVNP64rr:
1539 case X86::CMOVO16rr:
1540 case X86::CMOVO32rr:
1541 case X86::CMOVO64rr:
1542 case X86::CMOVNO16rr:
1543 case X86::CMOVNO32rr:
1544 case X86::CMOVNO64rr: {
1546 switch (MI->getOpcode()) {
1548 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1549 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1550 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1551 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1552 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1553 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1554 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1555 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1556 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1557 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1558 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1559 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1560 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1561 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1562 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1563 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1564 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1565 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1566 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1567 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1568 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1569 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1570 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1571 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1572 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1573 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1574 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1575 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1576 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1577 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1578 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1579 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1580 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1581 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1582 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1583 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1584 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1585 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1586 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1587 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1588 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1589 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1590 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1591 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1592 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1593 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1594 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1595 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1598 MachineFunction &MF = *MI->getParent()->getParent();
1599 MI = MF.CloneMachineInstr(MI);
1602 MI->setDesc(get(Opc));
1603 // Fallthrough intended.
1606 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1610 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1612 default: return X86::COND_INVALID;
1613 case X86::JE_4: return X86::COND_E;
1614 case X86::JNE_4: return X86::COND_NE;
1615 case X86::JL_4: return X86::COND_L;
1616 case X86::JLE_4: return X86::COND_LE;
1617 case X86::JG_4: return X86::COND_G;
1618 case X86::JGE_4: return X86::COND_GE;
1619 case X86::JB_4: return X86::COND_B;
1620 case X86::JBE_4: return X86::COND_BE;
1621 case X86::JA_4: return X86::COND_A;
1622 case X86::JAE_4: return X86::COND_AE;
1623 case X86::JS_4: return X86::COND_S;
1624 case X86::JNS_4: return X86::COND_NS;
1625 case X86::JP_4: return X86::COND_P;
1626 case X86::JNP_4: return X86::COND_NP;
1627 case X86::JO_4: return X86::COND_O;
1628 case X86::JNO_4: return X86::COND_NO;
1632 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1634 default: llvm_unreachable("Illegal condition code!");
1635 case X86::COND_E: return X86::JE_4;
1636 case X86::COND_NE: return X86::JNE_4;
1637 case X86::COND_L: return X86::JL_4;
1638 case X86::COND_LE: return X86::JLE_4;
1639 case X86::COND_G: return X86::JG_4;
1640 case X86::COND_GE: return X86::JGE_4;
1641 case X86::COND_B: return X86::JB_4;
1642 case X86::COND_BE: return X86::JBE_4;
1643 case X86::COND_A: return X86::JA_4;
1644 case X86::COND_AE: return X86::JAE_4;
1645 case X86::COND_S: return X86::JS_4;
1646 case X86::COND_NS: return X86::JNS_4;
1647 case X86::COND_P: return X86::JP_4;
1648 case X86::COND_NP: return X86::JNP_4;
1649 case X86::COND_O: return X86::JO_4;
1650 case X86::COND_NO: return X86::JNO_4;
1654 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1655 /// e.g. turning COND_E to COND_NE.
1656 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1658 default: llvm_unreachable("Illegal condition code!");
1659 case X86::COND_E: return X86::COND_NE;
1660 case X86::COND_NE: return X86::COND_E;
1661 case X86::COND_L: return X86::COND_GE;
1662 case X86::COND_LE: return X86::COND_G;
1663 case X86::COND_G: return X86::COND_LE;
1664 case X86::COND_GE: return X86::COND_L;
1665 case X86::COND_B: return X86::COND_AE;
1666 case X86::COND_BE: return X86::COND_A;
1667 case X86::COND_A: return X86::COND_BE;
1668 case X86::COND_AE: return X86::COND_B;
1669 case X86::COND_S: return X86::COND_NS;
1670 case X86::COND_NS: return X86::COND_S;
1671 case X86::COND_P: return X86::COND_NP;
1672 case X86::COND_NP: return X86::COND_P;
1673 case X86::COND_O: return X86::COND_NO;
1674 case X86::COND_NO: return X86::COND_O;
1678 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1679 const TargetInstrDesc &TID = MI->getDesc();
1680 if (!TID.isTerminator()) return false;
1682 // Conditional branch is a special case.
1683 if (TID.isBranch() && !TID.isBarrier())
1685 if (!TID.isPredicable())
1687 return !isPredicated(MI);
1690 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1691 MachineBasicBlock *&TBB,
1692 MachineBasicBlock *&FBB,
1693 SmallVectorImpl<MachineOperand> &Cond,
1694 bool AllowModify) const {
1695 // Start from the bottom of the block and work up, examining the
1696 // terminator instructions.
1697 MachineBasicBlock::iterator I = MBB.end();
1698 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1699 while (I != MBB.begin()) {
1701 if (I->isDebugValue())
1704 // Working from the bottom, when we see a non-terminator instruction, we're
1706 if (!isUnpredicatedTerminator(I))
1709 // A terminator that isn't a branch can't easily be handled by this
1711 if (!I->getDesc().isBranch())
1714 // Handle unconditional branches.
1715 if (I->getOpcode() == X86::JMP_4) {
1719 TBB = I->getOperand(0).getMBB();
1723 // If the block has any instructions after a JMP, delete them.
1724 while (llvm::next(I) != MBB.end())
1725 llvm::next(I)->eraseFromParent();
1730 // Delete the JMP if it's equivalent to a fall-through.
1731 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1733 I->eraseFromParent();
1735 UnCondBrIter = MBB.end();
1739 // TBB is used to indicate the unconditional destination.
1740 TBB = I->getOperand(0).getMBB();
1744 // Handle conditional branches.
1745 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1746 if (BranchCode == X86::COND_INVALID)
1747 return true; // Can't handle indirect branch.
1749 // Working from the bottom, handle the first conditional branch.
1751 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1752 if (AllowModify && UnCondBrIter != MBB.end() &&
1753 MBB.isLayoutSuccessor(TargetBB)) {
1754 // If we can modify the code and it ends in something like:
1762 // Then we can change this to:
1769 // Which is a bit more efficient.
1770 // We conditionally jump to the fall-through block.
1771 BranchCode = GetOppositeBranchCondition(BranchCode);
1772 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1773 MachineBasicBlock::iterator OldInst = I;
1775 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1776 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1777 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1779 MBB.addSuccessor(TargetBB);
1781 OldInst->eraseFromParent();
1782 UnCondBrIter->eraseFromParent();
1784 // Restart the analysis.
1785 UnCondBrIter = MBB.end();
1791 TBB = I->getOperand(0).getMBB();
1792 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1796 // Handle subsequent conditional branches. Only handle the case where all
1797 // conditional branches branch to the same destination and their condition
1798 // opcodes fit one of the special multi-branch idioms.
1799 assert(Cond.size() == 1);
1802 // Only handle the case where all conditional branches branch to the same
1804 if (TBB != I->getOperand(0).getMBB())
1807 // If the conditions are the same, we can leave them alone.
1808 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1809 if (OldBranchCode == BranchCode)
1812 // If they differ, see if they fit one of the known patterns. Theoretically,
1813 // we could handle more patterns here, but we shouldn't expect to see them
1814 // if instruction selection has done a reasonable job.
1815 if ((OldBranchCode == X86::COND_NP &&
1816 BranchCode == X86::COND_E) ||
1817 (OldBranchCode == X86::COND_E &&
1818 BranchCode == X86::COND_NP))
1819 BranchCode = X86::COND_NP_OR_E;
1820 else if ((OldBranchCode == X86::COND_P &&
1821 BranchCode == X86::COND_NE) ||
1822 (OldBranchCode == X86::COND_NE &&
1823 BranchCode == X86::COND_P))
1824 BranchCode = X86::COND_NE_OR_P;
1828 // Update the MachineOperand.
1829 Cond[0].setImm(BranchCode);
1835 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1836 MachineBasicBlock::iterator I = MBB.end();
1839 while (I != MBB.begin()) {
1841 if (I->isDebugValue())
1843 if (I->getOpcode() != X86::JMP_4 &&
1844 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1846 // Remove the branch.
1847 I->eraseFromParent();
1856 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1857 MachineBasicBlock *FBB,
1858 const SmallVectorImpl<MachineOperand> &Cond,
1859 DebugLoc DL) const {
1860 // Shouldn't be a fall through.
1861 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1862 assert((Cond.size() == 1 || Cond.size() == 0) &&
1863 "X86 branch conditions have one component!");
1866 // Unconditional branch?
1867 assert(!FBB && "Unconditional branch with multiple successors!");
1868 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
1872 // Conditional branch.
1874 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1876 case X86::COND_NP_OR_E:
1877 // Synthesize NP_OR_E with two branches.
1878 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
1880 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
1883 case X86::COND_NE_OR_P:
1884 // Synthesize NE_OR_P with two branches.
1885 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
1887 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
1891 unsigned Opc = GetCondBranchFromCond(CC);
1892 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
1897 // Two-way Conditional branch. Insert the second branch.
1898 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
1904 /// isHReg - Test if the given register is a physical h register.
1905 static bool isHReg(unsigned Reg) {
1906 return X86::GR8_ABCD_HRegClass.contains(Reg);
1909 // Try and copy between VR128/VR64 and GR64 registers.
1910 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg) {
1911 // SrcReg(VR128) -> DestReg(GR64)
1912 // SrcReg(VR64) -> DestReg(GR64)
1913 // SrcReg(GR64) -> DestReg(VR128)
1914 // SrcReg(GR64) -> DestReg(VR64)
1916 if (X86::GR64RegClass.contains(DestReg)) {
1917 if (X86::VR128RegClass.contains(SrcReg)) {
1918 // Copy from a VR128 register to a GR64 register.
1919 return X86::MOVPQIto64rr;
1920 } else if (X86::VR64RegClass.contains(SrcReg)) {
1921 // Copy from a VR64 register to a GR64 register.
1922 return X86::MOVSDto64rr;
1924 } else if (X86::GR64RegClass.contains(SrcReg)) {
1925 // Copy from a GR64 register to a VR128 register.
1926 if (X86::VR128RegClass.contains(DestReg))
1927 return X86::MOV64toPQIrr;
1928 // Copy from a GR64 register to a VR64 register.
1929 else if (X86::VR64RegClass.contains(DestReg))
1930 return X86::MOV64toSDrr;
1936 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1937 MachineBasicBlock::iterator MI, DebugLoc DL,
1938 unsigned DestReg, unsigned SrcReg,
1939 bool KillSrc) const {
1940 // First deal with the normal symmetric copies.
1942 if (X86::GR64RegClass.contains(DestReg, SrcReg))
1944 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
1946 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
1948 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
1949 // Copying to or from a physical H register on x86-64 requires a NOREX
1950 // move. Otherwise use a normal move.
1951 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1952 TM.getSubtarget<X86Subtarget>().is64Bit())
1953 Opc = X86::MOV8rr_NOREX;
1956 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
1957 Opc = X86::MOVAPSrr;
1958 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
1959 Opc = X86::MMX_MOVQ64rr;
1961 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg);
1964 BuildMI(MBB, MI, DL, get(Opc), DestReg)
1965 .addReg(SrcReg, getKillRegState(KillSrc));
1969 // Moving EFLAGS to / from another register requires a push and a pop.
1970 if (SrcReg == X86::EFLAGS) {
1971 if (X86::GR64RegClass.contains(DestReg)) {
1972 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
1973 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1975 } else if (X86::GR32RegClass.contains(DestReg)) {
1976 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
1977 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1981 if (DestReg == X86::EFLAGS) {
1982 if (X86::GR64RegClass.contains(SrcReg)) {
1983 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
1984 .addReg(SrcReg, getKillRegState(KillSrc));
1985 BuildMI(MBB, MI, DL, get(X86::POPF64));
1987 } else if (X86::GR32RegClass.contains(SrcReg)) {
1988 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
1989 .addReg(SrcReg, getKillRegState(KillSrc));
1990 BuildMI(MBB, MI, DL, get(X86::POPF32));
1995 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
1996 << " to " << RI.getName(DestReg) << '\n');
1997 llvm_unreachable("Cannot emit physreg copy instruction");
2000 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2001 const TargetRegisterClass *RC,
2002 bool isStackAligned,
2003 const TargetMachine &TM,
2005 switch (RC->getID()) {
2007 llvm_unreachable("Unknown regclass");
2008 case X86::GR64RegClassID:
2009 case X86::GR64_NOSPRegClassID:
2010 return load ? X86::MOV64rm : X86::MOV64mr;
2011 case X86::GR32RegClassID:
2012 case X86::GR32_NOSPRegClassID:
2013 case X86::GR32_ADRegClassID:
2014 return load ? X86::MOV32rm : X86::MOV32mr;
2015 case X86::GR16RegClassID:
2016 return load ? X86::MOV16rm : X86::MOV16mr;
2017 case X86::GR8RegClassID:
2018 // Copying to or from a physical H register on x86-64 requires a NOREX
2019 // move. Otherwise use a normal move.
2021 TM.getSubtarget<X86Subtarget>().is64Bit())
2022 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2024 return load ? X86::MOV8rm : X86::MOV8mr;
2025 case X86::GR64_ABCDRegClassID:
2026 return load ? X86::MOV64rm : X86::MOV64mr;
2027 case X86::GR32_ABCDRegClassID:
2028 return load ? X86::MOV32rm : X86::MOV32mr;
2029 case X86::GR16_ABCDRegClassID:
2030 return load ? X86::MOV16rm : X86::MOV16mr;
2031 case X86::GR8_ABCD_LRegClassID:
2032 return load ? X86::MOV8rm :X86::MOV8mr;
2033 case X86::GR8_ABCD_HRegClassID:
2034 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2035 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2037 return load ? X86::MOV8rm : X86::MOV8mr;
2038 case X86::GR64_NOREXRegClassID:
2039 case X86::GR64_NOREX_NOSPRegClassID:
2040 return load ? X86::MOV64rm : X86::MOV64mr;
2041 case X86::GR32_NOREXRegClassID:
2042 return load ? X86::MOV32rm : X86::MOV32mr;
2043 case X86::GR16_NOREXRegClassID:
2044 return load ? X86::MOV16rm : X86::MOV16mr;
2045 case X86::GR8_NOREXRegClassID:
2046 return load ? X86::MOV8rm : X86::MOV8mr;
2047 case X86::GR64_TCRegClassID:
2048 return load ? X86::MOV64rm_TC : X86::MOV64mr_TC;
2049 case X86::GR32_TCRegClassID:
2050 return load ? X86::MOV32rm_TC : X86::MOV32mr_TC;
2051 case X86::RFP80RegClassID:
2052 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2053 case X86::RFP64RegClassID:
2054 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2055 case X86::RFP32RegClassID:
2056 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2057 case X86::FR32RegClassID:
2058 return load ? X86::MOVSSrm : X86::MOVSSmr;
2059 case X86::FR64RegClassID:
2060 return load ? X86::MOVSDrm : X86::MOVSDmr;
2061 case X86::VR128RegClassID:
2062 // If stack is realigned we can use aligned stores.
2064 return load ? X86::MOVAPSrm : X86::MOVAPSmr;
2066 return load ? X86::MOVUPSrm : X86::MOVUPSmr;
2067 case X86::VR64RegClassID:
2068 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2072 static unsigned getStoreRegOpcode(unsigned SrcReg,
2073 const TargetRegisterClass *RC,
2074 bool isStackAligned,
2075 TargetMachine &TM) {
2076 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2080 static unsigned getLoadRegOpcode(unsigned DestReg,
2081 const TargetRegisterClass *RC,
2082 bool isStackAligned,
2083 const TargetMachine &TM) {
2084 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2087 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2088 MachineBasicBlock::iterator MI,
2089 unsigned SrcReg, bool isKill, int FrameIdx,
2090 const TargetRegisterClass *RC,
2091 const TargetRegisterInfo *TRI) const {
2092 const MachineFunction &MF = *MBB.getParent();
2093 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2094 "Stack slot too small for store");
2095 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2096 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2097 DebugLoc DL = MBB.findDebugLoc(MI);
2098 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2099 .addReg(SrcReg, getKillRegState(isKill));
2102 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2104 SmallVectorImpl<MachineOperand> &Addr,
2105 const TargetRegisterClass *RC,
2106 MachineInstr::mmo_iterator MMOBegin,
2107 MachineInstr::mmo_iterator MMOEnd,
2108 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2109 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2110 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2112 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2113 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2114 MIB.addOperand(Addr[i]);
2115 MIB.addReg(SrcReg, getKillRegState(isKill));
2116 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2117 NewMIs.push_back(MIB);
2121 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2122 MachineBasicBlock::iterator MI,
2123 unsigned DestReg, int FrameIdx,
2124 const TargetRegisterClass *RC,
2125 const TargetRegisterInfo *TRI) const {
2126 const MachineFunction &MF = *MBB.getParent();
2127 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2128 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2129 DebugLoc DL = MBB.findDebugLoc(MI);
2130 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2133 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2134 SmallVectorImpl<MachineOperand> &Addr,
2135 const TargetRegisterClass *RC,
2136 MachineInstr::mmo_iterator MMOBegin,
2137 MachineInstr::mmo_iterator MMOEnd,
2138 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2139 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2140 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2142 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2143 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2144 MIB.addOperand(Addr[i]);
2145 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2146 NewMIs.push_back(MIB);
2149 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2150 MachineBasicBlock::iterator MI,
2151 const std::vector<CalleeSavedInfo> &CSI,
2152 const TargetRegisterInfo *TRI) const {
2156 DebugLoc DL = MBB.findDebugLoc(MI);
2158 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2159 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2160 unsigned SlotSize = is64Bit ? 8 : 4;
2162 MachineFunction &MF = *MBB.getParent();
2163 unsigned FPReg = RI.getFrameRegister(MF);
2164 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2165 unsigned CalleeFrameSize = 0;
2167 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2168 for (unsigned i = CSI.size(); i != 0; --i) {
2169 unsigned Reg = CSI[i-1].getReg();
2170 // Add the callee-saved register as live-in. It's killed at the spill.
2173 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2175 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2176 CalleeFrameSize += SlotSize;
2177 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2179 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2180 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
2185 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2189 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2190 MachineBasicBlock::iterator MI,
2191 const std::vector<CalleeSavedInfo> &CSI,
2192 const TargetRegisterInfo *TRI) const {
2196 DebugLoc DL = MBB.findDebugLoc(MI);
2198 MachineFunction &MF = *MBB.getParent();
2199 unsigned FPReg = RI.getFrameRegister(MF);
2200 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2201 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2202 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2203 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2204 unsigned Reg = CSI[i].getReg();
2206 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2208 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2209 BuildMI(MBB, MI, DL, get(Opc), Reg);
2211 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2212 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
2220 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2221 int FrameIx, uint64_t Offset,
2222 const MDNode *MDPtr,
2223 DebugLoc DL) const {
2225 AM.BaseType = X86AddressMode::FrameIndexBase;
2226 AM.Base.FrameIndex = FrameIx;
2227 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2228 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2232 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2233 const SmallVectorImpl<MachineOperand> &MOs,
2235 const TargetInstrInfo &TII) {
2236 // Create the base instruction with the memory operand as the first part.
2237 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2238 MI->getDebugLoc(), true);
2239 MachineInstrBuilder MIB(NewMI);
2240 unsigned NumAddrOps = MOs.size();
2241 for (unsigned i = 0; i != NumAddrOps; ++i)
2242 MIB.addOperand(MOs[i]);
2243 if (NumAddrOps < 4) // FrameIndex only
2246 // Loop over the rest of the ri operands, converting them over.
2247 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2248 for (unsigned i = 0; i != NumOps; ++i) {
2249 MachineOperand &MO = MI->getOperand(i+2);
2252 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2253 MachineOperand &MO = MI->getOperand(i);
2259 static MachineInstr *FuseInst(MachineFunction &MF,
2260 unsigned Opcode, unsigned OpNo,
2261 const SmallVectorImpl<MachineOperand> &MOs,
2262 MachineInstr *MI, const TargetInstrInfo &TII) {
2263 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2264 MI->getDebugLoc(), true);
2265 MachineInstrBuilder MIB(NewMI);
2267 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2268 MachineOperand &MO = MI->getOperand(i);
2270 assert(MO.isReg() && "Expected to fold into reg operand!");
2271 unsigned NumAddrOps = MOs.size();
2272 for (unsigned i = 0; i != NumAddrOps; ++i)
2273 MIB.addOperand(MOs[i]);
2274 if (NumAddrOps < 4) // FrameIndex only
2283 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2284 const SmallVectorImpl<MachineOperand> &MOs,
2286 MachineFunction &MF = *MI->getParent()->getParent();
2287 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2289 unsigned NumAddrOps = MOs.size();
2290 for (unsigned i = 0; i != NumAddrOps; ++i)
2291 MIB.addOperand(MOs[i]);
2292 if (NumAddrOps < 4) // FrameIndex only
2294 return MIB.addImm(0);
2298 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2299 MachineInstr *MI, unsigned i,
2300 const SmallVectorImpl<MachineOperand> &MOs,
2301 unsigned Size, unsigned Align) const {
2302 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2303 bool isTwoAddrFold = false;
2304 unsigned NumOps = MI->getDesc().getNumOperands();
2305 bool isTwoAddr = NumOps > 1 &&
2306 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2308 MachineInstr *NewMI = NULL;
2309 // Folding a memory location into the two-address part of a two-address
2310 // instruction is different than folding it other places. It requires
2311 // replacing the *two* registers with the memory location.
2312 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2313 MI->getOperand(0).isReg() &&
2314 MI->getOperand(1).isReg() &&
2315 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2316 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2317 isTwoAddrFold = true;
2318 } else if (i == 0) { // If operand 0
2319 if (MI->getOpcode() == X86::MOV64r0)
2320 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2321 else if (MI->getOpcode() == X86::MOV32r0)
2322 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2323 else if (MI->getOpcode() == X86::MOV16r0)
2324 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2325 else if (MI->getOpcode() == X86::MOV8r0)
2326 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2330 OpcodeTablePtr = &RegOp2MemOpTable0;
2331 } else if (i == 1) {
2332 OpcodeTablePtr = &RegOp2MemOpTable1;
2333 } else if (i == 2) {
2334 OpcodeTablePtr = &RegOp2MemOpTable2;
2337 // If table selected...
2338 if (OpcodeTablePtr) {
2339 // Find the Opcode to fuse
2340 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2341 OpcodeTablePtr->find(MI->getOpcode());
2342 if (I != OpcodeTablePtr->end()) {
2343 unsigned Opcode = I->second.first;
2344 unsigned MinAlign = I->second.second;
2345 if (Align < MinAlign)
2347 bool NarrowToMOV32rm = false;
2349 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2350 if (Size < RCSize) {
2351 // Check if it's safe to fold the load. If the size of the object is
2352 // narrower than the load width, then it's not.
2353 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2355 // If this is a 64-bit load, but the spill slot is 32, then we can do
2356 // a 32-bit load which is implicitly zero-extended. This likely is due
2357 // to liveintervalanalysis remat'ing a load from stack slot.
2358 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2360 Opcode = X86::MOV32rm;
2361 NarrowToMOV32rm = true;
2366 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2368 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2370 if (NarrowToMOV32rm) {
2371 // If this is the special case where we use a MOV32rm to load a 32-bit
2372 // value and zero-extend the top bits. Change the destination register
2374 unsigned DstReg = NewMI->getOperand(0).getReg();
2375 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2376 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2379 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2386 if (PrintFailedFusing && !MI->isCopy())
2387 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2392 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2394 const SmallVectorImpl<unsigned> &Ops,
2395 int FrameIndex) const {
2396 // Check switch flag
2397 if (NoFusing) return NULL;
2399 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2400 switch (MI->getOpcode()) {
2401 case X86::CVTSD2SSrr:
2402 case X86::Int_CVTSD2SSrr:
2403 case X86::CVTSS2SDrr:
2404 case X86::Int_CVTSS2SDrr:
2406 case X86::RCPSSr_Int:
2410 case X86::RSQRTSSr_Int:
2412 case X86::SQRTSSr_Int:
2416 const MachineFrameInfo *MFI = MF.getFrameInfo();
2417 unsigned Size = MFI->getObjectSize(FrameIndex);
2418 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2419 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2420 unsigned NewOpc = 0;
2421 unsigned RCSize = 0;
2422 switch (MI->getOpcode()) {
2423 default: return NULL;
2424 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2425 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2426 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2427 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2429 // Check if it's safe to fold the load. If the size of the object is
2430 // narrower than the load width, then it's not.
2433 // Change to CMPXXri r, 0 first.
2434 MI->setDesc(get(NewOpc));
2435 MI->getOperand(1).ChangeToImmediate(0);
2436 } else if (Ops.size() != 1)
2439 SmallVector<MachineOperand,4> MOs;
2440 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2441 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2444 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2446 const SmallVectorImpl<unsigned> &Ops,
2447 MachineInstr *LoadMI) const {
2448 // Check switch flag
2449 if (NoFusing) return NULL;
2451 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2452 switch (MI->getOpcode()) {
2453 case X86::CVTSD2SSrr:
2454 case X86::Int_CVTSD2SSrr:
2455 case X86::CVTSS2SDrr:
2456 case X86::Int_CVTSS2SDrr:
2458 case X86::RCPSSr_Int:
2462 case X86::RSQRTSSr_Int:
2464 case X86::SQRTSSr_Int:
2468 // Determine the alignment of the load.
2469 unsigned Alignment = 0;
2470 if (LoadMI->hasOneMemOperand())
2471 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2473 switch (LoadMI->getOpcode()) {
2474 case X86::AVX_SET0PSY:
2475 case X86::AVX_SET0PDY:
2481 case X86::V_SETALLONES:
2482 case X86::AVX_SET0PS:
2483 case X86::AVX_SET0PD:
2484 case X86::AVX_SET0PI:
2494 llvm_unreachable("Don't know how to fold this instruction!");
2496 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2497 unsigned NewOpc = 0;
2498 switch (MI->getOpcode()) {
2499 default: return NULL;
2500 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2501 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2502 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2503 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2505 // Change to CMPXXri r, 0 first.
2506 MI->setDesc(get(NewOpc));
2507 MI->getOperand(1).ChangeToImmediate(0);
2508 } else if (Ops.size() != 1)
2511 // Make sure the subregisters match.
2512 // Otherwise we risk changing the size of the load.
2513 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2516 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2517 switch (LoadMI->getOpcode()) {
2521 case X86::V_SETALLONES:
2522 case X86::AVX_SET0PS:
2523 case X86::AVX_SET0PD:
2524 case X86::AVX_SET0PI:
2525 case X86::AVX_SET0PSY:
2526 case X86::AVX_SET0PDY:
2528 case X86::FsFLD0SS: {
2529 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2530 // Create a constant-pool entry and operands to load from it.
2532 // Medium and large mode can't fold loads this way.
2533 if (TM.getCodeModel() != CodeModel::Small &&
2534 TM.getCodeModel() != CodeModel::Kernel)
2537 // x86-32 PIC requires a PIC base register for constant pools.
2538 unsigned PICBase = 0;
2539 if (TM.getRelocationModel() == Reloc::PIC_) {
2540 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2543 // FIXME: PICBase = getGlobalBaseReg(&MF);
2544 // This doesn't work for several reasons.
2545 // 1. GlobalBaseReg may have been spilled.
2546 // 2. It may not be live at MI.
2550 // Create a constant-pool entry.
2551 MachineConstantPool &MCP = *MF.getConstantPool();
2553 unsigned Opc = LoadMI->getOpcode();
2554 if (Opc == X86::FsFLD0SS)
2555 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2556 else if (Opc == X86::FsFLD0SD)
2557 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2558 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2559 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2561 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2562 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2563 Constant::getAllOnesValue(Ty) :
2564 Constant::getNullValue(Ty);
2565 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2567 // Create operands to load from the constant pool entry.
2568 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2569 MOs.push_back(MachineOperand::CreateImm(1));
2570 MOs.push_back(MachineOperand::CreateReg(0, false));
2571 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2572 MOs.push_back(MachineOperand::CreateReg(0, false));
2576 // Folding a normal load. Just copy the load's address operands.
2577 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2578 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
2579 MOs.push_back(LoadMI->getOperand(i));
2583 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2587 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2588 const SmallVectorImpl<unsigned> &Ops) const {
2589 // Check switch flag
2590 if (NoFusing) return 0;
2592 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2593 switch (MI->getOpcode()) {
2594 default: return false;
2603 if (Ops.size() != 1)
2606 unsigned OpNum = Ops[0];
2607 unsigned Opc = MI->getOpcode();
2608 unsigned NumOps = MI->getDesc().getNumOperands();
2609 bool isTwoAddr = NumOps > 1 &&
2610 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2612 // Folding a memory location into the two-address part of a two-address
2613 // instruction is different than folding it other places. It requires
2614 // replacing the *two* registers with the memory location.
2615 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2616 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2617 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2618 } else if (OpNum == 0) { // If operand 0
2623 case X86::MOV64r0: return true;
2626 OpcodeTablePtr = &RegOp2MemOpTable0;
2627 } else if (OpNum == 1) {
2628 OpcodeTablePtr = &RegOp2MemOpTable1;
2629 } else if (OpNum == 2) {
2630 OpcodeTablePtr = &RegOp2MemOpTable2;
2633 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
2635 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
2638 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2639 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2640 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2641 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2642 MemOp2RegOpTable.find(MI->getOpcode());
2643 if (I == MemOp2RegOpTable.end())
2645 unsigned Opc = I->second.first;
2646 unsigned Index = I->second.second & 0xf;
2647 bool FoldedLoad = I->second.second & (1 << 4);
2648 bool FoldedStore = I->second.second & (1 << 5);
2649 if (UnfoldLoad && !FoldedLoad)
2651 UnfoldLoad &= FoldedLoad;
2652 if (UnfoldStore && !FoldedStore)
2654 UnfoldStore &= FoldedStore;
2656 const TargetInstrDesc &TID = get(Opc);
2657 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2658 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2659 if (!MI->hasOneMemOperand() &&
2660 RC == &X86::VR128RegClass &&
2661 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2662 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2663 // conservatively assume the address is unaligned. That's bad for
2666 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
2667 SmallVector<MachineOperand,2> BeforeOps;
2668 SmallVector<MachineOperand,2> AfterOps;
2669 SmallVector<MachineOperand,4> ImpOps;
2670 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2671 MachineOperand &Op = MI->getOperand(i);
2672 if (i >= Index && i < Index + X86::AddrNumOperands)
2673 AddrOps.push_back(Op);
2674 else if (Op.isReg() && Op.isImplicit())
2675 ImpOps.push_back(Op);
2677 BeforeOps.push_back(Op);
2679 AfterOps.push_back(Op);
2682 // Emit the load instruction.
2684 std::pair<MachineInstr::mmo_iterator,
2685 MachineInstr::mmo_iterator> MMOs =
2686 MF.extractLoadMemRefs(MI->memoperands_begin(),
2687 MI->memoperands_end());
2688 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2690 // Address operands cannot be marked isKill.
2691 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
2692 MachineOperand &MO = NewMIs[0]->getOperand(i);
2694 MO.setIsKill(false);
2699 // Emit the data processing instruction.
2700 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2701 MachineInstrBuilder MIB(DataMI);
2704 MIB.addReg(Reg, RegState::Define);
2705 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2706 MIB.addOperand(BeforeOps[i]);
2709 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2710 MIB.addOperand(AfterOps[i]);
2711 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2712 MachineOperand &MO = ImpOps[i];
2713 MIB.addReg(MO.getReg(),
2714 getDefRegState(MO.isDef()) |
2715 RegState::Implicit |
2716 getKillRegState(MO.isKill()) |
2717 getDeadRegState(MO.isDead()) |
2718 getUndefRegState(MO.isUndef()));
2720 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2721 unsigned NewOpc = 0;
2722 switch (DataMI->getOpcode()) {
2724 case X86::CMP64ri32:
2731 MachineOperand &MO0 = DataMI->getOperand(0);
2732 MachineOperand &MO1 = DataMI->getOperand(1);
2733 if (MO1.getImm() == 0) {
2734 switch (DataMI->getOpcode()) {
2737 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2739 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2741 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2742 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2744 DataMI->setDesc(get(NewOpc));
2745 MO1.ChangeToRegister(MO0.getReg(), false);
2749 NewMIs.push_back(DataMI);
2751 // Emit the store instruction.
2753 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2754 std::pair<MachineInstr::mmo_iterator,
2755 MachineInstr::mmo_iterator> MMOs =
2756 MF.extractStoreMemRefs(MI->memoperands_begin(),
2757 MI->memoperands_end());
2758 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2765 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2766 SmallVectorImpl<SDNode*> &NewNodes) const {
2767 if (!N->isMachineOpcode())
2770 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2771 MemOp2RegOpTable.find(N->getMachineOpcode());
2772 if (I == MemOp2RegOpTable.end())
2774 unsigned Opc = I->second.first;
2775 unsigned Index = I->second.second & 0xf;
2776 bool FoldedLoad = I->second.second & (1 << 4);
2777 bool FoldedStore = I->second.second & (1 << 5);
2778 const TargetInstrDesc &TID = get(Opc);
2779 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2780 unsigned NumDefs = TID.NumDefs;
2781 std::vector<SDValue> AddrOps;
2782 std::vector<SDValue> BeforeOps;
2783 std::vector<SDValue> AfterOps;
2784 DebugLoc dl = N->getDebugLoc();
2785 unsigned NumOps = N->getNumOperands();
2786 for (unsigned i = 0; i != NumOps-1; ++i) {
2787 SDValue Op = N->getOperand(i);
2788 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
2789 AddrOps.push_back(Op);
2790 else if (i < Index-NumDefs)
2791 BeforeOps.push_back(Op);
2792 else if (i > Index-NumDefs)
2793 AfterOps.push_back(Op);
2795 SDValue Chain = N->getOperand(NumOps-1);
2796 AddrOps.push_back(Chain);
2798 // Emit the load instruction.
2800 MachineFunction &MF = DAG.getMachineFunction();
2802 EVT VT = *RC->vt_begin();
2803 std::pair<MachineInstr::mmo_iterator,
2804 MachineInstr::mmo_iterator> MMOs =
2805 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2806 cast<MachineSDNode>(N)->memoperands_end());
2807 if (!(*MMOs.first) &&
2808 RC == &X86::VR128RegClass &&
2809 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2810 // Do not introduce a slow unaligned load.
2812 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2813 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2814 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2815 NewNodes.push_back(Load);
2817 // Preserve memory reference information.
2818 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2821 // Emit the data processing instruction.
2822 std::vector<EVT> VTs;
2823 const TargetRegisterClass *DstRC = 0;
2824 if (TID.getNumDefs() > 0) {
2825 DstRC = TID.OpInfo[0].getRegClass(&RI);
2826 VTs.push_back(*DstRC->vt_begin());
2828 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2829 EVT VT = N->getValueType(i);
2830 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2834 BeforeOps.push_back(SDValue(Load, 0));
2835 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2836 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2838 NewNodes.push_back(NewNode);
2840 // Emit the store instruction.
2843 AddrOps.push_back(SDValue(NewNode, 0));
2844 AddrOps.push_back(Chain);
2845 std::pair<MachineInstr::mmo_iterator,
2846 MachineInstr::mmo_iterator> MMOs =
2847 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2848 cast<MachineSDNode>(N)->memoperands_end());
2849 if (!(*MMOs.first) &&
2850 RC == &X86::VR128RegClass &&
2851 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2852 // Do not introduce a slow unaligned store.
2854 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2855 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2858 &AddrOps[0], AddrOps.size());
2859 NewNodes.push_back(Store);
2861 // Preserve memory reference information.
2862 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2868 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2869 bool UnfoldLoad, bool UnfoldStore,
2870 unsigned *LoadRegIndex) const {
2871 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2872 MemOp2RegOpTable.find(Opc);
2873 if (I == MemOp2RegOpTable.end())
2875 bool FoldedLoad = I->second.second & (1 << 4);
2876 bool FoldedStore = I->second.second & (1 << 5);
2877 if (UnfoldLoad && !FoldedLoad)
2879 if (UnfoldStore && !FoldedStore)
2882 *LoadRegIndex = I->second.second & 0xf;
2883 return I->second.first;
2887 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2888 int64_t &Offset1, int64_t &Offset2) const {
2889 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2891 unsigned Opc1 = Load1->getMachineOpcode();
2892 unsigned Opc2 = Load2->getMachineOpcode();
2894 default: return false;
2904 case X86::MMX_MOVD64rm:
2905 case X86::MMX_MOVQ64rm:
2906 case X86::FsMOVAPSrm:
2907 case X86::FsMOVAPDrm:
2910 case X86::MOVUPSrm_Int:
2914 case X86::MOVDQUrm_Int:
2918 default: return false;
2928 case X86::MMX_MOVD64rm:
2929 case X86::MMX_MOVQ64rm:
2930 case X86::FsMOVAPSrm:
2931 case X86::FsMOVAPDrm:
2934 case X86::MOVUPSrm_Int:
2938 case X86::MOVDQUrm_Int:
2942 // Check if chain operands and base addresses match.
2943 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2944 Load1->getOperand(5) != Load2->getOperand(5))
2946 // Segment operands should match as well.
2947 if (Load1->getOperand(4) != Load2->getOperand(4))
2949 // Scale should be 1, Index should be Reg0.
2950 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2951 Load1->getOperand(2) == Load2->getOperand(2)) {
2952 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2955 // Now let's examine the displacements.
2956 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2957 isa<ConstantSDNode>(Load2->getOperand(3))) {
2958 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2959 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2966 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2967 int64_t Offset1, int64_t Offset2,
2968 unsigned NumLoads) const {
2969 assert(Offset2 > Offset1);
2970 if ((Offset2 - Offset1) / 8 > 64)
2973 unsigned Opc1 = Load1->getMachineOpcode();
2974 unsigned Opc2 = Load2->getMachineOpcode();
2976 return false; // FIXME: overly conservative?
2983 case X86::MMX_MOVD64rm:
2984 case X86::MMX_MOVQ64rm:
2988 EVT VT = Load1->getValueType(0);
2989 switch (VT.getSimpleVT().SimpleTy) {
2991 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
2992 // have 16 of them to play with.
2993 if (TM.getSubtargetImpl()->is64Bit()) {
2996 } else if (NumLoads) {
3016 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3017 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3018 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3019 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3021 Cond[0].setImm(GetOppositeBranchCondition(CC));
3026 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3027 // FIXME: Return false for x87 stack register classes for now. We can't
3028 // allow any loads of these registers before FpGet_ST0_80.
3029 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3030 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3034 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3035 /// register? e.g. r8, xmm8, xmm13, etc.
3036 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3039 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3040 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3041 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3042 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3043 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3044 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3045 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3046 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3047 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3048 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3049 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
3050 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
3051 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
3052 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
3058 /// getGlobalBaseReg - Return a virtual register initialized with the
3059 /// the global base register value. Output instructions required to
3060 /// initialize the register in the function entry block, if necessary.
3062 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3064 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3065 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3066 "X86-64 PIC uses RIP relative addressing");
3068 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3069 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3070 if (GlobalBaseReg != 0)
3071 return GlobalBaseReg;
3073 // Create the register. The code to initialize it is inserted
3074 // later, by the CGBR pass (below).
3075 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3076 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3077 X86FI->setGlobalBaseReg(GlobalBaseReg);
3078 return GlobalBaseReg;
3081 // These are the replaceable SSE instructions. Some of these have Int variants
3082 // that we don't include here. We don't want to replace instructions selected
3084 static const unsigned ReplaceableInstrs[][3] = {
3085 //PackedSingle PackedDouble PackedInt
3086 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3087 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3088 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3089 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3090 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3091 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3092 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3093 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3094 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3095 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3096 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3097 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3098 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3099 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3100 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3101 // AVX 128-bit support
3102 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3103 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3104 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3105 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3106 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3107 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3108 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3109 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3110 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3111 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3112 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3113 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3114 { X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
3115 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3116 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3119 // FIXME: Some shuffle and unpack instructions have equivalents in different
3120 // domains, but they require a bit more work than just switching opcodes.
3122 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3123 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3124 if (ReplaceableInstrs[i][domain-1] == opcode)
3125 return ReplaceableInstrs[i];
3129 std::pair<uint16_t, uint16_t>
3130 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3131 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3132 return std::make_pair(domain,
3133 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3136 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3137 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3138 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3139 assert(dom && "Not an SSE instruction");
3140 const unsigned *table = lookup(MI->getOpcode(), dom);
3141 assert(table && "Cannot change domain");
3142 MI->setDesc(get(table[Domain-1]));
3145 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3146 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3147 NopInst.setOpcode(X86::NOOP);
3151 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3152 /// global base register for x86-32.
3153 struct CGBR : public MachineFunctionPass {
3155 CGBR() : MachineFunctionPass(ID) {}
3157 virtual bool runOnMachineFunction(MachineFunction &MF) {
3158 const X86TargetMachine *TM =
3159 static_cast<const X86TargetMachine *>(&MF.getTarget());
3161 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3162 "X86-64 PIC uses RIP relative addressing");
3164 // Only emit a global base reg in PIC mode.
3165 if (TM->getRelocationModel() != Reloc::PIC_)
3168 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3169 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3171 // If we didn't need a GlobalBaseReg, don't insert code.
3172 if (GlobalBaseReg == 0)
3175 // Insert the set of GlobalBaseReg into the first MBB of the function
3176 MachineBasicBlock &FirstMBB = MF.front();
3177 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3178 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3179 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3180 const X86InstrInfo *TII = TM->getInstrInfo();
3183 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3184 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3188 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3189 // only used in JIT code emission as displacement to pc.
3190 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3192 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3193 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3194 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3195 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3196 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3197 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3198 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3204 virtual const char *getPassName() const {
3205 return "X86 PIC Global Base Reg Initialization";
3208 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3209 AU.setPreservesCFG();
3210 MachineFunctionPass::getAnalysisUsage(AU);
3217 llvm::createGlobalBaseRegPass() { return new CGBR(); }