1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/MC/MCAsmInfo.h"
41 NoFusing("disable-spill-fusing",
42 cl::desc("Disable fusing of spill code into instructions"));
44 PrintFailedFusing("print-failed-fuse-candidates",
45 cl::desc("Print instructions that the allocator wants to"
46 " fuse, but the X86 backend currently can't"),
49 ReMatPICStubLoad("remat-pic-stub-load",
50 cl::desc("Re-materialize load from stub in PIC mode"),
51 cl::init(false), cl::Hidden);
53 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
54 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
55 TM(tm), RI(tm, *this) {
56 SmallVector<unsigned,16> AmbEntries;
57 static const unsigned OpTbl2Addr[][2] = {
58 { X86::ADC32ri, X86::ADC32mi },
59 { X86::ADC32ri8, X86::ADC32mi8 },
60 { X86::ADC32rr, X86::ADC32mr },
61 { X86::ADC64ri32, X86::ADC64mi32 },
62 { X86::ADC64ri8, X86::ADC64mi8 },
63 { X86::ADC64rr, X86::ADC64mr },
64 { X86::ADD16ri, X86::ADD16mi },
65 { X86::ADD16ri8, X86::ADD16mi8 },
66 { X86::ADD16rr, X86::ADD16mr },
67 { X86::ADD32ri, X86::ADD32mi },
68 { X86::ADD32ri8, X86::ADD32mi8 },
69 { X86::ADD32rr, X86::ADD32mr },
70 { X86::ADD64ri32, X86::ADD64mi32 },
71 { X86::ADD64ri8, X86::ADD64mi8 },
72 { X86::ADD64rr, X86::ADD64mr },
73 { X86::ADD8ri, X86::ADD8mi },
74 { X86::ADD8rr, X86::ADD8mr },
75 { X86::AND16ri, X86::AND16mi },
76 { X86::AND16ri8, X86::AND16mi8 },
77 { X86::AND16rr, X86::AND16mr },
78 { X86::AND32ri, X86::AND32mi },
79 { X86::AND32ri8, X86::AND32mi8 },
80 { X86::AND32rr, X86::AND32mr },
81 { X86::AND64ri32, X86::AND64mi32 },
82 { X86::AND64ri8, X86::AND64mi8 },
83 { X86::AND64rr, X86::AND64mr },
84 { X86::AND8ri, X86::AND8mi },
85 { X86::AND8rr, X86::AND8mr },
86 { X86::DEC16r, X86::DEC16m },
87 { X86::DEC32r, X86::DEC32m },
88 { X86::DEC64_16r, X86::DEC64_16m },
89 { X86::DEC64_32r, X86::DEC64_32m },
90 { X86::DEC64r, X86::DEC64m },
91 { X86::DEC8r, X86::DEC8m },
92 { X86::INC16r, X86::INC16m },
93 { X86::INC32r, X86::INC32m },
94 { X86::INC64_16r, X86::INC64_16m },
95 { X86::INC64_32r, X86::INC64_32m },
96 { X86::INC64r, X86::INC64m },
97 { X86::INC8r, X86::INC8m },
98 { X86::NEG16r, X86::NEG16m },
99 { X86::NEG32r, X86::NEG32m },
100 { X86::NEG64r, X86::NEG64m },
101 { X86::NEG8r, X86::NEG8m },
102 { X86::NOT16r, X86::NOT16m },
103 { X86::NOT32r, X86::NOT32m },
104 { X86::NOT64r, X86::NOT64m },
105 { X86::NOT8r, X86::NOT8m },
106 { X86::OR16ri, X86::OR16mi },
107 { X86::OR16ri8, X86::OR16mi8 },
108 { X86::OR16rr, X86::OR16mr },
109 { X86::OR32ri, X86::OR32mi },
110 { X86::OR32ri8, X86::OR32mi8 },
111 { X86::OR32rr, X86::OR32mr },
112 { X86::OR64ri32, X86::OR64mi32 },
113 { X86::OR64ri8, X86::OR64mi8 },
114 { X86::OR64rr, X86::OR64mr },
115 { X86::OR8ri, X86::OR8mi },
116 { X86::OR8rr, X86::OR8mr },
117 { X86::ROL16r1, X86::ROL16m1 },
118 { X86::ROL16rCL, X86::ROL16mCL },
119 { X86::ROL16ri, X86::ROL16mi },
120 { X86::ROL32r1, X86::ROL32m1 },
121 { X86::ROL32rCL, X86::ROL32mCL },
122 { X86::ROL32ri, X86::ROL32mi },
123 { X86::ROL64r1, X86::ROL64m1 },
124 { X86::ROL64rCL, X86::ROL64mCL },
125 { X86::ROL64ri, X86::ROL64mi },
126 { X86::ROL8r1, X86::ROL8m1 },
127 { X86::ROL8rCL, X86::ROL8mCL },
128 { X86::ROL8ri, X86::ROL8mi },
129 { X86::ROR16r1, X86::ROR16m1 },
130 { X86::ROR16rCL, X86::ROR16mCL },
131 { X86::ROR16ri, X86::ROR16mi },
132 { X86::ROR32r1, X86::ROR32m1 },
133 { X86::ROR32rCL, X86::ROR32mCL },
134 { X86::ROR32ri, X86::ROR32mi },
135 { X86::ROR64r1, X86::ROR64m1 },
136 { X86::ROR64rCL, X86::ROR64mCL },
137 { X86::ROR64ri, X86::ROR64mi },
138 { X86::ROR8r1, X86::ROR8m1 },
139 { X86::ROR8rCL, X86::ROR8mCL },
140 { X86::ROR8ri, X86::ROR8mi },
141 { X86::SAR16r1, X86::SAR16m1 },
142 { X86::SAR16rCL, X86::SAR16mCL },
143 { X86::SAR16ri, X86::SAR16mi },
144 { X86::SAR32r1, X86::SAR32m1 },
145 { X86::SAR32rCL, X86::SAR32mCL },
146 { X86::SAR32ri, X86::SAR32mi },
147 { X86::SAR64r1, X86::SAR64m1 },
148 { X86::SAR64rCL, X86::SAR64mCL },
149 { X86::SAR64ri, X86::SAR64mi },
150 { X86::SAR8r1, X86::SAR8m1 },
151 { X86::SAR8rCL, X86::SAR8mCL },
152 { X86::SAR8ri, X86::SAR8mi },
153 { X86::SBB32ri, X86::SBB32mi },
154 { X86::SBB32ri8, X86::SBB32mi8 },
155 { X86::SBB32rr, X86::SBB32mr },
156 { X86::SBB64ri32, X86::SBB64mi32 },
157 { X86::SBB64ri8, X86::SBB64mi8 },
158 { X86::SBB64rr, X86::SBB64mr },
159 { X86::SHL16rCL, X86::SHL16mCL },
160 { X86::SHL16ri, X86::SHL16mi },
161 { X86::SHL32rCL, X86::SHL32mCL },
162 { X86::SHL32ri, X86::SHL32mi },
163 { X86::SHL64rCL, X86::SHL64mCL },
164 { X86::SHL64ri, X86::SHL64mi },
165 { X86::SHL8rCL, X86::SHL8mCL },
166 { X86::SHL8ri, X86::SHL8mi },
167 { X86::SHLD16rrCL, X86::SHLD16mrCL },
168 { X86::SHLD16rri8, X86::SHLD16mri8 },
169 { X86::SHLD32rrCL, X86::SHLD32mrCL },
170 { X86::SHLD32rri8, X86::SHLD32mri8 },
171 { X86::SHLD64rrCL, X86::SHLD64mrCL },
172 { X86::SHLD64rri8, X86::SHLD64mri8 },
173 { X86::SHR16r1, X86::SHR16m1 },
174 { X86::SHR16rCL, X86::SHR16mCL },
175 { X86::SHR16ri, X86::SHR16mi },
176 { X86::SHR32r1, X86::SHR32m1 },
177 { X86::SHR32rCL, X86::SHR32mCL },
178 { X86::SHR32ri, X86::SHR32mi },
179 { X86::SHR64r1, X86::SHR64m1 },
180 { X86::SHR64rCL, X86::SHR64mCL },
181 { X86::SHR64ri, X86::SHR64mi },
182 { X86::SHR8r1, X86::SHR8m1 },
183 { X86::SHR8rCL, X86::SHR8mCL },
184 { X86::SHR8ri, X86::SHR8mi },
185 { X86::SHRD16rrCL, X86::SHRD16mrCL },
186 { X86::SHRD16rri8, X86::SHRD16mri8 },
187 { X86::SHRD32rrCL, X86::SHRD32mrCL },
188 { X86::SHRD32rri8, X86::SHRD32mri8 },
189 { X86::SHRD64rrCL, X86::SHRD64mrCL },
190 { X86::SHRD64rri8, X86::SHRD64mri8 },
191 { X86::SUB16ri, X86::SUB16mi },
192 { X86::SUB16ri8, X86::SUB16mi8 },
193 { X86::SUB16rr, X86::SUB16mr },
194 { X86::SUB32ri, X86::SUB32mi },
195 { X86::SUB32ri8, X86::SUB32mi8 },
196 { X86::SUB32rr, X86::SUB32mr },
197 { X86::SUB64ri32, X86::SUB64mi32 },
198 { X86::SUB64ri8, X86::SUB64mi8 },
199 { X86::SUB64rr, X86::SUB64mr },
200 { X86::SUB8ri, X86::SUB8mi },
201 { X86::SUB8rr, X86::SUB8mr },
202 { X86::XOR16ri, X86::XOR16mi },
203 { X86::XOR16ri8, X86::XOR16mi8 },
204 { X86::XOR16rr, X86::XOR16mr },
205 { X86::XOR32ri, X86::XOR32mi },
206 { X86::XOR32ri8, X86::XOR32mi8 },
207 { X86::XOR32rr, X86::XOR32mr },
208 { X86::XOR64ri32, X86::XOR64mi32 },
209 { X86::XOR64ri8, X86::XOR64mi8 },
210 { X86::XOR64rr, X86::XOR64mr },
211 { X86::XOR8ri, X86::XOR8mi },
212 { X86::XOR8rr, X86::XOR8mr }
215 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
216 unsigned RegOp = OpTbl2Addr[i][0];
217 unsigned MemOp = OpTbl2Addr[i][1];
218 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
219 std::make_pair(MemOp,0))).second)
220 assert(false && "Duplicated entries?");
221 // Index 0, folded load and store, no alignment requirement.
222 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
223 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
224 std::make_pair(RegOp,
226 AmbEntries.push_back(MemOp);
229 // If the third value is 1, then it's folding either a load or a store.
230 static const unsigned OpTbl0[][4] = {
231 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
232 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
233 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
234 { X86::CALL32r, X86::CALL32m, 1, 0 },
235 { X86::CALL64r, X86::CALL64m, 1, 0 },
236 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
237 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
238 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
239 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
240 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
241 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
242 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
243 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
244 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
245 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
246 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
247 { X86::DIV16r, X86::DIV16m, 1, 0 },
248 { X86::DIV32r, X86::DIV32m, 1, 0 },
249 { X86::DIV64r, X86::DIV64m, 1, 0 },
250 { X86::DIV8r, X86::DIV8m, 1, 0 },
251 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
252 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
253 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
254 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
255 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
256 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
257 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
258 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
259 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
260 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
261 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
262 { X86::JMP32r, X86::JMP32m, 1, 0 },
263 { X86::JMP64r, X86::JMP64m, 1, 0 },
264 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
265 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
266 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
267 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
268 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
269 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
270 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
271 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
272 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
273 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
274 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
275 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
276 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
277 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
278 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 },
279 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 },
280 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
281 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
282 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 },
283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
285 { X86::MUL16r, X86::MUL16m, 1, 0 },
286 { X86::MUL32r, X86::MUL32m, 1, 0 },
287 { X86::MUL64r, X86::MUL64m, 1, 0 },
288 { X86::MUL8r, X86::MUL8m, 1, 0 },
289 { X86::SETAEr, X86::SETAEm, 0, 0 },
290 { X86::SETAr, X86::SETAm, 0, 0 },
291 { X86::SETBEr, X86::SETBEm, 0, 0 },
292 { X86::SETBr, X86::SETBm, 0, 0 },
293 { X86::SETEr, X86::SETEm, 0, 0 },
294 { X86::SETGEr, X86::SETGEm, 0, 0 },
295 { X86::SETGr, X86::SETGm, 0, 0 },
296 { X86::SETLEr, X86::SETLEm, 0, 0 },
297 { X86::SETLr, X86::SETLm, 0, 0 },
298 { X86::SETNEr, X86::SETNEm, 0, 0 },
299 { X86::SETNOr, X86::SETNOm, 0, 0 },
300 { X86::SETNPr, X86::SETNPm, 0, 0 },
301 { X86::SETNSr, X86::SETNSm, 0, 0 },
302 { X86::SETOr, X86::SETOm, 0, 0 },
303 { X86::SETPr, X86::SETPm, 0, 0 },
304 { X86::SETSr, X86::SETSm, 0, 0 },
305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
306 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
307 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
308 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
309 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
312 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
313 unsigned RegOp = OpTbl0[i][0];
314 unsigned MemOp = OpTbl0[i][1];
315 unsigned Align = OpTbl0[i][3];
316 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
317 std::make_pair(MemOp,Align))).second)
318 assert(false && "Duplicated entries?");
319 unsigned FoldedLoad = OpTbl0[i][2];
320 // Index 0, folded load or store.
321 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
322 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
323 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
324 std::make_pair(RegOp, AuxInfo))).second)
325 AmbEntries.push_back(MemOp);
328 static const unsigned OpTbl1[][3] = {
329 { X86::CMP16rr, X86::CMP16rm, 0 },
330 { X86::CMP32rr, X86::CMP32rm, 0 },
331 { X86::CMP64rr, X86::CMP64rm, 0 },
332 { X86::CMP8rr, X86::CMP8rm, 0 },
333 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
334 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
335 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
336 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
337 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
338 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
339 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
340 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
341 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
342 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
343 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
344 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
345 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
346 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
347 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
348 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
349 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
350 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
351 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
352 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
353 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
354 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
355 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
356 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
357 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
358 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
359 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
360 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
361 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
362 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
363 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
364 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
365 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
366 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
367 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
368 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
369 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
370 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
371 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
372 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
373 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
374 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
375 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
376 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
377 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
378 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
379 { X86::MOV16rr, X86::MOV16rm, 0 },
380 { X86::MOV32rr, X86::MOV32rm, 0 },
381 { X86::MOV64rr, X86::MOV64rm, 0 },
382 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
383 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
384 { X86::MOV8rr, X86::MOV8rm, 0 },
385 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
386 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
387 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
388 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
389 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
390 { X86::MOVDQArr, X86::MOVDQArm, 16 },
391 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 },
392 { X86::MOVSDrr, X86::MOVSDrm, 0 },
393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
395 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 },
396 { X86::MOVSSrr, X86::MOVSSrm, 0 },
397 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
398 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
399 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
400 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
401 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
402 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
403 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
404 { X86::MOVUPSrr, X86::MOVUPSrm, 16 },
405 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
406 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
407 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
408 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
409 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
410 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
411 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
412 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
413 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
414 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
415 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
416 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
417 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
418 { X86::RCPPSr, X86::RCPPSm, 16 },
419 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
420 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
421 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
422 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
423 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
424 { X86::SQRTPDr, X86::SQRTPDm, 16 },
425 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
426 { X86::SQRTPSr, X86::SQRTPSm, 16 },
427 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
428 { X86::SQRTSDr, X86::SQRTSDm, 0 },
429 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
430 { X86::SQRTSSr, X86::SQRTSSm, 0 },
431 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
432 { X86::TEST16rr, X86::TEST16rm, 0 },
433 { X86::TEST32rr, X86::TEST32rm, 0 },
434 { X86::TEST64rr, X86::TEST64rm, 0 },
435 { X86::TEST8rr, X86::TEST8rm, 0 },
436 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
437 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
438 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
441 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
442 unsigned RegOp = OpTbl1[i][0];
443 unsigned MemOp = OpTbl1[i][1];
444 unsigned Align = OpTbl1[i][2];
445 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
446 std::make_pair(MemOp,Align))).second)
447 assert(false && "Duplicated entries?");
448 // Index 1, folded load
449 unsigned AuxInfo = 1 | (1 << 4);
450 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
451 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
452 std::make_pair(RegOp, AuxInfo))).second)
453 AmbEntries.push_back(MemOp);
456 static const unsigned OpTbl2[][3] = {
457 { X86::ADC32rr, X86::ADC32rm, 0 },
458 { X86::ADC64rr, X86::ADC64rm, 0 },
459 { X86::ADD16rr, X86::ADD16rm, 0 },
460 { X86::ADD32rr, X86::ADD32rm, 0 },
461 { X86::ADD64rr, X86::ADD64rm, 0 },
462 { X86::ADD8rr, X86::ADD8rm, 0 },
463 { X86::ADDPDrr, X86::ADDPDrm, 16 },
464 { X86::ADDPSrr, X86::ADDPSrm, 16 },
465 { X86::ADDSDrr, X86::ADDSDrm, 0 },
466 { X86::ADDSSrr, X86::ADDSSrm, 0 },
467 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
468 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
469 { X86::AND16rr, X86::AND16rm, 0 },
470 { X86::AND32rr, X86::AND32rm, 0 },
471 { X86::AND64rr, X86::AND64rm, 0 },
472 { X86::AND8rr, X86::AND8rm, 0 },
473 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
474 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
475 { X86::ANDPDrr, X86::ANDPDrm, 16 },
476 { X86::ANDPSrr, X86::ANDPSrm, 16 },
477 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
478 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
479 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
480 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
481 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
482 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
483 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
484 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
485 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
486 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
487 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
488 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
489 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
490 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
491 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
492 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
493 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
494 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
495 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
496 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
497 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
498 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
499 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
500 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
501 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
502 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
503 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
504 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
505 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
506 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
507 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
508 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
509 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
510 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
511 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
512 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
513 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
514 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
515 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
516 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
517 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
518 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
519 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
520 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
521 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
522 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
523 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
524 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
525 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
526 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
527 { X86::CMPSDrr, X86::CMPSDrm, 0 },
528 { X86::CMPSSrr, X86::CMPSSrm, 0 },
529 { X86::DIVPDrr, X86::DIVPDrm, 16 },
530 { X86::DIVPSrr, X86::DIVPSrm, 16 },
531 { X86::DIVSDrr, X86::DIVSDrm, 0 },
532 { X86::DIVSSrr, X86::DIVSSrm, 0 },
533 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
534 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
535 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
536 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
537 { X86::FsORPDrr, X86::FsORPDrm, 16 },
538 { X86::FsORPSrr, X86::FsORPSrm, 16 },
539 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
540 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
541 { X86::HADDPDrr, X86::HADDPDrm, 16 },
542 { X86::HADDPSrr, X86::HADDPSrm, 16 },
543 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
544 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
545 { X86::IMUL16rr, X86::IMUL16rm, 0 },
546 { X86::IMUL32rr, X86::IMUL32rm, 0 },
547 { X86::IMUL64rr, X86::IMUL64rm, 0 },
548 { X86::MAXPDrr, X86::MAXPDrm, 16 },
549 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
550 { X86::MAXPSrr, X86::MAXPSrm, 16 },
551 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
552 { X86::MAXSDrr, X86::MAXSDrm, 0 },
553 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
554 { X86::MAXSSrr, X86::MAXSSrm, 0 },
555 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
556 { X86::MINPDrr, X86::MINPDrm, 16 },
557 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
558 { X86::MINPSrr, X86::MINPSrm, 16 },
559 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
560 { X86::MINSDrr, X86::MINSDrm, 0 },
561 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
562 { X86::MINSSrr, X86::MINSSrm, 0 },
563 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
564 { X86::MULPDrr, X86::MULPDrm, 16 },
565 { X86::MULPSrr, X86::MULPSrm, 16 },
566 { X86::MULSDrr, X86::MULSDrm, 0 },
567 { X86::MULSSrr, X86::MULSSrm, 0 },
568 { X86::OR16rr, X86::OR16rm, 0 },
569 { X86::OR32rr, X86::OR32rm, 0 },
570 { X86::OR64rr, X86::OR64rm, 0 },
571 { X86::OR8rr, X86::OR8rm, 0 },
572 { X86::ORPDrr, X86::ORPDrm, 16 },
573 { X86::ORPSrr, X86::ORPSrm, 16 },
574 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
575 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
576 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
577 { X86::PADDBrr, X86::PADDBrm, 16 },
578 { X86::PADDDrr, X86::PADDDrm, 16 },
579 { X86::PADDQrr, X86::PADDQrm, 16 },
580 { X86::PADDSBrr, X86::PADDSBrm, 16 },
581 { X86::PADDSWrr, X86::PADDSWrm, 16 },
582 { X86::PADDWrr, X86::PADDWrm, 16 },
583 { X86::PANDNrr, X86::PANDNrm, 16 },
584 { X86::PANDrr, X86::PANDrm, 16 },
585 { X86::PAVGBrr, X86::PAVGBrm, 16 },
586 { X86::PAVGWrr, X86::PAVGWrm, 16 },
587 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
588 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
589 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
590 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
591 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
592 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
593 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
594 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
595 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
596 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
597 { X86::PMINSWrr, X86::PMINSWrm, 16 },
598 { X86::PMINUBrr, X86::PMINUBrm, 16 },
599 { X86::PMULDQrr, X86::PMULDQrm, 16 },
600 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
601 { X86::PMULHWrr, X86::PMULHWrm, 16 },
602 { X86::PMULLDrr, X86::PMULLDrm, 16 },
603 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
604 { X86::PMULLWrr, X86::PMULLWrm, 16 },
605 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
606 { X86::PORrr, X86::PORrm, 16 },
607 { X86::PSADBWrr, X86::PSADBWrm, 16 },
608 { X86::PSLLDrr, X86::PSLLDrm, 16 },
609 { X86::PSLLQrr, X86::PSLLQrm, 16 },
610 { X86::PSLLWrr, X86::PSLLWrm, 16 },
611 { X86::PSRADrr, X86::PSRADrm, 16 },
612 { X86::PSRAWrr, X86::PSRAWrm, 16 },
613 { X86::PSRLDrr, X86::PSRLDrm, 16 },
614 { X86::PSRLQrr, X86::PSRLQrm, 16 },
615 { X86::PSRLWrr, X86::PSRLWrm, 16 },
616 { X86::PSUBBrr, X86::PSUBBrm, 16 },
617 { X86::PSUBDrr, X86::PSUBDrm, 16 },
618 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
619 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
620 { X86::PSUBWrr, X86::PSUBWrm, 16 },
621 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
622 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
623 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
624 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
625 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
626 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
627 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
628 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
629 { X86::PXORrr, X86::PXORrm, 16 },
630 { X86::SBB32rr, X86::SBB32rm, 0 },
631 { X86::SBB64rr, X86::SBB64rm, 0 },
632 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
633 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
634 { X86::SUB16rr, X86::SUB16rm, 0 },
635 { X86::SUB32rr, X86::SUB32rm, 0 },
636 { X86::SUB64rr, X86::SUB64rm, 0 },
637 { X86::SUB8rr, X86::SUB8rm, 0 },
638 { X86::SUBPDrr, X86::SUBPDrm, 16 },
639 { X86::SUBPSrr, X86::SUBPSrm, 16 },
640 { X86::SUBSDrr, X86::SUBSDrm, 0 },
641 { X86::SUBSSrr, X86::SUBSSrm, 0 },
642 // FIXME: TEST*rr -> swapped operand of TEST*mr.
643 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
644 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
645 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
646 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
647 { X86::XOR16rr, X86::XOR16rm, 0 },
648 { X86::XOR32rr, X86::XOR32rm, 0 },
649 { X86::XOR64rr, X86::XOR64rm, 0 },
650 { X86::XOR8rr, X86::XOR8rm, 0 },
651 { X86::XORPDrr, X86::XORPDrm, 16 },
652 { X86::XORPSrr, X86::XORPSrm, 16 }
655 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
656 unsigned RegOp = OpTbl2[i][0];
657 unsigned MemOp = OpTbl2[i][1];
658 unsigned Align = OpTbl2[i][2];
659 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
660 std::make_pair(MemOp,Align))).second)
661 assert(false && "Duplicated entries?");
662 // Index 2, folded load
663 unsigned AuxInfo = 2 | (1 << 4);
664 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
665 std::make_pair(RegOp, AuxInfo))).second)
666 AmbEntries.push_back(MemOp);
669 // Remove ambiguous entries.
670 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
673 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
674 unsigned &SrcReg, unsigned &DstReg,
675 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
676 switch (MI.getOpcode()) {
680 case X86::MOV8rr_NOREX:
687 // FP Stack register class copies
688 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
689 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
690 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
692 case X86::FsMOVAPSrr:
693 case X86::FsMOVAPDrr:
697 case X86::MOVSS2PSrr:
698 case X86::MOVSD2PDrr:
699 case X86::MOVPS2SSrr:
700 case X86::MOVPD2SDrr:
701 case X86::MMX_MOVQ64rr:
702 assert(MI.getNumOperands() >= 2 &&
703 MI.getOperand(0).isReg() &&
704 MI.getOperand(1).isReg() &&
705 "invalid register-register move instruction");
706 SrcReg = MI.getOperand(1).getReg();
707 DstReg = MI.getOperand(0).getReg();
708 SrcSubIdx = MI.getOperand(1).getSubReg();
709 DstSubIdx = MI.getOperand(0).getSubReg();
714 /// isFrameOperand - Return true and the FrameIndex if the specified
715 /// operand and follow operands form a reference to the stack frame.
716 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
717 int &FrameIndex) const {
718 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
719 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
720 MI->getOperand(Op+1).getImm() == 1 &&
721 MI->getOperand(Op+2).getReg() == 0 &&
722 MI->getOperand(Op+3).getImm() == 0) {
723 FrameIndex = MI->getOperand(Op).getIndex();
729 static bool isFrameLoadOpcode(int Opcode) {
742 case X86::MMX_MOVD64rm:
743 case X86::MMX_MOVQ64rm:
750 static bool isFrameStoreOpcode(int Opcode) {
763 case X86::MMX_MOVD64mr:
764 case X86::MMX_MOVQ64mr:
765 case X86::MMX_MOVNTQmr:
771 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
772 int &FrameIndex) const {
773 if (isFrameLoadOpcode(MI->getOpcode()))
774 if (isFrameOperand(MI, 1, FrameIndex))
775 return MI->getOperand(0).getReg();
779 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
780 int &FrameIndex) const {
781 if (isFrameLoadOpcode(MI->getOpcode())) {
783 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
785 // Check for post-frame index elimination operations
786 return hasLoadFromStackSlot(MI, FrameIndex);
791 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
792 int &FrameIndex) const {
793 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
794 oe = MI->memoperands_end();
797 if ((*o)->isLoad() && (*o)->getValue())
798 if (const FixedStackPseudoSourceValue *Value =
799 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
800 FrameIndex = Value->getFrameIndex();
807 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
808 int &FrameIndex) const {
809 if (isFrameStoreOpcode(MI->getOpcode()))
810 if (isFrameOperand(MI, 0, FrameIndex))
811 return MI->getOperand(X86AddrNumOperands).getReg();
815 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
816 int &FrameIndex) const {
817 if (isFrameStoreOpcode(MI->getOpcode())) {
819 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
821 // Check for post-frame index elimination operations
822 return hasStoreToStackSlot(MI, FrameIndex);
827 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
828 int &FrameIndex) const {
829 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
830 oe = MI->memoperands_end();
833 if ((*o)->isStore() && (*o)->getValue())
834 if (const FixedStackPseudoSourceValue *Value =
835 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
836 FrameIndex = Value->getFrameIndex();
843 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
845 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
846 bool isPICBase = false;
847 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
848 E = MRI.def_end(); I != E; ++I) {
849 MachineInstr *DefMI = I.getOperand().getParent();
850 if (DefMI->getOpcode() != X86::MOVPC32r)
852 assert(!isPICBase && "More than one PIC base?");
859 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
860 AliasAnalysis *AA) const {
861 switch (MI->getOpcode()) {
873 case X86::MMX_MOVD64rm:
874 case X86::MMX_MOVQ64rm: {
875 // Loads from constant pools are trivially rematerializable.
876 if (MI->getOperand(1).isReg() &&
877 MI->getOperand(2).isImm() &&
878 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
879 MI->isInvariantLoad(AA)) {
880 unsigned BaseReg = MI->getOperand(1).getReg();
881 if (BaseReg == 0 || BaseReg == X86::RIP)
883 // Allow re-materialization of PIC load.
884 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
886 const MachineFunction &MF = *MI->getParent()->getParent();
887 const MachineRegisterInfo &MRI = MF.getRegInfo();
888 bool isPICBase = false;
889 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
890 E = MRI.def_end(); I != E; ++I) {
891 MachineInstr *DefMI = I.getOperand().getParent();
892 if (DefMI->getOpcode() != X86::MOVPC32r)
894 assert(!isPICBase && "More than one PIC base?");
904 if (MI->getOperand(2).isImm() &&
905 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
906 !MI->getOperand(4).isReg()) {
907 // lea fi#, lea GV, etc. are all rematerializable.
908 if (!MI->getOperand(1).isReg())
910 unsigned BaseReg = MI->getOperand(1).getReg();
913 // Allow re-materialization of lea PICBase + x.
914 const MachineFunction &MF = *MI->getParent()->getParent();
915 const MachineRegisterInfo &MRI = MF.getRegInfo();
916 return regIsPICBase(BaseReg, MRI);
922 // All other instructions marked M_REMATERIALIZABLE are always trivially
927 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
928 /// would clobber the EFLAGS condition register. Note the result may be
929 /// conservative. If it cannot definitely determine the safety after visiting
930 /// a few instructions in each direction it assumes it's not safe.
931 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
932 MachineBasicBlock::iterator I) {
933 // It's always safe to clobber EFLAGS at the end of a block.
937 // For compile time consideration, if we are not able to determine the
938 // safety after visiting 4 instructions in each direction, we will assume
940 MachineBasicBlock::iterator Iter = I;
941 for (unsigned i = 0; i < 4; ++i) {
942 bool SeenDef = false;
943 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
944 MachineOperand &MO = Iter->getOperand(j);
947 if (MO.getReg() == X86::EFLAGS) {
955 // This instruction defines EFLAGS, no need to look any further.
959 // If we make it to the end of the block, it's safe to clobber EFLAGS.
960 if (Iter == MBB.end())
965 for (unsigned i = 0; i < 4; ++i) {
966 // If we make it to the beginning of the block, it's safe to clobber
967 // EFLAGS iff EFLAGS is not live-in.
968 if (Iter == MBB.begin())
969 return !MBB.isLiveIn(X86::EFLAGS);
972 bool SawKill = false;
973 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
974 MachineOperand &MO = Iter->getOperand(j);
975 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
976 if (MO.isDef()) return MO.isDead();
977 if (MO.isKill()) SawKill = true;
982 // This instruction kills EFLAGS and doesn't redefine it, so
983 // there's no need to look further.
987 // Conservative answer.
991 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
992 MachineBasicBlock::iterator I,
993 unsigned DestReg, unsigned SubIdx,
994 const MachineInstr *Orig) const {
995 DebugLoc DL = DebugLoc::getUnknownLoc();
996 if (I != MBB.end()) DL = I->getDebugLoc();
998 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
999 DestReg = RI.getSubReg(DestReg, SubIdx);
1003 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1004 // Re-materialize them as movri instructions to avoid side effects.
1006 unsigned Opc = Orig->getOpcode();
1011 case X86::MOV32r0: {
1012 if (!isSafeToClobberEFLAGS(MBB, I)) {
1015 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1016 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1017 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1026 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1027 MI->getOperand(0).setReg(DestReg);
1030 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1033 MachineInstr *NewMI = prior(I);
1034 NewMI->getOperand(0).setSubReg(SubIdx);
1037 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1038 /// is not marked dead.
1039 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1040 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1041 MachineOperand &MO = MI->getOperand(i);
1042 if (MO.isReg() && MO.isDef() &&
1043 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1050 /// convertToThreeAddress - This method must be implemented by targets that
1051 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1052 /// may be able to convert a two-address instruction into a true
1053 /// three-address instruction on demand. This allows the X86 target (for
1054 /// example) to convert ADD and SHL instructions into LEA instructions if they
1055 /// would require register copies due to two-addressness.
1057 /// This method returns a null pointer if the transformation cannot be
1058 /// performed, otherwise it returns the new instruction.
1061 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1062 MachineBasicBlock::iterator &MBBI,
1063 LiveVariables *LV) const {
1064 MachineInstr *MI = MBBI;
1065 MachineFunction &MF = *MI->getParent()->getParent();
1066 // All instructions input are two-addr instructions. Get the known operands.
1067 unsigned Dest = MI->getOperand(0).getReg();
1068 unsigned Src = MI->getOperand(1).getReg();
1069 bool isDead = MI->getOperand(0).isDead();
1070 bool isKill = MI->getOperand(1).isKill();
1072 MachineInstr *NewMI = NULL;
1073 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1074 // we have better subtarget support, enable the 16-bit LEA generation here.
1075 bool DisableLEA16 = true;
1077 unsigned MIOpc = MI->getOpcode();
1079 case X86::SHUFPSrri: {
1080 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1081 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1083 unsigned B = MI->getOperand(1).getReg();
1084 unsigned C = MI->getOperand(2).getReg();
1085 if (B != C) return 0;
1086 unsigned A = MI->getOperand(0).getReg();
1087 unsigned M = MI->getOperand(3).getImm();
1088 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1089 .addReg(A, RegState::Define | getDeadRegState(isDead))
1090 .addReg(B, getKillRegState(isKill)).addImm(M);
1093 case X86::SHL64ri: {
1094 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1095 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1096 // the flags produced by a shift yet, so this is safe.
1097 unsigned ShAmt = MI->getOperand(2).getImm();
1098 if (ShAmt == 0 || ShAmt >= 4) return 0;
1100 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1101 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1102 .addReg(0).addImm(1 << ShAmt)
1103 .addReg(Src, getKillRegState(isKill))
1107 case X86::SHL32ri: {
1108 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1109 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1110 // the flags produced by a shift yet, so this is safe.
1111 unsigned ShAmt = MI->getOperand(2).getImm();
1112 if (ShAmt == 0 || ShAmt >= 4) return 0;
1114 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1115 X86::LEA64_32r : X86::LEA32r;
1116 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1117 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1118 .addReg(0).addImm(1 << ShAmt)
1119 .addReg(Src, getKillRegState(isKill)).addImm(0);
1122 case X86::SHL16ri: {
1123 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1124 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1125 // the flags produced by a shift yet, so this is safe.
1126 unsigned ShAmt = MI->getOperand(2).getImm();
1127 if (ShAmt == 0 || ShAmt >= 4) return 0;
1130 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1131 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1132 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1133 ? X86::LEA64_32r : X86::LEA32r;
1134 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1135 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1137 // Build and insert into an implicit UNDEF value. This is OK because
1138 // well be shifting and then extracting the lower 16-bits.
1139 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1140 MachineInstr *InsMI =
1141 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1143 .addReg(Src, getKillRegState(isKill))
1144 .addImm(X86::SUBREG_16BIT);
1146 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1147 .addReg(0).addImm(1 << ShAmt)
1148 .addReg(leaInReg, RegState::Kill)
1151 MachineInstr *ExtMI =
1152 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1153 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1154 .addReg(leaOutReg, RegState::Kill)
1155 .addImm(X86::SUBREG_16BIT);
1158 // Update live variables
1159 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1160 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1162 LV->replaceKillInstruction(Src, MI, InsMI);
1164 LV->replaceKillInstruction(Dest, MI, ExtMI);
1168 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1169 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1170 .addReg(0).addImm(1 << ShAmt)
1171 .addReg(Src, getKillRegState(isKill))
1177 // The following opcodes also sets the condition code register(s). Only
1178 // convert them to equivalent lea if the condition code register def's
1180 if (hasLiveCondCodeDef(MI))
1183 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1188 case X86::INC64_32r: {
1189 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1190 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1191 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1192 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1193 .addReg(Dest, RegState::Define |
1194 getDeadRegState(isDead)),
1199 case X86::INC64_16r:
1200 if (DisableLEA16) return 0;
1201 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1202 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1203 .addReg(Dest, RegState::Define |
1204 getDeadRegState(isDead)),
1209 case X86::DEC64_32r: {
1210 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1211 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1212 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1213 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1214 .addReg(Dest, RegState::Define |
1215 getDeadRegState(isDead)),
1220 case X86::DEC64_16r:
1221 if (DisableLEA16) return 0;
1222 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1223 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1224 .addReg(Dest, RegState::Define |
1225 getDeadRegState(isDead)),
1229 case X86::ADD32rr: {
1230 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1231 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1232 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1233 unsigned Src2 = MI->getOperand(2).getReg();
1234 bool isKill2 = MI->getOperand(2).isKill();
1235 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1236 .addReg(Dest, RegState::Define |
1237 getDeadRegState(isDead)),
1238 Src, isKill, Src2, isKill2);
1240 LV->replaceKillInstruction(Src2, MI, NewMI);
1243 case X86::ADD16rr: {
1244 if (DisableLEA16) return 0;
1245 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1246 unsigned Src2 = MI->getOperand(2).getReg();
1247 bool isKill2 = MI->getOperand(2).isKill();
1248 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1249 .addReg(Dest, RegState::Define |
1250 getDeadRegState(isDead)),
1251 Src, isKill, Src2, isKill2);
1253 LV->replaceKillInstruction(Src2, MI, NewMI);
1256 case X86::ADD64ri32:
1258 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1259 if (MI->getOperand(2).isImm())
1260 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1261 .addReg(Dest, RegState::Define |
1262 getDeadRegState(isDead)),
1263 Src, isKill, MI->getOperand(2).getImm());
1267 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1268 if (MI->getOperand(2).isImm()) {
1269 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1270 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1271 .addReg(Dest, RegState::Define |
1272 getDeadRegState(isDead)),
1273 Src, isKill, MI->getOperand(2).getImm());
1278 if (DisableLEA16) return 0;
1279 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1280 if (MI->getOperand(2).isImm())
1281 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1282 .addReg(Dest, RegState::Define |
1283 getDeadRegState(isDead)),
1284 Src, isKill, MI->getOperand(2).getImm());
1287 if (DisableLEA16) return 0;
1289 case X86::SHL64ri: {
1290 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1291 "Unknown shl instruction!");
1292 unsigned ShAmt = MI->getOperand(2).getImm();
1293 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1295 AM.Scale = 1 << ShAmt;
1297 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1298 : (MIOpc == X86::SHL32ri
1299 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1300 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1301 .addReg(Dest, RegState::Define |
1302 getDeadRegState(isDead)), AM);
1304 NewMI->getOperand(3).setIsKill(true);
1312 if (!NewMI) return 0;
1314 if (LV) { // Update live variables
1316 LV->replaceKillInstruction(Src, MI, NewMI);
1318 LV->replaceKillInstruction(Dest, MI, NewMI);
1321 MFI->insert(MBBI, NewMI); // Insert the new inst
1325 /// commuteInstruction - We have a few instructions that must be hacked on to
1329 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1330 switch (MI->getOpcode()) {
1331 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1332 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1333 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1334 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1335 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1336 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1339 switch (MI->getOpcode()) {
1340 default: llvm_unreachable("Unreachable!");
1341 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1342 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1343 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1344 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1345 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1346 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1348 unsigned Amt = MI->getOperand(3).getImm();
1350 MachineFunction &MF = *MI->getParent()->getParent();
1351 MI = MF.CloneMachineInstr(MI);
1354 MI->setDesc(get(Opc));
1355 MI->getOperand(3).setImm(Size-Amt);
1356 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1358 case X86::CMOVB16rr:
1359 case X86::CMOVB32rr:
1360 case X86::CMOVB64rr:
1361 case X86::CMOVAE16rr:
1362 case X86::CMOVAE32rr:
1363 case X86::CMOVAE64rr:
1364 case X86::CMOVE16rr:
1365 case X86::CMOVE32rr:
1366 case X86::CMOVE64rr:
1367 case X86::CMOVNE16rr:
1368 case X86::CMOVNE32rr:
1369 case X86::CMOVNE64rr:
1370 case X86::CMOVBE16rr:
1371 case X86::CMOVBE32rr:
1372 case X86::CMOVBE64rr:
1373 case X86::CMOVA16rr:
1374 case X86::CMOVA32rr:
1375 case X86::CMOVA64rr:
1376 case X86::CMOVL16rr:
1377 case X86::CMOVL32rr:
1378 case X86::CMOVL64rr:
1379 case X86::CMOVGE16rr:
1380 case X86::CMOVGE32rr:
1381 case X86::CMOVGE64rr:
1382 case X86::CMOVLE16rr:
1383 case X86::CMOVLE32rr:
1384 case X86::CMOVLE64rr:
1385 case X86::CMOVG16rr:
1386 case X86::CMOVG32rr:
1387 case X86::CMOVG64rr:
1388 case X86::CMOVS16rr:
1389 case X86::CMOVS32rr:
1390 case X86::CMOVS64rr:
1391 case X86::CMOVNS16rr:
1392 case X86::CMOVNS32rr:
1393 case X86::CMOVNS64rr:
1394 case X86::CMOVP16rr:
1395 case X86::CMOVP32rr:
1396 case X86::CMOVP64rr:
1397 case X86::CMOVNP16rr:
1398 case X86::CMOVNP32rr:
1399 case X86::CMOVNP64rr:
1400 case X86::CMOVO16rr:
1401 case X86::CMOVO32rr:
1402 case X86::CMOVO64rr:
1403 case X86::CMOVNO16rr:
1404 case X86::CMOVNO32rr:
1405 case X86::CMOVNO64rr: {
1407 switch (MI->getOpcode()) {
1409 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1410 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1411 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1412 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1413 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1414 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1415 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1416 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1417 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1418 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1419 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1420 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1421 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1422 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1423 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1424 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1425 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1426 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1427 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1428 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1429 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1430 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1431 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1432 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1433 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1434 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1435 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1436 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1437 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1438 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1439 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1440 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1441 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1442 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1443 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1444 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1445 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1446 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1447 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1448 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1449 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1450 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1451 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1452 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1453 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1454 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1455 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1456 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1459 MachineFunction &MF = *MI->getParent()->getParent();
1460 MI = MF.CloneMachineInstr(MI);
1463 MI->setDesc(get(Opc));
1464 // Fallthrough intended.
1467 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1471 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1473 default: return X86::COND_INVALID;
1474 case X86::JE: return X86::COND_E;
1475 case X86::JNE: return X86::COND_NE;
1476 case X86::JL: return X86::COND_L;
1477 case X86::JLE: return X86::COND_LE;
1478 case X86::JG: return X86::COND_G;
1479 case X86::JGE: return X86::COND_GE;
1480 case X86::JB: return X86::COND_B;
1481 case X86::JBE: return X86::COND_BE;
1482 case X86::JA: return X86::COND_A;
1483 case X86::JAE: return X86::COND_AE;
1484 case X86::JS: return X86::COND_S;
1485 case X86::JNS: return X86::COND_NS;
1486 case X86::JP: return X86::COND_P;
1487 case X86::JNP: return X86::COND_NP;
1488 case X86::JO: return X86::COND_O;
1489 case X86::JNO: return X86::COND_NO;
1493 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1495 default: llvm_unreachable("Illegal condition code!");
1496 case X86::COND_E: return X86::JE;
1497 case X86::COND_NE: return X86::JNE;
1498 case X86::COND_L: return X86::JL;
1499 case X86::COND_LE: return X86::JLE;
1500 case X86::COND_G: return X86::JG;
1501 case X86::COND_GE: return X86::JGE;
1502 case X86::COND_B: return X86::JB;
1503 case X86::COND_BE: return X86::JBE;
1504 case X86::COND_A: return X86::JA;
1505 case X86::COND_AE: return X86::JAE;
1506 case X86::COND_S: return X86::JS;
1507 case X86::COND_NS: return X86::JNS;
1508 case X86::COND_P: return X86::JP;
1509 case X86::COND_NP: return X86::JNP;
1510 case X86::COND_O: return X86::JO;
1511 case X86::COND_NO: return X86::JNO;
1515 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1516 /// e.g. turning COND_E to COND_NE.
1517 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1519 default: llvm_unreachable("Illegal condition code!");
1520 case X86::COND_E: return X86::COND_NE;
1521 case X86::COND_NE: return X86::COND_E;
1522 case X86::COND_L: return X86::COND_GE;
1523 case X86::COND_LE: return X86::COND_G;
1524 case X86::COND_G: return X86::COND_LE;
1525 case X86::COND_GE: return X86::COND_L;
1526 case X86::COND_B: return X86::COND_AE;
1527 case X86::COND_BE: return X86::COND_A;
1528 case X86::COND_A: return X86::COND_BE;
1529 case X86::COND_AE: return X86::COND_B;
1530 case X86::COND_S: return X86::COND_NS;
1531 case X86::COND_NS: return X86::COND_S;
1532 case X86::COND_P: return X86::COND_NP;
1533 case X86::COND_NP: return X86::COND_P;
1534 case X86::COND_O: return X86::COND_NO;
1535 case X86::COND_NO: return X86::COND_O;
1539 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1540 const TargetInstrDesc &TID = MI->getDesc();
1541 if (!TID.isTerminator()) return false;
1543 // Conditional branch is a special case.
1544 if (TID.isBranch() && !TID.isBarrier())
1546 if (!TID.isPredicable())
1548 return !isPredicated(MI);
1551 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1552 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1553 const X86InstrInfo &TII) {
1554 if (MI->getOpcode() == X86::FP_REG_KILL)
1556 return TII.isUnpredicatedTerminator(MI);
1559 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1560 MachineBasicBlock *&TBB,
1561 MachineBasicBlock *&FBB,
1562 SmallVectorImpl<MachineOperand> &Cond,
1563 bool AllowModify) const {
1564 // Start from the bottom of the block and work up, examining the
1565 // terminator instructions.
1566 MachineBasicBlock::iterator I = MBB.end();
1567 while (I != MBB.begin()) {
1569 // Working from the bottom, when we see a non-terminator
1570 // instruction, we're done.
1571 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1573 // A terminator that isn't a branch can't easily be handled
1574 // by this analysis.
1575 if (!I->getDesc().isBranch())
1577 // Handle unconditional branches.
1578 if (I->getOpcode() == X86::JMP) {
1580 TBB = I->getOperand(0).getMBB();
1584 // If the block has any instructions after a JMP, delete them.
1585 while (next(I) != MBB.end())
1586 next(I)->eraseFromParent();
1589 // Delete the JMP if it's equivalent to a fall-through.
1590 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1592 I->eraseFromParent();
1596 // TBB is used to indicate the unconditinal destination.
1597 TBB = I->getOperand(0).getMBB();
1600 // Handle conditional branches.
1601 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1602 if (BranchCode == X86::COND_INVALID)
1603 return true; // Can't handle indirect branch.
1604 // Working from the bottom, handle the first conditional branch.
1607 TBB = I->getOperand(0).getMBB();
1608 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1611 // Handle subsequent conditional branches. Only handle the case
1612 // where all conditional branches branch to the same destination
1613 // and their condition opcodes fit one of the special
1614 // multi-branch idioms.
1615 assert(Cond.size() == 1);
1617 // Only handle the case where all conditional branches branch to
1618 // the same destination.
1619 if (TBB != I->getOperand(0).getMBB())
1621 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1622 // If the conditions are the same, we can leave them alone.
1623 if (OldBranchCode == BranchCode)
1625 // If they differ, see if they fit one of the known patterns.
1626 // Theoretically we could handle more patterns here, but
1627 // we shouldn't expect to see them if instruction selection
1628 // has done a reasonable job.
1629 if ((OldBranchCode == X86::COND_NP &&
1630 BranchCode == X86::COND_E) ||
1631 (OldBranchCode == X86::COND_E &&
1632 BranchCode == X86::COND_NP))
1633 BranchCode = X86::COND_NP_OR_E;
1634 else if ((OldBranchCode == X86::COND_P &&
1635 BranchCode == X86::COND_NE) ||
1636 (OldBranchCode == X86::COND_NE &&
1637 BranchCode == X86::COND_P))
1638 BranchCode = X86::COND_NE_OR_P;
1641 // Update the MachineOperand.
1642 Cond[0].setImm(BranchCode);
1648 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1649 MachineBasicBlock::iterator I = MBB.end();
1652 while (I != MBB.begin()) {
1654 if (I->getOpcode() != X86::JMP &&
1655 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1657 // Remove the branch.
1658 I->eraseFromParent();
1667 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1668 MachineBasicBlock *FBB,
1669 const SmallVectorImpl<MachineOperand> &Cond) const {
1670 // FIXME this should probably have a DebugLoc operand
1671 DebugLoc dl = DebugLoc::getUnknownLoc();
1672 // Shouldn't be a fall through.
1673 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1674 assert((Cond.size() == 1 || Cond.size() == 0) &&
1675 "X86 branch conditions have one component!");
1678 // Unconditional branch?
1679 assert(!FBB && "Unconditional branch with multiple successors!");
1680 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1684 // Conditional branch.
1686 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1688 case X86::COND_NP_OR_E:
1689 // Synthesize NP_OR_E with two branches.
1690 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1692 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1695 case X86::COND_NE_OR_P:
1696 // Synthesize NE_OR_P with two branches.
1697 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1699 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1703 unsigned Opc = GetCondBranchFromCond(CC);
1704 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1709 // Two-way Conditional branch. Insert the second branch.
1710 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1716 /// isHReg - Test if the given register is a physical h register.
1717 static bool isHReg(unsigned Reg) {
1718 return X86::GR8_ABCD_HRegClass.contains(Reg);
1721 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1722 MachineBasicBlock::iterator MI,
1723 unsigned DestReg, unsigned SrcReg,
1724 const TargetRegisterClass *DestRC,
1725 const TargetRegisterClass *SrcRC) const {
1726 DebugLoc DL = DebugLoc::getUnknownLoc();
1727 if (MI != MBB.end()) DL = MI->getDebugLoc();
1729 // Determine if DstRC and SrcRC have a common superclass in common.
1730 const TargetRegisterClass *CommonRC = DestRC;
1731 if (DestRC == SrcRC)
1732 /* Source and destination have the same register class. */;
1733 else if (CommonRC->hasSuperClass(SrcRC))
1735 else if (!DestRC->hasSubClass(SrcRC)) {
1736 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1737 // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1738 // GR32_NOSP, copy as GR32.
1739 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1740 DestRC->hasSuperClass(&X86::GR64RegClass))
1741 CommonRC = &X86::GR64RegClass;
1742 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1743 DestRC->hasSuperClass(&X86::GR32RegClass))
1744 CommonRC = &X86::GR32RegClass;
1751 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1753 } else if (CommonRC == &X86::GR32RegClass ||
1754 CommonRC == &X86::GR32_NOSPRegClass) {
1756 } else if (CommonRC == &X86::GR16RegClass) {
1758 } else if (CommonRC == &X86::GR8RegClass) {
1759 // Copying to or from a physical H register on x86-64 requires a NOREX
1760 // move. Otherwise use a normal move.
1761 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1762 TM.getSubtarget<X86Subtarget>().is64Bit())
1763 Opc = X86::MOV8rr_NOREX;
1766 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1768 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1770 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1772 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1774 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1775 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1776 Opc = X86::MOV8rr_NOREX;
1779 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1780 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1782 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1784 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1786 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1788 } else if (CommonRC == &X86::RFP32RegClass) {
1789 Opc = X86::MOV_Fp3232;
1790 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1791 Opc = X86::MOV_Fp6464;
1792 } else if (CommonRC == &X86::RFP80RegClass) {
1793 Opc = X86::MOV_Fp8080;
1794 } else if (CommonRC == &X86::FR32RegClass) {
1795 Opc = X86::FsMOVAPSrr;
1796 } else if (CommonRC == &X86::FR64RegClass) {
1797 Opc = X86::FsMOVAPDrr;
1798 } else if (CommonRC == &X86::VR128RegClass) {
1799 Opc = X86::MOVAPSrr;
1800 } else if (CommonRC == &X86::VR64RegClass) {
1801 Opc = X86::MMX_MOVQ64rr;
1805 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1809 // Moving EFLAGS to / from another register requires a push and a pop.
1810 if (SrcRC == &X86::CCRRegClass) {
1811 if (SrcReg != X86::EFLAGS)
1813 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1814 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1815 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1817 } else if (DestRC == &X86::GR32RegClass ||
1818 DestRC == &X86::GR32_NOSPRegClass) {
1819 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1820 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1823 } else if (DestRC == &X86::CCRRegClass) {
1824 if (DestReg != X86::EFLAGS)
1826 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1827 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1828 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1830 } else if (SrcRC == &X86::GR32RegClass ||
1831 DestRC == &X86::GR32_NOSPRegClass) {
1832 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1833 BuildMI(MBB, MI, DL, get(X86::POPFD));
1838 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1839 if (SrcRC == &X86::RSTRegClass) {
1840 // Copying from ST(0)/ST(1).
1841 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1842 // Can only copy from ST(0)/ST(1) right now
1844 bool isST0 = SrcReg == X86::ST0;
1846 if (DestRC == &X86::RFP32RegClass)
1847 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1848 else if (DestRC == &X86::RFP64RegClass)
1849 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1851 if (DestRC != &X86::RFP80RegClass)
1853 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1855 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1859 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1860 if (DestRC == &X86::RSTRegClass) {
1861 // Copying to ST(0) / ST(1).
1862 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1863 // Can only copy to TOS right now
1865 bool isST0 = DestReg == X86::ST0;
1867 if (SrcRC == &X86::RFP32RegClass)
1868 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1869 else if (SrcRC == &X86::RFP64RegClass)
1870 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1872 if (SrcRC != &X86::RFP80RegClass)
1874 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1876 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1880 // Not yet supported!
1884 static unsigned getStoreRegOpcode(unsigned SrcReg,
1885 const TargetRegisterClass *RC,
1886 bool isStackAligned,
1887 TargetMachine &TM) {
1889 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1891 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1893 } else if (RC == &X86::GR16RegClass) {
1895 } else if (RC == &X86::GR8RegClass) {
1896 // Copying to or from a physical H register on x86-64 requires a NOREX
1897 // move. Otherwise use a normal move.
1898 if (isHReg(SrcReg) &&
1899 TM.getSubtarget<X86Subtarget>().is64Bit())
1900 Opc = X86::MOV8mr_NOREX;
1903 } else if (RC == &X86::GR64_ABCDRegClass) {
1905 } else if (RC == &X86::GR32_ABCDRegClass) {
1907 } else if (RC == &X86::GR16_ABCDRegClass) {
1909 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1911 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1912 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1913 Opc = X86::MOV8mr_NOREX;
1916 } else if (RC == &X86::GR64_NOREXRegClass ||
1917 RC == &X86::GR64_NOREX_NOSPRegClass) {
1919 } else if (RC == &X86::GR32_NOREXRegClass) {
1921 } else if (RC == &X86::GR16_NOREXRegClass) {
1923 } else if (RC == &X86::GR8_NOREXRegClass) {
1925 } else if (RC == &X86::RFP80RegClass) {
1926 Opc = X86::ST_FpP80m; // pops
1927 } else if (RC == &X86::RFP64RegClass) {
1928 Opc = X86::ST_Fp64m;
1929 } else if (RC == &X86::RFP32RegClass) {
1930 Opc = X86::ST_Fp32m;
1931 } else if (RC == &X86::FR32RegClass) {
1933 } else if (RC == &X86::FR64RegClass) {
1935 } else if (RC == &X86::VR128RegClass) {
1936 // If stack is realigned we can use aligned stores.
1937 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1938 } else if (RC == &X86::VR64RegClass) {
1939 Opc = X86::MMX_MOVQ64mr;
1941 llvm_unreachable("Unknown regclass");
1947 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1948 MachineBasicBlock::iterator MI,
1949 unsigned SrcReg, bool isKill, int FrameIdx,
1950 const TargetRegisterClass *RC) const {
1951 const MachineFunction &MF = *MBB.getParent();
1952 bool isAligned = (RI.getStackAlignment() >= 16) ||
1953 RI.needsStackRealignment(MF);
1954 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1955 DebugLoc DL = DebugLoc::getUnknownLoc();
1956 if (MI != MBB.end()) DL = MI->getDebugLoc();
1957 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1958 .addReg(SrcReg, getKillRegState(isKill));
1961 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1963 SmallVectorImpl<MachineOperand> &Addr,
1964 const TargetRegisterClass *RC,
1965 MachineInstr::mmo_iterator MMOBegin,
1966 MachineInstr::mmo_iterator MMOEnd,
1967 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1968 bool isAligned = (RI.getStackAlignment() >= 16) ||
1969 RI.needsStackRealignment(MF);
1970 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1971 DebugLoc DL = DebugLoc::getUnknownLoc();
1972 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1973 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1974 MIB.addOperand(Addr[i]);
1975 MIB.addReg(SrcReg, getKillRegState(isKill));
1976 (*MIB).setMemRefs(MMOBegin, MMOEnd);
1977 NewMIs.push_back(MIB);
1980 static unsigned getLoadRegOpcode(unsigned DestReg,
1981 const TargetRegisterClass *RC,
1982 bool isStackAligned,
1983 const TargetMachine &TM) {
1985 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1987 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1989 } else if (RC == &X86::GR16RegClass) {
1991 } else if (RC == &X86::GR8RegClass) {
1992 // Copying to or from a physical H register on x86-64 requires a NOREX
1993 // move. Otherwise use a normal move.
1994 if (isHReg(DestReg) &&
1995 TM.getSubtarget<X86Subtarget>().is64Bit())
1996 Opc = X86::MOV8rm_NOREX;
1999 } else if (RC == &X86::GR64_ABCDRegClass) {
2001 } else if (RC == &X86::GR32_ABCDRegClass) {
2003 } else if (RC == &X86::GR16_ABCDRegClass) {
2005 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2007 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2008 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2009 Opc = X86::MOV8rm_NOREX;
2012 } else if (RC == &X86::GR64_NOREXRegClass ||
2013 RC == &X86::GR64_NOREX_NOSPRegClass) {
2015 } else if (RC == &X86::GR32_NOREXRegClass) {
2017 } else if (RC == &X86::GR16_NOREXRegClass) {
2019 } else if (RC == &X86::GR8_NOREXRegClass) {
2021 } else if (RC == &X86::RFP80RegClass) {
2022 Opc = X86::LD_Fp80m;
2023 } else if (RC == &X86::RFP64RegClass) {
2024 Opc = X86::LD_Fp64m;
2025 } else if (RC == &X86::RFP32RegClass) {
2026 Opc = X86::LD_Fp32m;
2027 } else if (RC == &X86::FR32RegClass) {
2029 } else if (RC == &X86::FR64RegClass) {
2031 } else if (RC == &X86::VR128RegClass) {
2032 // If stack is realigned we can use aligned loads.
2033 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2034 } else if (RC == &X86::VR64RegClass) {
2035 Opc = X86::MMX_MOVQ64rm;
2037 llvm_unreachable("Unknown regclass");
2043 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2044 MachineBasicBlock::iterator MI,
2045 unsigned DestReg, int FrameIdx,
2046 const TargetRegisterClass *RC) const{
2047 const MachineFunction &MF = *MBB.getParent();
2048 bool isAligned = (RI.getStackAlignment() >= 16) ||
2049 RI.needsStackRealignment(MF);
2050 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2051 DebugLoc DL = DebugLoc::getUnknownLoc();
2052 if (MI != MBB.end()) DL = MI->getDebugLoc();
2053 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2056 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2057 SmallVectorImpl<MachineOperand> &Addr,
2058 const TargetRegisterClass *RC,
2059 MachineInstr::mmo_iterator MMOBegin,
2060 MachineInstr::mmo_iterator MMOEnd,
2061 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2062 bool isAligned = (RI.getStackAlignment() >= 16) ||
2063 RI.needsStackRealignment(MF);
2064 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2065 DebugLoc DL = DebugLoc::getUnknownLoc();
2066 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2067 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2068 MIB.addOperand(Addr[i]);
2069 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2070 NewMIs.push_back(MIB);
2073 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2074 MachineBasicBlock::iterator MI,
2075 const std::vector<CalleeSavedInfo> &CSI) const {
2079 DebugLoc DL = DebugLoc::getUnknownLoc();
2080 if (MI != MBB.end()) DL = MI->getDebugLoc();
2082 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2083 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2084 unsigned SlotSize = is64Bit ? 8 : 4;
2086 MachineFunction &MF = *MBB.getParent();
2087 unsigned FPReg = RI.getFrameRegister(MF);
2088 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2089 unsigned CalleeFrameSize = 0;
2091 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2092 for (unsigned i = CSI.size(); i != 0; --i) {
2093 unsigned Reg = CSI[i-1].getReg();
2094 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2095 // Add the callee-saved register as live-in. It's killed at the spill.
2098 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2100 if (RegClass != &X86::VR128RegClass && !isWin64) {
2101 CalleeFrameSize += SlotSize;
2102 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2104 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2108 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2112 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2113 MachineBasicBlock::iterator MI,
2114 const std::vector<CalleeSavedInfo> &CSI) const {
2118 DebugLoc DL = DebugLoc::getUnknownLoc();
2119 if (MI != MBB.end()) DL = MI->getDebugLoc();
2121 MachineFunction &MF = *MBB.getParent();
2122 unsigned FPReg = RI.getFrameRegister(MF);
2123 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2124 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2125 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2126 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2127 unsigned Reg = CSI[i].getReg();
2129 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2131 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2132 if (RegClass != &X86::VR128RegClass && !isWin64) {
2133 BuildMI(MBB, MI, DL, get(Opc), Reg);
2135 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2141 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2142 const SmallVectorImpl<MachineOperand> &MOs,
2144 const TargetInstrInfo &TII) {
2145 // Create the base instruction with the memory operand as the first part.
2146 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2147 MI->getDebugLoc(), true);
2148 MachineInstrBuilder MIB(NewMI);
2149 unsigned NumAddrOps = MOs.size();
2150 for (unsigned i = 0; i != NumAddrOps; ++i)
2151 MIB.addOperand(MOs[i]);
2152 if (NumAddrOps < 4) // FrameIndex only
2155 // Loop over the rest of the ri operands, converting them over.
2156 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2157 for (unsigned i = 0; i != NumOps; ++i) {
2158 MachineOperand &MO = MI->getOperand(i+2);
2161 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2162 MachineOperand &MO = MI->getOperand(i);
2168 static MachineInstr *FuseInst(MachineFunction &MF,
2169 unsigned Opcode, unsigned OpNo,
2170 const SmallVectorImpl<MachineOperand> &MOs,
2171 MachineInstr *MI, const TargetInstrInfo &TII) {
2172 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2173 MI->getDebugLoc(), true);
2174 MachineInstrBuilder MIB(NewMI);
2176 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2177 MachineOperand &MO = MI->getOperand(i);
2179 assert(MO.isReg() && "Expected to fold into reg operand!");
2180 unsigned NumAddrOps = MOs.size();
2181 for (unsigned i = 0; i != NumAddrOps; ++i)
2182 MIB.addOperand(MOs[i]);
2183 if (NumAddrOps < 4) // FrameIndex only
2192 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2193 const SmallVectorImpl<MachineOperand> &MOs,
2195 MachineFunction &MF = *MI->getParent()->getParent();
2196 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2198 unsigned NumAddrOps = MOs.size();
2199 for (unsigned i = 0; i != NumAddrOps; ++i)
2200 MIB.addOperand(MOs[i]);
2201 if (NumAddrOps < 4) // FrameIndex only
2203 return MIB.addImm(0);
2207 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2208 MachineInstr *MI, unsigned i,
2209 const SmallVectorImpl<MachineOperand> &MOs,
2210 unsigned Size, unsigned Align) const {
2211 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2212 bool isTwoAddrFold = false;
2213 unsigned NumOps = MI->getDesc().getNumOperands();
2214 bool isTwoAddr = NumOps > 1 &&
2215 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2217 MachineInstr *NewMI = NULL;
2218 // Folding a memory location into the two-address part of a two-address
2219 // instruction is different than folding it other places. It requires
2220 // replacing the *two* registers with the memory location.
2221 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2222 MI->getOperand(0).isReg() &&
2223 MI->getOperand(1).isReg() &&
2224 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2225 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2226 isTwoAddrFold = true;
2227 } else if (i == 0) { // If operand 0
2228 if (MI->getOpcode() == X86::MOV16r0)
2229 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2230 else if (MI->getOpcode() == X86::MOV32r0)
2231 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2232 else if (MI->getOpcode() == X86::MOV8r0)
2233 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2237 OpcodeTablePtr = &RegOp2MemOpTable0;
2238 } else if (i == 1) {
2239 OpcodeTablePtr = &RegOp2MemOpTable1;
2240 } else if (i == 2) {
2241 OpcodeTablePtr = &RegOp2MemOpTable2;
2244 // If table selected...
2245 if (OpcodeTablePtr) {
2246 // Find the Opcode to fuse
2247 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2248 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2249 if (I != OpcodeTablePtr->end()) {
2250 unsigned Opcode = I->second.first;
2251 unsigned MinAlign = I->second.second;
2252 if (Align < MinAlign)
2254 bool NarrowToMOV32rm = false;
2256 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2257 if (Size < RCSize) {
2258 // Check if it's safe to fold the load. If the size of the object is
2259 // narrower than the load width, then it's not.
2260 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2262 // If this is a 64-bit load, but the spill slot is 32, then we can do
2263 // a 32-bit load which is implicitly zero-extended. This likely is due
2264 // to liveintervalanalysis remat'ing a load from stack slot.
2265 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2267 Opcode = X86::MOV32rm;
2268 NarrowToMOV32rm = true;
2273 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2275 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2277 if (NarrowToMOV32rm) {
2278 // If this is the special case where we use a MOV32rm to load a 32-bit
2279 // value and zero-extend the top bits. Change the destination register
2281 unsigned DstReg = NewMI->getOperand(0).getReg();
2282 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2283 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2284 4/*x86_subreg_32bit*/));
2286 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2293 if (PrintFailedFusing)
2294 errs() << "We failed to fuse operand " << i << " in " << *MI;
2299 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2301 const SmallVectorImpl<unsigned> &Ops,
2302 int FrameIndex) const {
2303 // Check switch flag
2304 if (NoFusing) return NULL;
2306 const MachineFrameInfo *MFI = MF.getFrameInfo();
2307 unsigned Size = MFI->getObjectSize(FrameIndex);
2308 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2309 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2310 unsigned NewOpc = 0;
2311 unsigned RCSize = 0;
2312 switch (MI->getOpcode()) {
2313 default: return NULL;
2314 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2315 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2316 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2317 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2319 // Check if it's safe to fold the load. If the size of the object is
2320 // narrower than the load width, then it's not.
2323 // Change to CMPXXri r, 0 first.
2324 MI->setDesc(get(NewOpc));
2325 MI->getOperand(1).ChangeToImmediate(0);
2326 } else if (Ops.size() != 1)
2329 SmallVector<MachineOperand,4> MOs;
2330 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2331 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2334 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2336 const SmallVectorImpl<unsigned> &Ops,
2337 MachineInstr *LoadMI) const {
2338 // Check switch flag
2339 if (NoFusing) return NULL;
2341 // Determine the alignment of the load.
2342 unsigned Alignment = 0;
2343 if (LoadMI->hasOneMemOperand())
2344 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2346 switch (LoadMI->getOpcode()) {
2348 case X86::V_SETALLONES:
2358 llvm_unreachable("Don't know how to fold this instruction!");
2360 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2361 unsigned NewOpc = 0;
2362 switch (MI->getOpcode()) {
2363 default: return NULL;
2364 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2365 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2366 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2367 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2369 // Change to CMPXXri r, 0 first.
2370 MI->setDesc(get(NewOpc));
2371 MI->getOperand(1).ChangeToImmediate(0);
2372 } else if (Ops.size() != 1)
2375 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2376 switch (LoadMI->getOpcode()) {
2378 case X86::V_SETALLONES:
2380 case X86::FsFLD0SS: {
2381 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2382 // Create a constant-pool entry and operands to load from it.
2384 // x86-32 PIC requires a PIC base register for constant pools.
2385 unsigned PICBase = 0;
2386 if (TM.getRelocationModel() == Reloc::PIC_) {
2387 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2390 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2391 // This doesn't work for several reasons.
2392 // 1. GlobalBaseReg may have been spilled.
2393 // 2. It may not be live at MI.
2397 // Create a constant-pool entry.
2398 MachineConstantPool &MCP = *MF.getConstantPool();
2400 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2401 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2402 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2403 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2405 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2406 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2407 Constant::getAllOnesValue(Ty) :
2408 Constant::getNullValue(Ty);
2409 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2411 // Create operands to load from the constant pool entry.
2412 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2413 MOs.push_back(MachineOperand::CreateImm(1));
2414 MOs.push_back(MachineOperand::CreateReg(0, false));
2415 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2416 MOs.push_back(MachineOperand::CreateReg(0, false));
2420 // Folding a normal load. Just copy the load's address operands.
2421 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2422 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2423 MOs.push_back(LoadMI->getOperand(i));
2427 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2431 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2432 const SmallVectorImpl<unsigned> &Ops) const {
2433 // Check switch flag
2434 if (NoFusing) return 0;
2436 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2437 switch (MI->getOpcode()) {
2438 default: return false;
2447 if (Ops.size() != 1)
2450 unsigned OpNum = Ops[0];
2451 unsigned Opc = MI->getOpcode();
2452 unsigned NumOps = MI->getDesc().getNumOperands();
2453 bool isTwoAddr = NumOps > 1 &&
2454 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2456 // Folding a memory location into the two-address part of a two-address
2457 // instruction is different than folding it other places. It requires
2458 // replacing the *two* registers with the memory location.
2459 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2460 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2461 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2462 } else if (OpNum == 0) { // If operand 0
2470 OpcodeTablePtr = &RegOp2MemOpTable0;
2471 } else if (OpNum == 1) {
2472 OpcodeTablePtr = &RegOp2MemOpTable1;
2473 } else if (OpNum == 2) {
2474 OpcodeTablePtr = &RegOp2MemOpTable2;
2477 if (OpcodeTablePtr) {
2478 // Find the Opcode to fuse
2479 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2480 OpcodeTablePtr->find((unsigned*)Opc);
2481 if (I != OpcodeTablePtr->end())
2487 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2488 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2489 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2490 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2491 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2492 if (I == MemOp2RegOpTable.end())
2494 DebugLoc dl = MI->getDebugLoc();
2495 unsigned Opc = I->second.first;
2496 unsigned Index = I->second.second & 0xf;
2497 bool FoldedLoad = I->second.second & (1 << 4);
2498 bool FoldedStore = I->second.second & (1 << 5);
2499 if (UnfoldLoad && !FoldedLoad)
2501 UnfoldLoad &= FoldedLoad;
2502 if (UnfoldStore && !FoldedStore)
2504 UnfoldStore &= FoldedStore;
2506 const TargetInstrDesc &TID = get(Opc);
2507 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2508 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2509 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2510 SmallVector<MachineOperand,2> BeforeOps;
2511 SmallVector<MachineOperand,2> AfterOps;
2512 SmallVector<MachineOperand,4> ImpOps;
2513 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2514 MachineOperand &Op = MI->getOperand(i);
2515 if (i >= Index && i < Index + X86AddrNumOperands)
2516 AddrOps.push_back(Op);
2517 else if (Op.isReg() && Op.isImplicit())
2518 ImpOps.push_back(Op);
2520 BeforeOps.push_back(Op);
2522 AfterOps.push_back(Op);
2525 // Emit the load instruction.
2527 std::pair<MachineInstr::mmo_iterator,
2528 MachineInstr::mmo_iterator> MMOs =
2529 MF.extractLoadMemRefs(MI->memoperands_begin(),
2530 MI->memoperands_end());
2531 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2533 // Address operands cannot be marked isKill.
2534 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2535 MachineOperand &MO = NewMIs[0]->getOperand(i);
2537 MO.setIsKill(false);
2542 // Emit the data processing instruction.
2543 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2544 MachineInstrBuilder MIB(DataMI);
2547 MIB.addReg(Reg, RegState::Define);
2548 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2549 MIB.addOperand(BeforeOps[i]);
2552 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2553 MIB.addOperand(AfterOps[i]);
2554 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2555 MachineOperand &MO = ImpOps[i];
2556 MIB.addReg(MO.getReg(),
2557 getDefRegState(MO.isDef()) |
2558 RegState::Implicit |
2559 getKillRegState(MO.isKill()) |
2560 getDeadRegState(MO.isDead()) |
2561 getUndefRegState(MO.isUndef()));
2563 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2564 unsigned NewOpc = 0;
2565 switch (DataMI->getOpcode()) {
2567 case X86::CMP64ri32:
2571 MachineOperand &MO0 = DataMI->getOperand(0);
2572 MachineOperand &MO1 = DataMI->getOperand(1);
2573 if (MO1.getImm() == 0) {
2574 switch (DataMI->getOpcode()) {
2576 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2577 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2578 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2579 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2581 DataMI->setDesc(get(NewOpc));
2582 MO1.ChangeToRegister(MO0.getReg(), false);
2586 NewMIs.push_back(DataMI);
2588 // Emit the store instruction.
2590 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2591 std::pair<MachineInstr::mmo_iterator,
2592 MachineInstr::mmo_iterator> MMOs =
2593 MF.extractStoreMemRefs(MI->memoperands_begin(),
2594 MI->memoperands_end());
2595 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2602 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2603 SmallVectorImpl<SDNode*> &NewNodes) const {
2604 if (!N->isMachineOpcode())
2607 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2608 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2609 if (I == MemOp2RegOpTable.end())
2611 unsigned Opc = I->second.first;
2612 unsigned Index = I->second.second & 0xf;
2613 bool FoldedLoad = I->second.second & (1 << 4);
2614 bool FoldedStore = I->second.second & (1 << 5);
2615 const TargetInstrDesc &TID = get(Opc);
2616 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2617 unsigned NumDefs = TID.NumDefs;
2618 std::vector<SDValue> AddrOps;
2619 std::vector<SDValue> BeforeOps;
2620 std::vector<SDValue> AfterOps;
2621 DebugLoc dl = N->getDebugLoc();
2622 unsigned NumOps = N->getNumOperands();
2623 for (unsigned i = 0; i != NumOps-1; ++i) {
2624 SDValue Op = N->getOperand(i);
2625 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2626 AddrOps.push_back(Op);
2627 else if (i < Index-NumDefs)
2628 BeforeOps.push_back(Op);
2629 else if (i > Index-NumDefs)
2630 AfterOps.push_back(Op);
2632 SDValue Chain = N->getOperand(NumOps-1);
2633 AddrOps.push_back(Chain);
2635 // Emit the load instruction.
2637 MachineFunction &MF = DAG.getMachineFunction();
2639 EVT VT = *RC->vt_begin();
2640 bool isAligned = (RI.getStackAlignment() >= 16) ||
2641 RI.needsStackRealignment(MF);
2642 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2643 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2644 NewNodes.push_back(Load);
2646 // Preserve memory reference information.
2647 std::pair<MachineInstr::mmo_iterator,
2648 MachineInstr::mmo_iterator> MMOs =
2649 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2650 cast<MachineSDNode>(N)->memoperands_end());
2651 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2654 // Emit the data processing instruction.
2655 std::vector<EVT> VTs;
2656 const TargetRegisterClass *DstRC = 0;
2657 if (TID.getNumDefs() > 0) {
2658 DstRC = TID.OpInfo[0].getRegClass(&RI);
2659 VTs.push_back(*DstRC->vt_begin());
2661 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2662 EVT VT = N->getValueType(i);
2663 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2667 BeforeOps.push_back(SDValue(Load, 0));
2668 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2669 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2671 NewNodes.push_back(NewNode);
2673 // Emit the store instruction.
2676 AddrOps.push_back(SDValue(NewNode, 0));
2677 AddrOps.push_back(Chain);
2678 bool isAligned = (RI.getStackAlignment() >= 16) ||
2679 RI.needsStackRealignment(MF);
2680 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2683 &AddrOps[0], AddrOps.size());
2684 NewNodes.push_back(Store);
2686 // Preserve memory reference information.
2687 std::pair<MachineInstr::mmo_iterator,
2688 MachineInstr::mmo_iterator> MMOs =
2689 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2690 cast<MachineSDNode>(N)->memoperands_end());
2691 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2697 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2698 bool UnfoldLoad, bool UnfoldStore,
2699 unsigned *LoadRegIndex) const {
2700 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2701 MemOp2RegOpTable.find((unsigned*)Opc);
2702 if (I == MemOp2RegOpTable.end())
2704 bool FoldedLoad = I->second.second & (1 << 4);
2705 bool FoldedStore = I->second.second & (1 << 5);
2706 if (UnfoldLoad && !FoldedLoad)
2708 if (UnfoldStore && !FoldedStore)
2711 *LoadRegIndex = I->second.second & 0xf;
2712 return I->second.first;
2715 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2716 if (MBB.empty()) return false;
2718 switch (MBB.back().getOpcode()) {
2719 case X86::TCRETURNri:
2720 case X86::TCRETURNdi:
2721 case X86::RET: // Return.
2726 case X86::JMP: // Uncond branch.
2727 case X86::JMP32r: // Indirect branch.
2728 case X86::JMP64r: // Indirect branch (64-bit).
2729 case X86::JMP32m: // Indirect branch through mem.
2730 case X86::JMP64m: // Indirect branch through mem (64-bit).
2732 default: return false;
2737 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2738 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2739 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2740 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2742 Cond[0].setImm(GetOppositeBranchCondition(CC));
2747 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2748 // FIXME: Return false for x87 stack register classes for now. We can't
2749 // allow any loads of these registers before FpGet_ST0_80.
2750 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2751 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2754 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2755 switch (Desc->TSFlags & X86II::ImmMask) {
2756 case X86II::Imm8: return 1;
2757 case X86II::Imm16: return 2;
2758 case X86II::Imm32: return 4;
2759 case X86II::Imm64: return 8;
2760 default: llvm_unreachable("Immediate size not set!");
2765 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2766 /// e.g. r8, xmm8, etc.
2767 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2768 if (!MO.isReg()) return false;
2769 switch (MO.getReg()) {
2771 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2772 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2773 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2774 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2775 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2776 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2777 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2778 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2779 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2780 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2787 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2788 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2789 /// size, and 3) use of X86-64 extended registers.
2790 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2792 const TargetInstrDesc &Desc = MI.getDesc();
2794 // Pseudo instructions do not need REX prefix byte.
2795 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2797 if (Desc.TSFlags & X86II::REX_W)
2800 unsigned NumOps = Desc.getNumOperands();
2802 bool isTwoAddr = NumOps > 1 &&
2803 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2805 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2806 unsigned i = isTwoAddr ? 1 : 0;
2807 for (unsigned e = NumOps; i != e; ++i) {
2808 const MachineOperand& MO = MI.getOperand(i);
2810 unsigned Reg = MO.getReg();
2811 if (isX86_64NonExtLowByteReg(Reg))
2816 switch (Desc.TSFlags & X86II::FormMask) {
2817 case X86II::MRMInitReg:
2818 if (isX86_64ExtendedReg(MI.getOperand(0)))
2819 REX |= (1 << 0) | (1 << 2);
2821 case X86II::MRMSrcReg: {
2822 if (isX86_64ExtendedReg(MI.getOperand(0)))
2824 i = isTwoAddr ? 2 : 1;
2825 for (unsigned e = NumOps; i != e; ++i) {
2826 const MachineOperand& MO = MI.getOperand(i);
2827 if (isX86_64ExtendedReg(MO))
2832 case X86II::MRMSrcMem: {
2833 if (isX86_64ExtendedReg(MI.getOperand(0)))
2836 i = isTwoAddr ? 2 : 1;
2837 for (; i != NumOps; ++i) {
2838 const MachineOperand& MO = MI.getOperand(i);
2840 if (isX86_64ExtendedReg(MO))
2847 case X86II::MRM0m: case X86II::MRM1m:
2848 case X86II::MRM2m: case X86II::MRM3m:
2849 case X86II::MRM4m: case X86II::MRM5m:
2850 case X86II::MRM6m: case X86II::MRM7m:
2851 case X86II::MRMDestMem: {
2852 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2853 i = isTwoAddr ? 1 : 0;
2854 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2857 for (; i != e; ++i) {
2858 const MachineOperand& MO = MI.getOperand(i);
2860 if (isX86_64ExtendedReg(MO))
2868 if (isX86_64ExtendedReg(MI.getOperand(0)))
2870 i = isTwoAddr ? 2 : 1;
2871 for (unsigned e = NumOps; i != e; ++i) {
2872 const MachineOperand& MO = MI.getOperand(i);
2873 if (isX86_64ExtendedReg(MO))
2883 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2884 /// relative block address instruction
2886 static unsigned sizePCRelativeBlockAddress() {
2890 /// sizeGlobalAddress - Give the size of the emission of this global address
2892 static unsigned sizeGlobalAddress(bool dword) {
2893 return dword ? 8 : 4;
2896 /// sizeConstPoolAddress - Give the size of the emission of this constant
2899 static unsigned sizeConstPoolAddress(bool dword) {
2900 return dword ? 8 : 4;
2903 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2906 static unsigned sizeExternalSymbolAddress(bool dword) {
2907 return dword ? 8 : 4;
2910 /// sizeJumpTableAddress - Give the size of the emission of this jump
2913 static unsigned sizeJumpTableAddress(bool dword) {
2914 return dword ? 8 : 4;
2917 static unsigned sizeConstant(unsigned Size) {
2921 static unsigned sizeRegModRMByte(){
2925 static unsigned sizeSIBByte(){
2929 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2930 unsigned FinalSize = 0;
2931 // If this is a simple integer displacement that doesn't require a relocation.
2933 FinalSize += sizeConstant(4);
2937 // Otherwise, this is something that requires a relocation.
2938 if (RelocOp->isGlobal()) {
2939 FinalSize += sizeGlobalAddress(false);
2940 } else if (RelocOp->isCPI()) {
2941 FinalSize += sizeConstPoolAddress(false);
2942 } else if (RelocOp->isJTI()) {
2943 FinalSize += sizeJumpTableAddress(false);
2945 llvm_unreachable("Unknown value to relocate!");
2950 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2951 bool IsPIC, bool Is64BitMode) {
2952 const MachineOperand &Op3 = MI.getOperand(Op+3);
2954 const MachineOperand *DispForReloc = 0;
2955 unsigned FinalSize = 0;
2957 // Figure out what sort of displacement we have to handle here.
2958 if (Op3.isGlobal()) {
2959 DispForReloc = &Op3;
2960 } else if (Op3.isCPI()) {
2961 if (Is64BitMode || IsPIC) {
2962 DispForReloc = &Op3;
2966 } else if (Op3.isJTI()) {
2967 if (Is64BitMode || IsPIC) {
2968 DispForReloc = &Op3;
2976 const MachineOperand &Base = MI.getOperand(Op);
2977 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2979 unsigned BaseReg = Base.getReg();
2981 // Is a SIB byte needed?
2982 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2983 IndexReg.getReg() == 0 &&
2984 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2985 if (BaseReg == 0) { // Just a displacement?
2986 // Emit special case [disp32] encoding
2988 FinalSize += getDisplacementFieldSize(DispForReloc);
2990 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2991 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2992 // Emit simple indirect register encoding... [EAX] f.e.
2994 // Be pessimistic and assume it's a disp32, not a disp8
2996 // Emit the most general non-SIB encoding: [REG+disp32]
2998 FinalSize += getDisplacementFieldSize(DispForReloc);
3002 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
3003 assert(IndexReg.getReg() != X86::ESP &&
3004 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3006 bool ForceDisp32 = false;
3007 if (BaseReg == 0 || DispForReloc) {
3008 // Emit the normal disp32 encoding.
3015 FinalSize += sizeSIBByte();
3017 // Do we need to output a displacement?
3018 if (DispVal != 0 || ForceDisp32) {
3019 FinalSize += getDisplacementFieldSize(DispForReloc);
3026 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3027 const TargetInstrDesc *Desc,
3028 bool IsPIC, bool Is64BitMode) {
3030 unsigned Opcode = Desc->Opcode;
3031 unsigned FinalSize = 0;
3033 // Emit the lock opcode prefix as needed.
3034 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3036 // Emit segment override opcode prefix as needed.
3037 switch (Desc->TSFlags & X86II::SegOvrMask) {
3042 default: llvm_unreachable("Invalid segment!");
3043 case 0: break; // No segment override!
3046 // Emit the repeat opcode prefix as needed.
3047 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3049 // Emit the operand size opcode prefix as needed.
3050 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3052 // Emit the address size opcode prefix as needed.
3053 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3055 bool Need0FPrefix = false;
3056 switch (Desc->TSFlags & X86II::Op0Mask) {
3057 case X86II::TB: // Two-byte opcode prefix
3058 case X86II::T8: // 0F 38
3059 case X86II::TA: // 0F 3A
3060 Need0FPrefix = true;
3062 case X86II::TF: // F2 0F 38
3064 Need0FPrefix = true;
3066 case X86II::REP: break; // already handled.
3067 case X86II::XS: // F3 0F
3069 Need0FPrefix = true;
3071 case X86II::XD: // F2 0F
3073 Need0FPrefix = true;
3075 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3076 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3078 break; // Two-byte opcode prefix
3079 default: llvm_unreachable("Invalid prefix!");
3080 case 0: break; // No prefix!
3085 unsigned REX = X86InstrInfo::determineREX(MI);
3090 // 0x0F escape code must be emitted just before the opcode.
3094 switch (Desc->TSFlags & X86II::Op0Mask) {
3095 case X86II::T8: // 0F 38
3098 case X86II::TA: // 0F 3A
3101 case X86II::TF: // F2 0F 38
3106 // If this is a two-address instruction, skip one of the register operands.
3107 unsigned NumOps = Desc->getNumOperands();
3109 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3111 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3112 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3115 switch (Desc->TSFlags & X86II::FormMask) {
3116 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3118 // Remember the current PC offset, this is the PIC relocation
3123 case TargetInstrInfo::INLINEASM: {
3124 const MachineFunction *MF = MI.getParent()->getParent();
3125 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3126 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3127 *MF->getTarget().getMCAsmInfo());
3130 case TargetInstrInfo::DBG_LABEL:
3131 case TargetInstrInfo::EH_LABEL:
3133 case TargetInstrInfo::IMPLICIT_DEF:
3134 case TargetInstrInfo::KILL:
3135 case X86::DWARF_LOC:
3136 case X86::FP_REG_KILL:
3138 case X86::MOVPC32r: {
3139 // This emits the "call" portion of this pseudo instruction.
3141 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3150 if (CurOp != NumOps) {
3151 const MachineOperand &MO = MI.getOperand(CurOp++);
3153 FinalSize += sizePCRelativeBlockAddress();
3154 } else if (MO.isGlobal()) {
3155 FinalSize += sizeGlobalAddress(false);
3156 } else if (MO.isSymbol()) {
3157 FinalSize += sizeExternalSymbolAddress(false);
3158 } else if (MO.isImm()) {
3159 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3161 llvm_unreachable("Unknown RawFrm operand!");
3166 case X86II::AddRegFrm:
3170 if (CurOp != NumOps) {
3171 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3172 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3174 FinalSize += sizeConstant(Size);
3177 if (Opcode == X86::MOV64ri)
3179 if (MO1.isGlobal()) {
3180 FinalSize += sizeGlobalAddress(dword);
3181 } else if (MO1.isSymbol())
3182 FinalSize += sizeExternalSymbolAddress(dword);
3183 else if (MO1.isCPI())
3184 FinalSize += sizeConstPoolAddress(dword);
3185 else if (MO1.isJTI())
3186 FinalSize += sizeJumpTableAddress(dword);
3191 case X86II::MRMDestReg: {
3193 FinalSize += sizeRegModRMByte();
3195 if (CurOp != NumOps) {
3197 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3201 case X86II::MRMDestMem: {
3203 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3204 CurOp += X86AddrNumOperands + 1;
3205 if (CurOp != NumOps) {
3207 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3212 case X86II::MRMSrcReg:
3214 FinalSize += sizeRegModRMByte();
3216 if (CurOp != NumOps) {
3218 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3222 case X86II::MRMSrcMem: {
3224 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3225 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3226 AddrOperands = X86AddrNumOperands - 1; // No segment register
3228 AddrOperands = X86AddrNumOperands;
3231 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3232 CurOp += AddrOperands + 1;
3233 if (CurOp != NumOps) {
3235 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3240 case X86II::MRM0r: case X86II::MRM1r:
3241 case X86II::MRM2r: case X86II::MRM3r:
3242 case X86II::MRM4r: case X86II::MRM5r:
3243 case X86II::MRM6r: case X86II::MRM7r:
3245 if (Desc->getOpcode() == X86::LFENCE ||
3246 Desc->getOpcode() == X86::MFENCE) {
3247 // Special handling of lfence and mfence;
3248 FinalSize += sizeRegModRMByte();
3249 } else if (Desc->getOpcode() == X86::MONITOR ||
3250 Desc->getOpcode() == X86::MWAIT) {
3251 // Special handling of monitor and mwait.
3252 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3255 FinalSize += sizeRegModRMByte();
3258 if (CurOp != NumOps) {
3259 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3260 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3262 FinalSize += sizeConstant(Size);
3265 if (Opcode == X86::MOV64ri32)
3267 if (MO1.isGlobal()) {
3268 FinalSize += sizeGlobalAddress(dword);
3269 } else if (MO1.isSymbol())
3270 FinalSize += sizeExternalSymbolAddress(dword);
3271 else if (MO1.isCPI())
3272 FinalSize += sizeConstPoolAddress(dword);
3273 else if (MO1.isJTI())
3274 FinalSize += sizeJumpTableAddress(dword);
3279 case X86II::MRM0m: case X86II::MRM1m:
3280 case X86II::MRM2m: case X86II::MRM3m:
3281 case X86II::MRM4m: case X86II::MRM5m:
3282 case X86II::MRM6m: case X86II::MRM7m: {
3285 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3286 CurOp += X86AddrNumOperands;
3288 if (CurOp != NumOps) {
3289 const MachineOperand &MO = MI.getOperand(CurOp++);
3290 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3292 FinalSize += sizeConstant(Size);
3295 if (Opcode == X86::MOV64mi32)
3297 if (MO.isGlobal()) {
3298 FinalSize += sizeGlobalAddress(dword);
3299 } else if (MO.isSymbol())
3300 FinalSize += sizeExternalSymbolAddress(dword);
3301 else if (MO.isCPI())
3302 FinalSize += sizeConstPoolAddress(dword);
3303 else if (MO.isJTI())
3304 FinalSize += sizeJumpTableAddress(dword);
3310 case X86II::MRMInitReg:
3312 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3313 FinalSize += sizeRegModRMByte();
3318 if (!Desc->isVariadic() && CurOp != NumOps) {
3320 raw_string_ostream Msg(msg);
3321 Msg << "Cannot determine size: " << MI;
3322 llvm_report_error(Msg.str());
3330 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3331 const TargetInstrDesc &Desc = MI->getDesc();
3332 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3333 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3334 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3335 if (Desc.getOpcode() == X86::MOVPC32r)
3336 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3340 /// getGlobalBaseReg - Return a virtual register initialized with the
3341 /// the global base register value. Output instructions required to
3342 /// initialize the register in the function entry block, if necessary.
3344 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3345 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3346 "X86-64 PIC uses RIP relative addressing");
3348 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3349 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3350 if (GlobalBaseReg != 0)
3351 return GlobalBaseReg;
3353 // Insert the set of GlobalBaseReg into the first MBB of the function
3354 MachineBasicBlock &FirstMBB = MF->front();
3355 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3356 DebugLoc DL = DebugLoc::getUnknownLoc();
3357 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3358 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3359 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3361 const TargetInstrInfo *TII = TM.getInstrInfo();
3362 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3363 // only used in JIT code emission as displacement to pc.
3364 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3366 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3367 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3368 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3369 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3370 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3371 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3372 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3373 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3378 X86FI->setGlobalBaseReg(GlobalBaseReg);
3379 return GlobalBaseReg;