1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetOptions.h"
33 NoFusing("disable-spill-fusing",
34 cl::desc("Disable fusing of spill code into instructions"));
36 PrintFailedFusing("print-failed-fuse-candidates",
37 cl::desc("Print instructions that the allocator wants to"
38 " fuse, but the X86 backend currently can't"),
42 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
43 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
44 TM(tm), RI(tm, *this) {
45 SmallVector<unsigned,16> AmbEntries;
46 static const unsigned OpTbl2Addr[][2] = {
47 { X86::ADC32ri, X86::ADC32mi },
48 { X86::ADC32ri8, X86::ADC32mi8 },
49 { X86::ADC32rr, X86::ADC32mr },
50 { X86::ADC64ri32, X86::ADC64mi32 },
51 { X86::ADC64ri8, X86::ADC64mi8 },
52 { X86::ADC64rr, X86::ADC64mr },
53 { X86::ADD16ri, X86::ADD16mi },
54 { X86::ADD16ri8, X86::ADD16mi8 },
55 { X86::ADD16rr, X86::ADD16mr },
56 { X86::ADD32ri, X86::ADD32mi },
57 { X86::ADD32ri8, X86::ADD32mi8 },
58 { X86::ADD32rr, X86::ADD32mr },
59 { X86::ADD64ri32, X86::ADD64mi32 },
60 { X86::ADD64ri8, X86::ADD64mi8 },
61 { X86::ADD64rr, X86::ADD64mr },
62 { X86::ADD8ri, X86::ADD8mi },
63 { X86::ADD8rr, X86::ADD8mr },
64 { X86::AND16ri, X86::AND16mi },
65 { X86::AND16ri8, X86::AND16mi8 },
66 { X86::AND16rr, X86::AND16mr },
67 { X86::AND32ri, X86::AND32mi },
68 { X86::AND32ri8, X86::AND32mi8 },
69 { X86::AND32rr, X86::AND32mr },
70 { X86::AND64ri32, X86::AND64mi32 },
71 { X86::AND64ri8, X86::AND64mi8 },
72 { X86::AND64rr, X86::AND64mr },
73 { X86::AND8ri, X86::AND8mi },
74 { X86::AND8rr, X86::AND8mr },
75 { X86::DEC16r, X86::DEC16m },
76 { X86::DEC32r, X86::DEC32m },
77 { X86::DEC64_16r, X86::DEC64_16m },
78 { X86::DEC64_32r, X86::DEC64_32m },
79 { X86::DEC64r, X86::DEC64m },
80 { X86::DEC8r, X86::DEC8m },
81 { X86::INC16r, X86::INC16m },
82 { X86::INC32r, X86::INC32m },
83 { X86::INC64_16r, X86::INC64_16m },
84 { X86::INC64_32r, X86::INC64_32m },
85 { X86::INC64r, X86::INC64m },
86 { X86::INC8r, X86::INC8m },
87 { X86::NEG16r, X86::NEG16m },
88 { X86::NEG32r, X86::NEG32m },
89 { X86::NEG64r, X86::NEG64m },
90 { X86::NEG8r, X86::NEG8m },
91 { X86::NOT16r, X86::NOT16m },
92 { X86::NOT32r, X86::NOT32m },
93 { X86::NOT64r, X86::NOT64m },
94 { X86::NOT8r, X86::NOT8m },
95 { X86::OR16ri, X86::OR16mi },
96 { X86::OR16ri8, X86::OR16mi8 },
97 { X86::OR16rr, X86::OR16mr },
98 { X86::OR32ri, X86::OR32mi },
99 { X86::OR32ri8, X86::OR32mi8 },
100 { X86::OR32rr, X86::OR32mr },
101 { X86::OR64ri32, X86::OR64mi32 },
102 { X86::OR64ri8, X86::OR64mi8 },
103 { X86::OR64rr, X86::OR64mr },
104 { X86::OR8ri, X86::OR8mi },
105 { X86::OR8rr, X86::OR8mr },
106 { X86::ROL16r1, X86::ROL16m1 },
107 { X86::ROL16rCL, X86::ROL16mCL },
108 { X86::ROL16ri, X86::ROL16mi },
109 { X86::ROL32r1, X86::ROL32m1 },
110 { X86::ROL32rCL, X86::ROL32mCL },
111 { X86::ROL32ri, X86::ROL32mi },
112 { X86::ROL64r1, X86::ROL64m1 },
113 { X86::ROL64rCL, X86::ROL64mCL },
114 { X86::ROL64ri, X86::ROL64mi },
115 { X86::ROL8r1, X86::ROL8m1 },
116 { X86::ROL8rCL, X86::ROL8mCL },
117 { X86::ROL8ri, X86::ROL8mi },
118 { X86::ROR16r1, X86::ROR16m1 },
119 { X86::ROR16rCL, X86::ROR16mCL },
120 { X86::ROR16ri, X86::ROR16mi },
121 { X86::ROR32r1, X86::ROR32m1 },
122 { X86::ROR32rCL, X86::ROR32mCL },
123 { X86::ROR32ri, X86::ROR32mi },
124 { X86::ROR64r1, X86::ROR64m1 },
125 { X86::ROR64rCL, X86::ROR64mCL },
126 { X86::ROR64ri, X86::ROR64mi },
127 { X86::ROR8r1, X86::ROR8m1 },
128 { X86::ROR8rCL, X86::ROR8mCL },
129 { X86::ROR8ri, X86::ROR8mi },
130 { X86::SAR16r1, X86::SAR16m1 },
131 { X86::SAR16rCL, X86::SAR16mCL },
132 { X86::SAR16ri, X86::SAR16mi },
133 { X86::SAR32r1, X86::SAR32m1 },
134 { X86::SAR32rCL, X86::SAR32mCL },
135 { X86::SAR32ri, X86::SAR32mi },
136 { X86::SAR64r1, X86::SAR64m1 },
137 { X86::SAR64rCL, X86::SAR64mCL },
138 { X86::SAR64ri, X86::SAR64mi },
139 { X86::SAR8r1, X86::SAR8m1 },
140 { X86::SAR8rCL, X86::SAR8mCL },
141 { X86::SAR8ri, X86::SAR8mi },
142 { X86::SBB32ri, X86::SBB32mi },
143 { X86::SBB32ri8, X86::SBB32mi8 },
144 { X86::SBB32rr, X86::SBB32mr },
145 { X86::SBB64ri32, X86::SBB64mi32 },
146 { X86::SBB64ri8, X86::SBB64mi8 },
147 { X86::SBB64rr, X86::SBB64mr },
148 { X86::SHL16rCL, X86::SHL16mCL },
149 { X86::SHL16ri, X86::SHL16mi },
150 { X86::SHL32rCL, X86::SHL32mCL },
151 { X86::SHL32ri, X86::SHL32mi },
152 { X86::SHL64rCL, X86::SHL64mCL },
153 { X86::SHL64ri, X86::SHL64mi },
154 { X86::SHL8rCL, X86::SHL8mCL },
155 { X86::SHL8ri, X86::SHL8mi },
156 { X86::SHLD16rrCL, X86::SHLD16mrCL },
157 { X86::SHLD16rri8, X86::SHLD16mri8 },
158 { X86::SHLD32rrCL, X86::SHLD32mrCL },
159 { X86::SHLD32rri8, X86::SHLD32mri8 },
160 { X86::SHLD64rrCL, X86::SHLD64mrCL },
161 { X86::SHLD64rri8, X86::SHLD64mri8 },
162 { X86::SHR16r1, X86::SHR16m1 },
163 { X86::SHR16rCL, X86::SHR16mCL },
164 { X86::SHR16ri, X86::SHR16mi },
165 { X86::SHR32r1, X86::SHR32m1 },
166 { X86::SHR32rCL, X86::SHR32mCL },
167 { X86::SHR32ri, X86::SHR32mi },
168 { X86::SHR64r1, X86::SHR64m1 },
169 { X86::SHR64rCL, X86::SHR64mCL },
170 { X86::SHR64ri, X86::SHR64mi },
171 { X86::SHR8r1, X86::SHR8m1 },
172 { X86::SHR8rCL, X86::SHR8mCL },
173 { X86::SHR8ri, X86::SHR8mi },
174 { X86::SHRD16rrCL, X86::SHRD16mrCL },
175 { X86::SHRD16rri8, X86::SHRD16mri8 },
176 { X86::SHRD32rrCL, X86::SHRD32mrCL },
177 { X86::SHRD32rri8, X86::SHRD32mri8 },
178 { X86::SHRD64rrCL, X86::SHRD64mrCL },
179 { X86::SHRD64rri8, X86::SHRD64mri8 },
180 { X86::SUB16ri, X86::SUB16mi },
181 { X86::SUB16ri8, X86::SUB16mi8 },
182 { X86::SUB16rr, X86::SUB16mr },
183 { X86::SUB32ri, X86::SUB32mi },
184 { X86::SUB32ri8, X86::SUB32mi8 },
185 { X86::SUB32rr, X86::SUB32mr },
186 { X86::SUB64ri32, X86::SUB64mi32 },
187 { X86::SUB64ri8, X86::SUB64mi8 },
188 { X86::SUB64rr, X86::SUB64mr },
189 { X86::SUB8ri, X86::SUB8mi },
190 { X86::SUB8rr, X86::SUB8mr },
191 { X86::XOR16ri, X86::XOR16mi },
192 { X86::XOR16ri8, X86::XOR16mi8 },
193 { X86::XOR16rr, X86::XOR16mr },
194 { X86::XOR32ri, X86::XOR32mi },
195 { X86::XOR32ri8, X86::XOR32mi8 },
196 { X86::XOR32rr, X86::XOR32mr },
197 { X86::XOR64ri32, X86::XOR64mi32 },
198 { X86::XOR64ri8, X86::XOR64mi8 },
199 { X86::XOR64rr, X86::XOR64mr },
200 { X86::XOR8ri, X86::XOR8mi },
201 { X86::XOR8rr, X86::XOR8mr }
204 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
205 unsigned RegOp = OpTbl2Addr[i][0];
206 unsigned MemOp = OpTbl2Addr[i][1];
207 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
208 assert(false && "Duplicated entries?");
209 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
210 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
211 std::make_pair(RegOp, AuxInfo))))
212 AmbEntries.push_back(MemOp);
215 // If the third value is 1, then it's folding either a load or a store.
216 static const unsigned OpTbl0[][3] = {
217 { X86::CALL32r, X86::CALL32m, 1 },
218 { X86::CALL64r, X86::CALL64m, 1 },
219 { X86::CMP16ri, X86::CMP16mi, 1 },
220 { X86::CMP16ri8, X86::CMP16mi8, 1 },
221 { X86::CMP16rr, X86::CMP16mr, 1 },
222 { X86::CMP32ri, X86::CMP32mi, 1 },
223 { X86::CMP32ri8, X86::CMP32mi8, 1 },
224 { X86::CMP32rr, X86::CMP32mr, 1 },
225 { X86::CMP64ri32, X86::CMP64mi32, 1 },
226 { X86::CMP64ri8, X86::CMP64mi8, 1 },
227 { X86::CMP64rr, X86::CMP64mr, 1 },
228 { X86::CMP8ri, X86::CMP8mi, 1 },
229 { X86::CMP8rr, X86::CMP8mr, 1 },
230 { X86::DIV16r, X86::DIV16m, 1 },
231 { X86::DIV32r, X86::DIV32m, 1 },
232 { X86::DIV64r, X86::DIV64m, 1 },
233 { X86::DIV8r, X86::DIV8m, 1 },
234 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
235 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
236 { X86::IDIV16r, X86::IDIV16m, 1 },
237 { X86::IDIV32r, X86::IDIV32m, 1 },
238 { X86::IDIV64r, X86::IDIV64m, 1 },
239 { X86::IDIV8r, X86::IDIV8m, 1 },
240 { X86::IMUL16r, X86::IMUL16m, 1 },
241 { X86::IMUL32r, X86::IMUL32m, 1 },
242 { X86::IMUL64r, X86::IMUL64m, 1 },
243 { X86::IMUL8r, X86::IMUL8m, 1 },
244 { X86::JMP32r, X86::JMP32m, 1 },
245 { X86::JMP64r, X86::JMP64m, 1 },
246 { X86::MOV16ri, X86::MOV16mi, 0 },
247 { X86::MOV16rr, X86::MOV16mr, 0 },
248 { X86::MOV16to16_, X86::MOV16_mr, 0 },
249 { X86::MOV32ri, X86::MOV32mi, 0 },
250 { X86::MOV32rr, X86::MOV32mr, 0 },
251 { X86::MOV32to32_, X86::MOV32_mr, 0 },
252 { X86::MOV64ri32, X86::MOV64mi32, 0 },
253 { X86::MOV64rr, X86::MOV64mr, 0 },
254 { X86::MOV8ri, X86::MOV8mi, 0 },
255 { X86::MOV8rr, X86::MOV8mr, 0 },
256 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
257 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
258 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
259 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
260 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
261 { X86::MOVSDrr, X86::MOVSDmr, 0 },
262 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
263 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
264 { X86::MOVSSrr, X86::MOVSSmr, 0 },
265 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
266 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
267 { X86::MUL16r, X86::MUL16m, 1 },
268 { X86::MUL32r, X86::MUL32m, 1 },
269 { X86::MUL64r, X86::MUL64m, 1 },
270 { X86::MUL8r, X86::MUL8m, 1 },
271 { X86::SETAEr, X86::SETAEm, 0 },
272 { X86::SETAr, X86::SETAm, 0 },
273 { X86::SETBEr, X86::SETBEm, 0 },
274 { X86::SETBr, X86::SETBm, 0 },
275 { X86::SETEr, X86::SETEm, 0 },
276 { X86::SETGEr, X86::SETGEm, 0 },
277 { X86::SETGr, X86::SETGm, 0 },
278 { X86::SETLEr, X86::SETLEm, 0 },
279 { X86::SETLr, X86::SETLm, 0 },
280 { X86::SETNEr, X86::SETNEm, 0 },
281 { X86::SETNPr, X86::SETNPm, 0 },
282 { X86::SETNSr, X86::SETNSm, 0 },
283 { X86::SETPr, X86::SETPm, 0 },
284 { X86::SETSr, X86::SETSm, 0 },
285 { X86::TAILJMPr, X86::TAILJMPm, 1 },
286 { X86::TEST16ri, X86::TEST16mi, 1 },
287 { X86::TEST32ri, X86::TEST32mi, 1 },
288 { X86::TEST64ri32, X86::TEST64mi32, 1 },
289 { X86::TEST8ri, X86::TEST8mi, 1 }
292 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
293 unsigned RegOp = OpTbl0[i][0];
294 unsigned MemOp = OpTbl0[i][1];
295 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
296 assert(false && "Duplicated entries?");
297 unsigned FoldedLoad = OpTbl0[i][2];
298 // Index 0, folded load or store.
299 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
300 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
301 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
302 std::make_pair(RegOp, AuxInfo))))
303 AmbEntries.push_back(MemOp);
306 static const unsigned OpTbl1[][2] = {
307 { X86::CMP16rr, X86::CMP16rm },
308 { X86::CMP32rr, X86::CMP32rm },
309 { X86::CMP64rr, X86::CMP64rm },
310 { X86::CMP8rr, X86::CMP8rm },
311 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
312 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
313 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
314 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
315 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
316 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
317 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
318 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
319 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
320 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
321 { X86::FsMOVAPDrr, X86::MOVSDrm },
322 { X86::FsMOVAPSrr, X86::MOVSSrm },
323 { X86::IMUL16rri, X86::IMUL16rmi },
324 { X86::IMUL16rri8, X86::IMUL16rmi8 },
325 { X86::IMUL32rri, X86::IMUL32rmi },
326 { X86::IMUL32rri8, X86::IMUL32rmi8 },
327 { X86::IMUL64rri32, X86::IMUL64rmi32 },
328 { X86::IMUL64rri8, X86::IMUL64rmi8 },
329 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
330 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
331 { X86::Int_COMISDrr, X86::Int_COMISDrm },
332 { X86::Int_COMISSrr, X86::Int_COMISSrm },
333 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
334 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
335 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
336 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
337 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
338 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
339 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
340 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
341 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
342 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
343 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
344 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
345 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
346 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
347 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
348 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
349 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
350 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
351 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
352 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
353 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
354 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
355 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
356 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
357 { X86::MOV16rr, X86::MOV16rm },
358 { X86::MOV16to16_, X86::MOV16_rm },
359 { X86::MOV32rr, X86::MOV32rm },
360 { X86::MOV32to32_, X86::MOV32_rm },
361 { X86::MOV64rr, X86::MOV64rm },
362 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
363 { X86::MOV64toSDrr, X86::MOV64toSDrm },
364 { X86::MOV8rr, X86::MOV8rm },
365 { X86::MOVAPDrr, X86::MOVAPDrm },
366 { X86::MOVAPSrr, X86::MOVAPSrm },
367 { X86::MOVDDUPrr, X86::MOVDDUPrm },
368 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
369 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
370 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
371 { X86::MOVSDrr, X86::MOVSDrm },
372 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
373 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
374 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
375 { X86::MOVSSrr, X86::MOVSSrm },
376 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
377 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
378 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
379 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
380 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
381 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
382 { X86::MOVUPDrr, X86::MOVUPDrm },
383 { X86::MOVUPSrr, X86::MOVUPSrm },
384 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
385 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
386 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
387 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
388 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
389 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
390 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
391 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
392 { X86::PSHUFDri, X86::PSHUFDmi },
393 { X86::PSHUFHWri, X86::PSHUFHWmi },
394 { X86::PSHUFLWri, X86::PSHUFLWmi },
395 { X86::RCPPSr, X86::RCPPSm },
396 { X86::RCPPSr_Int, X86::RCPPSm_Int },
397 { X86::RSQRTPSr, X86::RSQRTPSm },
398 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
399 { X86::RSQRTSSr, X86::RSQRTSSm },
400 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
401 { X86::SQRTPDr, X86::SQRTPDm },
402 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
403 { X86::SQRTPSr, X86::SQRTPSm },
404 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
405 { X86::SQRTSDr, X86::SQRTSDm },
406 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
407 { X86::SQRTSSr, X86::SQRTSSm },
408 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
409 { X86::TEST16rr, X86::TEST16rm },
410 { X86::TEST32rr, X86::TEST32rm },
411 { X86::TEST64rr, X86::TEST64rm },
412 { X86::TEST8rr, X86::TEST8rm },
413 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
414 { X86::UCOMISDrr, X86::UCOMISDrm },
415 { X86::UCOMISSrr, X86::UCOMISSrm }
418 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
419 unsigned RegOp = OpTbl1[i][0];
420 unsigned MemOp = OpTbl1[i][1];
421 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
422 assert(false && "Duplicated entries?");
423 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
424 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
425 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
426 std::make_pair(RegOp, AuxInfo))))
427 AmbEntries.push_back(MemOp);
430 static const unsigned OpTbl2[][2] = {
431 { X86::ADC32rr, X86::ADC32rm },
432 { X86::ADC64rr, X86::ADC64rm },
433 { X86::ADD16rr, X86::ADD16rm },
434 { X86::ADD32rr, X86::ADD32rm },
435 { X86::ADD64rr, X86::ADD64rm },
436 { X86::ADD8rr, X86::ADD8rm },
437 { X86::ADDPDrr, X86::ADDPDrm },
438 { X86::ADDPSrr, X86::ADDPSrm },
439 { X86::ADDSDrr, X86::ADDSDrm },
440 { X86::ADDSSrr, X86::ADDSSrm },
441 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
442 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
443 { X86::AND16rr, X86::AND16rm },
444 { X86::AND32rr, X86::AND32rm },
445 { X86::AND64rr, X86::AND64rm },
446 { X86::AND8rr, X86::AND8rm },
447 { X86::ANDNPDrr, X86::ANDNPDrm },
448 { X86::ANDNPSrr, X86::ANDNPSrm },
449 { X86::ANDPDrr, X86::ANDPDrm },
450 { X86::ANDPSrr, X86::ANDPSrm },
451 { X86::CMOVA16rr, X86::CMOVA16rm },
452 { X86::CMOVA32rr, X86::CMOVA32rm },
453 { X86::CMOVA64rr, X86::CMOVA64rm },
454 { X86::CMOVAE16rr, X86::CMOVAE16rm },
455 { X86::CMOVAE32rr, X86::CMOVAE32rm },
456 { X86::CMOVAE64rr, X86::CMOVAE64rm },
457 { X86::CMOVB16rr, X86::CMOVB16rm },
458 { X86::CMOVB32rr, X86::CMOVB32rm },
459 { X86::CMOVB64rr, X86::CMOVB64rm },
460 { X86::CMOVBE16rr, X86::CMOVBE16rm },
461 { X86::CMOVBE32rr, X86::CMOVBE32rm },
462 { X86::CMOVBE64rr, X86::CMOVBE64rm },
463 { X86::CMOVE16rr, X86::CMOVE16rm },
464 { X86::CMOVE32rr, X86::CMOVE32rm },
465 { X86::CMOVE64rr, X86::CMOVE64rm },
466 { X86::CMOVG16rr, X86::CMOVG16rm },
467 { X86::CMOVG32rr, X86::CMOVG32rm },
468 { X86::CMOVG64rr, X86::CMOVG64rm },
469 { X86::CMOVGE16rr, X86::CMOVGE16rm },
470 { X86::CMOVGE32rr, X86::CMOVGE32rm },
471 { X86::CMOVGE64rr, X86::CMOVGE64rm },
472 { X86::CMOVL16rr, X86::CMOVL16rm },
473 { X86::CMOVL32rr, X86::CMOVL32rm },
474 { X86::CMOVL64rr, X86::CMOVL64rm },
475 { X86::CMOVLE16rr, X86::CMOVLE16rm },
476 { X86::CMOVLE32rr, X86::CMOVLE32rm },
477 { X86::CMOVLE64rr, X86::CMOVLE64rm },
478 { X86::CMOVNE16rr, X86::CMOVNE16rm },
479 { X86::CMOVNE32rr, X86::CMOVNE32rm },
480 { X86::CMOVNE64rr, X86::CMOVNE64rm },
481 { X86::CMOVNP16rr, X86::CMOVNP16rm },
482 { X86::CMOVNP32rr, X86::CMOVNP32rm },
483 { X86::CMOVNP64rr, X86::CMOVNP64rm },
484 { X86::CMOVNS16rr, X86::CMOVNS16rm },
485 { X86::CMOVNS32rr, X86::CMOVNS32rm },
486 { X86::CMOVNS64rr, X86::CMOVNS64rm },
487 { X86::CMOVP16rr, X86::CMOVP16rm },
488 { X86::CMOVP32rr, X86::CMOVP32rm },
489 { X86::CMOVP64rr, X86::CMOVP64rm },
490 { X86::CMOVS16rr, X86::CMOVS16rm },
491 { X86::CMOVS32rr, X86::CMOVS32rm },
492 { X86::CMOVS64rr, X86::CMOVS64rm },
493 { X86::CMPPDrri, X86::CMPPDrmi },
494 { X86::CMPPSrri, X86::CMPPSrmi },
495 { X86::CMPSDrr, X86::CMPSDrm },
496 { X86::CMPSSrr, X86::CMPSSrm },
497 { X86::DIVPDrr, X86::DIVPDrm },
498 { X86::DIVPSrr, X86::DIVPSrm },
499 { X86::DIVSDrr, X86::DIVSDrm },
500 { X86::DIVSSrr, X86::DIVSSrm },
501 { X86::FsANDNPDrr, X86::FsANDNPDrm },
502 { X86::FsANDNPSrr, X86::FsANDNPSrm },
503 { X86::FsANDPDrr, X86::FsANDPDrm },
504 { X86::FsANDPSrr, X86::FsANDPSrm },
505 { X86::FsORPDrr, X86::FsORPDrm },
506 { X86::FsORPSrr, X86::FsORPSrm },
507 { X86::FsXORPDrr, X86::FsXORPDrm },
508 { X86::FsXORPSrr, X86::FsXORPSrm },
509 { X86::HADDPDrr, X86::HADDPDrm },
510 { X86::HADDPSrr, X86::HADDPSrm },
511 { X86::HSUBPDrr, X86::HSUBPDrm },
512 { X86::HSUBPSrr, X86::HSUBPSrm },
513 { X86::IMUL16rr, X86::IMUL16rm },
514 { X86::IMUL32rr, X86::IMUL32rm },
515 { X86::IMUL64rr, X86::IMUL64rm },
516 { X86::MAXPDrr, X86::MAXPDrm },
517 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
518 { X86::MAXPSrr, X86::MAXPSrm },
519 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
520 { X86::MAXSDrr, X86::MAXSDrm },
521 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
522 { X86::MAXSSrr, X86::MAXSSrm },
523 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
524 { X86::MINPDrr, X86::MINPDrm },
525 { X86::MINPDrr_Int, X86::MINPDrm_Int },
526 { X86::MINPSrr, X86::MINPSrm },
527 { X86::MINPSrr_Int, X86::MINPSrm_Int },
528 { X86::MINSDrr, X86::MINSDrm },
529 { X86::MINSDrr_Int, X86::MINSDrm_Int },
530 { X86::MINSSrr, X86::MINSSrm },
531 { X86::MINSSrr_Int, X86::MINSSrm_Int },
532 { X86::MULPDrr, X86::MULPDrm },
533 { X86::MULPSrr, X86::MULPSrm },
534 { X86::MULSDrr, X86::MULSDrm },
535 { X86::MULSSrr, X86::MULSSrm },
536 { X86::OR16rr, X86::OR16rm },
537 { X86::OR32rr, X86::OR32rm },
538 { X86::OR64rr, X86::OR64rm },
539 { X86::OR8rr, X86::OR8rm },
540 { X86::ORPDrr, X86::ORPDrm },
541 { X86::ORPSrr, X86::ORPSrm },
542 { X86::PACKSSDWrr, X86::PACKSSDWrm },
543 { X86::PACKSSWBrr, X86::PACKSSWBrm },
544 { X86::PACKUSWBrr, X86::PACKUSWBrm },
545 { X86::PADDBrr, X86::PADDBrm },
546 { X86::PADDDrr, X86::PADDDrm },
547 { X86::PADDQrr, X86::PADDQrm },
548 { X86::PADDSBrr, X86::PADDSBrm },
549 { X86::PADDSWrr, X86::PADDSWrm },
550 { X86::PADDWrr, X86::PADDWrm },
551 { X86::PANDNrr, X86::PANDNrm },
552 { X86::PANDrr, X86::PANDrm },
553 { X86::PAVGBrr, X86::PAVGBrm },
554 { X86::PAVGWrr, X86::PAVGWrm },
555 { X86::PCMPEQBrr, X86::PCMPEQBrm },
556 { X86::PCMPEQDrr, X86::PCMPEQDrm },
557 { X86::PCMPEQWrr, X86::PCMPEQWrm },
558 { X86::PCMPGTBrr, X86::PCMPGTBrm },
559 { X86::PCMPGTDrr, X86::PCMPGTDrm },
560 { X86::PCMPGTWrr, X86::PCMPGTWrm },
561 { X86::PINSRWrri, X86::PINSRWrmi },
562 { X86::PMADDWDrr, X86::PMADDWDrm },
563 { X86::PMAXSWrr, X86::PMAXSWrm },
564 { X86::PMAXUBrr, X86::PMAXUBrm },
565 { X86::PMINSWrr, X86::PMINSWrm },
566 { X86::PMINUBrr, X86::PMINUBrm },
567 { X86::PMULHUWrr, X86::PMULHUWrm },
568 { X86::PMULHWrr, X86::PMULHWrm },
569 { X86::PMULLWrr, X86::PMULLWrm },
570 { X86::PMULUDQrr, X86::PMULUDQrm },
571 { X86::PORrr, X86::PORrm },
572 { X86::PSADBWrr, X86::PSADBWrm },
573 { X86::PSLLDrr, X86::PSLLDrm },
574 { X86::PSLLQrr, X86::PSLLQrm },
575 { X86::PSLLWrr, X86::PSLLWrm },
576 { X86::PSRADrr, X86::PSRADrm },
577 { X86::PSRAWrr, X86::PSRAWrm },
578 { X86::PSRLDrr, X86::PSRLDrm },
579 { X86::PSRLQrr, X86::PSRLQrm },
580 { X86::PSRLWrr, X86::PSRLWrm },
581 { X86::PSUBBrr, X86::PSUBBrm },
582 { X86::PSUBDrr, X86::PSUBDrm },
583 { X86::PSUBSBrr, X86::PSUBSBrm },
584 { X86::PSUBSWrr, X86::PSUBSWrm },
585 { X86::PSUBWrr, X86::PSUBWrm },
586 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
587 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
588 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
589 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
590 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
591 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
592 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
593 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
594 { X86::PXORrr, X86::PXORrm },
595 { X86::SBB32rr, X86::SBB32rm },
596 { X86::SBB64rr, X86::SBB64rm },
597 { X86::SHUFPDrri, X86::SHUFPDrmi },
598 { X86::SHUFPSrri, X86::SHUFPSrmi },
599 { X86::SUB16rr, X86::SUB16rm },
600 { X86::SUB32rr, X86::SUB32rm },
601 { X86::SUB64rr, X86::SUB64rm },
602 { X86::SUB8rr, X86::SUB8rm },
603 { X86::SUBPDrr, X86::SUBPDrm },
604 { X86::SUBPSrr, X86::SUBPSrm },
605 { X86::SUBSDrr, X86::SUBSDrm },
606 { X86::SUBSSrr, X86::SUBSSrm },
607 // FIXME: TEST*rr -> swapped operand of TEST*mr.
608 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
609 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
610 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
611 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
612 { X86::XOR16rr, X86::XOR16rm },
613 { X86::XOR32rr, X86::XOR32rm },
614 { X86::XOR64rr, X86::XOR64rm },
615 { X86::XOR8rr, X86::XOR8rm },
616 { X86::XORPDrr, X86::XORPDrm },
617 { X86::XORPSrr, X86::XORPSrm }
620 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
621 unsigned RegOp = OpTbl2[i][0];
622 unsigned MemOp = OpTbl2[i][1];
623 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
624 assert(false && "Duplicated entries?");
625 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
626 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
627 std::make_pair(RegOp, AuxInfo))))
628 AmbEntries.push_back(MemOp);
631 // Remove ambiguous entries.
632 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
635 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
637 unsigned& destReg) const {
638 switch (MI.getOpcode()) {
645 case X86::MOV16to16_:
646 case X86::MOV32to32_:
650 // FP Stack register class copies
651 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
652 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
653 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
655 case X86::FsMOVAPSrr:
656 case X86::FsMOVAPDrr:
659 case X86::MOVSS2PSrr:
660 case X86::MOVSD2PDrr:
661 case X86::MOVPS2SSrr:
662 case X86::MOVPD2SDrr:
663 case X86::MMX_MOVD64rr:
664 case X86::MMX_MOVQ64rr:
665 assert(MI.getNumOperands() >= 2 &&
666 MI.getOperand(0).isRegister() &&
667 MI.getOperand(1).isRegister() &&
668 "invalid register-register move instruction");
669 sourceReg = MI.getOperand(1).getReg();
670 destReg = MI.getOperand(0).getReg();
675 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
676 int &FrameIndex) const {
677 switch (MI->getOpcode()) {
690 case X86::MMX_MOVD64rm:
691 case X86::MMX_MOVQ64rm:
692 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
693 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
694 MI->getOperand(2).getImm() == 1 &&
695 MI->getOperand(3).getReg() == 0 &&
696 MI->getOperand(4).getImm() == 0) {
697 FrameIndex = MI->getOperand(1).getIndex();
698 return MI->getOperand(0).getReg();
705 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
706 int &FrameIndex) const {
707 switch (MI->getOpcode()) {
720 case X86::MMX_MOVD64mr:
721 case X86::MMX_MOVQ64mr:
722 case X86::MMX_MOVNTQmr:
723 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
724 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
725 MI->getOperand(1).getImm() == 1 &&
726 MI->getOperand(2).getReg() == 0 &&
727 MI->getOperand(3).getImm() == 0) {
728 FrameIndex = MI->getOperand(0).getIndex();
729 return MI->getOperand(4).getReg();
737 static bool regIsPICBase(MachineInstr *MI, unsigned BaseReg) {
738 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
739 bool isPICBase = false;
740 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
741 E = MRI.def_end(); I != E; ++I) {
742 MachineInstr *DefMI = I.getOperand().getParent();
743 if (DefMI->getOpcode() != X86::MOVPC32r)
745 assert(!isPICBase && "More than one PIC base?");
751 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
752 switch (MI->getOpcode()) {
765 case X86::MMX_MOVD64rm:
766 case X86::MMX_MOVQ64rm: {
767 // Loads from constant pools are trivially rematerializable.
768 if (MI->getOperand(1).isReg() &&
769 MI->getOperand(2).isImm() &&
770 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
771 MI->getOperand(4).isCPI()) {
772 unsigned BaseReg = MI->getOperand(1).getReg();
775 // Allow re-materialization of PIC load.
776 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
777 bool isPICBase = false;
778 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
779 E = MRI.def_end(); I != E; ++I) {
780 MachineInstr *DefMI = I.getOperand().getParent();
781 if (DefMI->getOpcode() != X86::MOVPC32r)
783 assert(!isPICBase && "More than one PIC base?");
793 if (MI->getOperand(1).isReg() &&
794 MI->getOperand(2).isImm() &&
795 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
796 !MI->getOperand(4).isReg()) {
797 // lea fi#, lea GV, etc. are all rematerializable.
798 unsigned BaseReg = MI->getOperand(1).getReg();
801 // Allow re-materialization of lea PICBase + x.
802 return regIsPICBase(MI, BaseReg);
808 // All other instructions marked M_REMATERIALIZABLE are always trivially
813 /// isInvariantLoad - Return true if the specified instruction (which is marked
814 /// mayLoad) is loading from a location whose value is invariant across the
815 /// function. For example, loading a value from the constant pool or from
816 /// from the argument area of a function if it does not change. This should
817 /// only return true of *all* loads the instruction does are invariant (if it
818 /// does multiple loads).
819 bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const {
820 // This code cares about loads from three cases: constant pool entries,
821 // invariant argument slots, and global stubs. In order to handle these cases
822 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
823 // operand and base our analysis on it. This is safe because the address of
824 // none of these three cases is ever used as anything other than a load base
825 // and X86 doesn't have any instructions that load from multiple places.
827 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
828 const MachineOperand &MO = MI->getOperand(i);
829 // Loads from constant pools are trivially invariant.
834 if (TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(MO.getGlobal(),
840 // If this is a load from an invariant stack slot, the load is a constant.
842 const MachineFrameInfo &MFI =
843 *MI->getParent()->getParent()->getFrameInfo();
844 int Idx = MO.getIndex();
845 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
849 // All other instances of these instructions are presumed to have other
854 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
855 /// is not marked dead.
856 static bool hasLiveCondCodeDef(MachineInstr *MI) {
857 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
858 MachineOperand &MO = MI->getOperand(i);
859 if (MO.isRegister() && MO.isDef() &&
860 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
867 /// convertToThreeAddress - This method must be implemented by targets that
868 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
869 /// may be able to convert a two-address instruction into a true
870 /// three-address instruction on demand. This allows the X86 target (for
871 /// example) to convert ADD and SHL instructions into LEA instructions if they
872 /// would require register copies due to two-addressness.
874 /// This method returns a null pointer if the transformation cannot be
875 /// performed, otherwise it returns the new instruction.
878 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
879 MachineBasicBlock::iterator &MBBI,
880 LiveVariables &LV) const {
881 MachineInstr *MI = MBBI;
882 // All instructions input are two-addr instructions. Get the known operands.
883 unsigned Dest = MI->getOperand(0).getReg();
884 unsigned Src = MI->getOperand(1).getReg();
886 MachineInstr *NewMI = NULL;
887 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
888 // we have better subtarget support, enable the 16-bit LEA generation here.
889 bool DisableLEA16 = true;
891 unsigned MIOpc = MI->getOpcode();
893 case X86::SHUFPSrri: {
894 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
895 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
897 unsigned A = MI->getOperand(0).getReg();
898 unsigned B = MI->getOperand(1).getReg();
899 unsigned C = MI->getOperand(2).getReg();
900 unsigned M = MI->getOperand(3).getImm();
901 if (B != C) return 0;
902 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
906 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
907 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
908 // the flags produced by a shift yet, so this is safe.
909 unsigned Dest = MI->getOperand(0).getReg();
910 unsigned Src = MI->getOperand(1).getReg();
911 unsigned ShAmt = MI->getOperand(2).getImm();
912 if (ShAmt == 0 || ShAmt >= 4) return 0;
914 NewMI = BuildMI(get(X86::LEA64r), Dest)
915 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
919 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
920 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
921 // the flags produced by a shift yet, so this is safe.
922 unsigned Dest = MI->getOperand(0).getReg();
923 unsigned Src = MI->getOperand(1).getReg();
924 unsigned ShAmt = MI->getOperand(2).getImm();
925 if (ShAmt == 0 || ShAmt >= 4) return 0;
927 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
928 X86::LEA64_32r : X86::LEA32r;
929 NewMI = BuildMI(get(Opc), Dest)
930 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
934 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
935 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
936 // the flags produced by a shift yet, so this is safe.
937 unsigned Dest = MI->getOperand(0).getReg();
938 unsigned Src = MI->getOperand(1).getReg();
939 unsigned ShAmt = MI->getOperand(2).getImm();
940 if (ShAmt == 0 || ShAmt >= 4) return 0;
943 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
944 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
945 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
946 ? X86::LEA64_32r : X86::LEA32r;
947 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
948 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
950 // Build and insert into an implicit UNDEF value. This is OK because
951 // well be shifting and then extracting the lower 16-bits.
952 MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), leaInReg);
955 BuildMI(get(X86::INSERT_SUBREG),leaInReg)
956 .addReg(leaInReg).addReg(Src).addImm(X86::SUBREG_16BIT);
958 NewMI = BuildMI(get(Opc), leaOutReg)
959 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
962 BuildMI(get(X86::EXTRACT_SUBREG), Dest)
963 .addReg(leaOutReg).addImm(X86::SUBREG_16BIT);
964 Ext->copyKillDeadInfo(MI);
966 MFI->insert(MBBI, Undef);
967 MFI->insert(MBBI, Ins); // Insert the insert_subreg
968 LV.instructionChanged(MI, NewMI); // Update live variables
969 LV.addVirtualRegisterKilled(leaInReg, NewMI);
970 MFI->insert(MBBI, NewMI); // Insert the new inst
971 LV.addVirtualRegisterKilled(leaOutReg, Ext);
972 MFI->insert(MBBI, Ext); // Insert the extract_subreg
975 NewMI = BuildMI(get(X86::LEA16r), Dest)
976 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
981 // The following opcodes also sets the condition code register(s). Only
982 // convert them to equivalent lea if the condition code register def's
984 if (hasLiveCondCodeDef(MI))
987 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
992 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
993 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
994 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
995 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
1000 if (DisableLEA16) return 0;
1001 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1002 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
1006 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1007 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1008 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1009 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
1013 case X86::DEC64_16r:
1014 if (DisableLEA16) return 0;
1015 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1016 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
1019 case X86::ADD32rr: {
1020 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1021 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1022 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1023 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
1024 MI->getOperand(2).getReg());
1028 if (DisableLEA16) return 0;
1029 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1030 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
1031 MI->getOperand(2).getReg());
1033 case X86::ADD64ri32:
1035 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1036 if (MI->getOperand(2).isImmediate())
1037 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
1038 MI->getOperand(2).getImm());
1042 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1043 if (MI->getOperand(2).isImmediate()) {
1044 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1045 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
1046 MI->getOperand(2).getImm());
1051 if (DisableLEA16) return 0;
1052 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1053 if (MI->getOperand(2).isImmediate())
1054 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
1055 MI->getOperand(2).getImm());
1058 if (DisableLEA16) return 0;
1060 case X86::SHL64ri: {
1061 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
1062 "Unknown shl instruction!");
1063 unsigned ShAmt = MI->getOperand(2).getImm();
1064 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1066 AM.Scale = 1 << ShAmt;
1068 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1069 : (MIOpc == X86::SHL32ri
1070 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1071 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
1079 if (!NewMI) return 0;
1081 NewMI->copyKillDeadInfo(MI);
1082 LV.instructionChanged(MI, NewMI); // Update live variables
1083 MFI->insert(MBBI, NewMI); // Insert the new inst
1087 /// commuteInstruction - We have a few instructions that must be hacked on to
1090 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
1091 switch (MI->getOpcode()) {
1092 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1093 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1094 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1095 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1096 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1097 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1100 switch (MI->getOpcode()) {
1101 default: assert(0 && "Unreachable!");
1102 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1103 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1104 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1105 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1106 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1107 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1109 unsigned Amt = MI->getOperand(3).getImm();
1110 unsigned A = MI->getOperand(0).getReg();
1111 unsigned B = MI->getOperand(1).getReg();
1112 unsigned C = MI->getOperand(2).getReg();
1113 bool BisKill = MI->getOperand(1).isKill();
1114 bool CisKill = MI->getOperand(2).isKill();
1115 // If machine instrs are no longer in two-address forms, update
1116 // destination register as well.
1118 // Must be two address instruction!
1119 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
1120 "Expecting a two-address instruction!");
1124 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
1125 .addReg(B, false, false, BisKill).addImm(Size-Amt);
1127 case X86::CMOVB16rr:
1128 case X86::CMOVB32rr:
1129 case X86::CMOVB64rr:
1130 case X86::CMOVAE16rr:
1131 case X86::CMOVAE32rr:
1132 case X86::CMOVAE64rr:
1133 case X86::CMOVE16rr:
1134 case X86::CMOVE32rr:
1135 case X86::CMOVE64rr:
1136 case X86::CMOVNE16rr:
1137 case X86::CMOVNE32rr:
1138 case X86::CMOVNE64rr:
1139 case X86::CMOVBE16rr:
1140 case X86::CMOVBE32rr:
1141 case X86::CMOVBE64rr:
1142 case X86::CMOVA16rr:
1143 case X86::CMOVA32rr:
1144 case X86::CMOVA64rr:
1145 case X86::CMOVL16rr:
1146 case X86::CMOVL32rr:
1147 case X86::CMOVL64rr:
1148 case X86::CMOVGE16rr:
1149 case X86::CMOVGE32rr:
1150 case X86::CMOVGE64rr:
1151 case X86::CMOVLE16rr:
1152 case X86::CMOVLE32rr:
1153 case X86::CMOVLE64rr:
1154 case X86::CMOVG16rr:
1155 case X86::CMOVG32rr:
1156 case X86::CMOVG64rr:
1157 case X86::CMOVS16rr:
1158 case X86::CMOVS32rr:
1159 case X86::CMOVS64rr:
1160 case X86::CMOVNS16rr:
1161 case X86::CMOVNS32rr:
1162 case X86::CMOVNS64rr:
1163 case X86::CMOVP16rr:
1164 case X86::CMOVP32rr:
1165 case X86::CMOVP64rr:
1166 case X86::CMOVNP16rr:
1167 case X86::CMOVNP32rr:
1168 case X86::CMOVNP64rr: {
1170 switch (MI->getOpcode()) {
1172 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1173 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1174 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1175 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1176 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1177 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1178 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1179 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1180 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1181 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1182 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1183 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1184 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1185 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1186 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1187 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1188 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1189 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1190 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1191 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1192 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1193 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1194 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1195 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1196 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1197 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1198 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1199 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1200 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1201 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1202 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1203 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1204 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
1205 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1206 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1207 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1208 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1209 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1210 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
1211 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1212 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1213 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1216 MI->setDesc(get(Opc));
1217 // Fallthrough intended.
1220 return TargetInstrInfoImpl::commuteInstruction(MI);
1224 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1226 default: return X86::COND_INVALID;
1227 case X86::JE: return X86::COND_E;
1228 case X86::JNE: return X86::COND_NE;
1229 case X86::JL: return X86::COND_L;
1230 case X86::JLE: return X86::COND_LE;
1231 case X86::JG: return X86::COND_G;
1232 case X86::JGE: return X86::COND_GE;
1233 case X86::JB: return X86::COND_B;
1234 case X86::JBE: return X86::COND_BE;
1235 case X86::JA: return X86::COND_A;
1236 case X86::JAE: return X86::COND_AE;
1237 case X86::JS: return X86::COND_S;
1238 case X86::JNS: return X86::COND_NS;
1239 case X86::JP: return X86::COND_P;
1240 case X86::JNP: return X86::COND_NP;
1241 case X86::JO: return X86::COND_O;
1242 case X86::JNO: return X86::COND_NO;
1246 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1248 default: assert(0 && "Illegal condition code!");
1249 case X86::COND_E: return X86::JE;
1250 case X86::COND_NE: return X86::JNE;
1251 case X86::COND_L: return X86::JL;
1252 case X86::COND_LE: return X86::JLE;
1253 case X86::COND_G: return X86::JG;
1254 case X86::COND_GE: return X86::JGE;
1255 case X86::COND_B: return X86::JB;
1256 case X86::COND_BE: return X86::JBE;
1257 case X86::COND_A: return X86::JA;
1258 case X86::COND_AE: return X86::JAE;
1259 case X86::COND_S: return X86::JS;
1260 case X86::COND_NS: return X86::JNS;
1261 case X86::COND_P: return X86::JP;
1262 case X86::COND_NP: return X86::JNP;
1263 case X86::COND_O: return X86::JO;
1264 case X86::COND_NO: return X86::JNO;
1268 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1269 /// e.g. turning COND_E to COND_NE.
1270 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1272 default: assert(0 && "Illegal condition code!");
1273 case X86::COND_E: return X86::COND_NE;
1274 case X86::COND_NE: return X86::COND_E;
1275 case X86::COND_L: return X86::COND_GE;
1276 case X86::COND_LE: return X86::COND_G;
1277 case X86::COND_G: return X86::COND_LE;
1278 case X86::COND_GE: return X86::COND_L;
1279 case X86::COND_B: return X86::COND_AE;
1280 case X86::COND_BE: return X86::COND_A;
1281 case X86::COND_A: return X86::COND_BE;
1282 case X86::COND_AE: return X86::COND_B;
1283 case X86::COND_S: return X86::COND_NS;
1284 case X86::COND_NS: return X86::COND_S;
1285 case X86::COND_P: return X86::COND_NP;
1286 case X86::COND_NP: return X86::COND_P;
1287 case X86::COND_O: return X86::COND_NO;
1288 case X86::COND_NO: return X86::COND_O;
1292 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1293 const TargetInstrDesc &TID = MI->getDesc();
1294 if (!TID.isTerminator()) return false;
1296 // Conditional branch is a special case.
1297 if (TID.isBranch() && !TID.isBarrier())
1299 if (!TID.isPredicable())
1301 return !isPredicated(MI);
1304 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1305 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1306 const X86InstrInfo &TII) {
1307 if (MI->getOpcode() == X86::FP_REG_KILL)
1309 return TII.isUnpredicatedTerminator(MI);
1312 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1313 MachineBasicBlock *&TBB,
1314 MachineBasicBlock *&FBB,
1315 std::vector<MachineOperand> &Cond) const {
1316 // If the block has no terminators, it just falls into the block after it.
1317 MachineBasicBlock::iterator I = MBB.end();
1318 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
1321 // Get the last instruction in the block.
1322 MachineInstr *LastInst = I;
1324 // If there is only one terminator instruction, process it.
1325 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
1326 if (!LastInst->getDesc().isBranch())
1329 // If the block ends with a branch there are 3 possibilities:
1330 // it's an unconditional, conditional, or indirect branch.
1332 if (LastInst->getOpcode() == X86::JMP) {
1333 TBB = LastInst->getOperand(0).getMBB();
1336 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
1337 if (BranchCode == X86::COND_INVALID)
1338 return true; // Can't handle indirect branch.
1340 // Otherwise, block ends with fall-through condbranch.
1341 TBB = LastInst->getOperand(0).getMBB();
1342 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1346 // Get the instruction before it if it's a terminator.
1347 MachineInstr *SecondLastInst = I;
1349 // If there are three terminators, we don't know what sort of block this is.
1350 if (SecondLastInst && I != MBB.begin() &&
1351 isBrAnalysisUnpredicatedTerminator(--I, *this))
1354 // If the block ends with X86::JMP and a conditional branch, handle it.
1355 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
1356 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
1357 TBB = SecondLastInst->getOperand(0).getMBB();
1358 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1359 FBB = LastInst->getOperand(0).getMBB();
1363 // If the block ends with two X86::JMPs, handle it. The second one is not
1364 // executed, so remove it.
1365 if (SecondLastInst->getOpcode() == X86::JMP &&
1366 LastInst->getOpcode() == X86::JMP) {
1367 TBB = SecondLastInst->getOperand(0).getMBB();
1369 I->eraseFromParent();
1373 // Otherwise, can't handle this.
1377 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1378 MachineBasicBlock::iterator I = MBB.end();
1379 if (I == MBB.begin()) return 0;
1381 if (I->getOpcode() != X86::JMP &&
1382 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1385 // Remove the branch.
1386 I->eraseFromParent();
1390 if (I == MBB.begin()) return 1;
1392 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1395 // Remove the branch.
1396 I->eraseFromParent();
1400 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
1401 MachineOperand &MO) {
1402 if (MO.isRegister())
1403 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
1404 false, false, MO.getSubReg());
1405 else if (MO.isImmediate())
1406 MIB = MIB.addImm(MO.getImm());
1407 else if (MO.isFrameIndex())
1408 MIB = MIB.addFrameIndex(MO.getIndex());
1409 else if (MO.isGlobalAddress())
1410 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
1411 else if (MO.isConstantPoolIndex())
1412 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
1413 else if (MO.isJumpTableIndex())
1414 MIB = MIB.addJumpTableIndex(MO.getIndex());
1415 else if (MO.isExternalSymbol())
1416 MIB = MIB.addExternalSymbol(MO.getSymbolName());
1418 assert(0 && "Unknown operand for X86InstrAddOperand!");
1424 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1425 MachineBasicBlock *FBB,
1426 const std::vector<MachineOperand> &Cond) const {
1427 // Shouldn't be a fall through.
1428 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1429 assert((Cond.size() == 1 || Cond.size() == 0) &&
1430 "X86 branch conditions have one component!");
1432 if (FBB == 0) { // One way branch.
1434 // Unconditional branch?
1435 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
1437 // Conditional branch.
1438 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1439 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1444 // Two-way Conditional branch.
1445 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1446 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1447 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
1451 void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1452 MachineBasicBlock::iterator MI,
1453 unsigned DestReg, unsigned SrcReg,
1454 const TargetRegisterClass *DestRC,
1455 const TargetRegisterClass *SrcRC) const {
1456 if (DestRC == SrcRC) {
1458 if (DestRC == &X86::GR64RegClass) {
1460 } else if (DestRC == &X86::GR32RegClass) {
1462 } else if (DestRC == &X86::GR16RegClass) {
1464 } else if (DestRC == &X86::GR8RegClass) {
1466 } else if (DestRC == &X86::GR32_RegClass) {
1467 Opc = X86::MOV32_rr;
1468 } else if (DestRC == &X86::GR16_RegClass) {
1469 Opc = X86::MOV16_rr;
1470 } else if (DestRC == &X86::RFP32RegClass) {
1471 Opc = X86::MOV_Fp3232;
1472 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
1473 Opc = X86::MOV_Fp6464;
1474 } else if (DestRC == &X86::RFP80RegClass) {
1475 Opc = X86::MOV_Fp8080;
1476 } else if (DestRC == &X86::FR32RegClass) {
1477 Opc = X86::FsMOVAPSrr;
1478 } else if (DestRC == &X86::FR64RegClass) {
1479 Opc = X86::FsMOVAPDrr;
1480 } else if (DestRC == &X86::VR128RegClass) {
1481 Opc = X86::MOVAPSrr;
1482 } else if (DestRC == &X86::VR64RegClass) {
1483 Opc = X86::MMX_MOVQ64rr;
1485 assert(0 && "Unknown regclass");
1488 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
1492 // Moving EFLAGS to / from another register requires a push and a pop.
1493 if (SrcRC == &X86::CCRRegClass) {
1494 assert(SrcReg == X86::EFLAGS);
1495 if (DestRC == &X86::GR64RegClass) {
1496 BuildMI(MBB, MI, get(X86::PUSHFQ));
1497 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
1499 } else if (DestRC == &X86::GR32RegClass) {
1500 BuildMI(MBB, MI, get(X86::PUSHFD));
1501 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
1504 } else if (DestRC == &X86::CCRRegClass) {
1505 assert(DestReg == X86::EFLAGS);
1506 if (SrcRC == &X86::GR64RegClass) {
1507 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
1508 BuildMI(MBB, MI, get(X86::POPFQ));
1510 } else if (SrcRC == &X86::GR32RegClass) {
1511 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
1512 BuildMI(MBB, MI, get(X86::POPFD));
1517 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1518 if (SrcRC == &X86::RSTRegClass) {
1519 // Copying from ST(0)/ST(1).
1520 assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
1521 "Can only copy from ST(0)/ST(1) right now");
1522 bool isST0 = SrcReg == X86::ST0;
1524 if (DestRC == &X86::RFP32RegClass)
1525 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1526 else if (DestRC == &X86::RFP64RegClass)
1527 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1529 assert(DestRC == &X86::RFP80RegClass);
1530 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1532 BuildMI(MBB, MI, get(Opc), DestReg);
1536 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1537 if (DestRC == &X86::RSTRegClass) {
1538 // Copying to ST(0). FIXME: handle ST(1) also
1539 assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
1541 if (SrcRC == &X86::RFP32RegClass)
1542 Opc = X86::FpSET_ST0_32;
1543 else if (SrcRC == &X86::RFP64RegClass)
1544 Opc = X86::FpSET_ST0_64;
1546 assert(SrcRC == &X86::RFP80RegClass);
1547 Opc = X86::FpSET_ST0_80;
1549 BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
1553 assert(0 && "Not yet supported!");
1557 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
1558 unsigned StackAlign) {
1560 if (RC == &X86::GR64RegClass) {
1562 } else if (RC == &X86::GR32RegClass) {
1564 } else if (RC == &X86::GR16RegClass) {
1566 } else if (RC == &X86::GR8RegClass) {
1568 } else if (RC == &X86::GR32_RegClass) {
1569 Opc = X86::MOV32_mr;
1570 } else if (RC == &X86::GR16_RegClass) {
1571 Opc = X86::MOV16_mr;
1572 } else if (RC == &X86::RFP80RegClass) {
1573 Opc = X86::ST_FpP80m; // pops
1574 } else if (RC == &X86::RFP64RegClass) {
1575 Opc = X86::ST_Fp64m;
1576 } else if (RC == &X86::RFP32RegClass) {
1577 Opc = X86::ST_Fp32m;
1578 } else if (RC == &X86::FR32RegClass) {
1580 } else if (RC == &X86::FR64RegClass) {
1582 } else if (RC == &X86::VR128RegClass) {
1583 // FIXME: Use movaps once we are capable of selectively
1584 // aligning functions that spill SSE registers on 16-byte boundaries.
1585 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
1586 } else if (RC == &X86::VR64RegClass) {
1587 Opc = X86::MMX_MOVQ64mr;
1589 assert(0 && "Unknown regclass");
1596 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1597 MachineBasicBlock::iterator MI,
1598 unsigned SrcReg, bool isKill, int FrameIdx,
1599 const TargetRegisterClass *RC) const {
1600 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1601 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
1602 .addReg(SrcReg, false, false, isKill);
1605 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1607 SmallVectorImpl<MachineOperand> &Addr,
1608 const TargetRegisterClass *RC,
1609 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1610 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1611 MachineInstrBuilder MIB = BuildMI(get(Opc));
1612 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1613 MIB = X86InstrAddOperand(MIB, Addr[i]);
1614 MIB.addReg(SrcReg, false, false, isKill);
1615 NewMIs.push_back(MIB);
1618 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
1619 unsigned StackAlign) {
1621 if (RC == &X86::GR64RegClass) {
1623 } else if (RC == &X86::GR32RegClass) {
1625 } else if (RC == &X86::GR16RegClass) {
1627 } else if (RC == &X86::GR8RegClass) {
1629 } else if (RC == &X86::GR32_RegClass) {
1630 Opc = X86::MOV32_rm;
1631 } else if (RC == &X86::GR16_RegClass) {
1632 Opc = X86::MOV16_rm;
1633 } else if (RC == &X86::RFP80RegClass) {
1634 Opc = X86::LD_Fp80m;
1635 } else if (RC == &X86::RFP64RegClass) {
1636 Opc = X86::LD_Fp64m;
1637 } else if (RC == &X86::RFP32RegClass) {
1638 Opc = X86::LD_Fp32m;
1639 } else if (RC == &X86::FR32RegClass) {
1641 } else if (RC == &X86::FR64RegClass) {
1643 } else if (RC == &X86::VR128RegClass) {
1644 // FIXME: Use movaps once we are capable of selectively
1645 // aligning functions that spill SSE registers on 16-byte boundaries.
1646 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
1647 } else if (RC == &X86::VR64RegClass) {
1648 Opc = X86::MMX_MOVQ64rm;
1650 assert(0 && "Unknown regclass");
1657 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1658 MachineBasicBlock::iterator MI,
1659 unsigned DestReg, int FrameIdx,
1660 const TargetRegisterClass *RC) const{
1661 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1662 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
1665 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1666 SmallVectorImpl<MachineOperand> &Addr,
1667 const TargetRegisterClass *RC,
1668 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1669 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1670 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
1671 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1672 MIB = X86InstrAddOperand(MIB, Addr[i]);
1673 NewMIs.push_back(MIB);
1676 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1677 MachineBasicBlock::iterator MI,
1678 const std::vector<CalleeSavedInfo> &CSI) const {
1682 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1683 unsigned SlotSize = is64Bit ? 8 : 4;
1685 MachineFunction &MF = *MBB.getParent();
1686 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1687 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1689 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1690 for (unsigned i = CSI.size(); i != 0; --i) {
1691 unsigned Reg = CSI[i-1].getReg();
1692 // Add the callee-saved register as live-in. It's killed at the spill.
1694 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1699 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1700 MachineBasicBlock::iterator MI,
1701 const std::vector<CalleeSavedInfo> &CSI) const {
1705 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1707 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1708 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1709 unsigned Reg = CSI[i].getReg();
1710 BuildMI(MBB, MI, get(Opc), Reg);
1715 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
1716 SmallVector<MachineOperand,4> &MOs,
1717 MachineInstr *MI, const TargetInstrInfo &TII) {
1718 // Create the base instruction with the memory operand as the first part.
1719 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1720 MachineInstrBuilder MIB(NewMI);
1721 unsigned NumAddrOps = MOs.size();
1722 for (unsigned i = 0; i != NumAddrOps; ++i)
1723 MIB = X86InstrAddOperand(MIB, MOs[i]);
1724 if (NumAddrOps < 4) // FrameIndex only
1725 MIB.addImm(1).addReg(0).addImm(0);
1727 // Loop over the rest of the ri operands, converting them over.
1728 unsigned NumOps = MI->getDesc().getNumOperands()-2;
1729 for (unsigned i = 0; i != NumOps; ++i) {
1730 MachineOperand &MO = MI->getOperand(i+2);
1731 MIB = X86InstrAddOperand(MIB, MO);
1733 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1734 MachineOperand &MO = MI->getOperand(i);
1735 MIB = X86InstrAddOperand(MIB, MO);
1740 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
1741 SmallVector<MachineOperand,4> &MOs,
1742 MachineInstr *MI, const TargetInstrInfo &TII) {
1743 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1744 MachineInstrBuilder MIB(NewMI);
1746 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1747 MachineOperand &MO = MI->getOperand(i);
1749 assert(MO.isRegister() && "Expected to fold into reg operand!");
1750 unsigned NumAddrOps = MOs.size();
1751 for (unsigned i = 0; i != NumAddrOps; ++i)
1752 MIB = X86InstrAddOperand(MIB, MOs[i]);
1753 if (NumAddrOps < 4) // FrameIndex only
1754 MIB.addImm(1).addReg(0).addImm(0);
1756 MIB = X86InstrAddOperand(MIB, MO);
1762 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1763 SmallVector<MachineOperand,4> &MOs,
1765 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
1767 unsigned NumAddrOps = MOs.size();
1768 for (unsigned i = 0; i != NumAddrOps; ++i)
1769 MIB = X86InstrAddOperand(MIB, MOs[i]);
1770 if (NumAddrOps < 4) // FrameIndex only
1771 MIB.addImm(1).addReg(0).addImm(0);
1772 return MIB.addImm(0);
1776 X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
1777 SmallVector<MachineOperand,4> &MOs) const {
1778 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1779 bool isTwoAddrFold = false;
1780 unsigned NumOps = MI->getDesc().getNumOperands();
1781 bool isTwoAddr = NumOps > 1 &&
1782 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1784 MachineInstr *NewMI = NULL;
1785 // Folding a memory location into the two-address part of a two-address
1786 // instruction is different than folding it other places. It requires
1787 // replacing the *two* registers with the memory location.
1788 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1789 MI->getOperand(0).isRegister() &&
1790 MI->getOperand(1).isRegister() &&
1791 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1792 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1793 isTwoAddrFold = true;
1794 } else if (i == 0) { // If operand 0
1795 if (MI->getOpcode() == X86::MOV16r0)
1796 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
1797 else if (MI->getOpcode() == X86::MOV32r0)
1798 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
1799 else if (MI->getOpcode() == X86::MOV64r0)
1800 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
1801 else if (MI->getOpcode() == X86::MOV8r0)
1802 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
1804 NewMI->copyKillDeadInfo(MI);
1808 OpcodeTablePtr = &RegOp2MemOpTable0;
1809 } else if (i == 1) {
1810 OpcodeTablePtr = &RegOp2MemOpTable1;
1811 } else if (i == 2) {
1812 OpcodeTablePtr = &RegOp2MemOpTable2;
1815 // If table selected...
1816 if (OpcodeTablePtr) {
1817 // Find the Opcode to fuse
1818 DenseMap<unsigned*, unsigned>::iterator I =
1819 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1820 if (I != OpcodeTablePtr->end()) {
1822 NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this);
1824 NewMI = FuseInst(I->second, i, MOs, MI, *this);
1825 NewMI->copyKillDeadInfo(MI);
1831 if (PrintFailedFusing)
1832 cerr << "We failed to fuse operand " << i << *MI;
1837 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1839 SmallVectorImpl<unsigned> &Ops,
1840 int FrameIndex) const {
1841 // Check switch flag
1842 if (NoFusing) return NULL;
1844 const MachineFrameInfo *MFI = MF.getFrameInfo();
1845 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
1846 // FIXME: Move alignment requirement into tables?
1847 if (Alignment < 16) {
1848 switch (MI->getOpcode()) {
1850 // Not always safe to fold movsd into these instructions since their load
1851 // folding variants expects the address to be 16 byte aligned.
1852 case X86::FsANDNPDrr:
1853 case X86::FsANDNPSrr:
1854 case X86::FsANDPDrr:
1855 case X86::FsANDPSrr:
1858 case X86::FsXORPDrr:
1859 case X86::FsXORPSrr:
1864 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1865 unsigned NewOpc = 0;
1866 switch (MI->getOpcode()) {
1867 default: return NULL;
1868 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1869 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1870 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1871 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1873 // Change to CMPXXri r, 0 first.
1874 MI->setDesc(get(NewOpc));
1875 MI->getOperand(1).ChangeToImmediate(0);
1876 } else if (Ops.size() != 1)
1879 SmallVector<MachineOperand,4> MOs;
1880 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
1881 return foldMemoryOperand(MI, Ops[0], MOs);
1884 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1886 SmallVectorImpl<unsigned> &Ops,
1887 MachineInstr *LoadMI) const {
1888 // Check switch flag
1889 if (NoFusing) return NULL;
1891 unsigned Alignment = 0;
1892 for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) {
1893 const MemOperand &MRO = LoadMI->getMemOperand(i);
1894 unsigned Align = MRO.getAlignment();
1895 if (Align > Alignment)
1899 // FIXME: Move alignment requirement into tables?
1900 if (Alignment < 16) {
1901 switch (MI->getOpcode()) {
1903 // Not always safe to fold movsd into these instructions since their load
1904 // folding variants expects the address to be 16 byte aligned.
1905 case X86::FsANDNPDrr:
1906 case X86::FsANDNPSrr:
1907 case X86::FsANDPDrr:
1908 case X86::FsANDPSrr:
1911 case X86::FsXORPDrr:
1912 case X86::FsXORPSrr:
1917 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1918 unsigned NewOpc = 0;
1919 switch (MI->getOpcode()) {
1920 default: return NULL;
1921 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1922 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1923 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1924 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1926 // Change to CMPXXri r, 0 first.
1927 MI->setDesc(get(NewOpc));
1928 MI->getOperand(1).ChangeToImmediate(0);
1929 } else if (Ops.size() != 1)
1932 SmallVector<MachineOperand,4> MOs;
1933 unsigned NumOps = LoadMI->getDesc().getNumOperands();
1934 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1935 MOs.push_back(LoadMI->getOperand(i));
1936 return foldMemoryOperand(MI, Ops[0], MOs);
1940 bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
1941 SmallVectorImpl<unsigned> &Ops) const {
1942 // Check switch flag
1943 if (NoFusing) return 0;
1945 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1946 switch (MI->getOpcode()) {
1947 default: return false;
1956 if (Ops.size() != 1)
1959 unsigned OpNum = Ops[0];
1960 unsigned Opc = MI->getOpcode();
1961 unsigned NumOps = MI->getDesc().getNumOperands();
1962 bool isTwoAddr = NumOps > 1 &&
1963 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1965 // Folding a memory location into the two-address part of a two-address
1966 // instruction is different than folding it other places. It requires
1967 // replacing the *two* registers with the memory location.
1968 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1969 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
1970 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1971 } else if (OpNum == 0) { // If operand 0
1980 OpcodeTablePtr = &RegOp2MemOpTable0;
1981 } else if (OpNum == 1) {
1982 OpcodeTablePtr = &RegOp2MemOpTable1;
1983 } else if (OpNum == 2) {
1984 OpcodeTablePtr = &RegOp2MemOpTable2;
1987 if (OpcodeTablePtr) {
1988 // Find the Opcode to fuse
1989 DenseMap<unsigned*, unsigned>::iterator I =
1990 OpcodeTablePtr->find((unsigned*)Opc);
1991 if (I != OpcodeTablePtr->end())
1997 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
1998 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
1999 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2000 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2001 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2002 if (I == MemOp2RegOpTable.end())
2004 unsigned Opc = I->second.first;
2005 unsigned Index = I->second.second & 0xf;
2006 bool FoldedLoad = I->second.second & (1 << 4);
2007 bool FoldedStore = I->second.second & (1 << 5);
2008 if (UnfoldLoad && !FoldedLoad)
2010 UnfoldLoad &= FoldedLoad;
2011 if (UnfoldStore && !FoldedStore)
2013 UnfoldStore &= FoldedStore;
2015 const TargetInstrDesc &TID = get(Opc);
2016 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2017 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2018 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2019 SmallVector<MachineOperand,4> AddrOps;
2020 SmallVector<MachineOperand,2> BeforeOps;
2021 SmallVector<MachineOperand,2> AfterOps;
2022 SmallVector<MachineOperand,4> ImpOps;
2023 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2024 MachineOperand &Op = MI->getOperand(i);
2025 if (i >= Index && i < Index+4)
2026 AddrOps.push_back(Op);
2027 else if (Op.isRegister() && Op.isImplicit())
2028 ImpOps.push_back(Op);
2030 BeforeOps.push_back(Op);
2032 AfterOps.push_back(Op);
2035 // Emit the load instruction.
2037 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2039 // Address operands cannot be marked isKill.
2040 for (unsigned i = 1; i != 5; ++i) {
2041 MachineOperand &MO = NewMIs[0]->getOperand(i);
2042 if (MO.isRegister())
2043 MO.setIsKill(false);
2048 // Emit the data processing instruction.
2049 MachineInstr *DataMI = new MachineInstr(TID, true);
2050 MachineInstrBuilder MIB(DataMI);
2053 MIB.addReg(Reg, true);
2054 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2055 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
2058 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2059 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
2060 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2061 MachineOperand &MO = ImpOps[i];
2062 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
2064 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2065 unsigned NewOpc = 0;
2066 switch (DataMI->getOpcode()) {
2068 case X86::CMP64ri32:
2072 MachineOperand &MO0 = DataMI->getOperand(0);
2073 MachineOperand &MO1 = DataMI->getOperand(1);
2074 if (MO1.getImm() == 0) {
2075 switch (DataMI->getOpcode()) {
2077 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2078 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2079 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2080 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2082 DataMI->setDesc(get(NewOpc));
2083 MO1.ChangeToRegister(MO0.getReg(), false);
2087 NewMIs.push_back(DataMI);
2089 // Emit the store instruction.
2091 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2092 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2093 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2094 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2101 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2102 SmallVectorImpl<SDNode*> &NewNodes) const {
2103 if (!N->isTargetOpcode())
2106 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2107 MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode());
2108 if (I == MemOp2RegOpTable.end())
2110 unsigned Opc = I->second.first;
2111 unsigned Index = I->second.second & 0xf;
2112 bool FoldedLoad = I->second.second & (1 << 4);
2113 bool FoldedStore = I->second.second & (1 << 5);
2114 const TargetInstrDesc &TID = get(Opc);
2115 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2116 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2117 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2118 std::vector<SDOperand> AddrOps;
2119 std::vector<SDOperand> BeforeOps;
2120 std::vector<SDOperand> AfterOps;
2121 unsigned NumOps = N->getNumOperands();
2122 for (unsigned i = 0; i != NumOps-1; ++i) {
2123 SDOperand Op = N->getOperand(i);
2124 if (i >= Index && i < Index+4)
2125 AddrOps.push_back(Op);
2127 BeforeOps.push_back(Op);
2129 AfterOps.push_back(Op);
2131 SDOperand Chain = N->getOperand(NumOps-1);
2132 AddrOps.push_back(Chain);
2134 // Emit the load instruction.
2137 MVT::ValueType VT = *RC->vt_begin();
2138 Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT,
2139 MVT::Other, &AddrOps[0], AddrOps.size());
2140 NewNodes.push_back(Load);
2143 // Emit the data processing instruction.
2144 std::vector<MVT::ValueType> VTs;
2145 const TargetRegisterClass *DstRC = 0;
2146 if (TID.getNumDefs() > 0) {
2147 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2148 DstRC = DstTOI.isLookupPtrRegClass()
2149 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2150 VTs.push_back(*DstRC->vt_begin());
2152 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2153 MVT::ValueType VT = N->getValueType(i);
2154 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2158 BeforeOps.push_back(SDOperand(Load, 0));
2159 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2160 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
2161 NewNodes.push_back(NewNode);
2163 // Emit the store instruction.
2166 AddrOps.push_back(SDOperand(NewNode, 0));
2167 AddrOps.push_back(Chain);
2168 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, RI.getStackAlignment()),
2169 MVT::Other, &AddrOps[0], AddrOps.size());
2170 NewNodes.push_back(Store);
2176 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2177 bool UnfoldLoad, bool UnfoldStore) const {
2178 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2179 MemOp2RegOpTable.find((unsigned*)Opc);
2180 if (I == MemOp2RegOpTable.end())
2182 bool FoldedLoad = I->second.second & (1 << 4);
2183 bool FoldedStore = I->second.second & (1 << 5);
2184 if (UnfoldLoad && !FoldedLoad)
2186 if (UnfoldStore && !FoldedStore)
2188 return I->second.first;
2191 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
2192 if (MBB.empty()) return false;
2194 switch (MBB.back().getOpcode()) {
2195 case X86::TCRETURNri:
2196 case X86::TCRETURNdi:
2197 case X86::RET: // Return.
2202 case X86::JMP: // Uncond branch.
2203 case X86::JMP32r: // Indirect branch.
2204 case X86::JMP64r: // Indirect branch (64-bit).
2205 case X86::JMP32m: // Indirect branch through mem.
2206 case X86::JMP64m: // Indirect branch through mem (64-bit).
2208 default: return false;
2213 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
2214 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2215 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
2219 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
2220 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
2221 if (Subtarget->is64Bit())
2222 return &X86::GR64RegClass;
2224 return &X86::GR32RegClass;