1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/MC/MCAsmInfo.h"
43 NoFusing("disable-spill-fusing",
44 cl::desc("Disable fusing of spill code into instructions"));
46 PrintFailedFusing("print-failed-fuse-candidates",
47 cl::desc("Print instructions that the allocator wants to"
48 " fuse, but the X86 backend currently can't"),
51 ReMatPICStubLoad("remat-pic-stub-load",
52 cl::desc("Re-materialize load from stub in PIC mode"),
53 cl::init(false), cl::Hidden);
55 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
56 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
57 TM(tm), RI(tm, *this) {
58 SmallVector<unsigned,16> AmbEntries;
59 static const unsigned OpTbl2Addr[][2] = {
60 { X86::ADC32ri, X86::ADC32mi },
61 { X86::ADC32ri8, X86::ADC32mi8 },
62 { X86::ADC32rr, X86::ADC32mr },
63 { X86::ADC64ri32, X86::ADC64mi32 },
64 { X86::ADC64ri8, X86::ADC64mi8 },
65 { X86::ADC64rr, X86::ADC64mr },
66 { X86::ADD16ri, X86::ADD16mi },
67 { X86::ADD16ri8, X86::ADD16mi8 },
68 { X86::ADD16rr, X86::ADD16mr },
69 { X86::ADD32ri, X86::ADD32mi },
70 { X86::ADD32ri8, X86::ADD32mi8 },
71 { X86::ADD32rr, X86::ADD32mr },
72 { X86::ADD64ri32, X86::ADD64mi32 },
73 { X86::ADD64ri8, X86::ADD64mi8 },
74 { X86::ADD64rr, X86::ADD64mr },
75 { X86::ADD8ri, X86::ADD8mi },
76 { X86::ADD8rr, X86::ADD8mr },
77 { X86::AND16ri, X86::AND16mi },
78 { X86::AND16ri8, X86::AND16mi8 },
79 { X86::AND16rr, X86::AND16mr },
80 { X86::AND32ri, X86::AND32mi },
81 { X86::AND32ri8, X86::AND32mi8 },
82 { X86::AND32rr, X86::AND32mr },
83 { X86::AND64ri32, X86::AND64mi32 },
84 { X86::AND64ri8, X86::AND64mi8 },
85 { X86::AND64rr, X86::AND64mr },
86 { X86::AND8ri, X86::AND8mi },
87 { X86::AND8rr, X86::AND8mr },
88 { X86::DEC16r, X86::DEC16m },
89 { X86::DEC32r, X86::DEC32m },
90 { X86::DEC64_16r, X86::DEC64_16m },
91 { X86::DEC64_32r, X86::DEC64_32m },
92 { X86::DEC64r, X86::DEC64m },
93 { X86::DEC8r, X86::DEC8m },
94 { X86::INC16r, X86::INC16m },
95 { X86::INC32r, X86::INC32m },
96 { X86::INC64_16r, X86::INC64_16m },
97 { X86::INC64_32r, X86::INC64_32m },
98 { X86::INC64r, X86::INC64m },
99 { X86::INC8r, X86::INC8m },
100 { X86::NEG16r, X86::NEG16m },
101 { X86::NEG32r, X86::NEG32m },
102 { X86::NEG64r, X86::NEG64m },
103 { X86::NEG8r, X86::NEG8m },
104 { X86::NOT16r, X86::NOT16m },
105 { X86::NOT32r, X86::NOT32m },
106 { X86::NOT64r, X86::NOT64m },
107 { X86::NOT8r, X86::NOT8m },
108 { X86::OR16ri, X86::OR16mi },
109 { X86::OR16ri8, X86::OR16mi8 },
110 { X86::OR16rr, X86::OR16mr },
111 { X86::OR32ri, X86::OR32mi },
112 { X86::OR32ri8, X86::OR32mi8 },
113 { X86::OR32rr, X86::OR32mr },
114 { X86::OR64ri32, X86::OR64mi32 },
115 { X86::OR64ri8, X86::OR64mi8 },
116 { X86::OR64rr, X86::OR64mr },
117 { X86::OR8ri, X86::OR8mi },
118 { X86::OR8rr, X86::OR8mr },
119 { X86::ROL16r1, X86::ROL16m1 },
120 { X86::ROL16rCL, X86::ROL16mCL },
121 { X86::ROL16ri, X86::ROL16mi },
122 { X86::ROL32r1, X86::ROL32m1 },
123 { X86::ROL32rCL, X86::ROL32mCL },
124 { X86::ROL32ri, X86::ROL32mi },
125 { X86::ROL64r1, X86::ROL64m1 },
126 { X86::ROL64rCL, X86::ROL64mCL },
127 { X86::ROL64ri, X86::ROL64mi },
128 { X86::ROL8r1, X86::ROL8m1 },
129 { X86::ROL8rCL, X86::ROL8mCL },
130 { X86::ROL8ri, X86::ROL8mi },
131 { X86::ROR16r1, X86::ROR16m1 },
132 { X86::ROR16rCL, X86::ROR16mCL },
133 { X86::ROR16ri, X86::ROR16mi },
134 { X86::ROR32r1, X86::ROR32m1 },
135 { X86::ROR32rCL, X86::ROR32mCL },
136 { X86::ROR32ri, X86::ROR32mi },
137 { X86::ROR64r1, X86::ROR64m1 },
138 { X86::ROR64rCL, X86::ROR64mCL },
139 { X86::ROR64ri, X86::ROR64mi },
140 { X86::ROR8r1, X86::ROR8m1 },
141 { X86::ROR8rCL, X86::ROR8mCL },
142 { X86::ROR8ri, X86::ROR8mi },
143 { X86::SAR16r1, X86::SAR16m1 },
144 { X86::SAR16rCL, X86::SAR16mCL },
145 { X86::SAR16ri, X86::SAR16mi },
146 { X86::SAR32r1, X86::SAR32m1 },
147 { X86::SAR32rCL, X86::SAR32mCL },
148 { X86::SAR32ri, X86::SAR32mi },
149 { X86::SAR64r1, X86::SAR64m1 },
150 { X86::SAR64rCL, X86::SAR64mCL },
151 { X86::SAR64ri, X86::SAR64mi },
152 { X86::SAR8r1, X86::SAR8m1 },
153 { X86::SAR8rCL, X86::SAR8mCL },
154 { X86::SAR8ri, X86::SAR8mi },
155 { X86::SBB32ri, X86::SBB32mi },
156 { X86::SBB32ri8, X86::SBB32mi8 },
157 { X86::SBB32rr, X86::SBB32mr },
158 { X86::SBB64ri32, X86::SBB64mi32 },
159 { X86::SBB64ri8, X86::SBB64mi8 },
160 { X86::SBB64rr, X86::SBB64mr },
161 { X86::SHL16rCL, X86::SHL16mCL },
162 { X86::SHL16ri, X86::SHL16mi },
163 { X86::SHL32rCL, X86::SHL32mCL },
164 { X86::SHL32ri, X86::SHL32mi },
165 { X86::SHL64rCL, X86::SHL64mCL },
166 { X86::SHL64ri, X86::SHL64mi },
167 { X86::SHL8rCL, X86::SHL8mCL },
168 { X86::SHL8ri, X86::SHL8mi },
169 { X86::SHLD16rrCL, X86::SHLD16mrCL },
170 { X86::SHLD16rri8, X86::SHLD16mri8 },
171 { X86::SHLD32rrCL, X86::SHLD32mrCL },
172 { X86::SHLD32rri8, X86::SHLD32mri8 },
173 { X86::SHLD64rrCL, X86::SHLD64mrCL },
174 { X86::SHLD64rri8, X86::SHLD64mri8 },
175 { X86::SHR16r1, X86::SHR16m1 },
176 { X86::SHR16rCL, X86::SHR16mCL },
177 { X86::SHR16ri, X86::SHR16mi },
178 { X86::SHR32r1, X86::SHR32m1 },
179 { X86::SHR32rCL, X86::SHR32mCL },
180 { X86::SHR32ri, X86::SHR32mi },
181 { X86::SHR64r1, X86::SHR64m1 },
182 { X86::SHR64rCL, X86::SHR64mCL },
183 { X86::SHR64ri, X86::SHR64mi },
184 { X86::SHR8r1, X86::SHR8m1 },
185 { X86::SHR8rCL, X86::SHR8mCL },
186 { X86::SHR8ri, X86::SHR8mi },
187 { X86::SHRD16rrCL, X86::SHRD16mrCL },
188 { X86::SHRD16rri8, X86::SHRD16mri8 },
189 { X86::SHRD32rrCL, X86::SHRD32mrCL },
190 { X86::SHRD32rri8, X86::SHRD32mri8 },
191 { X86::SHRD64rrCL, X86::SHRD64mrCL },
192 { X86::SHRD64rri8, X86::SHRD64mri8 },
193 { X86::SUB16ri, X86::SUB16mi },
194 { X86::SUB16ri8, X86::SUB16mi8 },
195 { X86::SUB16rr, X86::SUB16mr },
196 { X86::SUB32ri, X86::SUB32mi },
197 { X86::SUB32ri8, X86::SUB32mi8 },
198 { X86::SUB32rr, X86::SUB32mr },
199 { X86::SUB64ri32, X86::SUB64mi32 },
200 { X86::SUB64ri8, X86::SUB64mi8 },
201 { X86::SUB64rr, X86::SUB64mr },
202 { X86::SUB8ri, X86::SUB8mi },
203 { X86::SUB8rr, X86::SUB8mr },
204 { X86::XOR16ri, X86::XOR16mi },
205 { X86::XOR16ri8, X86::XOR16mi8 },
206 { X86::XOR16rr, X86::XOR16mr },
207 { X86::XOR32ri, X86::XOR32mi },
208 { X86::XOR32ri8, X86::XOR32mi8 },
209 { X86::XOR32rr, X86::XOR32mr },
210 { X86::XOR64ri32, X86::XOR64mi32 },
211 { X86::XOR64ri8, X86::XOR64mi8 },
212 { X86::XOR64rr, X86::XOR64mr },
213 { X86::XOR8ri, X86::XOR8mi },
214 { X86::XOR8rr, X86::XOR8mr }
217 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
218 unsigned RegOp = OpTbl2Addr[i][0];
219 unsigned MemOp = OpTbl2Addr[i][1];
220 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
221 std::make_pair(MemOp,0))).second)
222 assert(false && "Duplicated entries?");
223 // Index 0, folded load and store, no alignment requirement.
224 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
225 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
226 std::make_pair(RegOp,
228 AmbEntries.push_back(MemOp);
231 // If the third value is 1, then it's folding either a load or a store.
232 static const unsigned OpTbl0[][4] = {
233 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
234 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
235 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
236 { X86::CALL32r, X86::CALL32m, 1, 0 },
237 { X86::CALL64r, X86::CALL64m, 1, 0 },
238 { X86::WINCALL64r, X86::WINCALL64m, 1, 0 },
239 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
240 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
241 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
242 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
243 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
244 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
245 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
246 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
247 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
248 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
249 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
250 { X86::DIV16r, X86::DIV16m, 1, 0 },
251 { X86::DIV32r, X86::DIV32m, 1, 0 },
252 { X86::DIV64r, X86::DIV64m, 1, 0 },
253 { X86::DIV8r, X86::DIV8m, 1, 0 },
254 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
255 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
256 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
257 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
258 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
259 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
260 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
261 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
262 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
263 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
264 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
265 { X86::JMP32r, X86::JMP32m, 1, 0 },
266 { X86::JMP64r, X86::JMP64m, 1, 0 },
267 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
268 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
269 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
270 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
271 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 },
272 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
273 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
274 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
275 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
276 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
277 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
278 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
279 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
280 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
281 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
282 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
283 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
284 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
285 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
286 { X86::MUL16r, X86::MUL16m, 1, 0 },
287 { X86::MUL32r, X86::MUL32m, 1, 0 },
288 { X86::MUL64r, X86::MUL64m, 1, 0 },
289 { X86::MUL8r, X86::MUL8m, 1, 0 },
290 { X86::SETAEr, X86::SETAEm, 0, 0 },
291 { X86::SETAr, X86::SETAm, 0, 0 },
292 { X86::SETBEr, X86::SETBEm, 0, 0 },
293 { X86::SETBr, X86::SETBm, 0, 0 },
294 { X86::SETEr, X86::SETEm, 0, 0 },
295 { X86::SETGEr, X86::SETGEm, 0, 0 },
296 { X86::SETGr, X86::SETGm, 0, 0 },
297 { X86::SETLEr, X86::SETLEm, 0, 0 },
298 { X86::SETLr, X86::SETLm, 0, 0 },
299 { X86::SETNEr, X86::SETNEm, 0, 0 },
300 { X86::SETNOr, X86::SETNOm, 0, 0 },
301 { X86::SETNPr, X86::SETNPm, 0, 0 },
302 { X86::SETNSr, X86::SETNSm, 0, 0 },
303 { X86::SETOr, X86::SETOm, 0, 0 },
304 { X86::SETPr, X86::SETPm, 0, 0 },
305 { X86::SETSr, X86::SETSm, 0, 0 },
306 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
307 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
308 { X86::WINTAILJMPr64,X86::WINTAILJMPm64, 1, 0 },
309 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
310 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
311 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
312 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
315 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
316 unsigned RegOp = OpTbl0[i][0];
317 unsigned MemOp = OpTbl0[i][1];
318 unsigned Align = OpTbl0[i][3];
319 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
320 std::make_pair(MemOp,Align))).second)
321 assert(false && "Duplicated entries?");
322 unsigned FoldedLoad = OpTbl0[i][2];
323 // Index 0, folded load or store.
324 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
325 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
326 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
327 std::make_pair(RegOp, AuxInfo))).second)
328 AmbEntries.push_back(MemOp);
331 static const unsigned OpTbl1[][3] = {
332 { X86::CMP16rr, X86::CMP16rm, 0 },
333 { X86::CMP32rr, X86::CMP32rm, 0 },
334 { X86::CMP64rr, X86::CMP64rm, 0 },
335 { X86::CMP8rr, X86::CMP8rm, 0 },
336 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
337 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
338 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
339 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
340 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
341 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
342 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
343 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
344 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
345 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
346 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
347 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
348 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
349 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
350 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
351 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
352 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
353 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
354 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
355 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
356 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
357 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
358 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
359 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
360 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
361 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
362 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
363 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
364 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
365 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
366 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
367 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
368 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
369 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
370 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
371 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
372 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
373 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
374 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
375 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
376 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
377 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
378 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
379 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
380 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
381 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
382 { X86::MOV16rr, X86::MOV16rm, 0 },
383 { X86::MOV32rr, X86::MOV32rm, 0 },
384 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 },
385 { X86::MOV64rr, X86::MOV64rm, 0 },
386 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
387 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
388 { X86::MOV8rr, X86::MOV8rm, 0 },
389 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
390 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
391 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
392 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
393 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
394 { X86::MOVDQArr, X86::MOVDQArm, 16 },
395 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
396 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
397 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
398 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
399 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
400 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
401 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
402 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
403 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
404 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
405 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
406 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
407 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
408 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
409 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
410 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
411 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
412 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
413 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
414 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
415 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
416 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
417 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
418 { X86::RCPPSr, X86::RCPPSm, 16 },
419 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
420 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
421 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
422 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
423 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
424 { X86::SQRTPDr, X86::SQRTPDm, 16 },
425 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
426 { X86::SQRTPSr, X86::SQRTPSm, 16 },
427 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
428 { X86::SQRTSDr, X86::SQRTSDm, 0 },
429 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
430 { X86::SQRTSSr, X86::SQRTSSm, 0 },
431 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
432 { X86::TEST16rr, X86::TEST16rm, 0 },
433 { X86::TEST32rr, X86::TEST32rm, 0 },
434 { X86::TEST64rr, X86::TEST64rm, 0 },
435 { X86::TEST8rr, X86::TEST8rm, 0 },
436 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
437 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
438 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
441 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
442 unsigned RegOp = OpTbl1[i][0];
443 unsigned MemOp = OpTbl1[i][1];
444 unsigned Align = OpTbl1[i][2];
445 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
446 std::make_pair(MemOp,Align))).second)
447 assert(false && "Duplicated entries?");
448 // Index 1, folded load
449 unsigned AuxInfo = 1 | (1 << 4);
450 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
451 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
452 std::make_pair(RegOp, AuxInfo))).second)
453 AmbEntries.push_back(MemOp);
456 static const unsigned OpTbl2[][3] = {
457 { X86::ADC32rr, X86::ADC32rm, 0 },
458 { X86::ADC64rr, X86::ADC64rm, 0 },
459 { X86::ADD16rr, X86::ADD16rm, 0 },
460 { X86::ADD32rr, X86::ADD32rm, 0 },
461 { X86::ADD64rr, X86::ADD64rm, 0 },
462 { X86::ADD8rr, X86::ADD8rm, 0 },
463 { X86::ADDPDrr, X86::ADDPDrm, 16 },
464 { X86::ADDPSrr, X86::ADDPSrm, 16 },
465 { X86::ADDSDrr, X86::ADDSDrm, 0 },
466 { X86::ADDSSrr, X86::ADDSSrm, 0 },
467 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
468 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
469 { X86::AND16rr, X86::AND16rm, 0 },
470 { X86::AND32rr, X86::AND32rm, 0 },
471 { X86::AND64rr, X86::AND64rm, 0 },
472 { X86::AND8rr, X86::AND8rm, 0 },
473 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
474 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
475 { X86::ANDPDrr, X86::ANDPDrm, 16 },
476 { X86::ANDPSrr, X86::ANDPSrm, 16 },
477 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
478 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
479 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
480 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
481 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
482 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
483 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
484 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
485 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
486 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
487 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
488 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
489 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
490 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
491 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
492 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
493 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
494 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
495 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
496 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
497 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
498 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
499 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
500 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
501 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
502 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
503 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
504 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
505 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
506 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
507 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
508 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
509 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
510 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
511 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
512 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
513 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
514 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
515 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
516 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
517 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
518 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
519 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
520 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
521 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
522 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
523 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
524 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
525 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
526 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
527 { X86::CMPSDrr, X86::CMPSDrm, 0 },
528 { X86::CMPSSrr, X86::CMPSSrm, 0 },
529 { X86::DIVPDrr, X86::DIVPDrm, 16 },
530 { X86::DIVPSrr, X86::DIVPSrm, 16 },
531 { X86::DIVSDrr, X86::DIVSDrm, 0 },
532 { X86::DIVSSrr, X86::DIVSSrm, 0 },
533 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
534 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
535 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
536 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
537 { X86::FsORPDrr, X86::FsORPDrm, 16 },
538 { X86::FsORPSrr, X86::FsORPSrm, 16 },
539 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
540 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
541 { X86::HADDPDrr, X86::HADDPDrm, 16 },
542 { X86::HADDPSrr, X86::HADDPSrm, 16 },
543 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
544 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
545 { X86::IMUL16rr, X86::IMUL16rm, 0 },
546 { X86::IMUL32rr, X86::IMUL32rm, 0 },
547 { X86::IMUL64rr, X86::IMUL64rm, 0 },
548 { X86::MAXPDrr, X86::MAXPDrm, 16 },
549 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
550 { X86::MAXPSrr, X86::MAXPSrm, 16 },
551 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
552 { X86::MAXSDrr, X86::MAXSDrm, 0 },
553 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
554 { X86::MAXSSrr, X86::MAXSSrm, 0 },
555 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
556 { X86::MINPDrr, X86::MINPDrm, 16 },
557 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
558 { X86::MINPSrr, X86::MINPSrm, 16 },
559 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
560 { X86::MINSDrr, X86::MINSDrm, 0 },
561 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
562 { X86::MINSSrr, X86::MINSSrm, 0 },
563 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
564 { X86::MULPDrr, X86::MULPDrm, 16 },
565 { X86::MULPSrr, X86::MULPSrm, 16 },
566 { X86::MULSDrr, X86::MULSDrm, 0 },
567 { X86::MULSSrr, X86::MULSSrm, 0 },
568 { X86::OR16rr, X86::OR16rm, 0 },
569 { X86::OR32rr, X86::OR32rm, 0 },
570 { X86::OR64rr, X86::OR64rm, 0 },
571 { X86::OR8rr, X86::OR8rm, 0 },
572 { X86::ORPDrr, X86::ORPDrm, 16 },
573 { X86::ORPSrr, X86::ORPSrm, 16 },
574 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
575 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
576 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
577 { X86::PADDBrr, X86::PADDBrm, 16 },
578 { X86::PADDDrr, X86::PADDDrm, 16 },
579 { X86::PADDQrr, X86::PADDQrm, 16 },
580 { X86::PADDSBrr, X86::PADDSBrm, 16 },
581 { X86::PADDSWrr, X86::PADDSWrm, 16 },
582 { X86::PADDWrr, X86::PADDWrm, 16 },
583 { X86::PANDNrr, X86::PANDNrm, 16 },
584 { X86::PANDrr, X86::PANDrm, 16 },
585 { X86::PAVGBrr, X86::PAVGBrm, 16 },
586 { X86::PAVGWrr, X86::PAVGWrm, 16 },
587 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
588 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
589 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
590 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
591 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
592 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
593 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
594 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
595 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
596 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
597 { X86::PMINSWrr, X86::PMINSWrm, 16 },
598 { X86::PMINUBrr, X86::PMINUBrm, 16 },
599 { X86::PMULDQrr, X86::PMULDQrm, 16 },
600 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
601 { X86::PMULHWrr, X86::PMULHWrm, 16 },
602 { X86::PMULLDrr, X86::PMULLDrm, 16 },
603 { X86::PMULLWrr, X86::PMULLWrm, 16 },
604 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
605 { X86::PORrr, X86::PORrm, 16 },
606 { X86::PSADBWrr, X86::PSADBWrm, 16 },
607 { X86::PSLLDrr, X86::PSLLDrm, 16 },
608 { X86::PSLLQrr, X86::PSLLQrm, 16 },
609 { X86::PSLLWrr, X86::PSLLWrm, 16 },
610 { X86::PSRADrr, X86::PSRADrm, 16 },
611 { X86::PSRAWrr, X86::PSRAWrm, 16 },
612 { X86::PSRLDrr, X86::PSRLDrm, 16 },
613 { X86::PSRLQrr, X86::PSRLQrm, 16 },
614 { X86::PSRLWrr, X86::PSRLWrm, 16 },
615 { X86::PSUBBrr, X86::PSUBBrm, 16 },
616 { X86::PSUBDrr, X86::PSUBDrm, 16 },
617 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
618 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
619 { X86::PSUBWrr, X86::PSUBWrm, 16 },
620 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
621 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
622 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
623 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
624 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
625 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
626 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
627 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
628 { X86::PXORrr, X86::PXORrm, 16 },
629 { X86::SBB32rr, X86::SBB32rm, 0 },
630 { X86::SBB64rr, X86::SBB64rm, 0 },
631 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
632 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
633 { X86::SUB16rr, X86::SUB16rm, 0 },
634 { X86::SUB32rr, X86::SUB32rm, 0 },
635 { X86::SUB64rr, X86::SUB64rm, 0 },
636 { X86::SUB8rr, X86::SUB8rm, 0 },
637 { X86::SUBPDrr, X86::SUBPDrm, 16 },
638 { X86::SUBPSrr, X86::SUBPSrm, 16 },
639 { X86::SUBSDrr, X86::SUBSDrm, 0 },
640 { X86::SUBSSrr, X86::SUBSSrm, 0 },
641 // FIXME: TEST*rr -> swapped operand of TEST*mr.
642 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
643 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
644 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
645 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
646 { X86::XOR16rr, X86::XOR16rm, 0 },
647 { X86::XOR32rr, X86::XOR32rm, 0 },
648 { X86::XOR64rr, X86::XOR64rm, 0 },
649 { X86::XOR8rr, X86::XOR8rm, 0 },
650 { X86::XORPDrr, X86::XORPDrm, 16 },
651 { X86::XORPSrr, X86::XORPSrm, 16 }
654 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
655 unsigned RegOp = OpTbl2[i][0];
656 unsigned MemOp = OpTbl2[i][1];
657 unsigned Align = OpTbl2[i][2];
658 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
659 std::make_pair(MemOp,Align))).second)
660 assert(false && "Duplicated entries?");
661 // Index 2, folded load
662 unsigned AuxInfo = 2 | (1 << 4);
663 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
664 std::make_pair(RegOp, AuxInfo))).second)
665 AmbEntries.push_back(MemOp);
668 // Remove ambiguous entries.
669 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
673 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
674 unsigned &SrcReg, unsigned &DstReg,
675 unsigned &SubIdx) const {
676 switch (MI.getOpcode()) {
678 case X86::MOVSX16rr8:
679 case X86::MOVZX16rr8:
680 case X86::MOVSX32rr8:
681 case X86::MOVZX32rr8:
682 case X86::MOVSX64rr8:
683 case X86::MOVZX64rr8:
684 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
685 // It's not always legal to reference the low 8-bit of the larger
686 // register in 32-bit mode.
688 case X86::MOVSX32rr16:
689 case X86::MOVZX32rr16:
690 case X86::MOVSX64rr16:
691 case X86::MOVZX64rr16:
692 case X86::MOVSX64rr32:
693 case X86::MOVZX64rr32: {
694 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
697 SrcReg = MI.getOperand(1).getReg();
698 DstReg = MI.getOperand(0).getReg();
699 switch (MI.getOpcode()) {
703 case X86::MOVSX16rr8:
704 case X86::MOVZX16rr8:
705 case X86::MOVSX32rr8:
706 case X86::MOVZX32rr8:
707 case X86::MOVSX64rr8:
708 case X86::MOVZX64rr8:
709 SubIdx = X86::sub_8bit;
711 case X86::MOVSX32rr16:
712 case X86::MOVZX32rr16:
713 case X86::MOVSX64rr16:
714 case X86::MOVZX64rr16:
715 SubIdx = X86::sub_16bit;
717 case X86::MOVSX64rr32:
718 case X86::MOVZX64rr32:
719 SubIdx = X86::sub_32bit;
728 /// isFrameOperand - Return true and the FrameIndex if the specified
729 /// operand and follow operands form a reference to the stack frame.
730 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
731 int &FrameIndex) const {
732 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
733 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
734 MI->getOperand(Op+1).getImm() == 1 &&
735 MI->getOperand(Op+2).getReg() == 0 &&
736 MI->getOperand(Op+3).getImm() == 0) {
737 FrameIndex = MI->getOperand(Op).getIndex();
743 static bool isFrameLoadOpcode(int Opcode) {
749 case X86::MOV32rm_TC:
751 case X86::MOV64rm_TC:
758 case X86::MMX_MOVD64rm:
759 case X86::MMX_MOVQ64rm:
766 static bool isFrameStoreOpcode(int Opcode) {
772 case X86::MOV32mr_TC:
774 case X86::MOV64mr_TC:
781 case X86::MMX_MOVD64mr:
782 case X86::MMX_MOVQ64mr:
783 case X86::MMX_MOVNTQmr:
789 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
790 int &FrameIndex) const {
791 if (isFrameLoadOpcode(MI->getOpcode()))
792 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
793 return MI->getOperand(0).getReg();
797 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
798 int &FrameIndex) const {
799 if (isFrameLoadOpcode(MI->getOpcode())) {
801 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
803 // Check for post-frame index elimination operations
804 const MachineMemOperand *Dummy;
805 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
810 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
811 const MachineMemOperand *&MMO,
812 int &FrameIndex) const {
813 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
814 oe = MI->memoperands_end();
817 if ((*o)->isLoad() && (*o)->getValue())
818 if (const FixedStackPseudoSourceValue *Value =
819 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
820 FrameIndex = Value->getFrameIndex();
828 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
829 int &FrameIndex) const {
830 if (isFrameStoreOpcode(MI->getOpcode()))
831 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
832 isFrameOperand(MI, 0, FrameIndex))
833 return MI->getOperand(X86::AddrNumOperands).getReg();
837 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
838 int &FrameIndex) const {
839 if (isFrameStoreOpcode(MI->getOpcode())) {
841 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
843 // Check for post-frame index elimination operations
844 const MachineMemOperand *Dummy;
845 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
850 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
851 const MachineMemOperand *&MMO,
852 int &FrameIndex) const {
853 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
854 oe = MI->memoperands_end();
857 if ((*o)->isStore() && (*o)->getValue())
858 if (const FixedStackPseudoSourceValue *Value =
859 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
860 FrameIndex = Value->getFrameIndex();
868 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
870 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
871 bool isPICBase = false;
872 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
873 E = MRI.def_end(); I != E; ++I) {
874 MachineInstr *DefMI = I.getOperand().getParent();
875 if (DefMI->getOpcode() != X86::MOVPC32r)
877 assert(!isPICBase && "More than one PIC base?");
884 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
885 AliasAnalysis *AA) const {
886 switch (MI->getOpcode()) {
897 case X86::MOVUPSrm_Int:
900 case X86::MMX_MOVD64rm:
901 case X86::MMX_MOVQ64rm:
902 case X86::FsMOVAPSrm:
903 case X86::FsMOVAPDrm: {
904 // Loads from constant pools are trivially rematerializable.
905 if (MI->getOperand(1).isReg() &&
906 MI->getOperand(2).isImm() &&
907 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
908 MI->isInvariantLoad(AA)) {
909 unsigned BaseReg = MI->getOperand(1).getReg();
910 if (BaseReg == 0 || BaseReg == X86::RIP)
912 // Allow re-materialization of PIC load.
913 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
915 const MachineFunction &MF = *MI->getParent()->getParent();
916 const MachineRegisterInfo &MRI = MF.getRegInfo();
917 bool isPICBase = false;
918 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
919 E = MRI.def_end(); I != E; ++I) {
920 MachineInstr *DefMI = I.getOperand().getParent();
921 if (DefMI->getOpcode() != X86::MOVPC32r)
923 assert(!isPICBase && "More than one PIC base?");
933 if (MI->getOperand(2).isImm() &&
934 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
935 !MI->getOperand(4).isReg()) {
936 // lea fi#, lea GV, etc. are all rematerializable.
937 if (!MI->getOperand(1).isReg())
939 unsigned BaseReg = MI->getOperand(1).getReg();
942 // Allow re-materialization of lea PICBase + x.
943 const MachineFunction &MF = *MI->getParent()->getParent();
944 const MachineRegisterInfo &MRI = MF.getRegInfo();
945 return regIsPICBase(BaseReg, MRI);
951 // All other instructions marked M_REMATERIALIZABLE are always trivially
956 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
957 /// would clobber the EFLAGS condition register. Note the result may be
958 /// conservative. If it cannot definitely determine the safety after visiting
959 /// a few instructions in each direction it assumes it's not safe.
960 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
961 MachineBasicBlock::iterator I) {
962 MachineBasicBlock::iterator E = MBB.end();
964 // It's always safe to clobber EFLAGS at the end of a block.
968 // For compile time consideration, if we are not able to determine the
969 // safety after visiting 4 instructions in each direction, we will assume
971 MachineBasicBlock::iterator Iter = I;
972 for (unsigned i = 0; i < 4; ++i) {
973 bool SeenDef = false;
974 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
975 MachineOperand &MO = Iter->getOperand(j);
978 if (MO.getReg() == X86::EFLAGS) {
986 // This instruction defines EFLAGS, no need to look any further.
989 // Skip over DBG_VALUE.
990 while (Iter != E && Iter->isDebugValue())
993 // If we make it to the end of the block, it's safe to clobber EFLAGS.
998 MachineBasicBlock::iterator B = MBB.begin();
1000 for (unsigned i = 0; i < 4; ++i) {
1001 // If we make it to the beginning of the block, it's safe to clobber
1002 // EFLAGS iff EFLAGS is not live-in.
1004 return !MBB.isLiveIn(X86::EFLAGS);
1007 // Skip over DBG_VALUE.
1008 while (Iter != B && Iter->isDebugValue())
1011 bool SawKill = false;
1012 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1013 MachineOperand &MO = Iter->getOperand(j);
1014 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1015 if (MO.isDef()) return MO.isDead();
1016 if (MO.isKill()) SawKill = true;
1021 // This instruction kills EFLAGS and doesn't redefine it, so
1022 // there's no need to look further.
1026 // Conservative answer.
1030 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1031 MachineBasicBlock::iterator I,
1032 unsigned DestReg, unsigned SubIdx,
1033 const MachineInstr *Orig,
1034 const TargetRegisterInfo &TRI) const {
1035 DebugLoc DL = Orig->getDebugLoc();
1037 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1038 // Re-materialize them as movri instructions to avoid side effects.
1040 unsigned Opc = Orig->getOpcode();
1046 case X86::MOV64r0: {
1047 if (!isSafeToClobberEFLAGS(MBB, I)) {
1050 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1051 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1052 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1053 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1062 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1065 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1068 MachineInstr *NewMI = prior(I);
1069 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1072 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1073 /// is not marked dead.
1074 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1075 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1076 MachineOperand &MO = MI->getOperand(i);
1077 if (MO.isReg() && MO.isDef() &&
1078 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1085 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1086 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1087 /// to a 32-bit superregister and then truncating back down to a 16-bit
1090 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1091 MachineFunction::iterator &MFI,
1092 MachineBasicBlock::iterator &MBBI,
1093 LiveVariables *LV) const {
1094 MachineInstr *MI = MBBI;
1095 unsigned Dest = MI->getOperand(0).getReg();
1096 unsigned Src = MI->getOperand(1).getReg();
1097 bool isDead = MI->getOperand(0).isDead();
1098 bool isKill = MI->getOperand(1).isKill();
1100 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1101 ? X86::LEA64_32r : X86::LEA32r;
1102 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1103 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1104 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1106 // Build and insert into an implicit UNDEF value. This is OK because
1107 // well be shifting and then extracting the lower 16-bits.
1108 // This has the potential to cause partial register stall. e.g.
1109 // movw (%rbp,%rcx,2), %dx
1110 // leal -65(%rdx), %esi
1111 // But testing has shown this *does* help performance in 64-bit mode (at
1112 // least on modern x86 machines).
1113 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1114 MachineInstr *InsMI =
1115 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1116 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1117 .addReg(Src, getKillRegState(isKill));
1119 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1120 get(Opc), leaOutReg);
1123 llvm_unreachable(0);
1125 case X86::SHL16ri: {
1126 unsigned ShAmt = MI->getOperand(2).getImm();
1127 MIB.addReg(0).addImm(1 << ShAmt)
1128 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1132 case X86::INC64_16r:
1133 addRegOffset(MIB, leaInReg, true, 1);
1136 case X86::DEC64_16r:
1137 addRegOffset(MIB, leaInReg, true, -1);
1141 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1143 case X86::ADD16rr: {
1144 unsigned Src2 = MI->getOperand(2).getReg();
1145 bool isKill2 = MI->getOperand(2).isKill();
1146 unsigned leaInReg2 = 0;
1147 MachineInstr *InsMI2 = 0;
1149 // ADD16rr %reg1028<kill>, %reg1028
1150 // just a single insert_subreg.
1151 addRegReg(MIB, leaInReg, true, leaInReg, false);
1153 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1154 // Build and insert into an implicit UNDEF value. This is OK because
1155 // well be shifting and then extracting the lower 16-bits.
1156 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1158 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1159 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1160 .addReg(Src2, getKillRegState(isKill2));
1161 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1163 if (LV && isKill2 && InsMI2)
1164 LV->replaceKillInstruction(Src2, MI, InsMI2);
1169 MachineInstr *NewMI = MIB;
1170 MachineInstr *ExtMI =
1171 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1172 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1173 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1176 // Update live variables
1177 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1178 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1180 LV->replaceKillInstruction(Src, MI, InsMI);
1182 LV->replaceKillInstruction(Dest, MI, ExtMI);
1188 /// convertToThreeAddress - This method must be implemented by targets that
1189 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1190 /// may be able to convert a two-address instruction into a true
1191 /// three-address instruction on demand. This allows the X86 target (for
1192 /// example) to convert ADD and SHL instructions into LEA instructions if they
1193 /// would require register copies due to two-addressness.
1195 /// This method returns a null pointer if the transformation cannot be
1196 /// performed, otherwise it returns the new instruction.
1199 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1200 MachineBasicBlock::iterator &MBBI,
1201 LiveVariables *LV) const {
1202 MachineInstr *MI = MBBI;
1203 MachineFunction &MF = *MI->getParent()->getParent();
1204 // All instructions input are two-addr instructions. Get the known operands.
1205 unsigned Dest = MI->getOperand(0).getReg();
1206 unsigned Src = MI->getOperand(1).getReg();
1207 bool isDead = MI->getOperand(0).isDead();
1208 bool isKill = MI->getOperand(1).isKill();
1210 MachineInstr *NewMI = NULL;
1211 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1212 // we have better subtarget support, enable the 16-bit LEA generation here.
1213 // 16-bit LEA is also slow on Core2.
1214 bool DisableLEA16 = true;
1215 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1217 unsigned MIOpc = MI->getOpcode();
1219 case X86::SHUFPSrri: {
1220 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1221 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1223 unsigned B = MI->getOperand(1).getReg();
1224 unsigned C = MI->getOperand(2).getReg();
1225 if (B != C) return 0;
1226 unsigned A = MI->getOperand(0).getReg();
1227 unsigned M = MI->getOperand(3).getImm();
1228 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1229 .addReg(A, RegState::Define | getDeadRegState(isDead))
1230 .addReg(B, getKillRegState(isKill)).addImm(M);
1233 case X86::SHL64ri: {
1234 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1235 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1236 // the flags produced by a shift yet, so this is safe.
1237 unsigned ShAmt = MI->getOperand(2).getImm();
1238 if (ShAmt == 0 || ShAmt >= 4) return 0;
1240 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1241 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1242 .addReg(0).addImm(1 << ShAmt)
1243 .addReg(Src, getKillRegState(isKill))
1244 .addImm(0).addReg(0);
1247 case X86::SHL32ri: {
1248 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1249 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1250 // the flags produced by a shift yet, so this is safe.
1251 unsigned ShAmt = MI->getOperand(2).getImm();
1252 if (ShAmt == 0 || ShAmt >= 4) return 0;
1254 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1255 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1256 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1257 .addReg(0).addImm(1 << ShAmt)
1258 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1261 case X86::SHL16ri: {
1262 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1263 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1264 // the flags produced by a shift yet, so this is safe.
1265 unsigned ShAmt = MI->getOperand(2).getImm();
1266 if (ShAmt == 0 || ShAmt >= 4) return 0;
1269 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1270 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1271 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1272 .addReg(0).addImm(1 << ShAmt)
1273 .addReg(Src, getKillRegState(isKill))
1274 .addImm(0).addReg(0);
1278 // The following opcodes also sets the condition code register(s). Only
1279 // convert them to equivalent lea if the condition code register def's
1281 if (hasLiveCondCodeDef(MI))
1288 case X86::INC64_32r: {
1289 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1290 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1291 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1292 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1293 .addReg(Dest, RegState::Define |
1294 getDeadRegState(isDead)),
1299 case X86::INC64_16r:
1301 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1302 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1303 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1304 .addReg(Dest, RegState::Define |
1305 getDeadRegState(isDead)),
1310 case X86::DEC64_32r: {
1311 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1312 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1313 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1314 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1315 .addReg(Dest, RegState::Define |
1316 getDeadRegState(isDead)),
1321 case X86::DEC64_16r:
1323 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1324 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1325 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1326 .addReg(Dest, RegState::Define |
1327 getDeadRegState(isDead)),
1331 case X86::ADD32rr: {
1332 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1333 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1334 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1335 unsigned Src2 = MI->getOperand(2).getReg();
1336 bool isKill2 = MI->getOperand(2).isKill();
1337 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1338 .addReg(Dest, RegState::Define |
1339 getDeadRegState(isDead)),
1340 Src, isKill, Src2, isKill2);
1342 LV->replaceKillInstruction(Src2, MI, NewMI);
1345 case X86::ADD16rr: {
1347 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1348 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1349 unsigned Src2 = MI->getOperand(2).getReg();
1350 bool isKill2 = MI->getOperand(2).isKill();
1351 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1352 .addReg(Dest, RegState::Define |
1353 getDeadRegState(isDead)),
1354 Src, isKill, Src2, isKill2);
1356 LV->replaceKillInstruction(Src2, MI, NewMI);
1359 case X86::ADD64ri32:
1361 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1362 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1363 .addReg(Dest, RegState::Define |
1364 getDeadRegState(isDead)),
1365 Src, isKill, MI->getOperand(2).getImm());
1368 case X86::ADD32ri8: {
1369 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1370 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1371 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1372 .addReg(Dest, RegState::Define |
1373 getDeadRegState(isDead)),
1374 Src, isKill, MI->getOperand(2).getImm());
1380 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1381 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1382 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1383 .addReg(Dest, RegState::Define |
1384 getDeadRegState(isDead)),
1385 Src, isKill, MI->getOperand(2).getImm());
1391 if (!NewMI) return 0;
1393 if (LV) { // Update live variables
1395 LV->replaceKillInstruction(Src, MI, NewMI);
1397 LV->replaceKillInstruction(Dest, MI, NewMI);
1400 MFI->insert(MBBI, NewMI); // Insert the new inst
1404 /// commuteInstruction - We have a few instructions that must be hacked on to
1408 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1409 switch (MI->getOpcode()) {
1410 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1411 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1412 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1413 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1414 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1415 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1418 switch (MI->getOpcode()) {
1419 default: llvm_unreachable("Unreachable!");
1420 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1421 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1422 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1423 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1424 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1425 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1427 unsigned Amt = MI->getOperand(3).getImm();
1429 MachineFunction &MF = *MI->getParent()->getParent();
1430 MI = MF.CloneMachineInstr(MI);
1433 MI->setDesc(get(Opc));
1434 MI->getOperand(3).setImm(Size-Amt);
1435 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1437 case X86::CMOVB16rr:
1438 case X86::CMOVB32rr:
1439 case X86::CMOVB64rr:
1440 case X86::CMOVAE16rr:
1441 case X86::CMOVAE32rr:
1442 case X86::CMOVAE64rr:
1443 case X86::CMOVE16rr:
1444 case X86::CMOVE32rr:
1445 case X86::CMOVE64rr:
1446 case X86::CMOVNE16rr:
1447 case X86::CMOVNE32rr:
1448 case X86::CMOVNE64rr:
1449 case X86::CMOVBE16rr:
1450 case X86::CMOVBE32rr:
1451 case X86::CMOVBE64rr:
1452 case X86::CMOVA16rr:
1453 case X86::CMOVA32rr:
1454 case X86::CMOVA64rr:
1455 case X86::CMOVL16rr:
1456 case X86::CMOVL32rr:
1457 case X86::CMOVL64rr:
1458 case X86::CMOVGE16rr:
1459 case X86::CMOVGE32rr:
1460 case X86::CMOVGE64rr:
1461 case X86::CMOVLE16rr:
1462 case X86::CMOVLE32rr:
1463 case X86::CMOVLE64rr:
1464 case X86::CMOVG16rr:
1465 case X86::CMOVG32rr:
1466 case X86::CMOVG64rr:
1467 case X86::CMOVS16rr:
1468 case X86::CMOVS32rr:
1469 case X86::CMOVS64rr:
1470 case X86::CMOVNS16rr:
1471 case X86::CMOVNS32rr:
1472 case X86::CMOVNS64rr:
1473 case X86::CMOVP16rr:
1474 case X86::CMOVP32rr:
1475 case X86::CMOVP64rr:
1476 case X86::CMOVNP16rr:
1477 case X86::CMOVNP32rr:
1478 case X86::CMOVNP64rr:
1479 case X86::CMOVO16rr:
1480 case X86::CMOVO32rr:
1481 case X86::CMOVO64rr:
1482 case X86::CMOVNO16rr:
1483 case X86::CMOVNO32rr:
1484 case X86::CMOVNO64rr: {
1486 switch (MI->getOpcode()) {
1488 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1489 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1490 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1491 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1492 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1493 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1494 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1495 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1496 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1497 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1498 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1499 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1500 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1501 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1502 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1503 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1504 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1505 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1506 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1507 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1508 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1509 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1510 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1511 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1512 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1513 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1514 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1515 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1516 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1517 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1518 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1519 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1520 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1521 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1522 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1523 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1524 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1525 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1526 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1527 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1528 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1529 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1530 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1531 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1532 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1533 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1534 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1535 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1538 MachineFunction &MF = *MI->getParent()->getParent();
1539 MI = MF.CloneMachineInstr(MI);
1542 MI->setDesc(get(Opc));
1543 // Fallthrough intended.
1546 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1550 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1552 default: return X86::COND_INVALID;
1553 case X86::JE_4: return X86::COND_E;
1554 case X86::JNE_4: return X86::COND_NE;
1555 case X86::JL_4: return X86::COND_L;
1556 case X86::JLE_4: return X86::COND_LE;
1557 case X86::JG_4: return X86::COND_G;
1558 case X86::JGE_4: return X86::COND_GE;
1559 case X86::JB_4: return X86::COND_B;
1560 case X86::JBE_4: return X86::COND_BE;
1561 case X86::JA_4: return X86::COND_A;
1562 case X86::JAE_4: return X86::COND_AE;
1563 case X86::JS_4: return X86::COND_S;
1564 case X86::JNS_4: return X86::COND_NS;
1565 case X86::JP_4: return X86::COND_P;
1566 case X86::JNP_4: return X86::COND_NP;
1567 case X86::JO_4: return X86::COND_O;
1568 case X86::JNO_4: return X86::COND_NO;
1572 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1574 default: llvm_unreachable("Illegal condition code!");
1575 case X86::COND_E: return X86::JE_4;
1576 case X86::COND_NE: return X86::JNE_4;
1577 case X86::COND_L: return X86::JL_4;
1578 case X86::COND_LE: return X86::JLE_4;
1579 case X86::COND_G: return X86::JG_4;
1580 case X86::COND_GE: return X86::JGE_4;
1581 case X86::COND_B: return X86::JB_4;
1582 case X86::COND_BE: return X86::JBE_4;
1583 case X86::COND_A: return X86::JA_4;
1584 case X86::COND_AE: return X86::JAE_4;
1585 case X86::COND_S: return X86::JS_4;
1586 case X86::COND_NS: return X86::JNS_4;
1587 case X86::COND_P: return X86::JP_4;
1588 case X86::COND_NP: return X86::JNP_4;
1589 case X86::COND_O: return X86::JO_4;
1590 case X86::COND_NO: return X86::JNO_4;
1594 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1595 /// e.g. turning COND_E to COND_NE.
1596 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1598 default: llvm_unreachable("Illegal condition code!");
1599 case X86::COND_E: return X86::COND_NE;
1600 case X86::COND_NE: return X86::COND_E;
1601 case X86::COND_L: return X86::COND_GE;
1602 case X86::COND_LE: return X86::COND_G;
1603 case X86::COND_G: return X86::COND_LE;
1604 case X86::COND_GE: return X86::COND_L;
1605 case X86::COND_B: return X86::COND_AE;
1606 case X86::COND_BE: return X86::COND_A;
1607 case X86::COND_A: return X86::COND_BE;
1608 case X86::COND_AE: return X86::COND_B;
1609 case X86::COND_S: return X86::COND_NS;
1610 case X86::COND_NS: return X86::COND_S;
1611 case X86::COND_P: return X86::COND_NP;
1612 case X86::COND_NP: return X86::COND_P;
1613 case X86::COND_O: return X86::COND_NO;
1614 case X86::COND_NO: return X86::COND_O;
1618 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1619 const TargetInstrDesc &TID = MI->getDesc();
1620 if (!TID.isTerminator()) return false;
1622 // Conditional branch is a special case.
1623 if (TID.isBranch() && !TID.isBarrier())
1625 if (!TID.isPredicable())
1627 return !isPredicated(MI);
1630 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1631 MachineBasicBlock *&TBB,
1632 MachineBasicBlock *&FBB,
1633 SmallVectorImpl<MachineOperand> &Cond,
1634 bool AllowModify) const {
1635 // Start from the bottom of the block and work up, examining the
1636 // terminator instructions.
1637 MachineBasicBlock::iterator I = MBB.end();
1638 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1639 while (I != MBB.begin()) {
1641 if (I->isDebugValue())
1644 // Working from the bottom, when we see a non-terminator instruction, we're
1646 if (!isUnpredicatedTerminator(I))
1649 // A terminator that isn't a branch can't easily be handled by this
1651 if (!I->getDesc().isBranch())
1654 // Handle unconditional branches.
1655 if (I->getOpcode() == X86::JMP_4) {
1659 TBB = I->getOperand(0).getMBB();
1663 // If the block has any instructions after a JMP, delete them.
1664 while (llvm::next(I) != MBB.end())
1665 llvm::next(I)->eraseFromParent();
1670 // Delete the JMP if it's equivalent to a fall-through.
1671 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1673 I->eraseFromParent();
1675 UnCondBrIter = MBB.end();
1679 // TBB is used to indicate the unconditional destination.
1680 TBB = I->getOperand(0).getMBB();
1684 // Handle conditional branches.
1685 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1686 if (BranchCode == X86::COND_INVALID)
1687 return true; // Can't handle indirect branch.
1689 // Working from the bottom, handle the first conditional branch.
1691 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1692 if (AllowModify && UnCondBrIter != MBB.end() &&
1693 MBB.isLayoutSuccessor(TargetBB)) {
1694 // If we can modify the code and it ends in something like:
1702 // Then we can change this to:
1709 // Which is a bit more efficient.
1710 // We conditionally jump to the fall-through block.
1711 BranchCode = GetOppositeBranchCondition(BranchCode);
1712 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1713 MachineBasicBlock::iterator OldInst = I;
1715 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1716 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1717 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1719 MBB.addSuccessor(TargetBB);
1721 OldInst->eraseFromParent();
1722 UnCondBrIter->eraseFromParent();
1724 // Restart the analysis.
1725 UnCondBrIter = MBB.end();
1731 TBB = I->getOperand(0).getMBB();
1732 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1736 // Handle subsequent conditional branches. Only handle the case where all
1737 // conditional branches branch to the same destination and their condition
1738 // opcodes fit one of the special multi-branch idioms.
1739 assert(Cond.size() == 1);
1742 // Only handle the case where all conditional branches branch to the same
1744 if (TBB != I->getOperand(0).getMBB())
1747 // If the conditions are the same, we can leave them alone.
1748 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1749 if (OldBranchCode == BranchCode)
1752 // If they differ, see if they fit one of the known patterns. Theoretically,
1753 // we could handle more patterns here, but we shouldn't expect to see them
1754 // if instruction selection has done a reasonable job.
1755 if ((OldBranchCode == X86::COND_NP &&
1756 BranchCode == X86::COND_E) ||
1757 (OldBranchCode == X86::COND_E &&
1758 BranchCode == X86::COND_NP))
1759 BranchCode = X86::COND_NP_OR_E;
1760 else if ((OldBranchCode == X86::COND_P &&
1761 BranchCode == X86::COND_NE) ||
1762 (OldBranchCode == X86::COND_NE &&
1763 BranchCode == X86::COND_P))
1764 BranchCode = X86::COND_NE_OR_P;
1768 // Update the MachineOperand.
1769 Cond[0].setImm(BranchCode);
1775 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1776 MachineBasicBlock::iterator I = MBB.end();
1779 while (I != MBB.begin()) {
1781 if (I->isDebugValue())
1783 if (I->getOpcode() != X86::JMP_4 &&
1784 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1786 // Remove the branch.
1787 I->eraseFromParent();
1796 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1797 MachineBasicBlock *FBB,
1798 const SmallVectorImpl<MachineOperand> &Cond,
1799 DebugLoc DL) const {
1800 // Shouldn't be a fall through.
1801 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1802 assert((Cond.size() == 1 || Cond.size() == 0) &&
1803 "X86 branch conditions have one component!");
1806 // Unconditional branch?
1807 assert(!FBB && "Unconditional branch with multiple successors!");
1808 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
1812 // Conditional branch.
1814 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1816 case X86::COND_NP_OR_E:
1817 // Synthesize NP_OR_E with two branches.
1818 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
1820 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
1823 case X86::COND_NE_OR_P:
1824 // Synthesize NE_OR_P with two branches.
1825 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
1827 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
1831 unsigned Opc = GetCondBranchFromCond(CC);
1832 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
1837 // Two-way Conditional branch. Insert the second branch.
1838 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
1844 /// isHReg - Test if the given register is a physical h register.
1845 static bool isHReg(unsigned Reg) {
1846 return X86::GR8_ABCD_HRegClass.contains(Reg);
1849 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1850 MachineBasicBlock::iterator MI, DebugLoc DL,
1851 unsigned DestReg, unsigned SrcReg,
1852 bool KillSrc) const {
1853 // First deal with the normal symmetric copies.
1855 if (X86::GR64RegClass.contains(DestReg, SrcReg))
1857 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
1859 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
1861 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
1862 // Copying to or from a physical H register on x86-64 requires a NOREX
1863 // move. Otherwise use a normal move.
1864 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1865 TM.getSubtarget<X86Subtarget>().is64Bit())
1866 Opc = X86::MOV8rr_NOREX;
1869 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
1870 Opc = X86::MOVAPSrr;
1871 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
1872 Opc = X86::MMX_MOVQ64rr;
1875 BuildMI(MBB, MI, DL, get(Opc), DestReg)
1876 .addReg(SrcReg, getKillRegState(KillSrc));
1880 // Moving EFLAGS to / from another register requires a push and a pop.
1881 if (SrcReg == X86::EFLAGS) {
1882 if (X86::GR64RegClass.contains(DestReg)) {
1883 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
1884 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1886 } else if (X86::GR32RegClass.contains(DestReg)) {
1887 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
1888 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1892 if (DestReg == X86::EFLAGS) {
1893 if (X86::GR64RegClass.contains(SrcReg)) {
1894 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
1895 .addReg(SrcReg, getKillRegState(KillSrc));
1896 BuildMI(MBB, MI, DL, get(X86::POPF64));
1898 } else if (X86::GR32RegClass.contains(SrcReg)) {
1899 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
1900 .addReg(SrcReg, getKillRegState(KillSrc));
1901 BuildMI(MBB, MI, DL, get(X86::POPF32));
1906 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
1907 << " to " << RI.getName(DestReg) << '\n');
1908 llvm_unreachable("Cannot emit physreg copy instruction");
1911 static unsigned getLoadStoreRegOpcode(unsigned Reg,
1912 const TargetRegisterClass *RC,
1913 bool isStackAligned,
1914 const TargetMachine &TM,
1916 switch (RC->getID()) {
1918 llvm_unreachable("Unknown regclass");
1919 case X86::GR64RegClassID:
1920 case X86::GR64_NOSPRegClassID:
1921 return load ? X86::MOV64rm : X86::MOV64mr;
1922 case X86::GR32RegClassID:
1923 case X86::GR32_NOSPRegClassID:
1924 case X86::GR32_ADRegClassID:
1925 return load ? X86::MOV32rm : X86::MOV32mr;
1926 case X86::GR16RegClassID:
1927 return load ? X86::MOV16rm : X86::MOV16mr;
1928 case X86::GR8RegClassID:
1929 // Copying to or from a physical H register on x86-64 requires a NOREX
1930 // move. Otherwise use a normal move.
1932 TM.getSubtarget<X86Subtarget>().is64Bit())
1933 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
1935 return load ? X86::MOV8rm : X86::MOV8mr;
1936 case X86::GR64_ABCDRegClassID:
1937 return load ? X86::MOV64rm : X86::MOV64mr;
1938 case X86::GR32_ABCDRegClassID:
1939 return load ? X86::MOV32rm : X86::MOV32mr;
1940 case X86::GR16_ABCDRegClassID:
1941 return load ? X86::MOV16rm : X86::MOV16mr;
1942 case X86::GR8_ABCD_LRegClassID:
1943 return load ? X86::MOV8rm :X86::MOV8mr;
1944 case X86::GR8_ABCD_HRegClassID:
1945 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1946 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
1948 return load ? X86::MOV8rm : X86::MOV8mr;
1949 case X86::GR64_NOREXRegClassID:
1950 case X86::GR64_NOREX_NOSPRegClassID:
1951 return load ? X86::MOV64rm : X86::MOV64mr;
1952 case X86::GR32_NOREXRegClassID:
1953 return load ? X86::MOV32rm : X86::MOV32mr;
1954 case X86::GR16_NOREXRegClassID:
1955 return load ? X86::MOV16rm : X86::MOV16mr;
1956 case X86::GR8_NOREXRegClassID:
1957 return load ? X86::MOV8rm : X86::MOV8mr;
1958 case X86::GR64_TCRegClassID:
1959 return load ? X86::MOV64rm_TC : X86::MOV64mr_TC;
1960 case X86::GR32_TCRegClassID:
1961 return load ? X86::MOV32rm_TC : X86::MOV32mr_TC;
1962 case X86::RFP80RegClassID:
1963 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
1964 case X86::RFP64RegClassID:
1965 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
1966 case X86::RFP32RegClassID:
1967 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
1968 case X86::FR32RegClassID:
1969 return load ? X86::MOVSSrm : X86::MOVSSmr;
1970 case X86::FR64RegClassID:
1971 return load ? X86::MOVSDrm : X86::MOVSDmr;
1972 case X86::VR128RegClassID:
1973 // If stack is realigned we can use aligned stores.
1975 return load ? X86::MOVAPSrm : X86::MOVAPSmr;
1977 return load ? X86::MOVUPSrm : X86::MOVUPSmr;
1978 case X86::VR64RegClassID:
1979 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
1983 static unsigned getStoreRegOpcode(unsigned SrcReg,
1984 const TargetRegisterClass *RC,
1985 bool isStackAligned,
1986 TargetMachine &TM) {
1987 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
1991 static unsigned getLoadRegOpcode(unsigned DestReg,
1992 const TargetRegisterClass *RC,
1993 bool isStackAligned,
1994 const TargetMachine &TM) {
1995 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
1998 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1999 MachineBasicBlock::iterator MI,
2000 unsigned SrcReg, bool isKill, int FrameIdx,
2001 const TargetRegisterClass *RC,
2002 const TargetRegisterInfo *TRI) const {
2003 const MachineFunction &MF = *MBB.getParent();
2004 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2005 "Stack slot too small for store");
2006 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2007 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2008 DebugLoc DL = MBB.findDebugLoc(MI);
2009 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2010 .addReg(SrcReg, getKillRegState(isKill));
2013 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2015 SmallVectorImpl<MachineOperand> &Addr,
2016 const TargetRegisterClass *RC,
2017 MachineInstr::mmo_iterator MMOBegin,
2018 MachineInstr::mmo_iterator MMOEnd,
2019 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2020 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2021 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2023 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2024 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2025 MIB.addOperand(Addr[i]);
2026 MIB.addReg(SrcReg, getKillRegState(isKill));
2027 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2028 NewMIs.push_back(MIB);
2032 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2033 MachineBasicBlock::iterator MI,
2034 unsigned DestReg, int FrameIdx,
2035 const TargetRegisterClass *RC,
2036 const TargetRegisterInfo *TRI) const {
2037 const MachineFunction &MF = *MBB.getParent();
2038 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2039 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2040 DebugLoc DL = MBB.findDebugLoc(MI);
2041 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2044 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2045 SmallVectorImpl<MachineOperand> &Addr,
2046 const TargetRegisterClass *RC,
2047 MachineInstr::mmo_iterator MMOBegin,
2048 MachineInstr::mmo_iterator MMOEnd,
2049 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2050 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2051 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2053 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2054 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2055 MIB.addOperand(Addr[i]);
2056 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2057 NewMIs.push_back(MIB);
2060 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2061 MachineBasicBlock::iterator MI,
2062 const std::vector<CalleeSavedInfo> &CSI,
2063 const TargetRegisterInfo *TRI) const {
2067 DebugLoc DL = MBB.findDebugLoc(MI);
2069 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2070 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2071 unsigned SlotSize = is64Bit ? 8 : 4;
2073 MachineFunction &MF = *MBB.getParent();
2074 unsigned FPReg = RI.getFrameRegister(MF);
2075 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2076 unsigned CalleeFrameSize = 0;
2078 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2079 for (unsigned i = CSI.size(); i != 0; --i) {
2080 unsigned Reg = CSI[i-1].getReg();
2081 // Add the callee-saved register as live-in. It's killed at the spill.
2084 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2086 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2087 CalleeFrameSize += SlotSize;
2088 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2090 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2091 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
2096 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2100 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2101 MachineBasicBlock::iterator MI,
2102 const std::vector<CalleeSavedInfo> &CSI,
2103 const TargetRegisterInfo *TRI) const {
2107 DebugLoc DL = MBB.findDebugLoc(MI);
2109 MachineFunction &MF = *MBB.getParent();
2110 unsigned FPReg = RI.getFrameRegister(MF);
2111 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2112 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2113 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2114 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2115 unsigned Reg = CSI[i].getReg();
2117 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2119 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2120 BuildMI(MBB, MI, DL, get(Opc), Reg);
2122 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2123 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
2131 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2132 int FrameIx, uint64_t Offset,
2133 const MDNode *MDPtr,
2134 DebugLoc DL) const {
2136 AM.BaseType = X86AddressMode::FrameIndexBase;
2137 AM.Base.FrameIndex = FrameIx;
2138 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2139 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2143 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2144 const SmallVectorImpl<MachineOperand> &MOs,
2146 const TargetInstrInfo &TII) {
2147 // Create the base instruction with the memory operand as the first part.
2148 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2149 MI->getDebugLoc(), true);
2150 MachineInstrBuilder MIB(NewMI);
2151 unsigned NumAddrOps = MOs.size();
2152 for (unsigned i = 0; i != NumAddrOps; ++i)
2153 MIB.addOperand(MOs[i]);
2154 if (NumAddrOps < 4) // FrameIndex only
2157 // Loop over the rest of the ri operands, converting them over.
2158 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2159 for (unsigned i = 0; i != NumOps; ++i) {
2160 MachineOperand &MO = MI->getOperand(i+2);
2163 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2164 MachineOperand &MO = MI->getOperand(i);
2170 static MachineInstr *FuseInst(MachineFunction &MF,
2171 unsigned Opcode, unsigned OpNo,
2172 const SmallVectorImpl<MachineOperand> &MOs,
2173 MachineInstr *MI, const TargetInstrInfo &TII) {
2174 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2175 MI->getDebugLoc(), true);
2176 MachineInstrBuilder MIB(NewMI);
2178 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2179 MachineOperand &MO = MI->getOperand(i);
2181 assert(MO.isReg() && "Expected to fold into reg operand!");
2182 unsigned NumAddrOps = MOs.size();
2183 for (unsigned i = 0; i != NumAddrOps; ++i)
2184 MIB.addOperand(MOs[i]);
2185 if (NumAddrOps < 4) // FrameIndex only
2194 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2195 const SmallVectorImpl<MachineOperand> &MOs,
2197 MachineFunction &MF = *MI->getParent()->getParent();
2198 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2200 unsigned NumAddrOps = MOs.size();
2201 for (unsigned i = 0; i != NumAddrOps; ++i)
2202 MIB.addOperand(MOs[i]);
2203 if (NumAddrOps < 4) // FrameIndex only
2205 return MIB.addImm(0);
2209 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2210 MachineInstr *MI, unsigned i,
2211 const SmallVectorImpl<MachineOperand> &MOs,
2212 unsigned Size, unsigned Align) const {
2213 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2214 bool isTwoAddrFold = false;
2215 unsigned NumOps = MI->getDesc().getNumOperands();
2216 bool isTwoAddr = NumOps > 1 &&
2217 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2219 MachineInstr *NewMI = NULL;
2220 // Folding a memory location into the two-address part of a two-address
2221 // instruction is different than folding it other places. It requires
2222 // replacing the *two* registers with the memory location.
2223 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2224 MI->getOperand(0).isReg() &&
2225 MI->getOperand(1).isReg() &&
2226 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2227 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2228 isTwoAddrFold = true;
2229 } else if (i == 0) { // If operand 0
2230 if (MI->getOpcode() == X86::MOV64r0)
2231 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2232 else if (MI->getOpcode() == X86::MOV32r0)
2233 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2234 else if (MI->getOpcode() == X86::MOV16r0)
2235 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2236 else if (MI->getOpcode() == X86::MOV8r0)
2237 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2241 OpcodeTablePtr = &RegOp2MemOpTable0;
2242 } else if (i == 1) {
2243 OpcodeTablePtr = &RegOp2MemOpTable1;
2244 } else if (i == 2) {
2245 OpcodeTablePtr = &RegOp2MemOpTable2;
2248 // If table selected...
2249 if (OpcodeTablePtr) {
2250 // Find the Opcode to fuse
2251 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2252 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2253 if (I != OpcodeTablePtr->end()) {
2254 unsigned Opcode = I->second.first;
2255 unsigned MinAlign = I->second.second;
2256 if (Align < MinAlign)
2258 bool NarrowToMOV32rm = false;
2260 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2261 if (Size < RCSize) {
2262 // Check if it's safe to fold the load. If the size of the object is
2263 // narrower than the load width, then it's not.
2264 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2266 // If this is a 64-bit load, but the spill slot is 32, then we can do
2267 // a 32-bit load which is implicitly zero-extended. This likely is due
2268 // to liveintervalanalysis remat'ing a load from stack slot.
2269 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2271 Opcode = X86::MOV32rm;
2272 NarrowToMOV32rm = true;
2277 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2279 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2281 if (NarrowToMOV32rm) {
2282 // If this is the special case where we use a MOV32rm to load a 32-bit
2283 // value and zero-extend the top bits. Change the destination register
2285 unsigned DstReg = NewMI->getOperand(0).getReg();
2286 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2287 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2290 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2297 if (PrintFailedFusing && !MI->isCopy())
2298 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2303 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2305 const SmallVectorImpl<unsigned> &Ops,
2306 int FrameIndex) const {
2307 // Check switch flag
2308 if (NoFusing) return NULL;
2310 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2311 switch (MI->getOpcode()) {
2312 case X86::CVTSD2SSrr:
2313 case X86::Int_CVTSD2SSrr:
2314 case X86::CVTSS2SDrr:
2315 case X86::Int_CVTSS2SDrr:
2317 case X86::RCPSSr_Int:
2318 case X86::ROUNDSDr_Int:
2319 case X86::ROUNDSSr_Int:
2321 case X86::RSQRTSSr_Int:
2323 case X86::SQRTSSr_Int:
2327 const MachineFrameInfo *MFI = MF.getFrameInfo();
2328 unsigned Size = MFI->getObjectSize(FrameIndex);
2329 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2330 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2331 unsigned NewOpc = 0;
2332 unsigned RCSize = 0;
2333 switch (MI->getOpcode()) {
2334 default: return NULL;
2335 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2336 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2337 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2338 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2340 // Check if it's safe to fold the load. If the size of the object is
2341 // narrower than the load width, then it's not.
2344 // Change to CMPXXri r, 0 first.
2345 MI->setDesc(get(NewOpc));
2346 MI->getOperand(1).ChangeToImmediate(0);
2347 } else if (Ops.size() != 1)
2350 SmallVector<MachineOperand,4> MOs;
2351 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2352 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2355 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2357 const SmallVectorImpl<unsigned> &Ops,
2358 MachineInstr *LoadMI) const {
2359 // Check switch flag
2360 if (NoFusing) return NULL;
2362 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2363 switch (MI->getOpcode()) {
2364 case X86::CVTSD2SSrr:
2365 case X86::Int_CVTSD2SSrr:
2366 case X86::CVTSS2SDrr:
2367 case X86::Int_CVTSS2SDrr:
2369 case X86::RCPSSr_Int:
2370 case X86::ROUNDSDr_Int:
2371 case X86::ROUNDSSr_Int:
2373 case X86::RSQRTSSr_Int:
2375 case X86::SQRTSSr_Int:
2379 // Determine the alignment of the load.
2380 unsigned Alignment = 0;
2381 if (LoadMI->hasOneMemOperand())
2382 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2384 switch (LoadMI->getOpcode()) {
2385 case X86::AVX_SET0PSY:
2386 case X86::AVX_SET0PDY:
2392 case X86::V_SETALLONES:
2393 case X86::AVX_SET0PS:
2394 case X86::AVX_SET0PD:
2395 case X86::AVX_SET0PI:
2405 llvm_unreachable("Don't know how to fold this instruction!");
2407 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2408 unsigned NewOpc = 0;
2409 switch (MI->getOpcode()) {
2410 default: return NULL;
2411 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2412 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2413 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2414 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2416 // Change to CMPXXri r, 0 first.
2417 MI->setDesc(get(NewOpc));
2418 MI->getOperand(1).ChangeToImmediate(0);
2419 } else if (Ops.size() != 1)
2422 // Make sure the subregisters match.
2423 // Otherwise we risk changing the size of the load.
2424 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2427 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2428 switch (LoadMI->getOpcode()) {
2432 case X86::V_SETALLONES:
2433 case X86::AVX_SET0PS:
2434 case X86::AVX_SET0PD:
2435 case X86::AVX_SET0PI:
2436 case X86::AVX_SET0PSY:
2437 case X86::AVX_SET0PDY:
2439 case X86::FsFLD0SS: {
2440 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2441 // Create a constant-pool entry and operands to load from it.
2443 // Medium and large mode can't fold loads this way.
2444 if (TM.getCodeModel() != CodeModel::Small &&
2445 TM.getCodeModel() != CodeModel::Kernel)
2448 // x86-32 PIC requires a PIC base register for constant pools.
2449 unsigned PICBase = 0;
2450 if (TM.getRelocationModel() == Reloc::PIC_) {
2451 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2454 // FIXME: PICBase = getGlobalBaseReg(&MF);
2455 // This doesn't work for several reasons.
2456 // 1. GlobalBaseReg may have been spilled.
2457 // 2. It may not be live at MI.
2461 // Create a constant-pool entry.
2462 MachineConstantPool &MCP = *MF.getConstantPool();
2464 unsigned Opc = LoadMI->getOpcode();
2465 if (Opc == X86::FsFLD0SS)
2466 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2467 else if (Opc == X86::FsFLD0SD)
2468 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2469 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2470 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2472 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2473 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2474 Constant::getAllOnesValue(Ty) :
2475 Constant::getNullValue(Ty);
2476 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2478 // Create operands to load from the constant pool entry.
2479 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2480 MOs.push_back(MachineOperand::CreateImm(1));
2481 MOs.push_back(MachineOperand::CreateReg(0, false));
2482 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2483 MOs.push_back(MachineOperand::CreateReg(0, false));
2487 // Folding a normal load. Just copy the load's address operands.
2488 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2489 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
2490 MOs.push_back(LoadMI->getOperand(i));
2494 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2498 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2499 const SmallVectorImpl<unsigned> &Ops) const {
2500 // Check switch flag
2501 if (NoFusing) return 0;
2503 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2504 switch (MI->getOpcode()) {
2505 default: return false;
2514 if (Ops.size() != 1)
2517 unsigned OpNum = Ops[0];
2518 unsigned Opc = MI->getOpcode();
2519 unsigned NumOps = MI->getDesc().getNumOperands();
2520 bool isTwoAddr = NumOps > 1 &&
2521 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2523 // Folding a memory location into the two-address part of a two-address
2524 // instruction is different than folding it other places. It requires
2525 // replacing the *two* registers with the memory location.
2526 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2527 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2528 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2529 } else if (OpNum == 0) { // If operand 0
2538 OpcodeTablePtr = &RegOp2MemOpTable0;
2539 } else if (OpNum == 1) {
2540 OpcodeTablePtr = &RegOp2MemOpTable1;
2541 } else if (OpNum == 2) {
2542 OpcodeTablePtr = &RegOp2MemOpTable2;
2545 if (OpcodeTablePtr) {
2546 // Find the Opcode to fuse
2547 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2548 OpcodeTablePtr->find((unsigned*)Opc);
2549 if (I != OpcodeTablePtr->end())
2552 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
2555 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2556 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2557 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2558 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2559 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2560 if (I == MemOp2RegOpTable.end())
2562 unsigned Opc = I->second.first;
2563 unsigned Index = I->second.second & 0xf;
2564 bool FoldedLoad = I->second.second & (1 << 4);
2565 bool FoldedStore = I->second.second & (1 << 5);
2566 if (UnfoldLoad && !FoldedLoad)
2568 UnfoldLoad &= FoldedLoad;
2569 if (UnfoldStore && !FoldedStore)
2571 UnfoldStore &= FoldedStore;
2573 const TargetInstrDesc &TID = get(Opc);
2574 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2575 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2576 if (!MI->hasOneMemOperand() &&
2577 RC == &X86::VR128RegClass &&
2578 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2579 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2580 // conservatively assume the address is unaligned. That's bad for
2583 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
2584 SmallVector<MachineOperand,2> BeforeOps;
2585 SmallVector<MachineOperand,2> AfterOps;
2586 SmallVector<MachineOperand,4> ImpOps;
2587 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2588 MachineOperand &Op = MI->getOperand(i);
2589 if (i >= Index && i < Index + X86::AddrNumOperands)
2590 AddrOps.push_back(Op);
2591 else if (Op.isReg() && Op.isImplicit())
2592 ImpOps.push_back(Op);
2594 BeforeOps.push_back(Op);
2596 AfterOps.push_back(Op);
2599 // Emit the load instruction.
2601 std::pair<MachineInstr::mmo_iterator,
2602 MachineInstr::mmo_iterator> MMOs =
2603 MF.extractLoadMemRefs(MI->memoperands_begin(),
2604 MI->memoperands_end());
2605 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2607 // Address operands cannot be marked isKill.
2608 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
2609 MachineOperand &MO = NewMIs[0]->getOperand(i);
2611 MO.setIsKill(false);
2616 // Emit the data processing instruction.
2617 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2618 MachineInstrBuilder MIB(DataMI);
2621 MIB.addReg(Reg, RegState::Define);
2622 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2623 MIB.addOperand(BeforeOps[i]);
2626 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2627 MIB.addOperand(AfterOps[i]);
2628 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2629 MachineOperand &MO = ImpOps[i];
2630 MIB.addReg(MO.getReg(),
2631 getDefRegState(MO.isDef()) |
2632 RegState::Implicit |
2633 getKillRegState(MO.isKill()) |
2634 getDeadRegState(MO.isDead()) |
2635 getUndefRegState(MO.isUndef()));
2637 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2638 unsigned NewOpc = 0;
2639 switch (DataMI->getOpcode()) {
2641 case X86::CMP64ri32:
2648 MachineOperand &MO0 = DataMI->getOperand(0);
2649 MachineOperand &MO1 = DataMI->getOperand(1);
2650 if (MO1.getImm() == 0) {
2651 switch (DataMI->getOpcode()) {
2654 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2656 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2658 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2659 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2661 DataMI->setDesc(get(NewOpc));
2662 MO1.ChangeToRegister(MO0.getReg(), false);
2666 NewMIs.push_back(DataMI);
2668 // Emit the store instruction.
2670 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2671 std::pair<MachineInstr::mmo_iterator,
2672 MachineInstr::mmo_iterator> MMOs =
2673 MF.extractStoreMemRefs(MI->memoperands_begin(),
2674 MI->memoperands_end());
2675 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2682 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2683 SmallVectorImpl<SDNode*> &NewNodes) const {
2684 if (!N->isMachineOpcode())
2687 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2688 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2689 if (I == MemOp2RegOpTable.end())
2691 unsigned Opc = I->second.first;
2692 unsigned Index = I->second.second & 0xf;
2693 bool FoldedLoad = I->second.second & (1 << 4);
2694 bool FoldedStore = I->second.second & (1 << 5);
2695 const TargetInstrDesc &TID = get(Opc);
2696 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2697 unsigned NumDefs = TID.NumDefs;
2698 std::vector<SDValue> AddrOps;
2699 std::vector<SDValue> BeforeOps;
2700 std::vector<SDValue> AfterOps;
2701 DebugLoc dl = N->getDebugLoc();
2702 unsigned NumOps = N->getNumOperands();
2703 for (unsigned i = 0; i != NumOps-1; ++i) {
2704 SDValue Op = N->getOperand(i);
2705 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
2706 AddrOps.push_back(Op);
2707 else if (i < Index-NumDefs)
2708 BeforeOps.push_back(Op);
2709 else if (i > Index-NumDefs)
2710 AfterOps.push_back(Op);
2712 SDValue Chain = N->getOperand(NumOps-1);
2713 AddrOps.push_back(Chain);
2715 // Emit the load instruction.
2717 MachineFunction &MF = DAG.getMachineFunction();
2719 EVT VT = *RC->vt_begin();
2720 std::pair<MachineInstr::mmo_iterator,
2721 MachineInstr::mmo_iterator> MMOs =
2722 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2723 cast<MachineSDNode>(N)->memoperands_end());
2724 if (!(*MMOs.first) &&
2725 RC == &X86::VR128RegClass &&
2726 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2727 // Do not introduce a slow unaligned load.
2729 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2730 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2731 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2732 NewNodes.push_back(Load);
2734 // Preserve memory reference information.
2735 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2738 // Emit the data processing instruction.
2739 std::vector<EVT> VTs;
2740 const TargetRegisterClass *DstRC = 0;
2741 if (TID.getNumDefs() > 0) {
2742 DstRC = TID.OpInfo[0].getRegClass(&RI);
2743 VTs.push_back(*DstRC->vt_begin());
2745 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2746 EVT VT = N->getValueType(i);
2747 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2751 BeforeOps.push_back(SDValue(Load, 0));
2752 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2753 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2755 NewNodes.push_back(NewNode);
2757 // Emit the store instruction.
2760 AddrOps.push_back(SDValue(NewNode, 0));
2761 AddrOps.push_back(Chain);
2762 std::pair<MachineInstr::mmo_iterator,
2763 MachineInstr::mmo_iterator> MMOs =
2764 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2765 cast<MachineSDNode>(N)->memoperands_end());
2766 if (!(*MMOs.first) &&
2767 RC == &X86::VR128RegClass &&
2768 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2769 // Do not introduce a slow unaligned store.
2771 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2772 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2775 &AddrOps[0], AddrOps.size());
2776 NewNodes.push_back(Store);
2778 // Preserve memory reference information.
2779 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2785 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2786 bool UnfoldLoad, bool UnfoldStore,
2787 unsigned *LoadRegIndex) const {
2788 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2789 MemOp2RegOpTable.find((unsigned*)Opc);
2790 if (I == MemOp2RegOpTable.end())
2792 bool FoldedLoad = I->second.second & (1 << 4);
2793 bool FoldedStore = I->second.second & (1 << 5);
2794 if (UnfoldLoad && !FoldedLoad)
2796 if (UnfoldStore && !FoldedStore)
2799 *LoadRegIndex = I->second.second & 0xf;
2800 return I->second.first;
2804 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2805 int64_t &Offset1, int64_t &Offset2) const {
2806 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2808 unsigned Opc1 = Load1->getMachineOpcode();
2809 unsigned Opc2 = Load2->getMachineOpcode();
2811 default: return false;
2821 case X86::MMX_MOVD64rm:
2822 case X86::MMX_MOVQ64rm:
2823 case X86::FsMOVAPSrm:
2824 case X86::FsMOVAPDrm:
2827 case X86::MOVUPSrm_Int:
2831 case X86::MOVDQUrm_Int:
2835 default: return false;
2845 case X86::MMX_MOVD64rm:
2846 case X86::MMX_MOVQ64rm:
2847 case X86::FsMOVAPSrm:
2848 case X86::FsMOVAPDrm:
2851 case X86::MOVUPSrm_Int:
2855 case X86::MOVDQUrm_Int:
2859 // Check if chain operands and base addresses match.
2860 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2861 Load1->getOperand(5) != Load2->getOperand(5))
2863 // Segment operands should match as well.
2864 if (Load1->getOperand(4) != Load2->getOperand(4))
2866 // Scale should be 1, Index should be Reg0.
2867 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2868 Load1->getOperand(2) == Load2->getOperand(2)) {
2869 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2872 // Now let's examine the displacements.
2873 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2874 isa<ConstantSDNode>(Load2->getOperand(3))) {
2875 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2876 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2883 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2884 int64_t Offset1, int64_t Offset2,
2885 unsigned NumLoads) const {
2886 assert(Offset2 > Offset1);
2887 if ((Offset2 - Offset1) / 8 > 64)
2890 unsigned Opc1 = Load1->getMachineOpcode();
2891 unsigned Opc2 = Load2->getMachineOpcode();
2893 return false; // FIXME: overly conservative?
2900 case X86::MMX_MOVD64rm:
2901 case X86::MMX_MOVQ64rm:
2905 EVT VT = Load1->getValueType(0);
2906 switch (VT.getSimpleVT().SimpleTy) {
2908 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
2909 // have 16 of them to play with.
2910 if (TM.getSubtargetImpl()->is64Bit()) {
2913 } else if (NumLoads) {
2933 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2934 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2935 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2936 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2938 Cond[0].setImm(GetOppositeBranchCondition(CC));
2943 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2944 // FIXME: Return false for x87 stack register classes for now. We can't
2945 // allow any loads of these registers before FpGet_ST0_80.
2946 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2947 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2951 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
2952 /// register? e.g. r8, xmm8, xmm13, etc.
2953 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
2956 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2957 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2958 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2959 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2960 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2961 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2962 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2963 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2964 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2965 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2966 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
2967 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
2973 /// getGlobalBaseReg - Return a virtual register initialized with the
2974 /// the global base register value. Output instructions required to
2975 /// initialize the register in the function entry block, if necessary.
2977 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
2979 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
2980 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
2981 "X86-64 PIC uses RIP relative addressing");
2983 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2984 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
2985 if (GlobalBaseReg != 0)
2986 return GlobalBaseReg;
2988 // Create the register. The code to initialize it is inserted
2989 // later, by the CGBR pass (below).
2990 MachineRegisterInfo &RegInfo = MF->getRegInfo();
2991 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
2992 X86FI->setGlobalBaseReg(GlobalBaseReg);
2993 return GlobalBaseReg;
2996 // These are the replaceable SSE instructions. Some of these have Int variants
2997 // that we don't include here. We don't want to replace instructions selected
2999 static const unsigned ReplaceableInstrs[][3] = {
3000 //PackedSingle PackedDouble PackedInt
3001 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3002 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3003 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3004 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3005 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3006 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3007 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3008 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3009 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3010 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3011 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3012 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3013 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3014 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3015 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3016 // AVX 128-bit support
3017 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3018 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3019 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3020 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3021 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3022 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3023 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3024 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3025 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3026 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3027 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3028 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3029 { X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
3030 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3031 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3034 // FIXME: Some shuffle and unpack instructions have equivalents in different
3035 // domains, but they require a bit more work than just switching opcodes.
3037 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3038 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3039 if (ReplaceableInstrs[i][domain-1] == opcode)
3040 return ReplaceableInstrs[i];
3044 std::pair<uint16_t, uint16_t>
3045 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3046 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3047 return std::make_pair(domain,
3048 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3051 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3052 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3053 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3054 assert(dom && "Not an SSE instruction");
3055 const unsigned *table = lookup(MI->getOpcode(), dom);
3056 assert(table && "Cannot change domain");
3057 MI->setDesc(get(table[Domain-1]));
3060 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3061 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3062 NopInst.setOpcode(X86::NOOP);
3066 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3067 /// global base register for x86-32.
3068 struct CGBR : public MachineFunctionPass {
3070 CGBR() : MachineFunctionPass(ID) {}
3072 virtual bool runOnMachineFunction(MachineFunction &MF) {
3073 const X86TargetMachine *TM =
3074 static_cast<const X86TargetMachine *>(&MF.getTarget());
3076 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3077 "X86-64 PIC uses RIP relative addressing");
3079 // Only emit a global base reg in PIC mode.
3080 if (TM->getRelocationModel() != Reloc::PIC_)
3083 // Insert the set of GlobalBaseReg into the first MBB of the function
3084 MachineBasicBlock &FirstMBB = MF.front();
3085 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3086 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3087 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3088 const X86InstrInfo *TII = TM->getInstrInfo();
3091 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3092 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3094 PC = TII->getGlobalBaseReg(&MF);
3096 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3097 // only used in JIT code emission as displacement to pc.
3098 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3100 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3101 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3102 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3103 unsigned GlobalBaseReg = TII->getGlobalBaseReg(&MF);
3104 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3105 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3106 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3107 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3113 virtual const char *getPassName() const {
3114 return "X86 PIC Global Base Reg Initialization";
3117 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3118 AU.setPreservesCFG();
3119 MachineFunctionPass::getAnalysisUsage(AU);
3126 llvm::createGlobalBaseRegPass() { return new CGBR(); }