1 //===-- X86InstructionInfo.def - X86 Instruction Information ----*- C++ -*-===//
3 // This file describes all of the instructions that the X86 backend uses. It
4 // relys on an external 'I' macro being defined that takes the arguments
5 // specified below, and is used to make all of the information relevant to an
6 // instruction be in one place.
8 // Note that X86 Instructions always have the destination register listed as
9 // operand 0, unless it does not produce a value (in which case the TSFlags will
10 // include X86II::Void).
12 //===----------------------------------------------------------------------===//
14 // NOTE: No include guards desired
17 #errror "Must define I macro before including X86/X86InstructionInfo.def!"
20 // Macro to handle the implicit register uses lists...
22 #define IMPREGSLIST(NAME, ...)
25 // Implicit register usage info: O_ is for one register, T_ is for two registers
26 // NoIR means the instruction does not use implicit registers, in this form.
28 IMPREGSLIST(O_AL , X86::AL , 0)
29 IMPREGSLIST(O_AH , X86::AH , 0)
30 IMPREGSLIST(O_CL , X86::CL , 0)
31 IMPREGSLIST(O_AX , X86::AX , 0)
32 IMPREGSLIST(O_DX , X86::DX , 0)
33 IMPREGSLIST(O_EAX, X86::EAX, 0)
34 IMPREGSLIST(O_EDX, X86::EDX, 0)
35 IMPREGSLIST(O_EBP, X86::EBP, 0)
36 IMPREGSLIST(T_AXDX , X86::AX , X86::DX , 0)
37 IMPREGSLIST(T_EAXEDX, X86::EAX, X86::EDX, 0)
42 // Arguments to be passed into the I macro
43 // #1: Enum name - This ends up being the opcode symbol in the X86 namespace
44 // #2: Opcode name, as used by the gnu assembler
45 // #3: The base opcode for the instruction
46 // #4: Instruction Flags - This should be a field or'd together that contains
47 // constants from the MachineInstrInfo.h file.
48 // #5: Target Specific Flags - Another bitfield containing X86 specific flags
49 // that we are interested in for each instruction. These should be flags
50 // defined in X86InstrInfo.h in the X86II namespace.
51 // #6: Name of the implicit register uses list
52 // #7: Name of the implicit register definitions list
55 // The first instruction must always be the PHI instruction:
56 I(PHI , "phi", 0, 0, 0, NoIR, NoIR)
58 // The second instruction must always be the noop instruction:
59 I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void, NoIR, NoIR) // nop
61 // Flow control instructions
62 I(RET , "ret", 0xC3, M_RET_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // ret
63 I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // jmp foo
64 I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR,
66 I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR,
68 I(CALLpcrel32 , "call", 0xE8, M_BRANCH_FLAG, X86II::Void, NoIR, NoIR) // call pc+42
71 I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm, O_EBP, O_EBP) // leave
74 I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg, NoIR, NoIR) // R8 = R8
75 I(MOVrr16 , "movw", 0x89, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 = R16
76 I(MOVrr32 , "movl", 0x89, 0, X86II::MRMDestReg, NoIR, NoIR) // R32 = R32
77 I(MOVir8 , "movb", 0xB0, 0, X86II::AddRegFrm | X86II::Arg8, NoIR, NoIR) // R8 = imm8
78 I(MOVir16 , "movw", 0xB8, 0, X86II::AddRegFrm | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = imm16
79 I(MOVir32 , "movl", 0xB8, 0, X86II::AddRegFrm | X86II::Arg32, NoIR, NoIR) // R32 = imm32
80 I(MOVmr8 , "movb", 0x8A, 0, X86II::MRMSrcMem | X86II::Arg8, NoIR, NoIR) // R8 = [mem]
81 I(MOVmr16 , "movw", 0x8B, 0, X86II::MRMSrcMem | X86II::OpSize |
82 X86II::Arg16, NoIR, NoIR) // R16 = [mem]
83 I(MOVmr32 , "movl", 0x8B, 0, X86II::MRMSrcMem | X86II::Arg32, NoIR,
85 I(MOVrm8 , "movb", 0x88, 0, X86II::MRMDestMem | X86II::Void |
86 X86II::Arg8, NoIR, NoIR) // [mem] = R8
87 I(MOVrm16 , "movw", 0x89, 0, X86II::MRMDestMem | X86II::Void |
88 X86II::OpSize | X86II::Arg16, NoIR, NoIR) // [mem] = R16
89 I(MOVrm32 , "movl", 0x89, 0, X86II::MRMDestMem | X86II::Void |
90 X86II::Arg32, NoIR, NoIR) // [mem] = R32
92 I(PUSHr32 , "pushl", 0x50, 0, X86II::AddRegFrm | X86II::Void, NoIR, NoIR)
93 I(POPr32 , "popl", 0x58, 0, X86II::AddRegFrm, NoIR, NoIR)
95 // Arithmetic instructions
96 I(ADDrr8 , "addb", 0x00, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 += R8
97 I(ADDrr16 , "addw", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 += R16
98 I(ADDrr32 , "addl", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 += R32
99 I(ADDri32 , "add", 0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR) // R32 += imm32
100 I(SUBrr8 , "subb", 0x2A, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 -= R8
101 I(SUBrr16 , "subw", 0x2B, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16
102 I(SUBrr32 , "subl", 0x2B, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 -= R32
103 I(SUBri32 , "sub", 0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg32, NoIR, NoIR) // R32 -= imm32
104 I(MULrr8 , "mulb", 0xF6, 0, X86II::MRMS4r | X86II::Void, O_AL, O_AX) // AX = AL*R8
105 I(MULrr16 , "mulw", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16
106 X86II::OpSize, O_AX, T_AXDX)
107 I(MULrr32 , "mull", 0xF7, 0, X86II::MRMS4r | X86II::Void, O_EAX, T_EAXEDX) // ED:EA= EA*R32
109 // unsigned division/remainder
110 I(DIVrr8 , "divb", 0xF6, 0, X86II::MRMS6r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
111 I(DIVrr16 , "divw", 0xF7, 0, X86II::MRMS6r | X86II::Void | // ED:EA/r16=AX&DX
112 X86II::OpSize, T_AXDX, T_AXDX)
113 I(DIVrr32 , "divl", 0xF7, 0, X86II::MRMS6r | X86II::Void, T_EAXEDX,
114 T_EAXEDX) // ED:EA/r32=EA&ED
116 // signed division/remainder
117 I(IDIVrr8 , "idivb", 0xF6, 0, X86II::MRMS7r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
118 I(IDIVrr16 , "idivw", 0xF7, 0, X86II::MRMS7r | X86II::Void | // DA/r16=AX&DX
119 X86II::OpSize, T_AXDX, T_AXDX)
120 I(IDIVrr32 , "idivl", 0xF7, 0, X86II::MRMS7r | X86II::Void, T_EAXEDX,
121 T_EAXEDX) // DA/r32=EAX&DX
124 I(ANDrr8 , "andb", 0x20, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 &= R8
125 I(ANDrr16 , "andw", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 &= R16
126 I(ANDrr32 , "andl", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 &= R32
127 I(ORrr8 , "orb", 0x08, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 |= R8
128 I(ORrr16 , "orw", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 |= R16
129 I(ORrr32 , "orl", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 |= R32
130 I(XORrr8 , "xorb", 0x30, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 ^= R8
131 I(XORrr16 , "xorw", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 ^= R16
132 I(XORrr32 , "xorl", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 ^= R32
134 // Shift instructions
135 I(SHLrr8 , "shlb", 0xD2, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR) // R8 <<= cl
136 I(SHLrr16 , "shlw", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::OpSize, O_CL, NoIR) // R16 <<= cl
137 I(SHLrr32 , "shll", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR) // R32 <<= cl
138 I(SHLir8 , "shlb", 0xC0, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R8 <<= imm8
139 I(SHLir16 , "shlw", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 <<= imm8
140 I(SHLir32 , "shll", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R32 <<= imm8
141 I(SHRrr8 , "shrb", 0xD2, M_2_ADDR_FLAG, X86II::MRMS5r, O_CL, NoIR) // R8 >>>= cl
142 I(SHRrr16 , "shrw", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::OpSize, O_CL, NoIR) // R16 >>>= cl
143 I(SHRrr32 , "shrl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r, O_CL, NoIR) // R32 >>>= cl
144 I(SHRir8 , "shrb", 0xC0, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R8 >>>= imm8
145 I(SHRir16 , "shrw", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>>= imm8
146 I(SHRir32 , "shrl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R32 >>>= imm8
147 I(SARrr8 , "sarb", 0xD2, M_2_ADDR_FLAG, X86II::MRMS7r, O_CL, NoIR) // R8 >>= cl
148 I(SARrr16 , "sarw", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::OpSize, O_CL, NoIR) // R16 >>= cl
149 I(SARrr32 , "sarl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r, O_CL, NoIR) // R32 >>= cl
150 I(SARir8 , "sarb", 0xC0, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R8 >>= imm8
151 I(SARir16 , "sarw", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>= imm8
152 I(SARir32 , "sarl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R32 >>= imm8
154 // Floating point loads
155 I(FLDr32 , "flds", 0xD9, 0, X86II::MRMS0m, NoIR, NoIR) // push float
156 I(FLDr64 , "fldl", 0xDD, 0, X86II::MRMS0m, NoIR, NoIR) // push double
158 // Floating point compares
159 I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void, NoIR, NoIR) // compare+pop2x
161 // Floating point flag ops
162 I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void, NoIR, O_AX) // AX = fp flags
164 // Condition code ops, incl. set if equal/not equal/...
165 I(SAHF , "sahf", 0x9E, 0, X86II::RawFrm, O_AH, NoIR) // flags = AH
166 I(SETBr , "setb", 0x92, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = < unsign
167 I(SETAEr , "setae", 0x93, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = >=unsign
168 I(SETEr , "sete", 0x94, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = ==
169 I(SETNEr , "setne", 0x95, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = !=
170 I(SETBEr , "setbe", 0x96, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = <=unsign
171 I(SETAr , "seta", 0x97, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = > unsign
172 I(SETLr , "setl", 0x9C, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = < signed
173 I(SETGEr , "setge", 0x9D, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = >=signed
174 I(SETLEr , "setle", 0x9E, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = <=signed
175 I(SETGr , "setg", 0x9F, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = > signed
177 // Integer comparisons
178 I(CMPrr8 , "cmpb", 0x38, 0, X86II::MRMDestReg, NoIR, NoIR) // compare R8,R8
179 I(CMPrr16 , "cmpw", 0x39, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // compare R16,R16
180 I(CMPrr32 , "cmpl", 0x39, 0, X86II::MRMDestReg, NoIR, NoIR) // compare R32,R32
181 I(CMPri8 , "cmp", 0x80, 0, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // compare R8, imm8
183 // Sign extenders (first 3 are good for DIV/IDIV; the others are more general)
184 I(CBW , "cbw", 0x98, 0, X86II::RawFrm | X86II::OpSize, O_AL, O_AX) // AX = signext(AL)
185 I(CWD , "cwd", 0x99, 0, X86II::RawFrm, O_AX, O_DX) // DX:AX = signext(AX)
186 I(CDQ , "cdq", 0x99, 0, X86II::RawFrm, O_EAX, O_EDX) // EDX:EAX = signext(EAX)
187 I(MOVSXr16r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB | // R16 = signext(R8)
188 X86II::OpSize, NoIR, NoIR)
189 I(MOVSXr32r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = signext(R8)
190 I(MOVSXr32r16 , "movsx", 0xBF, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = signext(R16)
191 I(MOVZXr16r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB | // R16 = zeroext(R8)
192 X86II::OpSize, NoIR, NoIR)
193 I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R8)
194 I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R16)
196 // At this point, I is dead, so undefine the macro