1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
24 class X86RegisterInfo;
25 class X86TargetMachine;
28 // X86 specific condition code. These correspond to X86_*_COND in
29 // X86InstrInfo.td. They must be kept in synch.
48 // Artificial condition codes. These are used by AnalyzeBranch
49 // to indicate a block terminated with two conditional branches to
50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
51 // which can't be represented on x86 with a single condition. These
52 // are never used in MachineInstrs.
59 // Turn condition code into conditional branch opcode.
60 unsigned GetCondBranchFromCond(CondCode CC);
62 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
63 /// e.g. turning COND_E to COND_NE.
64 CondCode GetOppositeBranchCondition(X86::CondCode CC);
68 /// X86II - This namespace holds all of the target specific flags that
69 /// instruction info tracks.
73 //===------------------------------------------------------------------===//
74 // Instruction types. These are the standard/most common forms for X86
78 // PseudoFrm - This represents an instruction that is a pseudo instruction
79 // or one that has not been implemented yet. It is illegal to code generate
80 // it, but tolerated for intermediate implementation stages.
83 /// Raw - This form is for instructions that don't have any operands, so
84 /// they are just a fixed opcode value, like 'leave'.
87 /// AddRegFrm - This form is used for instructions like 'push r32' that have
88 /// their one register operand added to their opcode.
91 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
92 /// to specify a destination, which in this case is a register.
96 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
97 /// to specify a destination, which in this case is memory.
101 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
102 /// to specify a source, which in this case is a register.
106 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
107 /// to specify a source, which in this case is memory.
111 /// MRM[0-7][rm] - These forms are used to represent instructions that use
112 /// a Mod/RM byte, and use the middle field to hold extended opcode
113 /// information. In the intel manual these are represented as /0, /1, ...
116 // First, instructions that operate on a register r/m operand...
117 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
118 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
120 // Next, instructions that operate on a memory r/m operand...
121 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
122 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
124 // MRMInitReg - This form is used for instructions whose source and
125 // destinations are the same register.
130 //===------------------------------------------------------------------===//
133 // OpSize - Set if this instruction requires an operand size prefix (0x66),
134 // which most often indicates that the instruction operates on 16 bit data
135 // instead of 32 bit data.
138 // AsSize - Set if this instruction requires an operand size prefix (0x67),
139 // which most often indicates that the instruction address 16 bit address
140 // instead of 32 bit address (or 32 bit address in 64 bit mode).
143 //===------------------------------------------------------------------===//
144 // Op0Mask - There are several prefix bytes that are used to form two byte
145 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
146 // used to obtain the setting of this field. If no bits in this field is
147 // set, there is no prefix byte for obtaining a multibyte opcode.
150 Op0Mask = 0xF << Op0Shift,
152 // TB - TwoByte - Set if this instruction has a two byte opcode, which
153 // starts with a 0x0F byte before the real opcode.
156 // REP - The 0xF3 prefix byte indicating repetition of the following
160 // D8-DF - These escape opcodes are used by the floating point unit. These
161 // values must remain sequential.
162 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
163 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
164 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
165 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
167 // XS, XD - These prefix codes are for single and double precision scalar
168 // floating point operations performed in the SSE registers.
169 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
171 // T8, TA - Prefix after the 0x0F prefix.
172 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
174 //===------------------------------------------------------------------===//
175 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
176 // They are used to specify GPRs and SSE registers, 64-bit operand size,
177 // etc. We only cares about REX.W and REX.R bits and only the former is
178 // statically determined.
181 REX_W = 1 << REXShift,
183 //===------------------------------------------------------------------===//
184 // This three-bit field describes the size of an immediate operand. Zero is
185 // unused so that we can tell if we forgot to set a value.
187 ImmMask = 7 << ImmShift,
188 Imm8 = 1 << ImmShift,
189 Imm16 = 2 << ImmShift,
190 Imm32 = 3 << ImmShift,
191 Imm64 = 4 << ImmShift,
193 //===------------------------------------------------------------------===//
194 // FP Instruction Classification... Zero is non-fp instruction.
196 // FPTypeMask - Mask for all of the FP types...
198 FPTypeMask = 7 << FPTypeShift,
200 // NotFP - The default, set for instructions that do not use FP registers.
201 NotFP = 0 << FPTypeShift,
203 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
204 ZeroArgFP = 1 << FPTypeShift,
206 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
207 OneArgFP = 2 << FPTypeShift,
209 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
210 // result back to ST(0). For example, fcos, fsqrt, etc.
212 OneArgFPRW = 3 << FPTypeShift,
214 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
215 // explicit argument, storing the result to either ST(0) or the implicit
216 // argument. For example: fadd, fsub, fmul, etc...
217 TwoArgFP = 4 << FPTypeShift,
219 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
220 // explicit argument, but have no destination. Example: fucom, fucomi, ...
221 CompareFP = 5 << FPTypeShift,
223 // CondMovFP - "2 operand" floating point conditional move instructions.
224 CondMovFP = 6 << FPTypeShift,
226 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
227 SpecialFP = 7 << FPTypeShift,
231 LOCK = 1 << LOCKShift,
233 // Segment override prefixes. Currently we just need ability to address
234 // stuff in gs and fs segments.
236 SegOvrMask = 3 << SegOvrShift,
237 FS = 1 << SegOvrShift,
238 GS = 2 << SegOvrShift,
240 // Bits 22 -> 23 are unused
242 OpcodeMask = 0xFF << OpcodeShift
246 const int X86AddrNumOperands = 4;
248 inline static bool isScale(const MachineOperand &MO) {
250 (MO.getImm() == 1 || MO.getImm() == 2 ||
251 MO.getImm() == 4 || MO.getImm() == 8);
254 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
255 if (MI->getOperand(Op).isFI()) return true;
256 return Op+4 <= MI->getNumOperands() &&
257 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
258 MI->getOperand(Op+2).isReg() &&
259 (MI->getOperand(Op+3).isImm() ||
260 MI->getOperand(Op+3).isGlobal() ||
261 MI->getOperand(Op+3).isCPI() ||
262 MI->getOperand(Op+3).isJTI());
265 class X86InstrInfo : public TargetInstrInfoImpl {
266 X86TargetMachine &TM;
267 const X86RegisterInfo RI;
269 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
270 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
272 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
273 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
274 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
275 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
277 /// MemOp2RegOpTable - Load / store unfolding opcode map.
279 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
282 explicit X86InstrInfo(X86TargetMachine &tm);
284 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
285 /// such, whenever a client has an instance of instruction info, it should
286 /// always be able to get register info as well (through this method).
288 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
290 /// Return true if the instruction is a register to register move and return
291 /// the source and dest operands and their sub-register indices by reference.
292 virtual bool isMoveInstr(const MachineInstr &MI,
293 unsigned &SrcReg, unsigned &DstReg,
294 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
296 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
297 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
299 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const;
300 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
301 unsigned DestReg, const MachineInstr *Orig) const;
303 bool isInvariantLoad(const MachineInstr *MI) const;
305 /// convertToThreeAddress - This method must be implemented by targets that
306 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
307 /// may be able to convert a two-address instruction into a true
308 /// three-address instruction on demand. This allows the X86 target (for
309 /// example) to convert ADD and SHL instructions into LEA instructions if they
310 /// would require register copies due to two-addressness.
312 /// This method returns a null pointer if the transformation cannot be
313 /// performed, otherwise it returns the new instruction.
315 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
316 MachineBasicBlock::iterator &MBBI,
317 LiveVariables *LV) const;
319 /// commuteInstruction - We have a few instructions that must be hacked on to
322 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
325 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
326 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
327 MachineBasicBlock *&FBB,
328 SmallVectorImpl<MachineOperand> &Cond,
329 bool AllowModify) const;
330 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
331 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
332 MachineBasicBlock *FBB,
333 const SmallVectorImpl<MachineOperand> &Cond) const;
334 virtual bool copyRegToReg(MachineBasicBlock &MBB,
335 MachineBasicBlock::iterator MI,
336 unsigned DestReg, unsigned SrcReg,
337 const TargetRegisterClass *DestRC,
338 const TargetRegisterClass *SrcRC) const;
339 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
340 MachineBasicBlock::iterator MI,
341 unsigned SrcReg, bool isKill, int FrameIndex,
342 const TargetRegisterClass *RC) const;
344 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
345 SmallVectorImpl<MachineOperand> &Addr,
346 const TargetRegisterClass *RC,
347 SmallVectorImpl<MachineInstr*> &NewMIs) const;
349 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
350 MachineBasicBlock::iterator MI,
351 unsigned DestReg, int FrameIndex,
352 const TargetRegisterClass *RC) const;
354 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
355 SmallVectorImpl<MachineOperand> &Addr,
356 const TargetRegisterClass *RC,
357 SmallVectorImpl<MachineInstr*> &NewMIs) const;
359 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator MI,
361 const std::vector<CalleeSavedInfo> &CSI) const;
363 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
364 MachineBasicBlock::iterator MI,
365 const std::vector<CalleeSavedInfo> &CSI) const;
367 /// foldMemoryOperand - If this target supports it, fold a load or store of
368 /// the specified stack slot into the specified machine instruction for the
369 /// specified operand(s). If this is possible, the target should perform the
370 /// folding and return true, otherwise it should return false. If it folds
371 /// the instruction, it is likely that the MachineInstruction the iterator
372 /// references has been changed.
373 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
375 const SmallVectorImpl<unsigned> &Ops,
376 int FrameIndex) const;
378 /// foldMemoryOperand - Same as the previous version except it allows folding
379 /// of any load and store from / to any address, not just from a specific
381 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
383 const SmallVectorImpl<unsigned> &Ops,
384 MachineInstr* LoadMI) const;
386 /// canFoldMemoryOperand - Returns true if the specified load / store is
387 /// folding is possible.
388 virtual bool canFoldMemoryOperand(const MachineInstr*,
389 const SmallVectorImpl<unsigned> &) const;
391 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
392 /// a store or a load and a store into two or more instruction. If this is
393 /// possible, returns true as well as the new instructions by reference.
394 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
395 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
396 SmallVectorImpl<MachineInstr*> &NewMIs) const;
398 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
399 SmallVectorImpl<SDNode*> &NewNodes) const;
401 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
402 /// instruction after load / store are unfolded from an instruction of the
403 /// specified opcode. It returns zero if the specified unfolding is not
405 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
406 bool UnfoldLoad, bool UnfoldStore) const;
408 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
410 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
412 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
413 /// instruction that defines the specified register class.
414 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
416 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
417 // specified machine instruction.
419 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
420 return TID->TSFlags >> X86II::OpcodeShift;
422 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
423 return getBaseOpcodeFor(&get(Opcode));
426 static bool isX86_64NonExtLowByteReg(unsigned reg) {
427 return (reg == X86::SPL || reg == X86::BPL ||
428 reg == X86::SIL || reg == X86::DIL);
431 static unsigned sizeOfImm(const TargetInstrDesc *Desc);
432 static bool isX86_64ExtendedReg(const MachineOperand &MO);
433 static unsigned determineREX(const MachineInstr &MI);
435 /// GetInstSize - Returns the size of the specified MachineInstr.
437 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
439 /// getGlobalBaseReg - Return a virtual register initialized with the
440 /// the global base register value. Output instructions required to
441 /// initialize the register in the function entry block, if necessary.
443 unsigned getGlobalBaseReg(MachineFunction *MF) const;
446 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
449 const SmallVectorImpl<MachineOperand> &MOs) const;
452 } // End llvm namespace