1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
26 class X86RegisterInfo;
27 class X86TargetMachine;
30 // X86 specific condition code. These correspond to X86_*_COND in
31 // X86InstrInfo.td. They must be kept in synch.
50 // Artificial condition codes. These are used by AnalyzeBranch
51 // to indicate a block terminated with two conditional branches to
52 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
53 // which can't be represented on x86 with a single condition. These
54 // are never used in MachineInstrs.
61 // Turn condition code into conditional branch opcode.
62 unsigned GetCondBranchFromCond(CondCode CC);
64 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
65 /// e.g. turning COND_E to COND_NE.
66 CondCode GetOppositeBranchCondition(X86::CondCode CC);
67 } // end namespace X86;
70 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
71 /// a reference to a stub for a global, not the global itself.
72 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
74 case X86II::MO_DLLIMPORT: // dllimport stub.
75 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
76 case X86II::MO_GOT: // normal GOT reference.
77 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
78 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
79 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
86 /// isGlobalRelativeToPICBase - Return true if the specified global value
87 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
88 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
89 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
91 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
92 case X86II::MO_GOT: // isPICStyleGOT: other global.
93 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
94 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
95 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
96 case X86II::MO_TLVP: // ??? Pretty sure..
103 inline static bool isScale(const MachineOperand &MO) {
105 (MO.getImm() == 1 || MO.getImm() == 2 ||
106 MO.getImm() == 4 || MO.getImm() == 8);
109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
110 if (MI->getOperand(Op).isFI()) return true;
111 return Op+4 <= MI->getNumOperands() &&
112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
113 MI->getOperand(Op+2).isReg() &&
114 (MI->getOperand(Op+3).isImm() ||
115 MI->getOperand(Op+3).isGlobal() ||
116 MI->getOperand(Op+3).isCPI() ||
117 MI->getOperand(Op+3).isJTI());
120 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
121 if (MI->getOperand(Op).isFI()) return true;
122 return Op+5 <= MI->getNumOperands() &&
123 MI->getOperand(Op+4).isReg() &&
127 class X86InstrInfo : public X86GenInstrInfo {
128 X86TargetMachine &TM;
129 const X86RegisterInfo RI;
131 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
132 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
134 typedef DenseMap<unsigned,
135 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
136 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
137 RegOp2MemOpTableType RegOp2MemOpTable0;
138 RegOp2MemOpTableType RegOp2MemOpTable1;
139 RegOp2MemOpTableType RegOp2MemOpTable2;
140 RegOp2MemOpTableType RegOp2MemOpTable3;
142 /// MemOp2RegOpTable - Load / store unfolding opcode map.
144 typedef DenseMap<unsigned,
145 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
146 MemOp2RegOpTableType MemOp2RegOpTable;
148 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
149 MemOp2RegOpTableType &M2RTable,
150 unsigned RegOp, unsigned MemOp, unsigned Flags);
153 explicit X86InstrInfo(X86TargetMachine &tm);
155 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
156 /// such, whenever a client has an instance of instruction info, it should
157 /// always be able to get register info as well (through this method).
159 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
161 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
162 /// extension instruction. That is, it's like a copy where it's legal for the
163 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
164 /// true, then it's expected the pre-extension value is available as a subreg
165 /// of the result register. This also returns the sub-register index in
167 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
168 unsigned &SrcReg, unsigned &DstReg,
169 unsigned &SubIdx) const;
171 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
172 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
173 /// stack locations as well. This uses a heuristic so it isn't
174 /// reliable for correctness.
175 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
176 int &FrameIndex) const;
178 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
179 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
180 /// stack locations as well. This uses a heuristic so it isn't
181 /// reliable for correctness.
182 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
183 int &FrameIndex) const;
185 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
186 AliasAnalysis *AA) const;
187 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
188 unsigned DestReg, unsigned SubIdx,
189 const MachineInstr *Orig,
190 const TargetRegisterInfo &TRI) const;
192 /// convertToThreeAddress - This method must be implemented by targets that
193 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
194 /// may be able to convert a two-address instruction into a true
195 /// three-address instruction on demand. This allows the X86 target (for
196 /// example) to convert ADD and SHL instructions into LEA instructions if they
197 /// would require register copies due to two-addressness.
199 /// This method returns a null pointer if the transformation cannot be
200 /// performed, otherwise it returns the new instruction.
202 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
203 MachineBasicBlock::iterator &MBBI,
204 LiveVariables *LV) const;
206 /// commuteInstruction - We have a few instructions that must be hacked on to
209 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
212 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
213 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
214 MachineBasicBlock *&FBB,
215 SmallVectorImpl<MachineOperand> &Cond,
216 bool AllowModify) const;
217 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
218 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
219 MachineBasicBlock *FBB,
220 const SmallVectorImpl<MachineOperand> &Cond,
222 virtual void copyPhysReg(MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator MI, DebugLoc DL,
224 unsigned DestReg, unsigned SrcReg,
226 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
227 MachineBasicBlock::iterator MI,
228 unsigned SrcReg, bool isKill, int FrameIndex,
229 const TargetRegisterClass *RC,
230 const TargetRegisterInfo *TRI) const;
232 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
233 SmallVectorImpl<MachineOperand> &Addr,
234 const TargetRegisterClass *RC,
235 MachineInstr::mmo_iterator MMOBegin,
236 MachineInstr::mmo_iterator MMOEnd,
237 SmallVectorImpl<MachineInstr*> &NewMIs) const;
239 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator MI,
241 unsigned DestReg, int FrameIndex,
242 const TargetRegisterClass *RC,
243 const TargetRegisterInfo *TRI) const;
245 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
246 SmallVectorImpl<MachineOperand> &Addr,
247 const TargetRegisterClass *RC,
248 MachineInstr::mmo_iterator MMOBegin,
249 MachineInstr::mmo_iterator MMOEnd,
250 SmallVectorImpl<MachineInstr*> &NewMIs) const;
252 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
255 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
256 int FrameIx, uint64_t Offset,
260 /// foldMemoryOperand - If this target supports it, fold a load or store of
261 /// the specified stack slot into the specified machine instruction for the
262 /// specified operand(s). If this is possible, the target should perform the
263 /// folding and return true, otherwise it should return false. If it folds
264 /// the instruction, it is likely that the MachineInstruction the iterator
265 /// references has been changed.
266 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
268 const SmallVectorImpl<unsigned> &Ops,
269 int FrameIndex) const;
271 /// foldMemoryOperand - Same as the previous version except it allows folding
272 /// of any load and store from / to any address, not just from a specific
274 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
276 const SmallVectorImpl<unsigned> &Ops,
277 MachineInstr* LoadMI) const;
279 /// canFoldMemoryOperand - Returns true if the specified load / store is
280 /// folding is possible.
281 virtual bool canFoldMemoryOperand(const MachineInstr*,
282 const SmallVectorImpl<unsigned> &) const;
284 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
285 /// a store or a load and a store into two or more instruction. If this is
286 /// possible, returns true as well as the new instructions by reference.
287 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
288 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
289 SmallVectorImpl<MachineInstr*> &NewMIs) const;
291 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
292 SmallVectorImpl<SDNode*> &NewNodes) const;
294 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
295 /// instruction after load / store are unfolded from an instruction of the
296 /// specified opcode. It returns zero if the specified unfolding is not
297 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
298 /// index of the operand which will hold the register holding the loaded
300 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
301 bool UnfoldLoad, bool UnfoldStore,
302 unsigned *LoadRegIndex = 0) const;
304 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
305 /// to determine if two loads are loading from the same base address. It
306 /// should only return true if the base pointers are the same and the
307 /// only differences between the two addresses are the offset. It also returns
308 /// the offsets by reference.
309 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
310 int64_t &Offset1, int64_t &Offset2) const;
312 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
313 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
314 /// be scheduled togther. On some targets if two loads are loading from
315 /// addresses in the same cache line, it's better if they are scheduled
316 /// together. This function takes two integers that represent the load offsets
317 /// from the common base address. It returns true if it decides it's desirable
318 /// to schedule the two loads together. "NumLoads" is the number of loads that
319 /// have already been scheduled after Load1.
320 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
321 int64_t Offset1, int64_t Offset2,
322 unsigned NumLoads) const;
324 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
327 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
329 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
330 /// instruction that defines the specified register class.
331 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
333 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
334 if (!MO.isReg()) return false;
335 return X86II::isX86_64ExtendedReg(MO.getReg());
338 /// getGlobalBaseReg - Return a virtual register initialized with the
339 /// the global base register value. Output instructions required to
340 /// initialize the register in the function entry block, if necessary.
342 unsigned getGlobalBaseReg(MachineFunction *MF) const;
344 std::pair<uint16_t, uint16_t>
345 getExecutionDomain(const MachineInstr *MI) const;
347 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
349 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
350 const TargetRegisterInfo *TRI) const;
351 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
352 const TargetRegisterInfo *TRI) const;
354 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
357 const SmallVectorImpl<MachineOperand> &MOs,
358 unsigned Size, unsigned Alignment) const;
360 bool isHighLatencyDef(int opc) const;
362 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
363 const MachineRegisterInfo *MRI,
364 const MachineInstr *DefMI, unsigned DefIdx,
365 const MachineInstr *UseMI, unsigned UseIdx) const;
368 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
369 MachineFunction::iterator &MFI,
370 MachineBasicBlock::iterator &MBBI,
371 LiveVariables *LV) const;
373 /// isFrameOperand - Return true and the FrameIndex if the specified
374 /// operand and follow operands form a reference to the stack frame.
375 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
376 int &FrameIndex) const;
379 } // End llvm namespace