1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "X86RegisterInfo.h"
22 /// X86II - This namespace holds all of the target specific flags that
23 /// instruction info tracks.
27 //===------------------------------------------------------------------===//
28 // Instruction types. These are the standard/most common forms for X86
32 // PseudoFrm - This represents an instruction that is a pseudo instruction
33 // or one that has not been implemented yet. It is illegal to code generate
34 // it, but tolerated for intermediate implementation stages.
37 /// Raw - This form is for instructions that don't have any operands, so
38 /// they are just a fixed opcode value, like 'leave'.
41 /// AddRegFrm - This form is used for instructions like 'push r32' that have
42 /// their one register operand added to their opcode.
45 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
46 /// to specify a destination, which in this case is a register.
50 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
51 /// to specify a destination, which in this case is memory.
55 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
56 /// to specify a source, which in this case is a register.
60 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
61 /// to specify a source, which in this case is memory.
65 /// MRM[0-7][rm] - These forms are used to represent instructions that use
66 /// a Mod/RM byte, and use the middle field to hold extended opcode
67 /// information. In the intel manual these are represented as /0, /1, ...
70 // First, instructions that operate on a register r/m operand...
71 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
72 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
74 // Next, instructions that operate on a memory r/m operand...
75 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
76 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
80 //===------------------------------------------------------------------===//
83 // OpSize - Set if this instruction requires an operand size prefix (0x66),
84 // which most often indicates that the instruction operates on 16 bit data
85 // instead of 32 bit data.
88 // Op0Mask - There are several prefix bytes that are used to form two byte
89 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
90 // used to obtain the setting of this field. If no bits in this field is
91 // set, there is no prefix byte for obtaining a multibyte opcode.
94 Op0Mask = 0xF << Op0Shift,
96 // TB - TwoByte - Set if this instruction has a two byte opcode, which
97 // starts with a 0x0F byte before the real opcode.
100 // REP - The 0xF3 prefix byte indicating repetition of the following
104 // D8-DF - These escape opcodes are used by the floating point unit. These
105 // values must remain sequential.
106 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
107 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
108 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
109 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
111 //===------------------------------------------------------------------===//
112 // This three-bit field describes the size of a memory operand. Zero is
113 // unused so that we can tell if we forgot to set a value.
115 MemMask = 7 << MemShift,
116 Mem8 = 1 << MemShift,
117 Mem16 = 2 << MemShift,
118 Mem32 = 3 << MemShift,
119 Mem64 = 4 << MemShift,
120 Mem80 = 5 << MemShift,
121 Mem128 = 6 << MemShift,
123 //===------------------------------------------------------------------===//
124 // This two-bit field describes the size of an immediate operand. Zero is
125 // unused so that we can tell if we forgot to set a value.
127 ImmMask = 7 << ImmShift,
128 Imm8 = 1 << ImmShift,
129 Imm16 = 2 << ImmShift,
130 Imm32 = 3 << ImmShift,
132 //===------------------------------------------------------------------===//
133 // FP Instruction Classification... Zero is non-fp instruction.
135 // FPTypeMask - Mask for all of the FP types...
137 FPTypeMask = 7 << FPTypeShift,
139 // NotFP - The default, set for instructions that do not use FP registers.
140 NotFP = 0 << FPTypeShift,
142 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
143 ZeroArgFP = 1 << FPTypeShift,
145 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
146 OneArgFP = 2 << FPTypeShift,
148 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
149 // result back to ST(0). For example, fcos, fsqrt, etc.
151 OneArgFPRW = 3 << FPTypeShift,
153 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
154 // explicit argument, storing the result to either ST(0) or the implicit
155 // argument. For example: fadd, fsub, fmul, etc...
156 TwoArgFP = 4 << FPTypeShift,
158 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
159 // explicit argument, but have no destination. Example: fucom, fucomi, ...
160 CompareFP = 5 << FPTypeShift,
162 // CondMovFP - "2 operand" floating point conditional move instructions.
163 CondMovFP = 6 << FPTypeShift,
165 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
166 SpecialFP = 7 << FPTypeShift,
168 // PrintImplUsesAfter - Print out implicit uses in the assembly output after
169 // the normal operands.
170 PrintImplUsesAfter = 1 << 18,
172 // PrintImplUsesBefore - Print out implicit uses in the assembly output
173 // before the normal operands.
174 PrintImplUsesBefore = 1 << 19,
176 // PrintImplDefsAfter - Print out implicit defs in the assembly output
177 // after the normal operands.
178 PrintImplDefsBefore = 1 << 20,
179 PrintImplDefsAfter = 1 << 21,
182 OpcodeMask = 0xFF << OpcodeShift,
183 // Bits 27 -> 31 are unused
187 class X86InstrInfo : public TargetInstrInfo {
188 const X86RegisterInfo RI;
192 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
193 /// such, whenever a client has an instance of instruction info, it should
194 /// always be able to get register info as well (through this method).
196 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
199 // Return true if the instruction is a register to register move and
200 // leave the source and dest operands in the passed parameters.
202 virtual bool isMoveInstr(const MachineInstr& MI,
204 unsigned& destReg) const;
206 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
207 // specified opcode number.
209 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
210 return get(Opcode).TSFlags >> X86II::OpcodeShift;
214 } // End llvm namespace