1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "X86RegisterInfo.h"
22 /// X86II - This namespace holds all of the target specific flags that
23 /// instruction info tracks.
27 //===------------------------------------------------------------------===//
28 // Instruction types. These are the standard/most common forms for X86
32 // PseudoFrm - This represents an instruction that is a pseudo instruction
33 // or one that has not been implemented yet. It is illegal to code generate
34 // it, but tolerated for intermediate implementation stages.
37 /// Raw - This form is for instructions that don't have any operands, so
38 /// they are just a fixed opcode value, like 'leave'.
41 /// AddRegFrm - This form is used for instructions like 'push r32' that have
42 /// their one register operand added to their opcode.
45 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
46 /// to specify a destination, which in this case is a register.
50 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
51 /// to specify a destination, which in this case is memory.
55 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
56 /// to specify a source, which in this case is a register.
60 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
61 /// to specify a source, which in this case is memory.
65 /// MRM[0-7][rm] - These forms are used to represent instructions that use
66 /// a Mod/RM byte, and use the middle field to hold extended opcode
67 /// information. In the intel manual these are represented as /0, /1, ...
70 // First, instructions that operate on a register r/m operand...
71 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
72 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
74 // Next, instructions that operate on a memory r/m operand...
75 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
76 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
78 // MRMInitReg - This form is used for instructions whose source and
79 // destinations are the same register.
84 //===------------------------------------------------------------------===//
87 // OpSize - Set if this instruction requires an operand size prefix (0x66),
88 // which most often indicates that the instruction operates on 16 bit data
89 // instead of 32 bit data.
92 // Op0Mask - There are several prefix bytes that are used to form two byte
93 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
94 // used to obtain the setting of this field. If no bits in this field is
95 // set, there is no prefix byte for obtaining a multibyte opcode.
98 Op0Mask = 0xF << Op0Shift,
100 // TB - TwoByte - Set if this instruction has a two byte opcode, which
101 // starts with a 0x0F byte before the real opcode.
104 // REP - The 0xF3 prefix byte indicating repetition of the following
108 // D8-DF - These escape opcodes are used by the floating point unit. These
109 // values must remain sequential.
110 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
111 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
112 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
113 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
115 // XS, XD - These prefix codes are for single and double precision scalar
116 // floating point operations performed in the SSE registers.
117 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
119 //===------------------------------------------------------------------===//
120 // This two-bit field describes the size of an immediate operand. Zero is
121 // unused so that we can tell if we forgot to set a value.
123 ImmMask = 7 << ImmShift,
124 Imm8 = 1 << ImmShift,
125 Imm16 = 2 << ImmShift,
126 Imm32 = 3 << ImmShift,
128 //===------------------------------------------------------------------===//
129 // FP Instruction Classification... Zero is non-fp instruction.
131 // FPTypeMask - Mask for all of the FP types...
133 FPTypeMask = 7 << FPTypeShift,
135 // NotFP - The default, set for instructions that do not use FP registers.
136 NotFP = 0 << FPTypeShift,
138 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
139 ZeroArgFP = 1 << FPTypeShift,
141 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
142 OneArgFP = 2 << FPTypeShift,
144 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
145 // result back to ST(0). For example, fcos, fsqrt, etc.
147 OneArgFPRW = 3 << FPTypeShift,
149 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
150 // explicit argument, storing the result to either ST(0) or the implicit
151 // argument. For example: fadd, fsub, fmul, etc...
152 TwoArgFP = 4 << FPTypeShift,
154 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
155 // explicit argument, but have no destination. Example: fucom, fucomi, ...
156 CompareFP = 5 << FPTypeShift,
158 // CondMovFP - "2 operand" floating point conditional move instructions.
159 CondMovFP = 6 << FPTypeShift,
161 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
162 SpecialFP = 7 << FPTypeShift,
166 OpcodeMask = 0xFF << OpcodeShift,
167 // Bits 25 -> 31 are unused
171 class X86InstrInfo : public TargetInstrInfo {
172 const X86RegisterInfo RI;
176 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
177 /// such, whenever a client has an instance of instruction info, it should
178 /// always be able to get register info as well (through this method).
180 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
182 // Return true if the instruction is a register to register move and
183 // leave the source and dest operands in the passed parameters.
185 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
186 unsigned& destReg) const;
187 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
188 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
190 /// convertToThreeAddress - This method must be implemented by targets that
191 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
192 /// may be able to convert a two-address instruction into a true
193 /// three-address instruction on demand. This allows the X86 target (for
194 /// example) to convert ADD and SHL instructions into LEA instructions if they
195 /// would require register copies due to two-addressness.
197 /// This method returns a null pointer if the transformation cannot be
198 /// performed, otherwise it returns the new instruction.
200 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const;
202 /// commuteInstruction - We have a few instructions that must be hacked on to
205 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
208 /// Insert a goto (unconditional branch) sequence to TMBB, at the
210 virtual void insertGoto(MachineBasicBlock& MBB,
211 MachineBasicBlock& TMBB) const;
213 /// Reverses the branch condition of the MachineInstr pointed by
214 /// MI. The instruction is replaced and the new MI is returned.
215 virtual MachineBasicBlock::iterator
216 reverseBranchCondition(MachineBasicBlock::iterator MI) const;
218 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
219 // specified opcode number.
221 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
222 return get(Opcode).TSFlags >> X86II::OpcodeShift;
226 } // End llvm namespace