1 //===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
3 // This file contains the X86 implementation of the TargetInstrInfo class.
5 //===----------------------------------------------------------------------===//
7 #ifndef X86INSTRUCTIONINFO_H
8 #define X86INSTRUCTIONINFO_H
10 #include "llvm/Target/TargetInstrInfo.h"
11 #include "X86RegisterInfo.h"
13 /// X86II - This namespace holds all of the target specific flags that
14 /// instruction info tracks.
18 //===------------------------------------------------------------------===//
19 // Instruction types. These are the standard/most common forms for X86
23 // PseudoFrm - This represents an instruction that is a pseudo instruction
24 // or one that has not been implemented yet. It is illegal to code generate
25 // it, but tolerated for intermediate implementation stages.
28 /// Raw - This form is for instructions that don't have any operands, so
29 /// they are just a fixed opcode value, like 'leave'.
32 /// AddRegFrm - This form is used for instructions like 'push r32' that have
33 /// their one register operand added to their opcode.
36 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
37 /// to specify a destination, which in this case is a register.
41 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
42 /// to specify a destination, which in this case is memory.
46 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
47 /// to specify a source, which in this case is a register.
51 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
52 /// to specify a source, which in this case is memory.
56 /// MRMS[0-7][rm] - These forms are used to represent instructions that use
57 /// a Mod/RM byte, and use the middle field to hold extended opcode
58 /// information. In the intel manual these are represented as /0, /1, ...
61 // First, instructions that operate on a register r/m operand...
62 MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3
63 MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7
65 // Next, instructions that operate on a memory r/m operand...
66 MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3
67 MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7
71 //===------------------------------------------------------------------===//
74 /// Void - Set if this instruction produces no value
77 // OpSize - Set if this instruction requires an operand size prefix (0x66),
78 // which most often indicates that the instruction operates on 16 bit data
79 // instead of 32 bit data.
82 // Op0Mask - There are several prefix bytes that are used to form two byte
83 // opcodes. These are currently 0x0F, and 0xD8-0xDF. This mask is used to
84 // obtain the setting of this field. If no bits in this field is set, there
85 // is no prefix byte for obtaining a multibyte opcode.
90 // TB - TwoByte - Set if this instruction has a two byte opcode, which
91 // starts with a 0x0F byte before the real opcode.
94 // D8-DF - These escape opcodes are used by the floating point unit. These
95 // values must remain sequential.
96 D8 = 2 << 7, D9 = 3 << 7, DA = 4 << 7, DB = 5 << 7,
97 DC = 6 << 7, DD = 7 << 7, DE = 8 << 7, DF = 9 << 7,
99 //===------------------------------------------------------------------===//
100 // This three-bit field describes the size of a memory operand. Zero is
101 // unused so that we can tell if we forgot to set a value.
105 Arg64 = 4 << 11, // 64 bit int argument for FILD64
111 //===------------------------------------------------------------------===//
112 // FP Instruction Classification... Zero is non-fp instruction.
114 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
117 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
120 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
121 // result back to ST(0). For example, fcos, fsqrt, etc.
123 OneArgFPRW = 3 << 14,
125 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
126 // explicit argument, storing the result to either ST(0) or the implicit
127 // argument. For example: fadd, fsub, fmul, etc...
130 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
133 // FPTypeMask - Mask for all of the FP types...
134 FPTypeMask = 7 << 14,
136 // Bits 17 -> 31 are unused
140 class X86InstrInfo : public TargetInstrInfo {
141 const X86RegisterInfo RI;
145 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
146 /// such, whenever a client has an instance of instruction info, it should
147 /// always be able to get register info as well (through this method).
149 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
151 /// createNOPinstr - returns the target's implementation of NOP, which is
152 /// usually a pseudo-instruction, implemented by a degenerate version of
153 /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
155 MachineInstr* createNOPinstr() const;
157 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
158 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
159 /// more than one way to `do nothing' but only one canonical way to slack off.
161 bool isNOPinstr(const MachineInstr &MI) const;
163 /// print - Print out an x86 instruction in intel syntax
165 virtual void print(const MachineInstr *MI, std::ostream &O,
166 const TargetMachine &TM) const;
168 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
169 // specified opcode number.
171 unsigned char getBaseOpcodeFor(unsigned Opcode) const;