1 //===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
3 // This file contains the X86 implementation of the TargetInstrInfo class.
5 //===----------------------------------------------------------------------===//
7 #ifndef X86INSTRUCTIONINFO_H
8 #define X86INSTRUCTIONINFO_H
10 #include "llvm/Target/TargetInstrInfo.h"
11 #include "X86RegisterInfo.h"
13 /// X86II - This namespace holds all of the target specific flags that
14 /// instruction info tracks.
18 //===------------------------------------------------------------------===//
19 // Instruction types. These are the standard/most common forms for X86
23 // PseudoFrm - This represents an instruction that is a pseudo instruction
24 // or one that has not been implemented yet. It is illegal to code generate
25 // it, but tolerated for intermediate implementation stages.
28 /// Raw - This form is for instructions that don't have any operands, so
29 /// they are just a fixed opcode value, like 'leave'.
32 /// AddRegFrm - This form is used for instructions like 'push r32' that have
33 /// their one register operand added to their opcode.
36 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
37 /// to specify a destination, which in this case is a register.
41 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
42 /// to specify a destination, which in this case is memory.
46 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
47 /// to specify a source, which in this case is a register.
51 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
52 /// to specify a source, which in this case is memory.
56 /// MRMS[0-7][rm] - These forms are used to represent instructions that use
57 /// a Mod/RM byte, and use the middle field to hold extended opcode
58 /// information. In the intel manual these are represented as /0, /1, ...
61 // First, instructions that operate on a register r/m operand...
62 MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3
63 MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7
65 // Next, instructions that operate on a memory r/m operand...
66 MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3
67 MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7
71 //===------------------------------------------------------------------===//
74 // OpSize - Set if this instruction requires an operand size prefix (0x66),
75 // which most often indicates that the instruction operates on 16 bit data
76 // instead of 32 bit data.
79 // Op0Mask - There are several prefix bytes that are used to form two byte
80 // opcodes. These are currently 0x0F, and 0xD8-0xDF. This mask is used to
81 // obtain the setting of this field. If no bits in this field is set, there
82 // is no prefix byte for obtaining a multibyte opcode.
85 Op0Mask = 0xF << Op0Shift,
87 // TB - TwoByte - Set if this instruction has a two byte opcode, which
88 // starts with a 0x0F byte before the real opcode.
91 // D8-DF - These escape opcodes are used by the floating point unit. These
92 // values must remain sequential.
93 D8 = 2 << Op0Shift, D9 = 3 << Op0Shift,
94 DA = 4 << Op0Shift, DB = 5 << Op0Shift,
95 DC = 6 << Op0Shift, DD = 7 << Op0Shift,
96 DE = 8 << Op0Shift, DF = 9 << Op0Shift,
98 //===------------------------------------------------------------------===//
99 // This three-bit field describes the size of a memory operand. Zero is
100 // unused so that we can tell if we forgot to set a value.
102 ArgMask = 7 << ArgShift,
103 Arg8 = 1 << ArgShift,
104 Arg16 = 2 << ArgShift,
105 Arg32 = 3 << ArgShift,
106 Arg64 = 4 << ArgShift, // 64 bit int argument for FILD64
107 ArgF32 = 5 << ArgShift,
108 ArgF64 = 6 << ArgShift,
109 ArgF80 = 7 << ArgShift,
111 //===------------------------------------------------------------------===//
112 // FP Instruction Classification... Zero is non-fp instruction.
114 // FPTypeMask - Mask for all of the FP types...
116 FPTypeMask = 7 << FPTypeShift,
118 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
119 ZeroArgFP = 1 << FPTypeShift,
121 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
122 OneArgFP = 2 << FPTypeShift,
124 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
125 // result back to ST(0). For example, fcos, fsqrt, etc.
127 OneArgFPRW = 3 << FPTypeShift,
129 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
130 // explicit argument, storing the result to either ST(0) or the implicit
131 // argument. For example: fadd, fsub, fmul, etc...
132 TwoArgFP = 4 << FPTypeShift,
134 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
135 SpecialFP = 5 << FPTypeShift,
137 // PrintImplUses - Print out implicit uses in the assembly output.
138 PrintImplUses = 1 << 16,
141 OpcodeMask = 0xFF << OpcodeShift,
142 // Bits 25 -> 31 are unused
146 class X86InstrInfo : public TargetInstrInfo {
147 const X86RegisterInfo RI;
151 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
152 /// such, whenever a client has an instance of instruction info, it should
153 /// always be able to get register info as well (through this method).
155 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
157 /// createNOPinstr - returns the target's implementation of NOP, which is
158 /// usually a pseudo-instruction, implemented by a degenerate version of
159 /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
161 MachineInstr* createNOPinstr() const;
163 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
164 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
165 /// more than one way to `do nothing' but only one canonical way to slack off.
167 bool isNOPinstr(const MachineInstr &MI) const;
169 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
170 // specified opcode number.
172 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
173 return get(Opcode).TSFlags >> X86II::OpcodeShift;