1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
26 class X86RegisterInfo;
27 class X86TargetMachine;
30 // X86 specific condition code. These correspond to X86_*_COND in
31 // X86InstrInfo.td. They must be kept in synch.
50 // Artificial condition codes. These are used by AnalyzeBranch
51 // to indicate a block terminated with two conditional branches to
52 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
53 // which can't be represented on x86 with a single condition. These
54 // are never used in MachineInstrs.
61 // Turn condition code into conditional branch opcode.
62 unsigned GetCondBranchFromCond(CondCode CC);
64 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
65 /// e.g. turning COND_E to COND_NE.
66 CondCode GetOppositeBranchCondition(X86::CondCode CC);
67 } // end namespace X86;
70 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
71 /// a reference to a stub for a global, not the global itself.
72 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
74 case X86II::MO_DLLIMPORT: // dllimport stub.
75 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
76 case X86II::MO_GOT: // normal GOT reference.
77 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
78 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
79 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
86 /// isGlobalRelativeToPICBase - Return true if the specified global value
87 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
88 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
89 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
91 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
92 case X86II::MO_GOT: // isPICStyleGOT: other global.
93 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
94 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
95 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
96 case X86II::MO_TLVP: // ??? Pretty sure..
103 inline static bool isScale(const MachineOperand &MO) {
105 (MO.getImm() == 1 || MO.getImm() == 2 ||
106 MO.getImm() == 4 || MO.getImm() == 8);
109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
110 if (MI->getOperand(Op).isFI()) return true;
111 return Op+4 <= MI->getNumOperands() &&
112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
113 MI->getOperand(Op+2).isReg() &&
114 (MI->getOperand(Op+3).isImm() ||
115 MI->getOperand(Op+3).isGlobal() ||
116 MI->getOperand(Op+3).isCPI() ||
117 MI->getOperand(Op+3).isJTI());
120 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
121 if (MI->getOperand(Op).isFI()) return true;
122 return Op+5 <= MI->getNumOperands() &&
123 MI->getOperand(Op+4).isReg() &&
127 class X86InstrInfo : public X86GenInstrInfo {
128 X86TargetMachine &TM;
129 const X86RegisterInfo RI;
131 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable2Addr,
132 /// RegOp2MemOpTable0, RegOp2MemOpTable1,
133 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
135 typedef DenseMap<unsigned,
136 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
137 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
138 RegOp2MemOpTableType RegOp2MemOpTable0;
139 RegOp2MemOpTableType RegOp2MemOpTable1;
140 RegOp2MemOpTableType RegOp2MemOpTable2;
141 RegOp2MemOpTableType RegOp2MemOpTable3;
143 /// MemOp2RegOpTable - Load / store unfolding opcode map.
145 typedef DenseMap<unsigned,
146 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
147 MemOp2RegOpTableType MemOp2RegOpTable;
149 void AddTableEntry(RegOp2MemOpTableType &R2MTable,
150 MemOp2RegOpTableType &M2RTable,
151 unsigned RegOp, unsigned MemOp, unsigned Flags);
154 explicit X86InstrInfo(X86TargetMachine &tm);
156 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
157 /// such, whenever a client has an instance of instruction info, it should
158 /// always be able to get register info as well (through this method).
160 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
162 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
163 /// extension instruction. That is, it's like a copy where it's legal for the
164 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
165 /// true, then it's expected the pre-extension value is available as a subreg
166 /// of the result register. This also returns the sub-register index in
168 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
169 unsigned &SrcReg, unsigned &DstReg,
170 unsigned &SubIdx) const;
172 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
173 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
174 /// stack locations as well. This uses a heuristic so it isn't
175 /// reliable for correctness.
176 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
177 int &FrameIndex) const;
179 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
180 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
181 /// stack locations as well. This uses a heuristic so it isn't
182 /// reliable for correctness.
183 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
184 int &FrameIndex) const;
186 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
187 AliasAnalysis *AA) const;
188 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
189 unsigned DestReg, unsigned SubIdx,
190 const MachineInstr *Orig,
191 const TargetRegisterInfo &TRI) const;
193 /// convertToThreeAddress - This method must be implemented by targets that
194 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
195 /// may be able to convert a two-address instruction into a true
196 /// three-address instruction on demand. This allows the X86 target (for
197 /// example) to convert ADD and SHL instructions into LEA instructions if they
198 /// would require register copies due to two-addressness.
200 /// This method returns a null pointer if the transformation cannot be
201 /// performed, otherwise it returns the new instruction.
203 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
204 MachineBasicBlock::iterator &MBBI,
205 LiveVariables *LV) const;
207 /// commuteInstruction - We have a few instructions that must be hacked on to
210 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
213 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
214 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
215 MachineBasicBlock *&FBB,
216 SmallVectorImpl<MachineOperand> &Cond,
217 bool AllowModify) const;
218 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
219 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
220 MachineBasicBlock *FBB,
221 const SmallVectorImpl<MachineOperand> &Cond,
223 virtual void copyPhysReg(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator MI, DebugLoc DL,
225 unsigned DestReg, unsigned SrcReg,
227 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
228 MachineBasicBlock::iterator MI,
229 unsigned SrcReg, bool isKill, int FrameIndex,
230 const TargetRegisterClass *RC,
231 const TargetRegisterInfo *TRI) const;
233 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
234 SmallVectorImpl<MachineOperand> &Addr,
235 const TargetRegisterClass *RC,
236 MachineInstr::mmo_iterator MMOBegin,
237 MachineInstr::mmo_iterator MMOEnd,
238 SmallVectorImpl<MachineInstr*> &NewMIs) const;
240 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
241 MachineBasicBlock::iterator MI,
242 unsigned DestReg, int FrameIndex,
243 const TargetRegisterClass *RC,
244 const TargetRegisterInfo *TRI) const;
246 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
247 SmallVectorImpl<MachineOperand> &Addr,
248 const TargetRegisterClass *RC,
249 MachineInstr::mmo_iterator MMOBegin,
250 MachineInstr::mmo_iterator MMOEnd,
251 SmallVectorImpl<MachineInstr*> &NewMIs) const;
253 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
256 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
257 int FrameIx, uint64_t Offset,
261 /// foldMemoryOperand - If this target supports it, fold a load or store of
262 /// the specified stack slot into the specified machine instruction for the
263 /// specified operand(s). If this is possible, the target should perform the
264 /// folding and return true, otherwise it should return false. If it folds
265 /// the instruction, it is likely that the MachineInstruction the iterator
266 /// references has been changed.
267 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
269 const SmallVectorImpl<unsigned> &Ops,
270 int FrameIndex) const;
272 /// foldMemoryOperand - Same as the previous version except it allows folding
273 /// of any load and store from / to any address, not just from a specific
275 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
277 const SmallVectorImpl<unsigned> &Ops,
278 MachineInstr* LoadMI) const;
280 /// canFoldMemoryOperand - Returns true if the specified load / store is
281 /// folding is possible.
282 virtual bool canFoldMemoryOperand(const MachineInstr*,
283 const SmallVectorImpl<unsigned> &) const;
285 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
286 /// a store or a load and a store into two or more instruction. If this is
287 /// possible, returns true as well as the new instructions by reference.
288 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
289 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
290 SmallVectorImpl<MachineInstr*> &NewMIs) const;
292 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
293 SmallVectorImpl<SDNode*> &NewNodes) const;
295 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
296 /// instruction after load / store are unfolded from an instruction of the
297 /// specified opcode. It returns zero if the specified unfolding is not
298 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
299 /// index of the operand which will hold the register holding the loaded
301 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
302 bool UnfoldLoad, bool UnfoldStore,
303 unsigned *LoadRegIndex = 0) const;
305 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
306 /// to determine if two loads are loading from the same base address. It
307 /// should only return true if the base pointers are the same and the
308 /// only differences between the two addresses are the offset. It also returns
309 /// the offsets by reference.
310 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
311 int64_t &Offset1, int64_t &Offset2) const;
313 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
314 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
315 /// be scheduled togther. On some targets if two loads are loading from
316 /// addresses in the same cache line, it's better if they are scheduled
317 /// together. This function takes two integers that represent the load offsets
318 /// from the common base address. It returns true if it decides it's desirable
319 /// to schedule the two loads together. "NumLoads" is the number of loads that
320 /// have already been scheduled after Load1.
321 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
322 int64_t Offset1, int64_t Offset2,
323 unsigned NumLoads) const;
325 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
328 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
330 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
331 /// instruction that defines the specified register class.
332 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
334 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
335 if (!MO.isReg()) return false;
336 return X86II::isX86_64ExtendedReg(MO.getReg());
339 /// getGlobalBaseReg - Return a virtual register initialized with the
340 /// the global base register value. Output instructions required to
341 /// initialize the register in the function entry block, if necessary.
343 unsigned getGlobalBaseReg(MachineFunction *MF) const;
345 std::pair<uint16_t, uint16_t>
346 getExecutionDomain(const MachineInstr *MI) const;
348 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
350 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
351 const TargetRegisterInfo *TRI) const;
352 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
353 const TargetRegisterInfo *TRI) const;
355 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
358 const SmallVectorImpl<MachineOperand> &MOs,
359 unsigned Size, unsigned Alignment) const;
361 bool isHighLatencyDef(int opc) const;
363 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
364 const MachineRegisterInfo *MRI,
365 const MachineInstr *DefMI, unsigned DefIdx,
366 const MachineInstr *UseMI, unsigned UseIdx) const;
369 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
370 MachineFunction::iterator &MFI,
371 MachineBasicBlock::iterator &MBBI,
372 LiveVariables *LV) const;
374 /// isFrameOperand - Return true and the FrameIndex if the specified
375 /// operand and follow operands form a reference to the stack frame.
376 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
377 int &FrameIndex) const;
380 } // End llvm namespace