1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "X86RegisterInfo.h"
22 /// X86II - This namespace holds all of the target specific flags that
23 /// instruction info tracks.
27 //===------------------------------------------------------------------===//
28 // Instruction types. These are the standard/most common forms for X86
32 // PseudoFrm - This represents an instruction that is a pseudo instruction
33 // or one that has not been implemented yet. It is illegal to code generate
34 // it, but tolerated for intermediate implementation stages.
37 /// Raw - This form is for instructions that don't have any operands, so
38 /// they are just a fixed opcode value, like 'leave'.
41 /// AddRegFrm - This form is used for instructions like 'push r32' that have
42 /// their one register operand added to their opcode.
45 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
46 /// to specify a destination, which in this case is a register.
50 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
51 /// to specify a destination, which in this case is memory.
55 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
56 /// to specify a source, which in this case is a register.
60 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
61 /// to specify a source, which in this case is memory.
65 /// MRMS[0-7][rm] - These forms are used to represent instructions that use
66 /// a Mod/RM byte, and use the middle field to hold extended opcode
67 /// information. In the intel manual these are represented as /0, /1, ...
70 // First, instructions that operate on a register r/m operand...
71 MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3
72 MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7
74 // Next, instructions that operate on a memory r/m operand...
75 MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3
76 MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7
80 //===------------------------------------------------------------------===//
83 // OpSize - Set if this instruction requires an operand size prefix (0x66),
84 // which most often indicates that the instruction operates on 16 bit data
85 // instead of 32 bit data.
88 // Op0Mask - There are several prefix bytes that are used to form two byte
89 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
90 // used to obtain the setting of this field. If no bits in this field is
91 // set, there is no prefix byte for obtaining a multibyte opcode.
94 Op0Mask = 0xF << Op0Shift,
96 // TB - TwoByte - Set if this instruction has a two byte opcode, which
97 // starts with a 0x0F byte before the real opcode.
100 // REP - The 0xF3 prefix byte indicating repetition of the following
104 // D8-DF - These escape opcodes are used by the floating point unit. These
105 // values must remain sequential.
106 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
107 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
108 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
109 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
111 //===------------------------------------------------------------------===//
112 // This three-bit field describes the size of a memory operand. Zero is
113 // unused so that we can tell if we forgot to set a value.
115 ArgMask = 7 << ArgShift,
116 Arg8 = 1 << ArgShift,
117 Arg16 = 2 << ArgShift,
118 Arg32 = 3 << ArgShift,
119 Arg64 = 4 << ArgShift, // 64 bit int argument for FILD64
120 ArgF32 = 5 << ArgShift,
121 ArgF64 = 6 << ArgShift,
122 ArgF80 = 7 << ArgShift,
124 //===------------------------------------------------------------------===//
125 // FP Instruction Classification... Zero is non-fp instruction.
127 // FPTypeMask - Mask for all of the FP types...
129 FPTypeMask = 7 << FPTypeShift,
131 // NotFP - The default, set for instructions that do not use FP registers.
132 NotFP = 0 << FPTypeShift,
134 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
135 ZeroArgFP = 1 << FPTypeShift,
137 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
138 OneArgFP = 2 << FPTypeShift,
140 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
141 // result back to ST(0). For example, fcos, fsqrt, etc.
143 OneArgFPRW = 3 << FPTypeShift,
145 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
146 // explicit argument, storing the result to either ST(0) or the implicit
147 // argument. For example: fadd, fsub, fmul, etc...
148 TwoArgFP = 4 << FPTypeShift,
150 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
151 SpecialFP = 5 << FPTypeShift,
153 // PrintImplUses - Print out implicit uses in the assembly output.
154 PrintImplUses = 1 << 16,
157 OpcodeMask = 0xFF << OpcodeShift,
158 // Bits 25 -> 31 are unused
162 class X86InstrInfo : public TargetInstrInfo {
163 const X86RegisterInfo RI;
167 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
168 /// such, whenever a client has an instance of instruction info, it should
169 /// always be able to get register info as well (through this method).
171 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
173 /// createNOPinstr - returns the target's implementation of NOP, which is
174 /// usually a pseudo-instruction, implemented by a degenerate version of
175 /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
177 MachineInstr* createNOPinstr() const;
180 // Return true if the instruction is a register to register move and
181 // leave the source and dest operands in the passed parameters.
183 virtual bool isMoveInstr(const MachineInstr& MI,
185 unsigned& destReg) const;
187 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
188 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
189 /// more than one way to `do nothing' but only one canonical way to slack off.
191 bool isNOPinstr(const MachineInstr &MI) const;
193 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
194 // specified opcode number.
196 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
197 return get(Opcode).TSFlags >> X86II::OpcodeShift;
201 } // End llvm namespace