1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
23 class X86RegisterInfo;
24 class X86TargetMachine;
27 // X86 specific condition code. These correspond to X86_*_COND in
28 // X86InstrInfo.td. They must be kept in synch.
47 // Artificial condition codes. These are used by AnalyzeBranch
48 // to indicate a block terminated with two conditional branches to
49 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
50 // which can't be represented on x86 with a single condition. These
51 // are never used in MachineInstrs.
58 // Turn condition code into conditional branch opcode.
59 unsigned GetCondBranchFromCond(CondCode CC);
61 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
62 /// e.g. turning COND_E to COND_NE.
63 CondCode GetOppositeBranchCondition(X86::CondCode CC);
67 /// X86II - This namespace holds all of the target specific flags that
68 /// instruction info tracks.
71 /// Target Operand Flag enum.
73 //===------------------------------------------------------------------===//
74 // X86 Specific MachineOperand flags.
78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
80 /// SYMBOL_LABEL + [. - PICBASELABEL]
81 MO_GOT_ABSOLUTE_ADDRESS,
83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
84 /// immediate should get the value of the symbol minus the PIC base label:
85 /// SYMBOL_LABEL - PICBASELABEL
88 /// MO_GOT - On a symbol operand this indicates that the immediate is the
89 /// offset to the GOT entry for the symbol name from the base of the GOT.
91 /// See the X86-64 ELF ABI supplement for more details.
95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
96 /// the offset to the location of the symbol name from the base of the GOT.
98 /// See the X86-64 ELF ABI supplement for more details.
99 /// SYMBOL_LABEL @GOTOFF
102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
103 /// offset to the GOT entry for the symbol name from the current code
106 /// See the X86-64 ELF ABI supplement for more details.
107 /// SYMBOL_LABEL @GOTPCREL
110 /// MO_PLT - On a symbol operand this indicates that the immediate is
111 /// offset to the PLT entry of symbol name from the current code location.
113 /// See the X86-64 ELF ABI supplement for more details.
114 /// SYMBOL_LABEL @PLT
117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
120 /// See 'ELF Handling for Thread-Local Storage' for more details.
121 /// SYMBOL_LABEL @TLSGD
124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
127 /// See 'ELF Handling for Thread-Local Storage' for more details.
128 /// SYMBOL_LABEL @GOTTPOFF
131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
134 /// See 'ELF Handling for Thread-Local Storage' for more details.
135 /// SYMBOL_LABEL @INDNTPOFF
138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
141 /// See 'ELF Handling for Thread-Local Storage' for more details.
142 /// SYMBOL_LABEL @TPOFF
145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
148 /// See 'ELF Handling for Thread-Local Storage' for more details.
149 /// SYMBOL_LABEL @NTPOFF
152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
153 /// reference is actually to the "__imp_FOO" symbol. This is used for
154 /// dllimport linkage on windows.
157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
158 /// reference is actually to the "FOO$stub" symbol. This is used for calls
159 /// and jumps to external functions on Tiger and before.
162 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
163 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
164 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
167 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
168 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
169 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
170 MO_DARWIN_NONLAZY_PIC_BASE,
172 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
173 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
174 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
176 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
178 /// MO_TLVP - On a symbol operand this indicates that the immediate is
181 /// This is the TLS offset for the Darwin TLS mechanism.
184 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
185 /// is some TLS offset from the picbase.
187 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
192 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
193 /// a reference to a stub for a global, not the global itself.
194 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
195 switch (TargetFlag) {
196 case X86II::MO_DLLIMPORT: // dllimport stub.
197 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
198 case X86II::MO_GOT: // normal GOT reference.
199 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
200 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
201 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
208 /// isGlobalRelativeToPICBase - Return true if the specified global value
209 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
210 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
211 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
212 switch (TargetFlag) {
213 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
214 case X86II::MO_GOT: // isPICStyleGOT: other global.
215 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
216 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
217 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
218 case X86II::MO_TLVP: // ??? Pretty sure..
225 /// X86II - This namespace holds all of the target specific flags that
226 /// instruction info tracks.
230 //===------------------------------------------------------------------===//
231 // Instruction encodings. These are the standard/most common forms for X86
235 // PseudoFrm - This represents an instruction that is a pseudo instruction
236 // or one that has not been implemented yet. It is illegal to code generate
237 // it, but tolerated for intermediate implementation stages.
240 /// Raw - This form is for instructions that don't have any operands, so
241 /// they are just a fixed opcode value, like 'leave'.
244 /// AddRegFrm - This form is used for instructions like 'push r32' that have
245 /// their one register operand added to their opcode.
248 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
249 /// to specify a destination, which in this case is a register.
253 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
254 /// to specify a destination, which in this case is memory.
258 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
259 /// to specify a source, which in this case is a register.
263 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
264 /// to specify a source, which in this case is memory.
268 /// MRM[0-7][rm] - These forms are used to represent instructions that use
269 /// a Mod/RM byte, and use the middle field to hold extended opcode
270 /// information. In the intel manual these are represented as /0, /1, ...
273 // First, instructions that operate on a register r/m operand...
274 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
275 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
277 // Next, instructions that operate on a memory r/m operand...
278 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
279 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
281 // MRMInitReg - This form is used for instructions whose source and
282 // destinations are the same register.
285 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
299 //===------------------------------------------------------------------===//
302 // OpSize - Set if this instruction requires an operand size prefix (0x66),
303 // which most often indicates that the instruction operates on 16 bit data
304 // instead of 32 bit data.
307 // AsSize - Set if this instruction requires an operand size prefix (0x67),
308 // which most often indicates that the instruction address 16 bit address
309 // instead of 32 bit address (or 32 bit address in 64 bit mode).
312 //===------------------------------------------------------------------===//
313 // Op0Mask - There are several prefix bytes that are used to form two byte
314 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
315 // used to obtain the setting of this field. If no bits in this field is
316 // set, there is no prefix byte for obtaining a multibyte opcode.
319 Op0Mask = 0xF << Op0Shift,
321 // TB - TwoByte - Set if this instruction has a two byte opcode, which
322 // starts with a 0x0F byte before the real opcode.
325 // REP - The 0xF3 prefix byte indicating repetition of the following
329 // D8-DF - These escape opcodes are used by the floating point unit. These
330 // values must remain sequential.
331 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
332 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
333 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
334 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
336 // XS, XD - These prefix codes are for single and double precision scalar
337 // floating point operations performed in the SSE registers.
338 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
340 // T8, TA - Prefix after the 0x0F prefix.
341 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
343 // TF - Prefix before and after 0x0F
346 //===------------------------------------------------------------------===//
347 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
348 // They are used to specify GPRs and SSE registers, 64-bit operand size,
349 // etc. We only cares about REX.W and REX.R bits and only the former is
350 // statically determined.
353 REX_W = 1 << REXShift,
355 //===------------------------------------------------------------------===//
356 // This three-bit field describes the size of an immediate operand. Zero is
357 // unused so that we can tell if we forgot to set a value.
359 ImmMask = 7 << ImmShift,
360 Imm8 = 1 << ImmShift,
361 Imm8PCRel = 2 << ImmShift,
362 Imm16 = 3 << ImmShift,
363 Imm32 = 4 << ImmShift,
364 Imm32PCRel = 5 << ImmShift,
365 Imm64 = 6 << ImmShift,
367 //===------------------------------------------------------------------===//
368 // FP Instruction Classification... Zero is non-fp instruction.
370 // FPTypeMask - Mask for all of the FP types...
372 FPTypeMask = 7 << FPTypeShift,
374 // NotFP - The default, set for instructions that do not use FP registers.
375 NotFP = 0 << FPTypeShift,
377 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
378 ZeroArgFP = 1 << FPTypeShift,
380 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
381 OneArgFP = 2 << FPTypeShift,
383 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
384 // result back to ST(0). For example, fcos, fsqrt, etc.
386 OneArgFPRW = 3 << FPTypeShift,
388 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
389 // explicit argument, storing the result to either ST(0) or the implicit
390 // argument. For example: fadd, fsub, fmul, etc...
391 TwoArgFP = 4 << FPTypeShift,
393 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
394 // explicit argument, but have no destination. Example: fucom, fucomi, ...
395 CompareFP = 5 << FPTypeShift,
397 // CondMovFP - "2 operand" floating point conditional move instructions.
398 CondMovFP = 6 << FPTypeShift,
400 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
401 SpecialFP = 7 << FPTypeShift,
405 LOCK = 1 << LOCKShift,
407 // Segment override prefixes. Currently we just need ability to address
408 // stuff in gs and fs segments.
410 SegOvrMask = 3 << SegOvrShift,
411 FS = 1 << SegOvrShift,
412 GS = 2 << SegOvrShift,
414 // Execution domain for SSE instructions in bits 22, 23.
415 // 0 in bits 22-23 means normal, non-SSE instruction.
419 OpcodeMask = 0xFF << OpcodeShift
423 // FIXME: The enum opcode space is over and more bits are needed. Anywhere
424 // those enums below are used, TSFlags must be shifted right by 32 first.
426 //===------------------------------------------------------------------===//
427 // VEXPrefix - VEX prefixes are instruction prefixes used in AVX.
428 // VEX_4V is used to specify an additional AVX/SSE register. Several 2
429 // address instructions in SSE are represented as 3 address ones in AVX
430 // and the additional register is encoded in VEX_VVVV prefix.
434 VEX_4V = 2 << VEXShift
437 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
438 // specified machine instruction.
440 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
441 return TSFlags >> X86II::OpcodeShift;
444 static inline bool hasImm(uint64_t TSFlags) {
445 return (TSFlags & X86II::ImmMask) != 0;
448 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
449 /// of the specified instruction.
450 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
451 switch (TSFlags & X86II::ImmMask) {
452 default: assert(0 && "Unknown immediate size");
454 case X86II::Imm8PCRel: return 1;
455 case X86II::Imm16: return 2;
457 case X86II::Imm32PCRel: return 4;
458 case X86II::Imm64: return 8;
462 /// isImmPCRel - Return true if the immediate of the specified instruction's
463 /// TSFlags indicates that it is pc relative.
464 static inline unsigned isImmPCRel(uint64_t TSFlags) {
465 switch (TSFlags & X86II::ImmMask) {
466 default: assert(0 && "Unknown immediate size");
467 case X86II::Imm8PCRel:
468 case X86II::Imm32PCRel:
479 const int X86AddrNumOperands = 5;
481 inline static bool isScale(const MachineOperand &MO) {
483 (MO.getImm() == 1 || MO.getImm() == 2 ||
484 MO.getImm() == 4 || MO.getImm() == 8);
487 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
488 if (MI->getOperand(Op).isFI()) return true;
489 return Op+4 <= MI->getNumOperands() &&
490 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
491 MI->getOperand(Op+2).isReg() &&
492 (MI->getOperand(Op+3).isImm() ||
493 MI->getOperand(Op+3).isGlobal() ||
494 MI->getOperand(Op+3).isCPI() ||
495 MI->getOperand(Op+3).isJTI());
498 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
499 if (MI->getOperand(Op).isFI()) return true;
500 return Op+5 <= MI->getNumOperands() &&
501 MI->getOperand(Op+4).isReg() &&
505 class X86InstrInfo : public TargetInstrInfoImpl {
506 X86TargetMachine &TM;
507 const X86RegisterInfo RI;
509 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
510 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
512 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
513 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
514 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
515 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
517 /// MemOp2RegOpTable - Load / store unfolding opcode map.
519 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
522 explicit X86InstrInfo(X86TargetMachine &tm);
524 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
525 /// such, whenever a client has an instance of instruction info, it should
526 /// always be able to get register info as well (through this method).
528 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
530 /// Return true if the instruction is a register to register move and return
531 /// the source and dest operands and their sub-register indices by reference.
532 virtual bool isMoveInstr(const MachineInstr &MI,
533 unsigned &SrcReg, unsigned &DstReg,
534 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
536 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
537 /// extension instruction. That is, it's like a copy where it's legal for the
538 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
539 /// true, then it's expected the pre-extension value is available as a subreg
540 /// of the result register. This also returns the sub-register index in
542 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
543 unsigned &SrcReg, unsigned &DstReg,
544 unsigned &SubIdx) const;
546 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
547 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
548 /// stack locations as well. This uses a heuristic so it isn't
549 /// reliable for correctness.
550 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
551 int &FrameIndex) const;
553 /// hasLoadFromStackSlot - If the specified machine instruction has
554 /// a load from a stack slot, return true along with the FrameIndex
555 /// of the loaded stack slot and the machine mem operand containing
556 /// the reference. If not, return false. Unlike
557 /// isLoadFromStackSlot, this returns true for any instructions that
558 /// loads from the stack. This is a hint only and may not catch all
560 bool hasLoadFromStackSlot(const MachineInstr *MI,
561 const MachineMemOperand *&MMO,
562 int &FrameIndex) const;
564 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
565 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
566 /// stack locations as well. This uses a heuristic so it isn't
567 /// reliable for correctness.
568 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
569 int &FrameIndex) const;
571 /// hasStoreToStackSlot - If the specified machine instruction has a
572 /// store to a stack slot, return true along with the FrameIndex of
573 /// the loaded stack slot and the machine mem operand containing the
574 /// reference. If not, return false. Unlike isStoreToStackSlot,
575 /// this returns true for any instructions that loads from the
576 /// stack. This is a hint only and may not catch all cases.
577 bool hasStoreToStackSlot(const MachineInstr *MI,
578 const MachineMemOperand *&MMO,
579 int &FrameIndex) const;
581 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
582 AliasAnalysis *AA) const;
583 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
584 unsigned DestReg, unsigned SubIdx,
585 const MachineInstr *Orig,
586 const TargetRegisterInfo &TRI) const;
588 /// convertToThreeAddress - This method must be implemented by targets that
589 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
590 /// may be able to convert a two-address instruction into a true
591 /// three-address instruction on demand. This allows the X86 target (for
592 /// example) to convert ADD and SHL instructions into LEA instructions if they
593 /// would require register copies due to two-addressness.
595 /// This method returns a null pointer if the transformation cannot be
596 /// performed, otherwise it returns the new instruction.
598 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
599 MachineBasicBlock::iterator &MBBI,
600 LiveVariables *LV) const;
602 /// commuteInstruction - We have a few instructions that must be hacked on to
605 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
608 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
609 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
610 MachineBasicBlock *&FBB,
611 SmallVectorImpl<MachineOperand> &Cond,
612 bool AllowModify) const;
613 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
614 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
615 MachineBasicBlock *FBB,
616 const SmallVectorImpl<MachineOperand> &Cond,
618 virtual bool copyRegToReg(MachineBasicBlock &MBB,
619 MachineBasicBlock::iterator MI,
620 unsigned DestReg, unsigned SrcReg,
621 const TargetRegisterClass *DestRC,
622 const TargetRegisterClass *SrcRC,
624 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
625 MachineBasicBlock::iterator MI,
626 unsigned SrcReg, bool isKill, int FrameIndex,
627 const TargetRegisterClass *RC,
628 const TargetRegisterInfo *TRI) const;
630 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
631 SmallVectorImpl<MachineOperand> &Addr,
632 const TargetRegisterClass *RC,
633 MachineInstr::mmo_iterator MMOBegin,
634 MachineInstr::mmo_iterator MMOEnd,
635 SmallVectorImpl<MachineInstr*> &NewMIs) const;
637 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
638 MachineBasicBlock::iterator MI,
639 unsigned DestReg, int FrameIndex,
640 const TargetRegisterClass *RC,
641 const TargetRegisterInfo *TRI) const;
643 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
644 SmallVectorImpl<MachineOperand> &Addr,
645 const TargetRegisterClass *RC,
646 MachineInstr::mmo_iterator MMOBegin,
647 MachineInstr::mmo_iterator MMOEnd,
648 SmallVectorImpl<MachineInstr*> &NewMIs) const;
650 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator MI,
652 const std::vector<CalleeSavedInfo> &CSI,
653 const TargetRegisterInfo *TRI) const;
655 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
656 MachineBasicBlock::iterator MI,
657 const std::vector<CalleeSavedInfo> &CSI,
658 const TargetRegisterInfo *TRI) const;
661 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
662 int FrameIx, uint64_t Offset,
666 /// foldMemoryOperand - If this target supports it, fold a load or store of
667 /// the specified stack slot into the specified machine instruction for the
668 /// specified operand(s). If this is possible, the target should perform the
669 /// folding and return true, otherwise it should return false. If it folds
670 /// the instruction, it is likely that the MachineInstruction the iterator
671 /// references has been changed.
672 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
674 const SmallVectorImpl<unsigned> &Ops,
675 int FrameIndex) const;
677 /// foldMemoryOperand - Same as the previous version except it allows folding
678 /// of any load and store from / to any address, not just from a specific
680 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
682 const SmallVectorImpl<unsigned> &Ops,
683 MachineInstr* LoadMI) const;
685 /// canFoldMemoryOperand - Returns true if the specified load / store is
686 /// folding is possible.
687 virtual bool canFoldMemoryOperand(const MachineInstr*,
688 const SmallVectorImpl<unsigned> &) const;
690 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
691 /// a store or a load and a store into two or more instruction. If this is
692 /// possible, returns true as well as the new instructions by reference.
693 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
694 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
695 SmallVectorImpl<MachineInstr*> &NewMIs) const;
697 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
698 SmallVectorImpl<SDNode*> &NewNodes) const;
700 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
701 /// instruction after load / store are unfolded from an instruction of the
702 /// specified opcode. It returns zero if the specified unfolding is not
703 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
704 /// index of the operand which will hold the register holding the loaded
706 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
707 bool UnfoldLoad, bool UnfoldStore,
708 unsigned *LoadRegIndex = 0) const;
710 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
711 /// to determine if two loads are loading from the same base address. It
712 /// should only return true if the base pointers are the same and the
713 /// only differences between the two addresses are the offset. It also returns
714 /// the offsets by reference.
715 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
716 int64_t &Offset1, int64_t &Offset2) const;
718 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
719 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
720 /// be scheduled togther. On some targets if two loads are loading from
721 /// addresses in the same cache line, it's better if they are scheduled
722 /// together. This function takes two integers that represent the load offsets
723 /// from the common base address. It returns true if it decides it's desirable
724 /// to schedule the two loads together. "NumLoads" is the number of loads that
725 /// have already been scheduled after Load1.
726 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
727 int64_t Offset1, int64_t Offset2,
728 unsigned NumLoads) const;
730 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
733 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
735 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
736 /// instruction that defines the specified register class.
737 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
739 static bool isX86_64NonExtLowByteReg(unsigned reg) {
740 return (reg == X86::SPL || reg == X86::BPL ||
741 reg == X86::SIL || reg == X86::DIL);
744 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
745 if (!MO.isReg()) return false;
746 return isX86_64ExtendedReg(MO.getReg());
748 static unsigned determineREX(const MachineInstr &MI);
750 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
751 /// higher) register? e.g. r8, xmm8, xmm13, etc.
752 static bool isX86_64ExtendedReg(unsigned RegNo);
754 /// GetInstSize - Returns the size of the specified MachineInstr.
756 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
758 /// getGlobalBaseReg - Return a virtual register initialized with the
759 /// the global base register value. Output instructions required to
760 /// initialize the register in the function entry block, if necessary.
762 unsigned getGlobalBaseReg(MachineFunction *MF) const;
764 /// GetSSEDomain - Return the SSE execution domain of MI as the first element,
765 /// and a bitmask of possible arguments to SetSSEDomain ase the second.
766 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;
768 /// SetSSEDomain - Set the SSEDomain of MI.
769 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const;
772 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
773 MachineFunction::iterator &MFI,
774 MachineBasicBlock::iterator &MBBI,
775 LiveVariables *LV) const;
777 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
780 const SmallVectorImpl<MachineOperand> &MOs,
781 unsigned Size, unsigned Alignment) const;
783 /// isFrameOperand - Return true and the FrameIndex if the specified
784 /// operand and follow operands form a reference to the stack frame.
785 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
786 int &FrameIndex) const;
789 } // End llvm namespace