1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
26 class X86RegisterInfo;
27 class X86TargetMachine;
30 // X86 specific condition code. These correspond to X86_*_COND in
31 // X86InstrInfo.td. They must be kept in synch.
50 // Artificial condition codes. These are used by AnalyzeBranch
51 // to indicate a block terminated with two conditional branches to
52 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
53 // which can't be represented on x86 with a single condition. These
54 // are never used in MachineInstrs.
61 // Turn condition code into conditional branch opcode.
62 unsigned GetCondBranchFromCond(CondCode CC);
64 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
65 /// e.g. turning COND_E to COND_NE.
66 CondCode GetOppositeBranchCondition(X86::CondCode CC);
67 } // end namespace X86;
70 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
71 /// a reference to a stub for a global, not the global itself.
72 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
74 case X86II::MO_DLLIMPORT: // dllimport stub.
75 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
76 case X86II::MO_GOT: // normal GOT reference.
77 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
78 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
79 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
86 /// isGlobalRelativeToPICBase - Return true if the specified global value
87 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
88 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
89 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
91 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
92 case X86II::MO_GOT: // isPICStyleGOT: other global.
93 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
94 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
95 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
96 case X86II::MO_TLVP: // ??? Pretty sure..
103 inline static bool isScale(const MachineOperand &MO) {
105 (MO.getImm() == 1 || MO.getImm() == 2 ||
106 MO.getImm() == 4 || MO.getImm() == 8);
109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
110 if (MI->getOperand(Op).isFI()) return true;
111 return Op+4 <= MI->getNumOperands() &&
112 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
113 MI->getOperand(Op+2).isReg() &&
114 (MI->getOperand(Op+3).isImm() ||
115 MI->getOperand(Op+3).isGlobal() ||
116 MI->getOperand(Op+3).isCPI() ||
117 MI->getOperand(Op+3).isJTI());
120 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
121 if (MI->getOperand(Op).isFI()) return true;
122 return Op+5 <= MI->getNumOperands() &&
123 MI->getOperand(Op+4).isReg() &&
127 class X86InstrInfo : public X86GenInstrInfo {
128 X86TargetMachine &TM;
129 const X86RegisterInfo RI;
131 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
132 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
134 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
135 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
136 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
137 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
139 /// MemOp2RegOpTable - Load / store unfolding opcode map.
141 DenseMap<unsigned, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
144 explicit X86InstrInfo(X86TargetMachine &tm);
146 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
147 /// such, whenever a client has an instance of instruction info, it should
148 /// always be able to get register info as well (through this method).
150 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
152 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
153 /// extension instruction. That is, it's like a copy where it's legal for the
154 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
155 /// true, then it's expected the pre-extension value is available as a subreg
156 /// of the result register. This also returns the sub-register index in
158 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
159 unsigned &SrcReg, unsigned &DstReg,
160 unsigned &SubIdx) const;
162 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
163 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
164 /// stack locations as well. This uses a heuristic so it isn't
165 /// reliable for correctness.
166 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
167 int &FrameIndex) const;
169 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
170 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
171 /// stack locations as well. This uses a heuristic so it isn't
172 /// reliable for correctness.
173 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
174 int &FrameIndex) const;
176 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
177 AliasAnalysis *AA) const;
178 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
179 unsigned DestReg, unsigned SubIdx,
180 const MachineInstr *Orig,
181 const TargetRegisterInfo &TRI) const;
183 /// convertToThreeAddress - This method must be implemented by targets that
184 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
185 /// may be able to convert a two-address instruction into a true
186 /// three-address instruction on demand. This allows the X86 target (for
187 /// example) to convert ADD and SHL instructions into LEA instructions if they
188 /// would require register copies due to two-addressness.
190 /// This method returns a null pointer if the transformation cannot be
191 /// performed, otherwise it returns the new instruction.
193 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
194 MachineBasicBlock::iterator &MBBI,
195 LiveVariables *LV) const;
197 /// commuteInstruction - We have a few instructions that must be hacked on to
200 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
203 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
204 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
205 MachineBasicBlock *&FBB,
206 SmallVectorImpl<MachineOperand> &Cond,
207 bool AllowModify) const;
208 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
209 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
210 MachineBasicBlock *FBB,
211 const SmallVectorImpl<MachineOperand> &Cond,
213 virtual void copyPhysReg(MachineBasicBlock &MBB,
214 MachineBasicBlock::iterator MI, DebugLoc DL,
215 unsigned DestReg, unsigned SrcReg,
217 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
218 MachineBasicBlock::iterator MI,
219 unsigned SrcReg, bool isKill, int FrameIndex,
220 const TargetRegisterClass *RC,
221 const TargetRegisterInfo *TRI) const;
223 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
224 SmallVectorImpl<MachineOperand> &Addr,
225 const TargetRegisterClass *RC,
226 MachineInstr::mmo_iterator MMOBegin,
227 MachineInstr::mmo_iterator MMOEnd,
228 SmallVectorImpl<MachineInstr*> &NewMIs) const;
230 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
231 MachineBasicBlock::iterator MI,
232 unsigned DestReg, int FrameIndex,
233 const TargetRegisterClass *RC,
234 const TargetRegisterInfo *TRI) const;
236 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
237 SmallVectorImpl<MachineOperand> &Addr,
238 const TargetRegisterClass *RC,
239 MachineInstr::mmo_iterator MMOBegin,
240 MachineInstr::mmo_iterator MMOEnd,
241 SmallVectorImpl<MachineInstr*> &NewMIs) const;
243 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
244 int FrameIx, uint64_t Offset,
248 /// foldMemoryOperand - If this target supports it, fold a load or store of
249 /// the specified stack slot into the specified machine instruction for the
250 /// specified operand(s). If this is possible, the target should perform the
251 /// folding and return true, otherwise it should return false. If it folds
252 /// the instruction, it is likely that the MachineInstruction the iterator
253 /// references has been changed.
254 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
256 const SmallVectorImpl<unsigned> &Ops,
257 int FrameIndex) const;
259 /// foldMemoryOperand - Same as the previous version except it allows folding
260 /// of any load and store from / to any address, not just from a specific
262 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
264 const SmallVectorImpl<unsigned> &Ops,
265 MachineInstr* LoadMI) const;
267 /// canFoldMemoryOperand - Returns true if the specified load / store is
268 /// folding is possible.
269 virtual bool canFoldMemoryOperand(const MachineInstr*,
270 const SmallVectorImpl<unsigned> &) const;
272 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
273 /// a store or a load and a store into two or more instruction. If this is
274 /// possible, returns true as well as the new instructions by reference.
275 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
276 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
277 SmallVectorImpl<MachineInstr*> &NewMIs) const;
279 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
280 SmallVectorImpl<SDNode*> &NewNodes) const;
282 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
283 /// instruction after load / store are unfolded from an instruction of the
284 /// specified opcode. It returns zero if the specified unfolding is not
285 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
286 /// index of the operand which will hold the register holding the loaded
288 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
289 bool UnfoldLoad, bool UnfoldStore,
290 unsigned *LoadRegIndex = 0) const;
292 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
293 /// to determine if two loads are loading from the same base address. It
294 /// should only return true if the base pointers are the same and the
295 /// only differences between the two addresses are the offset. It also returns
296 /// the offsets by reference.
297 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
298 int64_t &Offset1, int64_t &Offset2) const;
300 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
301 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
302 /// be scheduled togther. On some targets if two loads are loading from
303 /// addresses in the same cache line, it's better if they are scheduled
304 /// together. This function takes two integers that represent the load offsets
305 /// from the common base address. It returns true if it decides it's desirable
306 /// to schedule the two loads together. "NumLoads" is the number of loads that
307 /// have already been scheduled after Load1.
308 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
309 int64_t Offset1, int64_t Offset2,
310 unsigned NumLoads) const;
312 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
315 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
317 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
318 /// instruction that defines the specified register class.
319 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
321 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
322 if (!MO.isReg()) return false;
323 return X86II::isX86_64ExtendedReg(MO.getReg());
326 /// getGlobalBaseReg - Return a virtual register initialized with the
327 /// the global base register value. Output instructions required to
328 /// initialize the register in the function entry block, if necessary.
330 unsigned getGlobalBaseReg(MachineFunction *MF) const;
332 /// GetSSEDomain - Return the SSE execution domain of MI as the first element,
333 /// and a bitmask of possible arguments to SetSSEDomain ase the second.
334 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;
336 /// SetSSEDomain - Set the SSEDomain of MI.
337 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const;
339 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
342 const SmallVectorImpl<MachineOperand> &MOs,
343 unsigned Size, unsigned Alignment) const;
345 bool isHighLatencyDef(int opc) const;
347 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
348 const MachineRegisterInfo *MRI,
349 const MachineInstr *DefMI, unsigned DefIdx,
350 const MachineInstr *UseMI, unsigned UseIdx) const;
353 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
354 MachineFunction::iterator &MFI,
355 MachineBasicBlock::iterator &MBBI,
356 LiveVariables *LV) const;
358 /// isFrameOperand - Return true and the FrameIndex if the specified
359 /// operand and follow operands form a reference to the stack frame.
360 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
361 int &FrameIndex) const;
364 } // End llvm namespace