1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
26 class X86RegisterInfo;
27 class X86TargetMachine;
30 // X86 specific condition code. These correspond to X86_*_COND in
31 // X86InstrInfo.td. They must be kept in synch.
50 // Artificial condition codes. These are used by AnalyzeBranch
51 // to indicate a block terminated with two conditional branches to
52 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
53 // which can't be represented on x86 with a single condition. These
54 // are never used in MachineInstrs.
61 // Turn condition code into conditional branch opcode.
62 unsigned GetCondBranchFromCond(CondCode CC);
64 // Turn CMov opcode into condition code.
65 CondCode getCondFromCMovOpc(unsigned Opc);
67 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
68 /// e.g. turning COND_E to COND_NE.
69 CondCode GetOppositeBranchCondition(X86::CondCode CC);
70 } // end namespace X86;
73 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
74 /// a reference to a stub for a global, not the global itself.
75 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
77 case X86II::MO_DLLIMPORT: // dllimport stub.
78 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
79 case X86II::MO_GOT: // normal GOT reference.
80 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
81 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
82 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
89 /// isGlobalRelativeToPICBase - Return true if the specified global value
90 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
91 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
92 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
94 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
95 case X86II::MO_GOT: // isPICStyleGOT: other global.
96 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
97 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
98 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
99 case X86II::MO_TLVP: // ??? Pretty sure..
106 inline static bool isScale(const MachineOperand &MO) {
108 (MO.getImm() == 1 || MO.getImm() == 2 ||
109 MO.getImm() == 4 || MO.getImm() == 8);
112 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
113 if (MI->getOperand(Op).isFI()) return true;
114 return Op+4 <= MI->getNumOperands() &&
115 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
116 MI->getOperand(Op+2).isReg() &&
117 (MI->getOperand(Op+3).isImm() ||
118 MI->getOperand(Op+3).isGlobal() ||
119 MI->getOperand(Op+3).isCPI() ||
120 MI->getOperand(Op+3).isJTI());
123 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
124 if (MI->getOperand(Op).isFI()) return true;
125 return Op+5 <= MI->getNumOperands() &&
126 MI->getOperand(Op+4).isReg() &&
130 class X86InstrInfo : public X86GenInstrInfo {
131 X86TargetMachine &TM;
132 const X86RegisterInfo RI;
134 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
135 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
137 typedef DenseMap<unsigned,
138 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
139 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
140 RegOp2MemOpTableType RegOp2MemOpTable0;
141 RegOp2MemOpTableType RegOp2MemOpTable1;
142 RegOp2MemOpTableType RegOp2MemOpTable2;
143 RegOp2MemOpTableType RegOp2MemOpTable3;
145 /// MemOp2RegOpTable - Load / store unfolding opcode map.
147 typedef DenseMap<unsigned,
148 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
149 MemOp2RegOpTableType MemOp2RegOpTable;
151 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
152 MemOp2RegOpTableType &M2RTable,
153 unsigned RegOp, unsigned MemOp, unsigned Flags);
155 virtual void anchor();
158 explicit X86InstrInfo(X86TargetMachine &tm);
160 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
161 /// such, whenever a client has an instance of instruction info, it should
162 /// always be able to get register info as well (through this method).
164 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
166 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
167 /// extension instruction. That is, it's like a copy where it's legal for the
168 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
169 /// true, then it's expected the pre-extension value is available as a subreg
170 /// of the result register. This also returns the sub-register index in
172 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
173 unsigned &SrcReg, unsigned &DstReg,
174 unsigned &SubIdx) const;
176 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
177 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
178 /// stack locations as well. This uses a heuristic so it isn't
179 /// reliable for correctness.
180 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
181 int &FrameIndex) const;
183 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
184 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
185 /// stack locations as well. This uses a heuristic so it isn't
186 /// reliable for correctness.
187 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
188 int &FrameIndex) const;
190 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
191 AliasAnalysis *AA) const;
192 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
193 unsigned DestReg, unsigned SubIdx,
194 const MachineInstr *Orig,
195 const TargetRegisterInfo &TRI) const;
197 /// Given an operand within a MachineInstr, insert preceding code to put it
198 /// into the right format for a particular kind of LEA instruction. This may
199 /// involve using an appropriate super-register instead (with an implicit use
200 /// of the original) or creating a new virtual register and inserting COPY
201 /// instructions to get the data into the right class.
203 /// Reference parameters are set to indicate how caller should add this
204 /// operand to the LEA instruction.
205 bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
206 unsigned LEAOpcode, bool AllowSP,
207 unsigned &NewSrc, bool &isKill,
208 bool &isUndef, MachineOperand &ImplicitOp) const;
210 /// convertToThreeAddress - This method must be implemented by targets that
211 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
212 /// may be able to convert a two-address instruction into a true
213 /// three-address instruction on demand. This allows the X86 target (for
214 /// example) to convert ADD and SHL instructions into LEA instructions if they
215 /// would require register copies due to two-addressness.
217 /// This method returns a null pointer if the transformation cannot be
218 /// performed, otherwise it returns the new instruction.
220 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
221 MachineBasicBlock::iterator &MBBI,
222 LiveVariables *LV) const;
224 /// commuteInstruction - We have a few instructions that must be hacked on to
227 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
230 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
231 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
232 MachineBasicBlock *&FBB,
233 SmallVectorImpl<MachineOperand> &Cond,
234 bool AllowModify) const;
235 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
236 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
237 MachineBasicBlock *FBB,
238 const SmallVectorImpl<MachineOperand> &Cond,
240 virtual bool canInsertSelect(const MachineBasicBlock&,
241 const SmallVectorImpl<MachineOperand> &Cond,
242 unsigned, unsigned, int&, int&, int&) const;
243 virtual void insertSelect(MachineBasicBlock &MBB,
244 MachineBasicBlock::iterator MI, DebugLoc DL,
246 const SmallVectorImpl<MachineOperand> &Cond,
247 unsigned TrueReg, unsigned FalseReg) const;
248 virtual void copyPhysReg(MachineBasicBlock &MBB,
249 MachineBasicBlock::iterator MI, DebugLoc DL,
250 unsigned DestReg, unsigned SrcReg,
252 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator MI,
254 unsigned SrcReg, bool isKill, int FrameIndex,
255 const TargetRegisterClass *RC,
256 const TargetRegisterInfo *TRI) const;
258 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
259 SmallVectorImpl<MachineOperand> &Addr,
260 const TargetRegisterClass *RC,
261 MachineInstr::mmo_iterator MMOBegin,
262 MachineInstr::mmo_iterator MMOEnd,
263 SmallVectorImpl<MachineInstr*> &NewMIs) const;
265 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator MI,
267 unsigned DestReg, int FrameIndex,
268 const TargetRegisterClass *RC,
269 const TargetRegisterInfo *TRI) const;
271 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
272 SmallVectorImpl<MachineOperand> &Addr,
273 const TargetRegisterClass *RC,
274 MachineInstr::mmo_iterator MMOBegin,
275 MachineInstr::mmo_iterator MMOEnd,
276 SmallVectorImpl<MachineInstr*> &NewMIs) const;
278 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
280 /// foldMemoryOperand - If this target supports it, fold a load or store of
281 /// the specified stack slot into the specified machine instruction for the
282 /// specified operand(s). If this is possible, the target should perform the
283 /// folding and return true, otherwise it should return false. If it folds
284 /// the instruction, it is likely that the MachineInstruction the iterator
285 /// references has been changed.
286 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
288 const SmallVectorImpl<unsigned> &Ops,
289 int FrameIndex) const;
291 /// foldMemoryOperand - Same as the previous version except it allows folding
292 /// of any load and store from / to any address, not just from a specific
294 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
296 const SmallVectorImpl<unsigned> &Ops,
297 MachineInstr* LoadMI) const;
299 /// canFoldMemoryOperand - Returns true if the specified load / store is
300 /// folding is possible.
301 virtual bool canFoldMemoryOperand(const MachineInstr*,
302 const SmallVectorImpl<unsigned> &) const;
304 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
305 /// a store or a load and a store into two or more instruction. If this is
306 /// possible, returns true as well as the new instructions by reference.
307 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
308 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
309 SmallVectorImpl<MachineInstr*> &NewMIs) const;
311 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
312 SmallVectorImpl<SDNode*> &NewNodes) const;
314 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
315 /// instruction after load / store are unfolded from an instruction of the
316 /// specified opcode. It returns zero if the specified unfolding is not
317 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
318 /// index of the operand which will hold the register holding the loaded
320 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
321 bool UnfoldLoad, bool UnfoldStore,
322 unsigned *LoadRegIndex = 0) const;
324 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
325 /// to determine if two loads are loading from the same base address. It
326 /// should only return true if the base pointers are the same and the
327 /// only differences between the two addresses are the offset. It also returns
328 /// the offsets by reference.
329 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
330 int64_t &Offset1, int64_t &Offset2) const;
332 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
333 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
334 /// be scheduled togther. On some targets if two loads are loading from
335 /// addresses in the same cache line, it's better if they are scheduled
336 /// together. This function takes two integers that represent the load offsets
337 /// from the common base address. It returns true if it decides it's desirable
338 /// to schedule the two loads together. "NumLoads" is the number of loads that
339 /// have already been scheduled after Load1.
340 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
341 int64_t Offset1, int64_t Offset2,
342 unsigned NumLoads) const;
344 virtual bool shouldScheduleAdjacent(MachineInstr* First,
345 MachineInstr *Second) const LLVM_OVERRIDE;
347 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
350 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
352 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
353 /// instruction that defines the specified register class.
354 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
356 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
357 if (!MO.isReg()) return false;
358 return X86II::isX86_64ExtendedReg(MO.getReg());
361 /// getGlobalBaseReg - Return a virtual register initialized with the
362 /// the global base register value. Output instructions required to
363 /// initialize the register in the function entry block, if necessary.
365 unsigned getGlobalBaseReg(MachineFunction *MF) const;
367 std::pair<uint16_t, uint16_t>
368 getExecutionDomain(const MachineInstr *MI) const;
370 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
372 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
373 const TargetRegisterInfo *TRI) const;
374 unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
375 const TargetRegisterInfo *TRI) const;
376 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
377 const TargetRegisterInfo *TRI) const;
379 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
382 const SmallVectorImpl<MachineOperand> &MOs,
383 unsigned Size, unsigned Alignment) const;
385 bool isHighLatencyDef(int opc) const;
387 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
388 const MachineRegisterInfo *MRI,
389 const MachineInstr *DefMI, unsigned DefIdx,
390 const MachineInstr *UseMI, unsigned UseIdx) const;
392 /// analyzeCompare - For a comparison instruction, return the source registers
393 /// in SrcReg and SrcReg2 if having two register operands, and the value it
394 /// compares against in CmpValue. Return true if the comparison instruction
396 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
398 int &CmpMask, int &CmpValue) const;
400 /// optimizeCompareInstr - Check if there exists an earlier instruction that
401 /// operates on the same source operands and sets flags in the same way as
402 /// Compare; remove Compare if possible.
403 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
404 unsigned SrcReg2, int CmpMask, int CmpValue,
405 const MachineRegisterInfo *MRI) const;
407 /// optimizeLoadInstr - Try to remove the load by folding it to a register
408 /// operand at the use. We fold the load instructions if and only if the
409 /// def and use are in the same BB. We only look at one load and see
410 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
411 /// defined by the load we are trying to fold. DefMI returns the machine
412 /// instruction that defines FoldAsLoadDefReg, and the function returns
413 /// the machine instruction generated due to folding.
414 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
415 const MachineRegisterInfo *MRI,
416 unsigned &FoldAsLoadDefReg,
417 MachineInstr *&DefMI) const;
420 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
421 MachineFunction::iterator &MFI,
422 MachineBasicBlock::iterator &MBBI,
423 LiveVariables *LV) const;
425 /// isFrameOperand - Return true and the FrameIndex if the specified
426 /// operand and follow operands form a reference to the stack frame.
427 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
428 int &FrameIndex) const;
431 } // End llvm namespace