1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
24 class X86RegisterInfo;
25 class X86TargetMachine;
28 // X86 specific condition code. These correspond to X86_*_COND in
29 // X86InstrInfo.td. They must be kept in synch.
48 // Artificial condition codes. These are used by AnalyzeBranch
49 // to indicate a block terminated with two conditional branches to
50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
51 // which can't be represented on x86 with a single condition. These
52 // are never used in MachineInstrs.
59 // Turn condition code into conditional branch opcode.
60 unsigned GetCondBranchFromCond(CondCode CC);
62 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
63 /// e.g. turning COND_E to COND_NE.
64 CondCode GetOppositeBranchCondition(X86::CondCode CC);
68 /// X86II - This namespace holds all of the target specific flags that
69 /// instruction info tracks.
72 /// Target Operand Flag enum.
74 //===------------------------------------------------------------------===//
75 // X86 Specific MachineOperand flags.
79 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
81 /// SYMBOL_LABEL + [. - PICBASELABEL]
82 MO_GOT_ABSOLUTE_ADDRESS,
84 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
85 /// immediate should get the value of the symbol minus the PIC base label:
86 /// SYMBOL_LABEL - PICBASELABEL
89 /// MO_GOT - On a symbol operand this indicates that the immediate is the
90 /// offset to the GOT entry for the symbol name from the base of the GOT.
92 /// See the X86-64 ELF ABI supplement for more details.
96 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
97 /// the offset to the location of the symbol name from the base of the GOT.
99 /// See the X86-64 ELF ABI supplement for more details.
100 /// SYMBOL_LABEL @GOTOFF
103 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
104 /// offset to the GOT entry for the symbol name from the current code
107 /// See the X86-64 ELF ABI supplement for more details.
108 /// SYMBOL_LABEL @GOTPCREL
111 /// MO_PLT - On a symbol operand this indicates that the immediate is
112 /// offset to the PLT entry of symbol name from the current code location.
114 /// See the X86-64 ELF ABI supplement for more details.
115 /// SYMBOL_LABEL @PLT
118 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
121 /// See 'ELF Handling for Thread-Local Storage' for more details.
122 /// SYMBOL_LABEL @TLSGD
125 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
128 /// See 'ELF Handling for Thread-Local Storage' for more details.
129 /// SYMBOL_LABEL @GOTTPOFF
132 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
135 /// See 'ELF Handling for Thread-Local Storage' for more details.
136 /// SYMBOL_LABEL @INDNTPOFF
139 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
142 /// See 'ELF Handling for Thread-Local Storage' for more details.
143 /// SYMBOL_LABEL @TPOFF
146 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
149 /// See 'ELF Handling for Thread-Local Storage' for more details.
150 /// SYMBOL_LABEL @NTPOFF
153 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
154 /// reference is actually to the "__imp_FOO" symbol. This is used for
155 /// dllimport linkage on windows.
158 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
159 /// reference is actually to the "FOO$stub" symbol. This is used for calls
160 /// and jumps to external functions on Tiger and before.
163 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
164 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
165 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
168 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
169 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
170 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
171 MO_DARWIN_NONLAZY_PIC_BASE,
173 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
174 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
175 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
177 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
181 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
182 /// a reference to a stub for a global, not the global itself.
183 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
184 switch (TargetFlag) {
185 case X86II::MO_DLLIMPORT: // dllimport stub.
186 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
187 case X86II::MO_GOT: // normal GOT reference.
188 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
189 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
190 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
197 /// isGlobalRelativeToPICBase - Return true if the specified global value
198 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
199 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
200 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
201 switch (TargetFlag) {
202 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
203 case X86II::MO_GOT: // isPICStyleGOT: other global.
204 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
205 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
206 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
213 /// X86II - This namespace holds all of the target specific flags that
214 /// instruction info tracks.
218 //===------------------------------------------------------------------===//
219 // Instruction encodings. These are the standard/most common forms for X86
223 // PseudoFrm - This represents an instruction that is a pseudo instruction
224 // or one that has not been implemented yet. It is illegal to code generate
225 // it, but tolerated for intermediate implementation stages.
228 /// Raw - This form is for instructions that don't have any operands, so
229 /// they are just a fixed opcode value, like 'leave'.
232 /// AddRegFrm - This form is used for instructions like 'push r32' that have
233 /// their one register operand added to their opcode.
236 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
237 /// to specify a destination, which in this case is a register.
241 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
242 /// to specify a destination, which in this case is memory.
246 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
247 /// to specify a source, which in this case is a register.
251 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
252 /// to specify a source, which in this case is memory.
256 /// MRM[0-7][rm] - These forms are used to represent instructions that use
257 /// a Mod/RM byte, and use the middle field to hold extended opcode
258 /// information. In the intel manual these are represented as /0, /1, ...
261 // First, instructions that operate on a register r/m operand...
262 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
263 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
265 // Next, instructions that operate on a memory r/m operand...
266 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
267 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
269 // MRMInitReg - This form is used for instructions whose source and
270 // destinations are the same register.
275 //===------------------------------------------------------------------===//
278 // OpSize - Set if this instruction requires an operand size prefix (0x66),
279 // which most often indicates that the instruction operates on 16 bit data
280 // instead of 32 bit data.
283 // AsSize - Set if this instruction requires an operand size prefix (0x67),
284 // which most often indicates that the instruction address 16 bit address
285 // instead of 32 bit address (or 32 bit address in 64 bit mode).
288 //===------------------------------------------------------------------===//
289 // Op0Mask - There are several prefix bytes that are used to form two byte
290 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
291 // used to obtain the setting of this field. If no bits in this field is
292 // set, there is no prefix byte for obtaining a multibyte opcode.
295 Op0Mask = 0xF << Op0Shift,
297 // TB - TwoByte - Set if this instruction has a two byte opcode, which
298 // starts with a 0x0F byte before the real opcode.
301 // REP - The 0xF3 prefix byte indicating repetition of the following
305 // D8-DF - These escape opcodes are used by the floating point unit. These
306 // values must remain sequential.
307 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
308 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
309 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
310 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
312 // XS, XD - These prefix codes are for single and double precision scalar
313 // floating point operations performed in the SSE registers.
314 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
316 // T8, TA - Prefix after the 0x0F prefix.
317 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
319 // TF - Prefix before and after 0x0F
322 //===------------------------------------------------------------------===//
323 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
324 // They are used to specify GPRs and SSE registers, 64-bit operand size,
325 // etc. We only cares about REX.W and REX.R bits and only the former is
326 // statically determined.
329 REX_W = 1 << REXShift,
331 //===------------------------------------------------------------------===//
332 // This three-bit field describes the size of an immediate operand. Zero is
333 // unused so that we can tell if we forgot to set a value.
335 ImmMask = 7 << ImmShift,
336 Imm8 = 1 << ImmShift,
337 Imm16 = 2 << ImmShift,
338 Imm32 = 3 << ImmShift,
339 Imm64 = 4 << ImmShift,
341 //===------------------------------------------------------------------===//
342 // FP Instruction Classification... Zero is non-fp instruction.
344 // FPTypeMask - Mask for all of the FP types...
346 FPTypeMask = 7 << FPTypeShift,
348 // NotFP - The default, set for instructions that do not use FP registers.
349 NotFP = 0 << FPTypeShift,
351 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
352 ZeroArgFP = 1 << FPTypeShift,
354 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
355 OneArgFP = 2 << FPTypeShift,
357 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
358 // result back to ST(0). For example, fcos, fsqrt, etc.
360 OneArgFPRW = 3 << FPTypeShift,
362 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
363 // explicit argument, storing the result to either ST(0) or the implicit
364 // argument. For example: fadd, fsub, fmul, etc...
365 TwoArgFP = 4 << FPTypeShift,
367 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
368 // explicit argument, but have no destination. Example: fucom, fucomi, ...
369 CompareFP = 5 << FPTypeShift,
371 // CondMovFP - "2 operand" floating point conditional move instructions.
372 CondMovFP = 6 << FPTypeShift,
374 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
375 SpecialFP = 7 << FPTypeShift,
379 LOCK = 1 << LOCKShift,
381 // Segment override prefixes. Currently we just need ability to address
382 // stuff in gs and fs segments.
384 SegOvrMask = 3 << SegOvrShift,
385 FS = 1 << SegOvrShift,
386 GS = 2 << SegOvrShift,
388 // Bits 22 -> 23 are unused
390 OpcodeMask = 0xFF << OpcodeShift
393 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
394 // specified machine instruction.
396 static inline unsigned char getBaseOpcodeFor(unsigned TSFlags) {
397 return TSFlags >> X86II::OpcodeShift;
400 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
401 /// of the specified instruction.
402 static inline unsigned getSizeOfImm(unsigned TSFlags) {
403 switch (TSFlags & X86II::ImmMask) {
404 default: assert(0 && "Unknown immediate size");
405 case X86II::Imm8: return 1;
406 case X86II::Imm16: return 2;
407 case X86II::Imm32: return 4;
408 case X86II::Imm64: return 8;
413 const int X86AddrNumOperands = 5;
415 inline static bool isScale(const MachineOperand &MO) {
417 (MO.getImm() == 1 || MO.getImm() == 2 ||
418 MO.getImm() == 4 || MO.getImm() == 8);
421 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
422 if (MI->getOperand(Op).isFI()) return true;
423 return Op+4 <= MI->getNumOperands() &&
424 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
425 MI->getOperand(Op+2).isReg() &&
426 (MI->getOperand(Op+3).isImm() ||
427 MI->getOperand(Op+3).isGlobal() ||
428 MI->getOperand(Op+3).isCPI() ||
429 MI->getOperand(Op+3).isJTI());
432 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
433 if (MI->getOperand(Op).isFI()) return true;
434 return Op+5 <= MI->getNumOperands() &&
435 MI->getOperand(Op+4).isReg() &&
439 class X86InstrInfo : public TargetInstrInfoImpl {
440 X86TargetMachine &TM;
441 const X86RegisterInfo RI;
443 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
444 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
446 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
447 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
448 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
449 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
451 /// MemOp2RegOpTable - Load / store unfolding opcode map.
453 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
456 explicit X86InstrInfo(X86TargetMachine &tm);
458 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
459 /// such, whenever a client has an instance of instruction info, it should
460 /// always be able to get register info as well (through this method).
462 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
464 /// Return true if the instruction is a register to register move and return
465 /// the source and dest operands and their sub-register indices by reference.
466 virtual bool isMoveInstr(const MachineInstr &MI,
467 unsigned &SrcReg, unsigned &DstReg,
468 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
470 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
471 /// extension instruction. That is, it's like a copy where it's legal for the
472 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
473 /// true, then it's expected the pre-extension value is available as a subreg
474 /// of the result register. This also returns the sub-register index in
476 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
477 unsigned &SrcReg, unsigned &DstReg,
478 unsigned &SubIdx) const;
480 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
481 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
482 /// stack locations as well. This uses a heuristic so it isn't
483 /// reliable for correctness.
484 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
485 int &FrameIndex) const;
487 /// hasLoadFromStackSlot - If the specified machine instruction has
488 /// a load from a stack slot, return true along with the FrameIndex
489 /// of the loaded stack slot and the machine mem operand containing
490 /// the reference. If not, return false. Unlike
491 /// isLoadFromStackSlot, this returns true for any instructions that
492 /// loads from the stack. This is a hint only and may not catch all
494 bool hasLoadFromStackSlot(const MachineInstr *MI,
495 const MachineMemOperand *&MMO,
496 int &FrameIndex) const;
498 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
499 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
500 /// stack locations as well. This uses a heuristic so it isn't
501 /// reliable for correctness.
502 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
503 int &FrameIndex) const;
505 /// hasStoreToStackSlot - If the specified machine instruction has a
506 /// store to a stack slot, return true along with the FrameIndex of
507 /// the loaded stack slot and the machine mem operand containing the
508 /// reference. If not, return false. Unlike isStoreToStackSlot,
509 /// this returns true for any instructions that loads from the
510 /// stack. This is a hint only and may not catch all cases.
511 bool hasStoreToStackSlot(const MachineInstr *MI,
512 const MachineMemOperand *&MMO,
513 int &FrameIndex) const;
515 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
516 AliasAnalysis *AA) const;
517 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
518 unsigned DestReg, unsigned SubIdx,
519 const MachineInstr *Orig,
520 const TargetRegisterInfo *TRI) const;
522 /// convertToThreeAddress - This method must be implemented by targets that
523 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
524 /// may be able to convert a two-address instruction into a true
525 /// three-address instruction on demand. This allows the X86 target (for
526 /// example) to convert ADD and SHL instructions into LEA instructions if they
527 /// would require register copies due to two-addressness.
529 /// This method returns a null pointer if the transformation cannot be
530 /// performed, otherwise it returns the new instruction.
532 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
533 MachineBasicBlock::iterator &MBBI,
534 LiveVariables *LV) const;
536 /// commuteInstruction - We have a few instructions that must be hacked on to
539 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
542 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
543 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
544 MachineBasicBlock *&FBB,
545 SmallVectorImpl<MachineOperand> &Cond,
546 bool AllowModify) const;
547 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
548 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
549 MachineBasicBlock *FBB,
550 const SmallVectorImpl<MachineOperand> &Cond) const;
551 virtual bool copyRegToReg(MachineBasicBlock &MBB,
552 MachineBasicBlock::iterator MI,
553 unsigned DestReg, unsigned SrcReg,
554 const TargetRegisterClass *DestRC,
555 const TargetRegisterClass *SrcRC) const;
556 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
557 MachineBasicBlock::iterator MI,
558 unsigned SrcReg, bool isKill, int FrameIndex,
559 const TargetRegisterClass *RC) const;
561 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
562 SmallVectorImpl<MachineOperand> &Addr,
563 const TargetRegisterClass *RC,
564 MachineInstr::mmo_iterator MMOBegin,
565 MachineInstr::mmo_iterator MMOEnd,
566 SmallVectorImpl<MachineInstr*> &NewMIs) const;
568 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
569 MachineBasicBlock::iterator MI,
570 unsigned DestReg, int FrameIndex,
571 const TargetRegisterClass *RC) const;
573 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
574 SmallVectorImpl<MachineOperand> &Addr,
575 const TargetRegisterClass *RC,
576 MachineInstr::mmo_iterator MMOBegin,
577 MachineInstr::mmo_iterator MMOEnd,
578 SmallVectorImpl<MachineInstr*> &NewMIs) const;
580 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
581 MachineBasicBlock::iterator MI,
582 const std::vector<CalleeSavedInfo> &CSI) const;
584 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
585 MachineBasicBlock::iterator MI,
586 const std::vector<CalleeSavedInfo> &CSI) const;
588 /// foldMemoryOperand - If this target supports it, fold a load or store of
589 /// the specified stack slot into the specified machine instruction for the
590 /// specified operand(s). If this is possible, the target should perform the
591 /// folding and return true, otherwise it should return false. If it folds
592 /// the instruction, it is likely that the MachineInstruction the iterator
593 /// references has been changed.
594 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
596 const SmallVectorImpl<unsigned> &Ops,
597 int FrameIndex) const;
599 /// foldMemoryOperand - Same as the previous version except it allows folding
600 /// of any load and store from / to any address, not just from a specific
602 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
604 const SmallVectorImpl<unsigned> &Ops,
605 MachineInstr* LoadMI) const;
607 /// canFoldMemoryOperand - Returns true if the specified load / store is
608 /// folding is possible.
609 virtual bool canFoldMemoryOperand(const MachineInstr*,
610 const SmallVectorImpl<unsigned> &) const;
612 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
613 /// a store or a load and a store into two or more instruction. If this is
614 /// possible, returns true as well as the new instructions by reference.
615 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
616 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
617 SmallVectorImpl<MachineInstr*> &NewMIs) const;
619 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
620 SmallVectorImpl<SDNode*> &NewNodes) const;
622 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
623 /// instruction after load / store are unfolded from an instruction of the
624 /// specified opcode. It returns zero if the specified unfolding is not
625 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
626 /// index of the operand which will hold the register holding the loaded
628 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
629 bool UnfoldLoad, bool UnfoldStore,
630 unsigned *LoadRegIndex = 0) const;
632 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
633 /// to determine if two loads are loading from the same base address. It
634 /// should only return true if the base pointers are the same and the
635 /// only differences between the two addresses are the offset. It also returns
636 /// the offsets by reference.
637 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
638 int64_t &Offset1, int64_t &Offset2) const;
640 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
641 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
642 /// be scheduled togther. On some targets if two loads are loading from
643 /// addresses in the same cache line, it's better if they are scheduled
644 /// together. This function takes two integers that represent the load offsets
645 /// from the common base address. It returns true if it decides it's desirable
646 /// to schedule the two loads together. "NumLoads" is the number of loads that
647 /// have already been scheduled after Load1.
648 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
649 int64_t Offset1, int64_t Offset2,
650 unsigned NumLoads) const;
653 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
655 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
656 /// instruction that defines the specified register class.
657 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
659 static bool isX86_64NonExtLowByteReg(unsigned reg) {
660 return (reg == X86::SPL || reg == X86::BPL ||
661 reg == X86::SIL || reg == X86::DIL);
664 static bool isX86_64ExtendedReg(const MachineOperand &MO);
665 static unsigned determineREX(const MachineInstr &MI);
667 /// GetInstSize - Returns the size of the specified MachineInstr.
669 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
671 /// getGlobalBaseReg - Return a virtual register initialized with the
672 /// the global base register value. Output instructions required to
673 /// initialize the register in the function entry block, if necessary.
675 unsigned getGlobalBaseReg(MachineFunction *MF) const;
678 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
679 MachineFunction::iterator &MFI,
680 MachineBasicBlock::iterator &MBBI,
681 LiveVariables *LV) const;
683 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
686 const SmallVectorImpl<MachineOperand> &MOs,
687 unsigned Size, unsigned Alignment) const;
689 /// isFrameOperand - Return true and the FrameIndex if the specified
690 /// operand and follow operands form a reference to the stack frame.
691 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
692 int &FrameIndex) const;
695 } // End llvm namespace