1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/IndexedMap.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
24 class X86RegisterInfo;
25 class X86TargetMachine;
28 // X86 specific condition code. These correspond to X86_*_COND in
29 // X86InstrInfo.td. They must be kept in synch.
50 // Turn condition code into conditional branch opcode.
51 unsigned GetCondBranchFromCond(CondCode CC);
53 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
54 /// e.g. turning COND_E to COND_NE.
55 CondCode GetOppositeBranchCondition(X86::CondCode CC);
59 /// X86II - This namespace holds all of the target specific flags that
60 /// instruction info tracks.
64 //===------------------------------------------------------------------===//
65 // Instruction types. These are the standard/most common forms for X86
69 // PseudoFrm - This represents an instruction that is a pseudo instruction
70 // or one that has not been implemented yet. It is illegal to code generate
71 // it, but tolerated for intermediate implementation stages.
74 /// Raw - This form is for instructions that don't have any operands, so
75 /// they are just a fixed opcode value, like 'leave'.
78 /// AddRegFrm - This form is used for instructions like 'push r32' that have
79 /// their one register operand added to their opcode.
82 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
83 /// to specify a destination, which in this case is a register.
87 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
88 /// to specify a destination, which in this case is memory.
92 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
93 /// to specify a source, which in this case is a register.
97 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
98 /// to specify a source, which in this case is memory.
102 /// MRM[0-7][rm] - These forms are used to represent instructions that use
103 /// a Mod/RM byte, and use the middle field to hold extended opcode
104 /// information. In the intel manual these are represented as /0, /1, ...
107 // First, instructions that operate on a register r/m operand...
108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
111 // Next, instructions that operate on a memory r/m operand...
112 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
113 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
115 // MRMInitReg - This form is used for instructions whose source and
116 // destinations are the same register.
121 //===------------------------------------------------------------------===//
124 // OpSize - Set if this instruction requires an operand size prefix (0x66),
125 // which most often indicates that the instruction operates on 16 bit data
126 // instead of 32 bit data.
129 // AsSize - Set if this instruction requires an operand size prefix (0x67),
130 // which most often indicates that the instruction address 16 bit address
131 // instead of 32 bit address (or 32 bit address in 64 bit mode).
134 //===------------------------------------------------------------------===//
135 // Op0Mask - There are several prefix bytes that are used to form two byte
136 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
137 // used to obtain the setting of this field. If no bits in this field is
138 // set, there is no prefix byte for obtaining a multibyte opcode.
141 Op0Mask = 0xF << Op0Shift,
143 // TB - TwoByte - Set if this instruction has a two byte opcode, which
144 // starts with a 0x0F byte before the real opcode.
147 // REP - The 0xF3 prefix byte indicating repetition of the following
151 // D8-DF - These escape opcodes are used by the floating point unit. These
152 // values must remain sequential.
153 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
154 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
155 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
156 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
158 // XS, XD - These prefix codes are for single and double precision scalar
159 // floating point operations performed in the SSE registers.
160 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
162 // T8, TA - Prefix after the 0x0F prefix.
163 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
165 //===------------------------------------------------------------------===//
166 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
167 // They are used to specify GPRs and SSE registers, 64-bit operand size,
168 // etc. We only cares about REX.W and REX.R bits and only the former is
169 // statically determined.
172 REX_W = 1 << REXShift,
174 //===------------------------------------------------------------------===//
175 // This three-bit field describes the size of an immediate operand. Zero is
176 // unused so that we can tell if we forgot to set a value.
178 ImmMask = 7 << ImmShift,
179 Imm8 = 1 << ImmShift,
180 Imm16 = 2 << ImmShift,
181 Imm32 = 3 << ImmShift,
182 Imm64 = 4 << ImmShift,
184 //===------------------------------------------------------------------===//
185 // FP Instruction Classification... Zero is non-fp instruction.
187 // FPTypeMask - Mask for all of the FP types...
189 FPTypeMask = 7 << FPTypeShift,
191 // NotFP - The default, set for instructions that do not use FP registers.
192 NotFP = 0 << FPTypeShift,
194 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
195 ZeroArgFP = 1 << FPTypeShift,
197 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
198 OneArgFP = 2 << FPTypeShift,
200 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
201 // result back to ST(0). For example, fcos, fsqrt, etc.
203 OneArgFPRW = 3 << FPTypeShift,
205 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
206 // explicit argument, storing the result to either ST(0) or the implicit
207 // argument. For example: fadd, fsub, fmul, etc...
208 TwoArgFP = 4 << FPTypeShift,
210 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
211 // explicit argument, but have no destination. Example: fucom, fucomi, ...
212 CompareFP = 5 << FPTypeShift,
214 // CondMovFP - "2 operand" floating point conditional move instructions.
215 CondMovFP = 6 << FPTypeShift,
217 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
218 SpecialFP = 7 << FPTypeShift,
222 LOCK = 1 << LOCKShift,
224 // Segment override prefixes. Currently we just need ability to address
225 // stuff in gs and fs segments.
227 SegOvrMask = 3 << SegOvrShift,
228 FS = 1 << SegOvrShift,
229 GS = 2 << SegOvrShift,
231 // Bits 22 -> 23 are unused
233 OpcodeMask = 0xFF << OpcodeShift
237 inline static bool isScale(const MachineOperand &MO) {
239 (MO.getImm() == 1 || MO.getImm() == 2 ||
240 MO.getImm() == 4 || MO.getImm() == 8);
243 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
244 if (MI->getOperand(Op).isFI()) return true;
245 return Op+4 <= MI->getNumOperands() &&
246 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
247 MI->getOperand(Op+2).isReg() &&
248 (MI->getOperand(Op+3).isImm() ||
249 MI->getOperand(Op+3).isGlobal() ||
250 MI->getOperand(Op+3).isCPI() ||
251 MI->getOperand(Op+3).isJTI());
254 class X86InstrInfo : public TargetInstrInfoImpl {
255 X86TargetMachine &TM;
256 const X86RegisterInfo RI;
258 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
259 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
261 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
262 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
263 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
264 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
266 /// MemOp2RegOpTable - Load / store unfolding opcode map.
268 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
271 explicit X86InstrInfo(X86TargetMachine &tm);
273 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
274 /// such, whenever a client has an instance of instruction info, it should
275 /// always be able to get register info as well (through this method).
277 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
279 // Return true if the instruction is a register to register move and
280 // leave the source and dest operands in the passed parameters.
282 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
283 unsigned& destReg) const;
284 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
285 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
287 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const;
288 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
289 unsigned DestReg, const MachineInstr *Orig) const;
291 bool isInvariantLoad(MachineInstr *MI) const;
293 /// convertToThreeAddress - This method must be implemented by targets that
294 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
295 /// may be able to convert a two-address instruction into a true
296 /// three-address instruction on demand. This allows the X86 target (for
297 /// example) to convert ADD and SHL instructions into LEA instructions if they
298 /// would require register copies due to two-addressness.
300 /// This method returns a null pointer if the transformation cannot be
301 /// performed, otherwise it returns the new instruction.
303 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
304 MachineBasicBlock::iterator &MBBI,
305 LiveVariables *LV) const;
307 /// commuteInstruction - We have a few instructions that must be hacked on to
310 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
313 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
314 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
315 MachineBasicBlock *&FBB,
316 SmallVectorImpl<MachineOperand> &Cond) const;
317 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
318 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
319 MachineBasicBlock *FBB,
320 const SmallVectorImpl<MachineOperand> &Cond) const;
321 virtual bool copyRegToReg(MachineBasicBlock &MBB,
322 MachineBasicBlock::iterator MI,
323 unsigned DestReg, unsigned SrcReg,
324 const TargetRegisterClass *DestRC,
325 const TargetRegisterClass *SrcRC) const;
326 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator MI,
328 unsigned SrcReg, bool isKill, int FrameIndex,
329 const TargetRegisterClass *RC) const;
331 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
332 SmallVectorImpl<MachineOperand> &Addr,
333 const TargetRegisterClass *RC,
334 SmallVectorImpl<MachineInstr*> &NewMIs) const;
336 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
337 MachineBasicBlock::iterator MI,
338 unsigned DestReg, int FrameIndex,
339 const TargetRegisterClass *RC) const;
341 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
342 SmallVectorImpl<MachineOperand> &Addr,
343 const TargetRegisterClass *RC,
344 SmallVectorImpl<MachineInstr*> &NewMIs) const;
346 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
347 MachineBasicBlock::iterator MI,
348 const std::vector<CalleeSavedInfo> &CSI) const;
350 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
351 MachineBasicBlock::iterator MI,
352 const std::vector<CalleeSavedInfo> &CSI) const;
354 /// foldMemoryOperand - If this target supports it, fold a load or store of
355 /// the specified stack slot into the specified machine instruction for the
356 /// specified operand(s). If this is possible, the target should perform the
357 /// folding and return true, otherwise it should return false. If it folds
358 /// the instruction, it is likely that the MachineInstruction the iterator
359 /// references has been changed.
360 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
362 const SmallVectorImpl<unsigned> &Ops,
363 int FrameIndex) const;
365 /// foldMemoryOperand - Same as the previous version except it allows folding
366 /// of any load and store from / to any address, not just from a specific
368 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
370 const SmallVectorImpl<unsigned> &Ops,
371 MachineInstr* LoadMI) const;
373 /// canFoldMemoryOperand - Returns true if the specified load / store is
374 /// folding is possible.
375 virtual bool canFoldMemoryOperand(const MachineInstr*,
376 const SmallVectorImpl<unsigned> &) const;
378 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
379 /// a store or a load and a store into two or more instruction. If this is
380 /// possible, returns true as well as the new instructions by reference.
381 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
382 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
383 SmallVectorImpl<MachineInstr*> &NewMIs) const;
385 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
386 SmallVectorImpl<SDNode*> &NewNodes) const;
388 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
389 /// instruction after load / store are unfolded from an instruction of the
390 /// specified opcode. It returns zero if the specified unfolding is not
392 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
393 bool UnfoldLoad, bool UnfoldStore) const;
395 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
397 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
399 const TargetRegisterClass *getPointerRegClass() const;
401 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
402 // specified machine instruction.
404 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
405 return TID->TSFlags >> X86II::OpcodeShift;
407 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
408 return getBaseOpcodeFor(&get(Opcode));
411 static bool isX86_64NonExtLowByteReg(unsigned reg) {
412 return (reg == X86::SPL || reg == X86::BPL ||
413 reg == X86::SIL || reg == X86::DIL);
416 static unsigned sizeOfImm(const TargetInstrDesc *Desc);
417 static unsigned getX86RegNum(unsigned RegNo);
418 static bool isX86_64ExtendedReg(const MachineOperand &MO);
419 static unsigned determineREX(const MachineInstr &MI);
421 /// GetInstSize - Returns the size of the specified MachineInstr.
423 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
425 /// getGlobalBaseReg - Return a virtual register initialized with the
426 /// the global base register value. Output instructions required to
427 /// initialize the register in the function entry block, if necessary.
429 unsigned getGlobalBaseReg(MachineFunction *MF) const;
432 MachineInstr* foldMemoryOperand(MachineFunction &MF,
435 const SmallVector<MachineOperand,4> &MOs) const;
438 } // End llvm namespace