1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
209 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
210 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
212 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
213 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
215 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
216 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
218 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
219 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
221 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
224 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
225 SDTypeProfile<1, 1, [SDTCisInt<0>,
227 [SDNPHasChain, SDNPSideEffect]>;
228 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
229 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
230 [SDNPHasChain, SDNPSideEffect]>;
232 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
233 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
235 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
237 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
238 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
240 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
242 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
243 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
245 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
246 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
247 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
249 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
251 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
254 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
256 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
258 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
259 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
261 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
264 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
265 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
267 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
268 [SDNPHasChain, SDNPOutGlue]>;
270 //===----------------------------------------------------------------------===//
271 // X86 Operand Definitions.
274 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
275 // the index operand of an address, to conform to x86 encoding restrictions.
276 def ptr_rc_nosp : PointerLikeRegClass<1>;
278 // *mem - Operand definitions for the funky X86 addressing mode operands.
280 def X86MemAsmOperand : AsmOperandClass {
283 def X86Mem8AsmOperand : AsmOperandClass {
284 let Name = "Mem8"; let RenderMethod = "addMemOperands";
286 def X86Mem16AsmOperand : AsmOperandClass {
287 let Name = "Mem16"; let RenderMethod = "addMemOperands";
289 def X86Mem32AsmOperand : AsmOperandClass {
290 let Name = "Mem32"; let RenderMethod = "addMemOperands";
292 def X86Mem64AsmOperand : AsmOperandClass {
293 let Name = "Mem64"; let RenderMethod = "addMemOperands";
295 def X86Mem80AsmOperand : AsmOperandClass {
296 let Name = "Mem80"; let RenderMethod = "addMemOperands";
298 def X86Mem128AsmOperand : AsmOperandClass {
299 let Name = "Mem128"; let RenderMethod = "addMemOperands";
301 def X86Mem256AsmOperand : AsmOperandClass {
302 let Name = "Mem256"; let RenderMethod = "addMemOperands";
304 def X86Mem512AsmOperand : AsmOperandClass {
305 let Name = "Mem512"; let RenderMethod = "addMemOperands";
308 // Gather mem operands
309 def X86MemVX32Operand : AsmOperandClass {
310 let Name = "MemVX32"; let RenderMethod = "addMemOperands";
312 def X86MemVY32Operand : AsmOperandClass {
313 let Name = "MemVY32"; let RenderMethod = "addMemOperands";
315 def X86MemVZ32Operand : AsmOperandClass {
316 let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
318 def X86MemVX64Operand : AsmOperandClass {
319 let Name = "MemVX64"; let RenderMethod = "addMemOperands";
321 def X86MemVY64Operand : AsmOperandClass {
322 let Name = "MemVY64"; let RenderMethod = "addMemOperands";
324 def X86MemVZ64Operand : AsmOperandClass {
325 let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
328 def X86AbsMemAsmOperand : AsmOperandClass {
330 let SuperClasses = [X86MemAsmOperand];
332 class X86MemOperand<string printMethod> : Operand<iPTR> {
333 let PrintMethod = printMethod;
334 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
335 let ParserMatchClass = X86MemAsmOperand;
338 let OperandType = "OPERAND_MEMORY" in {
339 def opaque32mem : X86MemOperand<"printopaquemem">;
340 def opaque48mem : X86MemOperand<"printopaquemem">;
341 def opaque80mem : X86MemOperand<"printopaquemem">;
342 def opaque512mem : X86MemOperand<"printopaquemem">;
344 def i8mem : X86MemOperand<"printi8mem"> {
345 let ParserMatchClass = X86Mem8AsmOperand; }
346 def i16mem : X86MemOperand<"printi16mem"> {
347 let ParserMatchClass = X86Mem16AsmOperand; }
348 def i32mem : X86MemOperand<"printi32mem"> {
349 let ParserMatchClass = X86Mem32AsmOperand; }
350 def i64mem : X86MemOperand<"printi64mem"> {
351 let ParserMatchClass = X86Mem64AsmOperand; }
352 def i128mem : X86MemOperand<"printi128mem"> {
353 let ParserMatchClass = X86Mem128AsmOperand; }
354 def i256mem : X86MemOperand<"printi256mem"> {
355 let ParserMatchClass = X86Mem256AsmOperand; }
356 def i512mem : X86MemOperand<"printi512mem"> {
357 let ParserMatchClass = X86Mem512AsmOperand; }
358 def f32mem : X86MemOperand<"printf32mem"> {
359 let ParserMatchClass = X86Mem32AsmOperand; }
360 def f64mem : X86MemOperand<"printf64mem"> {
361 let ParserMatchClass = X86Mem64AsmOperand; }
362 def f80mem : X86MemOperand<"printf80mem"> {
363 let ParserMatchClass = X86Mem80AsmOperand; }
364 def f128mem : X86MemOperand<"printf128mem"> {
365 let ParserMatchClass = X86Mem128AsmOperand; }
366 def f256mem : X86MemOperand<"printf256mem">{
367 let ParserMatchClass = X86Mem256AsmOperand; }
368 def f512mem : X86MemOperand<"printf512mem">{
369 let ParserMatchClass = X86Mem512AsmOperand; }
370 def v512mem : Operand<iPTR> {
371 let PrintMethod = "printf512mem";
372 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
373 let ParserMatchClass = X86Mem512AsmOperand; }
375 // Gather mem operands
376 def vx32mem : X86MemOperand<"printi32mem">{
377 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
378 let ParserMatchClass = X86MemVX32Operand; }
379 def vy32mem : X86MemOperand<"printi32mem">{
380 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
381 let ParserMatchClass = X86MemVY32Operand; }
382 def vx64mem : X86MemOperand<"printi64mem">{
383 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
384 let ParserMatchClass = X86MemVX64Operand; }
385 def vy64mem : X86MemOperand<"printi64mem">{
386 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
387 let ParserMatchClass = X86MemVY64Operand; }
388 def vy64xmem : X86MemOperand<"printi64mem">{
389 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
390 let ParserMatchClass = X86MemVY64Operand; }
391 def vz32mem : X86MemOperand<"printi32mem">{
392 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
393 let ParserMatchClass = X86MemVZ32Operand; }
394 def vz64mem : X86MemOperand<"printi64mem">{
395 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
396 let ParserMatchClass = X86MemVZ64Operand; }
399 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
400 // plain GR64, so that it doesn't potentially require a REX prefix.
401 def i8mem_NOREX : Operand<i64> {
402 let PrintMethod = "printi8mem";
403 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
404 let ParserMatchClass = X86Mem8AsmOperand;
405 let OperandType = "OPERAND_MEMORY";
408 // GPRs available for tailcall.
409 // It represents GR32_TC, GR64_TC or GR64_TCW64.
410 def ptr_rc_tailcall : PointerLikeRegClass<2>;
412 // Special i32mem for addresses of load folding tail calls. These are not
413 // allowed to use callee-saved registers since they must be scheduled
414 // after callee-saved register are popped.
415 def i32mem_TC : Operand<i32> {
416 let PrintMethod = "printi32mem";
417 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
419 let ParserMatchClass = X86Mem32AsmOperand;
420 let OperandType = "OPERAND_MEMORY";
423 // Special i64mem for addresses of load folding tail calls. These are not
424 // allowed to use callee-saved registers since they must be scheduled
425 // after callee-saved register are popped.
426 def i64mem_TC : Operand<i64> {
427 let PrintMethod = "printi64mem";
428 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
429 ptr_rc_tailcall, i32imm, i8imm);
430 let ParserMatchClass = X86Mem64AsmOperand;
431 let OperandType = "OPERAND_MEMORY";
434 let OperandType = "OPERAND_PCREL",
435 ParserMatchClass = X86AbsMemAsmOperand,
436 PrintMethod = "printPCRelImm" in {
437 def i32imm_pcrel : Operand<i32>;
438 def i16imm_pcrel : Operand<i16>;
440 // Branch targets have OtherVT type and print as pc-relative values.
441 def brtarget : Operand<OtherVT>;
442 def brtarget8 : Operand<OtherVT>;
446 def X86SrcIdx8Operand : AsmOperandClass {
447 let Name = "SrcIdx8";
448 let RenderMethod = "addSrcIdxOperands";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86SrcIdx16Operand : AsmOperandClass {
452 let Name = "SrcIdx16";
453 let RenderMethod = "addSrcIdxOperands";
454 let SuperClasses = [X86Mem16AsmOperand];
456 def X86SrcIdx32Operand : AsmOperandClass {
457 let Name = "SrcIdx32";
458 let RenderMethod = "addSrcIdxOperands";
459 let SuperClasses = [X86Mem32AsmOperand];
461 def X86SrcIdx64Operand : AsmOperandClass {
462 let Name = "SrcIdx64";
463 let RenderMethod = "addSrcIdxOperands";
464 let SuperClasses = [X86Mem64AsmOperand];
466 def X86DstIdx8Operand : AsmOperandClass {
467 let Name = "DstIdx8";
468 let RenderMethod = "addDstIdxOperands";
469 let SuperClasses = [X86Mem8AsmOperand];
471 def X86DstIdx16Operand : AsmOperandClass {
472 let Name = "DstIdx16";
473 let RenderMethod = "addDstIdxOperands";
474 let SuperClasses = [X86Mem16AsmOperand];
476 def X86DstIdx32Operand : AsmOperandClass {
477 let Name = "DstIdx32";
478 let RenderMethod = "addDstIdxOperands";
479 let SuperClasses = [X86Mem32AsmOperand];
481 def X86DstIdx64Operand : AsmOperandClass {
482 let Name = "DstIdx64";
483 let RenderMethod = "addDstIdxOperands";
484 let SuperClasses = [X86Mem64AsmOperand];
486 def X86MemOffs8AsmOperand : AsmOperandClass {
487 let Name = "MemOffs8";
488 let RenderMethod = "addMemOffsOperands";
489 let SuperClasses = [X86Mem8AsmOperand];
491 def X86MemOffs16AsmOperand : AsmOperandClass {
492 let Name = "MemOffs16";
493 let RenderMethod = "addMemOffsOperands";
494 let SuperClasses = [X86Mem16AsmOperand];
496 def X86MemOffs32AsmOperand : AsmOperandClass {
497 let Name = "MemOffs32";
498 let RenderMethod = "addMemOffsOperands";
499 let SuperClasses = [X86Mem32AsmOperand];
501 def X86MemOffs64AsmOperand : AsmOperandClass {
502 let Name = "MemOffs64";
503 let RenderMethod = "addMemOffsOperands";
504 let SuperClasses = [X86Mem64AsmOperand];
506 let OperandType = "OPERAND_MEMORY" in {
507 def srcidx8 : Operand<iPTR> {
508 let ParserMatchClass = X86SrcIdx8Operand;
509 let MIOperandInfo = (ops ptr_rc, i8imm);
510 let PrintMethod = "printSrcIdx8"; }
511 def srcidx16 : Operand<iPTR> {
512 let ParserMatchClass = X86SrcIdx16Operand;
513 let MIOperandInfo = (ops ptr_rc, i8imm);
514 let PrintMethod = "printSrcIdx16"; }
515 def srcidx32 : Operand<iPTR> {
516 let ParserMatchClass = X86SrcIdx32Operand;
517 let MIOperandInfo = (ops ptr_rc, i8imm);
518 let PrintMethod = "printSrcIdx32"; }
519 def srcidx64 : Operand<iPTR> {
520 let ParserMatchClass = X86SrcIdx64Operand;
521 let MIOperandInfo = (ops ptr_rc, i8imm);
522 let PrintMethod = "printSrcIdx64"; }
523 def dstidx8 : Operand<iPTR> {
524 let ParserMatchClass = X86DstIdx8Operand;
525 let MIOperandInfo = (ops ptr_rc);
526 let PrintMethod = "printDstIdx8"; }
527 def dstidx16 : Operand<iPTR> {
528 let ParserMatchClass = X86DstIdx16Operand;
529 let MIOperandInfo = (ops ptr_rc);
530 let PrintMethod = "printDstIdx16"; }
531 def dstidx32 : Operand<iPTR> {
532 let ParserMatchClass = X86DstIdx32Operand;
533 let MIOperandInfo = (ops ptr_rc);
534 let PrintMethod = "printDstIdx32"; }
535 def dstidx64 : Operand<iPTR> {
536 let ParserMatchClass = X86DstIdx64Operand;
537 let MIOperandInfo = (ops ptr_rc);
538 let PrintMethod = "printDstIdx64"; }
539 def offset8 : Operand<iPTR> {
540 let ParserMatchClass = X86MemOffs8AsmOperand;
541 let MIOperandInfo = (ops i64imm, i8imm);
542 let PrintMethod = "printMemOffs8"; }
543 def offset16 : Operand<iPTR> {
544 let ParserMatchClass = X86MemOffs16AsmOperand;
545 let MIOperandInfo = (ops i64imm, i8imm);
546 let PrintMethod = "printMemOffs16"; }
547 def offset32 : Operand<iPTR> {
548 let ParserMatchClass = X86MemOffs32AsmOperand;
549 let MIOperandInfo = (ops i64imm, i8imm);
550 let PrintMethod = "printMemOffs32"; }
551 def offset64 : Operand<iPTR> {
552 let ParserMatchClass = X86MemOffs64AsmOperand;
553 let MIOperandInfo = (ops i64imm, i8imm);
554 let PrintMethod = "printMemOffs64"; }
558 def SSECC : Operand<i8> {
559 let PrintMethod = "printSSECC";
560 let OperandType = "OPERAND_IMMEDIATE";
563 def AVXCC : Operand<i8> {
564 let PrintMethod = "printAVXCC";
565 let OperandType = "OPERAND_IMMEDIATE";
568 class ImmSExtAsmOperandClass : AsmOperandClass {
569 let SuperClasses = [ImmAsmOperand];
570 let RenderMethod = "addImmOperands";
573 class ImmZExtAsmOperandClass : AsmOperandClass {
574 let SuperClasses = [ImmAsmOperand];
575 let RenderMethod = "addImmOperands";
578 def X86GR32orGR64AsmOperand : AsmOperandClass {
579 let Name = "GR32orGR64";
582 def GR32orGR64 : RegisterOperand<GR32> {
583 let ParserMatchClass = X86GR32orGR64AsmOperand;
586 def AVX512RC : Operand<i32> {
587 let PrintMethod = "printRoundingControl";
588 let OperandType = "OPERAND_IMMEDIATE";
590 // Sign-extended immediate classes. We don't need to define the full lattice
591 // here because there is no instruction with an ambiguity between ImmSExti64i32
594 // The strange ranges come from the fact that the assembler always works with
595 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
596 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
599 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
600 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
601 let Name = "ImmSExti64i32";
604 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
605 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
606 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
607 let Name = "ImmSExti16i8";
608 let SuperClasses = [ImmSExti64i32AsmOperand];
611 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
612 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
613 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
614 let Name = "ImmSExti32i8";
618 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
619 let Name = "ImmZExtu32u8";
624 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
625 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
626 let Name = "ImmSExti64i8";
627 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
628 ImmSExti64i32AsmOperand];
631 // A couple of more descriptive operand definitions.
632 // 16-bits but only 8 bits are significant.
633 def i16i8imm : Operand<i16> {
634 let ParserMatchClass = ImmSExti16i8AsmOperand;
635 let OperandType = "OPERAND_IMMEDIATE";
637 // 32-bits but only 8 bits are significant.
638 def i32i8imm : Operand<i32> {
639 let ParserMatchClass = ImmSExti32i8AsmOperand;
640 let OperandType = "OPERAND_IMMEDIATE";
642 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
643 def u32u8imm : Operand<i32> {
644 let ParserMatchClass = ImmZExtu32u8AsmOperand;
645 let OperandType = "OPERAND_IMMEDIATE";
648 // 64-bits but only 32 bits are significant.
649 def i64i32imm : Operand<i64> {
650 let ParserMatchClass = ImmSExti64i32AsmOperand;
651 let OperandType = "OPERAND_IMMEDIATE";
654 // 64-bits but only 32 bits are significant, and those bits are treated as being
656 def i64i32imm_pcrel : Operand<i64> {
657 let PrintMethod = "printPCRelImm";
658 let ParserMatchClass = X86AbsMemAsmOperand;
659 let OperandType = "OPERAND_PCREL";
662 // 64-bits but only 8 bits are significant.
663 def i64i8imm : Operand<i64> {
664 let ParserMatchClass = ImmSExti64i8AsmOperand;
665 let OperandType = "OPERAND_IMMEDIATE";
668 def lea64_32mem : Operand<i32> {
669 let PrintMethod = "printi32mem";
670 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
671 let ParserMatchClass = X86MemAsmOperand;
674 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
675 def lea64mem : Operand<i64> {
676 let PrintMethod = "printi64mem";
677 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
678 let ParserMatchClass = X86MemAsmOperand;
682 //===----------------------------------------------------------------------===//
683 // X86 Complex Pattern Definitions.
686 // Define X86 specific addressing mode.
687 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
688 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
689 [add, sub, mul, X86mul_imm, shl, or, frameindex],
691 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
692 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
693 [add, sub, mul, X86mul_imm, shl, or,
694 frameindex, X86WrapperRIP],
697 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
698 [tglobaltlsaddr], []>;
700 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
701 [tglobaltlsaddr], []>;
703 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
704 [add, sub, mul, X86mul_imm, shl, or, frameindex,
707 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
708 [tglobaltlsaddr], []>;
710 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
711 [tglobaltlsaddr], []>;
713 //===----------------------------------------------------------------------===//
714 // X86 Instruction Predicate Definitions.
715 def HasCMov : Predicate<"Subtarget->hasCMov()">;
716 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
718 def HasMMX : Predicate<"Subtarget->hasMMX()">;
719 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
720 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
721 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
722 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
723 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
724 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
725 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
726 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
727 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
728 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
729 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
730 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
731 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
732 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
733 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
734 def HasAVX : Predicate<"Subtarget->hasAVX()">;
735 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
736 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
737 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
738 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
739 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
740 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
741 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
742 def HasCDI : Predicate<"Subtarget->hasCDI()">;
743 def HasPFI : Predicate<"Subtarget->hasPFI()">;
744 def HasERI : Predicate<"Subtarget->hasERI()">;
746 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
747 def HasAES : Predicate<"Subtarget->hasAES()">;
748 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
749 def HasFMA : Predicate<"Subtarget->hasFMA()">;
750 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
751 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
752 def HasXOP : Predicate<"Subtarget->hasXOP()">;
753 def HasTBM : Predicate<"Subtarget->hasTBM()">;
754 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
755 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
756 def HasF16C : Predicate<"Subtarget->hasF16C()">;
757 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
758 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
759 def HasBMI : Predicate<"Subtarget->hasBMI()">;
760 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
761 def HasRTM : Predicate<"Subtarget->hasRTM()">;
762 def HasHLE : Predicate<"Subtarget->hasHLE()">;
763 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
764 def HasADX : Predicate<"Subtarget->hasADX()">;
765 def HasSHA : Predicate<"Subtarget->hasSHA()">;
766 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
767 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
768 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
769 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
770 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
771 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
772 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
773 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
774 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
775 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
776 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
777 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
778 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
779 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
780 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
781 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
782 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
783 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
784 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
785 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
786 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
787 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
788 "TM.getCodeModel() != CodeModel::Kernel">;
789 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
790 "TM.getCodeModel() == CodeModel::Kernel">;
791 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
792 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
793 def OptForSize : Predicate<"OptForSize">;
794 def OptForSpeed : Predicate<"!OptForSize">;
795 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
796 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
797 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
799 //===----------------------------------------------------------------------===//
800 // X86 Instruction Format Definitions.
803 include "X86InstrFormats.td"
805 //===----------------------------------------------------------------------===//
806 // Pattern fragments.
809 // X86 specific condition code. These correspond to CondCode in
810 // X86InstrInfo.h. They must be kept in synch.
811 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
812 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
813 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
814 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
815 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
816 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
817 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
818 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
819 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
820 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
821 def X86_COND_NO : PatLeaf<(i8 10)>;
822 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
823 def X86_COND_NS : PatLeaf<(i8 12)>;
824 def X86_COND_O : PatLeaf<(i8 13)>;
825 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
826 def X86_COND_S : PatLeaf<(i8 15)>;
828 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
829 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
830 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
831 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
834 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
837 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
839 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
841 def i64immZExt32SExt8 : ImmLeaf<i64, [{
842 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
845 // Helper fragments for loads.
846 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
847 // known to be 32-bit aligned or better. Ditto for i8 to i16.
848 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
849 LoadSDNode *LD = cast<LoadSDNode>(N);
850 ISD::LoadExtType ExtType = LD->getExtensionType();
851 if (ExtType == ISD::NON_EXTLOAD)
853 if (ExtType == ISD::EXTLOAD)
854 return LD->getAlignment() >= 2 && !LD->isVolatile();
858 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
859 LoadSDNode *LD = cast<LoadSDNode>(N);
860 ISD::LoadExtType ExtType = LD->getExtensionType();
861 if (ExtType == ISD::EXTLOAD)
862 return LD->getAlignment() >= 2 && !LD->isVolatile();
866 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
867 LoadSDNode *LD = cast<LoadSDNode>(N);
868 ISD::LoadExtType ExtType = LD->getExtensionType();
869 if (ExtType == ISD::NON_EXTLOAD)
871 if (ExtType == ISD::EXTLOAD)
872 return LD->getAlignment() >= 4 && !LD->isVolatile();
876 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
877 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
878 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
879 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
880 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
882 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
883 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
884 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
885 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
886 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
887 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
889 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
890 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
891 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
892 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
893 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
894 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
895 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
896 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
897 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
898 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
900 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
901 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
902 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
903 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
904 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
905 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
906 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
907 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
908 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
909 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
912 // An 'and' node with a single use.
913 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
914 return N->hasOneUse();
916 // An 'srl' node with a single use.
917 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
918 return N->hasOneUse();
920 // An 'trunc' node with a single use.
921 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
922 return N->hasOneUse();
925 //===----------------------------------------------------------------------===//
930 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
931 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
932 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
933 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
934 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
935 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
939 // Constructing a stack frame.
940 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
941 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
943 let SchedRW = [WriteALU] in {
944 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
945 def LEAVE : I<0xC9, RawFrm,
946 (outs), (ins), "leave", [], IIC_LEAVE>,
947 Requires<[Not64BitMode]>;
949 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
950 def LEAVE64 : I<0xC9, RawFrm,
951 (outs), (ins), "leave", [], IIC_LEAVE>,
952 Requires<[In64BitMode]>;
955 //===----------------------------------------------------------------------===//
956 // Miscellaneous Instructions.
959 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
960 let mayLoad = 1, SchedRW = [WriteLoad] in {
961 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
962 IIC_POP_REG16>, OpSize16;
963 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
964 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
965 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
966 IIC_POP_REG>, OpSize16;
967 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
968 IIC_POP_MEM>, OpSize16;
969 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
970 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
971 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
972 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
974 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
976 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
977 OpSize32, Requires<[Not64BitMode]>;
978 } // mayLoad, SchedRW
980 let mayStore = 1, SchedRW = [WriteStore] in {
981 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
982 IIC_PUSH_REG>, OpSize16;
983 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
984 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
985 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
986 IIC_PUSH_REG>, OpSize16;
987 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
988 IIC_PUSH_MEM>, OpSize16;
989 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
990 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
991 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
992 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
994 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
995 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
996 Requires<[Not64BitMode]>;
997 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
998 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
999 Requires<[Not64BitMode]>;
1000 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1001 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1002 Requires<[Not64BitMode]>;
1003 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1004 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1005 Requires<[Not64BitMode]>;
1007 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1009 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1010 OpSize32, Requires<[Not64BitMode]>;
1012 } // mayStore, SchedRW
1015 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
1016 let mayLoad = 1, SchedRW = [WriteLoad] in {
1017 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1018 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1019 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1020 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1021 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1022 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1023 } // mayLoad, SchedRW
1024 let mayStore = 1, SchedRW = [WriteStore] in {
1025 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1026 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1027 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1028 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1029 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1030 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1031 } // mayStore, SchedRW
1034 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
1035 SchedRW = [WriteStore] in {
1036 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1037 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1038 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1039 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1040 Requires<[In64BitMode]>;
1041 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1042 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1043 Requires<[In64BitMode]>;
1046 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
1047 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1048 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1049 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
1050 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1051 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1053 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1054 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
1055 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1056 OpSize32, Requires<[Not64BitMode]>;
1057 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1058 OpSize16, Requires<[Not64BitMode]>;
1060 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1061 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
1062 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1063 OpSize32, Requires<[Not64BitMode]>;
1064 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1065 OpSize16, Requires<[Not64BitMode]>;
1068 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1069 // GR32 = bswap GR32
1070 def BSWAP32r : I<0xC8, AddRegFrm,
1071 (outs GR32:$dst), (ins GR32:$src),
1073 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1075 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1077 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1078 } // Constraints = "$src = $dst", SchedRW
1080 // Bit scan instructions.
1081 let Defs = [EFLAGS] in {
1082 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1083 "bsf{w}\t{$src, $dst|$dst, $src}",
1084 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1085 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1086 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1087 "bsf{w}\t{$src, $dst|$dst, $src}",
1088 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1089 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1090 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1091 "bsf{l}\t{$src, $dst|$dst, $src}",
1092 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1093 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1094 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1095 "bsf{l}\t{$src, $dst|$dst, $src}",
1096 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1097 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1098 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1099 "bsf{q}\t{$src, $dst|$dst, $src}",
1100 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1101 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1102 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1103 "bsf{q}\t{$src, $dst|$dst, $src}",
1104 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1105 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1107 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1108 "bsr{w}\t{$src, $dst|$dst, $src}",
1109 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1110 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1111 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1112 "bsr{w}\t{$src, $dst|$dst, $src}",
1113 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1114 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1115 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1116 "bsr{l}\t{$src, $dst|$dst, $src}",
1117 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1118 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1119 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1120 "bsr{l}\t{$src, $dst|$dst, $src}",
1121 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1122 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1123 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1124 "bsr{q}\t{$src, $dst|$dst, $src}",
1125 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1126 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1127 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1128 "bsr{q}\t{$src, $dst|$dst, $src}",
1129 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1130 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1131 } // Defs = [EFLAGS]
1133 let SchedRW = [WriteMicrocoded] in {
1134 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1135 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1136 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1137 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1138 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1139 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1140 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1141 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1142 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1143 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1146 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1147 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1148 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1149 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1150 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1151 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1152 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1153 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1154 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1155 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1156 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1157 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1158 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1160 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1161 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1162 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1163 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1164 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1165 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1166 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1167 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1168 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1169 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1170 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1171 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1172 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1174 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1175 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1176 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1177 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1178 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1179 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1180 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1181 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1182 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1183 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1187 //===----------------------------------------------------------------------===//
1188 // Move Instructions.
1190 let SchedRW = [WriteMove] in {
1191 let neverHasSideEffects = 1 in {
1192 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1193 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1194 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1195 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1196 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1197 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1198 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1199 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1202 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1203 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1204 "mov{b}\t{$src, $dst|$dst, $src}",
1205 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1206 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1207 "mov{w}\t{$src, $dst|$dst, $src}",
1208 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1209 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1210 "mov{l}\t{$src, $dst|$dst, $src}",
1211 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1212 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1213 "mov{q}\t{$src, $dst|$dst, $src}",
1214 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1216 let isReMaterializable = 1 in {
1217 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1218 "movabs{q}\t{$src, $dst|$dst, $src}",
1219 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1222 // Longer forms that use a ModR/M byte. Needed for disassembler
1223 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1224 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1225 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1226 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1227 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1228 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1229 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1233 let SchedRW = [WriteStore] in {
1234 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1235 "mov{b}\t{$src, $dst|$dst, $src}",
1236 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1237 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1238 "mov{w}\t{$src, $dst|$dst, $src}",
1239 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1240 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1241 "mov{l}\t{$src, $dst|$dst, $src}",
1242 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1243 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1244 "mov{q}\t{$src, $dst|$dst, $src}",
1245 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1248 let hasSideEffects = 0 in {
1250 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1251 /// 32-bit offset from the segment base. These are only valid in x86-32 mode.
1252 let SchedRW = [WriteALU] in {
1253 let mayLoad = 1 in {
1255 def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1256 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1257 Requires<[In32BitMode]>;
1259 def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1260 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1261 OpSize16, Requires<[In32BitMode]>;
1263 def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1264 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1265 OpSize32, Requires<[In32BitMode]>;
1268 def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1269 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1270 AdSize, Requires<[In16BitMode]>;
1272 def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1273 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1274 OpSize16, AdSize, Requires<[In16BitMode]>;
1276 def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1277 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1278 AdSize, OpSize32, Requires<[In16BitMode]>;
1280 let mayStore = 1 in {
1282 def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1283 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1284 Requires<[In32BitMode]>;
1286 def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1287 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1288 OpSize16, Requires<[In32BitMode]>;
1290 def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1291 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1292 OpSize32, Requires<[In32BitMode]>;
1295 def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1296 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1297 AdSize, Requires<[In16BitMode]>;
1299 def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1300 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1301 OpSize16, AdSize, Requires<[In16BitMode]>;
1303 def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1304 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1305 OpSize32, AdSize, Requires<[In16BitMode]>;
1309 // These forms all have full 64-bit absolute addresses in their instructions
1310 // and use the movabs mnemonic to indicate this specific form.
1311 let mayLoad = 1 in {
1313 def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1314 "movabs{b}\t{$src, %al|al, $src}", []>,
1315 Requires<[In64BitMode]>;
1317 def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1318 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
1319 Requires<[In64BitMode]>;
1321 def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1322 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1323 Requires<[In64BitMode]>;
1325 def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
1326 "movabs{q}\t{$src, %rax|rax, $src}", []>,
1327 Requires<[In64BitMode]>;
1330 let mayStore = 1 in {
1332 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1333 "movabs{b}\t{%al, $dst|$dst, al}", []>,
1334 Requires<[In64BitMode]>;
1336 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1337 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
1338 Requires<[In64BitMode]>;
1340 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1341 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1342 Requires<[In64BitMode]>;
1344 def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
1345 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1346 Requires<[In64BitMode]>;
1348 } // hasSideEffects = 0
1350 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1351 SchedRW = [WriteMove] in {
1352 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1353 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1354 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1355 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1356 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1357 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1358 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1359 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1362 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1363 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1364 "mov{b}\t{$src, $dst|$dst, $src}",
1365 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1366 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1367 "mov{w}\t{$src, $dst|$dst, $src}",
1368 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1369 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1370 "mov{l}\t{$src, $dst|$dst, $src}",
1371 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1372 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1373 "mov{q}\t{$src, $dst|$dst, $src}",
1374 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1377 let SchedRW = [WriteStore] in {
1378 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1379 "mov{b}\t{$src, $dst|$dst, $src}",
1380 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1381 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1382 "mov{w}\t{$src, $dst|$dst, $src}",
1383 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1384 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1385 "mov{l}\t{$src, $dst|$dst, $src}",
1386 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1387 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1388 "mov{q}\t{$src, $dst|$dst, $src}",
1389 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1392 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1393 // that they can be used for copying and storing h registers, which can't be
1394 // encoded when a REX prefix is present.
1395 let isCodeGenOnly = 1 in {
1396 let neverHasSideEffects = 1 in
1397 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1398 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1399 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1401 let mayStore = 1, neverHasSideEffects = 1 in
1402 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1403 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1404 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1405 IIC_MOV_MEM>, Sched<[WriteStore]>;
1406 let mayLoad = 1, neverHasSideEffects = 1,
1407 canFoldAsLoad = 1, isReMaterializable = 1 in
1408 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1409 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1410 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1411 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1415 // Condition code ops, incl. set if equal/not equal/...
1416 let SchedRW = [WriteALU] in {
1417 let Defs = [EFLAGS], Uses = [AH] in
1418 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1419 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1420 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1421 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1422 IIC_AHF>; // AH = flags
1425 //===----------------------------------------------------------------------===//
1426 // Bit tests instructions: BT, BTS, BTR, BTC.
1428 let Defs = [EFLAGS] in {
1429 let SchedRW = [WriteALU] in {
1430 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1431 "bt{w}\t{$src2, $src1|$src1, $src2}",
1432 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1434 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1435 "bt{l}\t{$src2, $src1|$src1, $src2}",
1436 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1438 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1439 "bt{q}\t{$src2, $src1|$src1, $src2}",
1440 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1443 // Unlike with the register+register form, the memory+register form of the
1444 // bt instruction does not ignore the high bits of the index. From ISel's
1445 // perspective, this is pretty bizarre. Make these instructions disassembly
1448 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1449 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1450 "bt{w}\t{$src2, $src1|$src1, $src2}",
1451 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1452 // (implicit EFLAGS)]
1454 >, OpSize16, TB, Requires<[FastBTMem]>;
1455 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1456 "bt{l}\t{$src2, $src1|$src1, $src2}",
1457 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1458 // (implicit EFLAGS)]
1460 >, OpSize32, TB, Requires<[FastBTMem]>;
1461 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1462 "bt{q}\t{$src2, $src1|$src1, $src2}",
1463 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1464 // (implicit EFLAGS)]
1469 let SchedRW = [WriteALU] in {
1470 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1471 "bt{w}\t{$src2, $src1|$src1, $src2}",
1472 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1473 IIC_BT_RI>, OpSize16, TB;
1474 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1475 "bt{l}\t{$src2, $src1|$src1, $src2}",
1476 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1477 IIC_BT_RI>, OpSize32, TB;
1478 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1479 "bt{q}\t{$src2, $src1|$src1, $src2}",
1480 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1484 // Note that these instructions don't need FastBTMem because that
1485 // only applies when the other operand is in a register. When it's
1486 // an immediate, bt is still fast.
1487 let SchedRW = [WriteALU] in {
1488 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1489 "bt{w}\t{$src2, $src1|$src1, $src2}",
1490 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1491 ], IIC_BT_MI>, OpSize16, TB;
1492 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1493 "bt{l}\t{$src2, $src1|$src1, $src2}",
1494 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1495 ], IIC_BT_MI>, OpSize32, TB;
1496 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1497 "bt{q}\t{$src2, $src1|$src1, $src2}",
1498 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1499 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1502 let hasSideEffects = 0 in {
1503 let SchedRW = [WriteALU] in {
1504 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1505 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1507 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1508 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1510 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1511 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1514 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1515 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1516 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1518 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1519 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1521 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1522 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1525 let SchedRW = [WriteALU] in {
1526 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1527 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1529 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1530 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1532 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1533 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1536 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1537 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1538 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1540 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1541 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1543 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1544 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1547 let SchedRW = [WriteALU] in {
1548 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1549 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1551 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1552 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1554 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1555 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1558 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1559 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1560 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1562 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1563 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1565 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1566 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1569 let SchedRW = [WriteALU] in {
1570 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1571 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1573 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1574 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1576 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1577 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1580 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1581 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1582 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1584 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1585 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1587 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1588 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1591 let SchedRW = [WriteALU] in {
1592 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1593 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1595 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1596 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1598 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1599 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1602 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1603 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1604 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1606 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1607 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1609 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1610 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1613 let SchedRW = [WriteALU] in {
1614 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1615 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1617 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1618 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1620 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1621 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1624 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1625 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1626 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1628 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1629 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1631 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1632 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1634 } // hasSideEffects = 0
1635 } // Defs = [EFLAGS]
1638 //===----------------------------------------------------------------------===//
1642 // Atomic swap. These are just normal xchg instructions. But since a memory
1643 // operand is referenced, the atomicity is ensured.
1644 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1645 InstrItinClass itin> {
1646 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1647 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1648 (ins GR8:$val, i8mem:$ptr),
1649 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1652 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1654 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1655 (ins GR16:$val, i16mem:$ptr),
1656 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1659 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1661 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1662 (ins GR32:$val, i32mem:$ptr),
1663 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1666 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1668 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1669 (ins GR64:$val, i64mem:$ptr),
1670 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1673 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1678 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1680 // Swap between registers.
1681 let SchedRW = [WriteALU] in {
1682 let Constraints = "$val = $dst" in {
1683 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1684 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1685 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1686 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1688 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1689 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1691 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1692 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1695 // Swap between EAX and other registers.
1696 let Uses = [AX], Defs = [AX] in
1697 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1698 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1699 let Uses = [EAX], Defs = [EAX] in
1700 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1701 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1702 OpSize32, Requires<[Not64BitMode]>;
1703 let Uses = [EAX], Defs = [EAX] in
1704 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1705 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1706 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1707 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1708 OpSize32, Requires<[In64BitMode]>;
1709 let Uses = [RAX], Defs = [RAX] in
1710 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1711 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1714 let SchedRW = [WriteALU] in {
1715 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1716 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1717 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1718 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1720 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1721 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1723 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1724 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1727 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1728 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1729 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1730 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1731 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1733 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1734 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1736 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1737 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1741 let SchedRW = [WriteALU] in {
1742 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1743 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1744 IIC_CMPXCHG_REG8>, TB;
1745 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1746 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1747 IIC_CMPXCHG_REG>, TB, OpSize16;
1748 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1749 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1750 IIC_CMPXCHG_REG>, TB, OpSize32;
1751 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1752 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1753 IIC_CMPXCHG_REG>, TB;
1756 let SchedRW = [WriteALULd, WriteRMW] in {
1757 let mayLoad = 1, mayStore = 1 in {
1758 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1759 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1760 IIC_CMPXCHG_MEM8>, TB;
1761 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1762 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1763 IIC_CMPXCHG_MEM>, TB, OpSize16;
1764 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1765 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1766 IIC_CMPXCHG_MEM>, TB, OpSize32;
1767 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1768 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1769 IIC_CMPXCHG_MEM>, TB;
1772 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1773 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1774 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1776 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1777 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1778 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1779 TB, Requires<[HasCmpxchg16b]>;
1783 // Lock instruction prefix
1784 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1786 // Rex64 instruction prefix
1787 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1788 Requires<[In64BitMode]>;
1790 // Data16 instruction prefix
1791 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1793 // Repeat string operation instruction prefixes
1794 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1795 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1796 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1797 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1798 // Repeat while not equal (used with CMPS and SCAS)
1799 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1803 // String manipulation instructions
1804 let SchedRW = [WriteMicrocoded] in {
1805 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1806 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1807 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1808 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1809 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1810 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1811 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1812 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1813 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1814 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1815 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1816 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1817 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1820 let SchedRW = [WriteSystem] in {
1821 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1822 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1823 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1824 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1825 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1826 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1827 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1828 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1831 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1832 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1833 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1834 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1835 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1836 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1837 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1838 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1842 // Flag instructions
1843 let SchedRW = [WriteALU] in {
1844 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1845 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1846 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1847 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1848 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1849 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1850 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1852 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1855 // Table lookup instructions
1856 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1859 let SchedRW = [WriteMicrocoded] in {
1860 // ASCII Adjust After Addition
1861 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1862 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1863 Requires<[Not64BitMode]>;
1865 // ASCII Adjust AX Before Division
1866 // sets AL, AH and EFLAGS and uses AL and AH
1867 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1868 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1870 // ASCII Adjust AX After Multiply
1871 // sets AL, AH and EFLAGS and uses AL
1872 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1873 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1875 // ASCII Adjust AL After Subtraction - sets
1876 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1877 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1878 Requires<[Not64BitMode]>;
1880 // Decimal Adjust AL after Addition
1881 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1882 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1883 Requires<[Not64BitMode]>;
1885 // Decimal Adjust AL after Subtraction
1886 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1887 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1888 Requires<[Not64BitMode]>;
1891 let SchedRW = [WriteSystem] in {
1892 // Check Array Index Against Bounds
1893 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1894 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1895 Requires<[Not64BitMode]>;
1896 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1897 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1898 Requires<[Not64BitMode]>;
1900 // Adjust RPL Field of Segment Selector
1901 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1902 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1903 Requires<[Not64BitMode]>;
1904 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1905 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1906 Requires<[Not64BitMode]>;
1909 //===----------------------------------------------------------------------===//
1910 // MOVBE Instructions
1912 let Predicates = [HasMOVBE] in {
1913 let SchedRW = [WriteALULd] in {
1914 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1915 "movbe{w}\t{$src, $dst|$dst, $src}",
1916 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1918 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1919 "movbe{l}\t{$src, $dst|$dst, $src}",
1920 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1922 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1923 "movbe{q}\t{$src, $dst|$dst, $src}",
1924 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1927 let SchedRW = [WriteStore] in {
1928 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1929 "movbe{w}\t{$src, $dst|$dst, $src}",
1930 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1932 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1933 "movbe{l}\t{$src, $dst|$dst, $src}",
1934 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1936 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1937 "movbe{q}\t{$src, $dst|$dst, $src}",
1938 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1943 //===----------------------------------------------------------------------===//
1944 // RDRAND Instruction
1946 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1947 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1949 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1950 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1952 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1953 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1955 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1958 //===----------------------------------------------------------------------===//
1959 // RDSEED Instruction
1961 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1962 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1964 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1965 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1967 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
1968 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1970 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1973 //===----------------------------------------------------------------------===//
1974 // LZCNT Instruction
1976 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1977 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1978 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1979 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1981 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1982 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1983 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1984 (implicit EFLAGS)]>, XS, OpSize16;
1986 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1987 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1988 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1990 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1991 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1992 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1993 (implicit EFLAGS)]>, XS, OpSize32;
1995 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1996 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1997 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1999 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2000 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2001 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2002 (implicit EFLAGS)]>, XS;
2005 let Predicates = [HasLZCNT] in {
2006 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E),
2007 (X86cmp GR16:$src, (i16 0))),
2008 (LZCNT16rr GR16:$src)>;
2009 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E),
2010 (X86cmp GR32:$src, (i32 0))),
2011 (LZCNT32rr GR32:$src)>;
2012 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E),
2013 (X86cmp GR64:$src, (i64 0))),
2014 (LZCNT64rr GR64:$src)>;
2015 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E),
2016 (X86cmp GR16:$src, (i16 0))),
2017 (LZCNT16rr GR16:$src)>;
2018 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E),
2019 (X86cmp GR32:$src, (i32 0))),
2020 (LZCNT32rr GR32:$src)>;
2021 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E),
2022 (X86cmp GR64:$src, (i64 0))),
2023 (LZCNT64rr GR64:$src)>;
2025 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E),
2026 (X86cmp (loadi16 addr:$src), (i16 0))),
2027 (LZCNT16rm addr:$src)>;
2028 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E),
2029 (X86cmp (loadi32 addr:$src), (i32 0))),
2030 (LZCNT32rm addr:$src)>;
2031 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E),
2032 (X86cmp (loadi64 addr:$src), (i64 0))),
2033 (LZCNT64rm addr:$src)>;
2034 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E),
2035 (X86cmp (loadi16 addr:$src), (i16 0))),
2036 (LZCNT16rm addr:$src)>;
2037 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E),
2038 (X86cmp (loadi32 addr:$src), (i32 0))),
2039 (LZCNT32rm addr:$src)>;
2040 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E),
2041 (X86cmp (loadi64 addr:$src), (i64 0))),
2042 (LZCNT64rm addr:$src)>;
2045 //===----------------------------------------------------------------------===//
2048 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2049 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2050 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2051 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2053 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2054 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2055 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2056 (implicit EFLAGS)]>, XS, OpSize16;
2058 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2059 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2060 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2062 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2063 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2064 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2065 (implicit EFLAGS)]>, XS, OpSize32;
2067 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2068 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2069 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2071 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2072 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2073 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2074 (implicit EFLAGS)]>, XS;
2077 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2078 RegisterClass RC, X86MemOperand x86memop> {
2079 let hasSideEffects = 0 in {
2080 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2081 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2084 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2085 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2090 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2091 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2092 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2093 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2094 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2095 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2096 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2099 //===----------------------------------------------------------------------===//
2100 // Pattern fragments to auto generate BMI instructions.
2101 //===----------------------------------------------------------------------===//
2103 let Predicates = [HasBMI] in {
2104 // FIXME: patterns for the load versions are not implemented
2105 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2106 (BLSR32rr GR32:$src)>;
2107 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2108 (BLSR64rr GR64:$src)>;
2110 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2111 (BLSMSK32rr GR32:$src)>;
2112 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2113 (BLSMSK64rr GR64:$src)>;
2115 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2116 (BLSI32rr GR32:$src)>;
2117 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2118 (BLSI64rr GR64:$src)>;
2121 let Predicates = [HasBMI] in {
2122 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E),
2123 (X86cmp GR16:$src, (i16 0))),
2124 (TZCNT16rr GR16:$src)>;
2125 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E),
2126 (X86cmp GR32:$src, (i32 0))),
2127 (TZCNT32rr GR32:$src)>;
2128 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E),
2129 (X86cmp GR64:$src, (i64 0))),
2130 (TZCNT64rr GR64:$src)>;
2131 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E),
2132 (X86cmp GR16:$src, (i16 0))),
2133 (TZCNT16rr GR16:$src)>;
2134 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E),
2135 (X86cmp GR32:$src, (i32 0))),
2136 (TZCNT32rr GR32:$src)>;
2137 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E),
2138 (X86cmp GR64:$src, (i64 0))),
2139 (TZCNT64rr GR64:$src)>;
2141 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E),
2142 (X86cmp (loadi16 addr:$src), (i16 0))),
2143 (TZCNT16rm addr:$src)>;
2144 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E),
2145 (X86cmp (loadi32 addr:$src), (i32 0))),
2146 (TZCNT32rm addr:$src)>;
2147 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E),
2148 (X86cmp (loadi64 addr:$src), (i64 0))),
2149 (TZCNT64rm addr:$src)>;
2150 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E),
2151 (X86cmp (loadi16 addr:$src), (i16 0))),
2152 (TZCNT16rm addr:$src)>;
2153 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E),
2154 (X86cmp (loadi32 addr:$src), (i32 0))),
2155 (TZCNT32rm addr:$src)>;
2156 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E),
2157 (X86cmp (loadi64 addr:$src), (i64 0))),
2158 (TZCNT64rm addr:$src)>;
2162 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2163 X86MemOperand x86memop, Intrinsic Int,
2165 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2166 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2167 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2169 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2170 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2171 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2172 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2175 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2176 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2177 int_x86_bmi_bextr_32, loadi32>;
2178 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2179 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2182 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2183 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2184 int_x86_bmi_bzhi_32, loadi32>;
2185 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2186 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2190 def CountTrailingOnes : SDNodeXForm<imm, [{
2191 // Count the trailing ones in the immediate.
2192 return getI8Imm(CountTrailingOnes_64(N->getZExtValue()));
2195 def BZHIMask : ImmLeaf<i64, [{
2196 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32);
2199 let Predicates = [HasBMI2] in {
2200 def : Pat<(and GR64:$src, BZHIMask:$mask),
2201 (BZHI64rr GR64:$src,
2202 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2203 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2205 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2206 (BZHI32rr GR32:$src,
2207 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2209 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2210 (BZHI32rm addr:$src,
2211 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2213 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2214 (BZHI64rr GR64:$src,
2215 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2217 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2218 (BZHI64rm addr:$src,
2219 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2222 let Predicates = [HasBMI] in {
2223 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2224 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2225 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2226 (BEXTR32rm addr:$src1, GR32:$src2)>;
2227 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2228 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2229 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2230 (BEXTR64rm addr:$src1, GR64:$src2)>;
2233 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2234 X86MemOperand x86memop, Intrinsic Int,
2236 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2237 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2238 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2240 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2241 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2242 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2245 let Predicates = [HasBMI2] in {
2246 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2247 int_x86_bmi_pdep_32, loadi32>, T8XD;
2248 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2249 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2250 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2251 int_x86_bmi_pext_32, loadi32>, T8XS;
2252 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2253 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2256 //===----------------------------------------------------------------------===//
2259 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2261 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2262 X86MemOperand x86memop, PatFrag ld_frag,
2263 Intrinsic Int, Operand immtype,
2264 SDPatternOperator immoperator> {
2265 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2266 !strconcat(OpcodeStr,
2267 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2268 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2270 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2271 (ins x86memop:$src1, immtype:$cntl),
2272 !strconcat(OpcodeStr,
2273 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2274 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2278 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2279 int_x86_tbm_bextri_u32, i32imm, imm>;
2280 let ImmT = Imm32S in
2281 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2282 int_x86_tbm_bextri_u64, i64i32imm,
2283 i64immSExt32>, VEX_W;
2285 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2286 RegisterClass RC, string OpcodeStr,
2287 X86MemOperand x86memop, PatFrag ld_frag> {
2288 let hasSideEffects = 0 in {
2289 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2290 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2293 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2294 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2299 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2300 Format FormReg, Format FormMem> {
2301 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2303 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2307 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2308 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2309 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2310 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2311 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2312 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2313 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2314 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2315 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2318 //===----------------------------------------------------------------------===//
2319 // Pattern fragments to auto generate TBM instructions.
2320 //===----------------------------------------------------------------------===//
2322 let Predicates = [HasTBM] in {
2323 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2324 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2325 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2326 (BEXTRI32mi addr:$src1, imm:$src2)>;
2327 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2328 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2329 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2330 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2332 // FIXME: patterns for the load versions are not implemented
2333 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2334 (BLCFILL32rr GR32:$src)>;
2335 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2336 (BLCFILL64rr GR64:$src)>;
2338 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2339 (BLCI32rr GR32:$src)>;
2340 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2341 (BLCI64rr GR64:$src)>;
2343 // Extra patterns because opt can optimize the above patterns to this.
2344 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2345 (BLCI32rr GR32:$src)>;
2346 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2347 (BLCI64rr GR64:$src)>;
2349 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2350 (BLCIC32rr GR32:$src)>;
2351 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2352 (BLCIC64rr GR64:$src)>;
2354 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2355 (BLCMSK32rr GR32:$src)>;
2356 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2357 (BLCMSK64rr GR64:$src)>;
2359 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2360 (BLCS32rr GR32:$src)>;
2361 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2362 (BLCS64rr GR64:$src)>;
2364 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2365 (BLSFILL32rr GR32:$src)>;
2366 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2367 (BLSFILL64rr GR64:$src)>;
2369 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2370 (BLSIC32rr GR32:$src)>;
2371 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2372 (BLSIC64rr GR64:$src)>;
2374 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2375 (T1MSKC32rr GR32:$src)>;
2376 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2377 (T1MSKC64rr GR64:$src)>;
2379 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2380 (TZMSK32rr GR32:$src)>;
2381 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2382 (TZMSK64rr GR64:$src)>;
2385 //===----------------------------------------------------------------------===//
2387 //===----------------------------------------------------------------------===//
2389 include "X86InstrArithmetic.td"
2390 include "X86InstrCMovSetCC.td"
2391 include "X86InstrExtension.td"
2392 include "X86InstrControl.td"
2393 include "X86InstrShiftRotate.td"
2395 // X87 Floating Point Stack.
2396 include "X86InstrFPStack.td"
2398 // SIMD support (SSE, MMX and AVX)
2399 include "X86InstrFragmentsSIMD.td"
2401 // FMA - Fused Multiply-Add support (requires FMA)
2402 include "X86InstrFMA.td"
2405 include "X86InstrXOP.td"
2407 // SSE, MMX and 3DNow! vector support.
2408 include "X86InstrSSE.td"
2409 include "X86InstrAVX512.td"
2410 include "X86InstrMMX.td"
2411 include "X86Instr3DNow.td"
2413 include "X86InstrVMX.td"
2414 include "X86InstrSVM.td"
2416 include "X86InstrTSX.td"
2418 // System instructions.
2419 include "X86InstrSystem.td"
2421 // Compiler Pseudo Instructions and Pat Patterns
2422 include "X86InstrCompiler.td"
2424 //===----------------------------------------------------------------------===//
2425 // Assembler Mnemonic Aliases
2426 //===----------------------------------------------------------------------===//
2428 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2429 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2430 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2432 def : MnemonicAlias<"cbw", "cbtw", "att">;
2433 def : MnemonicAlias<"cwde", "cwtl", "att">;
2434 def : MnemonicAlias<"cwd", "cwtd", "att">;
2435 def : MnemonicAlias<"cdq", "cltd", "att">;
2436 def : MnemonicAlias<"cdqe", "cltq", "att">;
2437 def : MnemonicAlias<"cqo", "cqto", "att">;
2439 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2440 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2441 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2443 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2444 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2446 def : MnemonicAlias<"loopz", "loope", "att">;
2447 def : MnemonicAlias<"loopnz", "loopne", "att">;
2449 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2450 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2451 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2452 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2453 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2454 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2455 def : MnemonicAlias<"popfd", "popfl", "att">;
2457 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2458 // all modes. However: "push (addr)" and "push $42" should default to
2459 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2460 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2461 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2462 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2463 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2464 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2465 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2466 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2468 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2469 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2470 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2471 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2472 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2473 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2475 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2476 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2477 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2478 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2480 def : MnemonicAlias<"repe", "rep", "att">;
2481 def : MnemonicAlias<"repz", "rep", "att">;
2482 def : MnemonicAlias<"repnz", "repne", "att">;
2484 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2485 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2486 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2488 def : MnemonicAlias<"salb", "shlb", "att">;
2489 def : MnemonicAlias<"salw", "shlw", "att">;
2490 def : MnemonicAlias<"sall", "shll", "att">;
2491 def : MnemonicAlias<"salq", "shlq", "att">;
2493 def : MnemonicAlias<"smovb", "movsb", "att">;
2494 def : MnemonicAlias<"smovw", "movsw", "att">;
2495 def : MnemonicAlias<"smovl", "movsl", "att">;
2496 def : MnemonicAlias<"smovq", "movsq", "att">;
2498 def : MnemonicAlias<"ud2a", "ud2", "att">;
2499 def : MnemonicAlias<"verrw", "verr", "att">;
2501 // System instruction aliases.
2502 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2503 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2504 def : MnemonicAlias<"sysret", "sysretl", "att">;
2505 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2507 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2508 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2509 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2510 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2511 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2512 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2513 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2514 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2515 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2516 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2517 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2518 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2521 // Floating point stack aliases.
2522 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2523 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2524 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2525 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2526 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2527 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2528 def : MnemonicAlias<"fildq", "fildll", "att">;
2529 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2530 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2531 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2532 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2533 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2534 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2535 def : MnemonicAlias<"fwait", "wait", "att">;
2538 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2540 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2541 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2543 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2544 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2545 /// example "setz" -> "sete".
2546 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2548 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2549 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2550 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2551 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2552 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2553 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2554 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2555 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2556 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2557 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2559 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2560 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2561 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2562 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2565 // Aliases for set<CC>
2566 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2567 // Aliases for j<CC>
2568 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2569 // Aliases for cmov<CC>{w,l,q}
2570 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2571 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2572 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2573 // No size suffix for intel-style asm.
2574 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2577 //===----------------------------------------------------------------------===//
2578 // Assembler Instruction Aliases
2579 //===----------------------------------------------------------------------===//
2581 // aad/aam default to base 10 if no operand is specified.
2582 def : InstAlias<"aad", (AAD8i8 10)>;
2583 def : InstAlias<"aam", (AAM8i8 10)>;
2585 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2586 // Likewise for btc/btr/bts.
2587 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2588 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2589 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2590 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2591 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2592 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2593 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2594 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2597 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2598 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2599 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2600 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2602 // lods aliases. Accept the destination being omitted because it's implicit
2603 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2604 // in the destination.
2605 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2606 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2607 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2608 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2609 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2610 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2611 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2612 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2614 // stos aliases. Accept the source being omitted because it's implicit in
2615 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2617 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2618 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2619 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2620 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2621 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2622 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2623 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2624 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2626 // scas aliases. Accept the destination being omitted because it's implicit
2627 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2628 // in the destination.
2629 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2630 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2631 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2632 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2633 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2634 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2635 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2636 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2638 // div and idiv aliases for explicit A register.
2639 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2640 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2641 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2642 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2643 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2644 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2645 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2646 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2647 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2648 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2649 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2650 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2651 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2652 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2653 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2654 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2658 // Various unary fpstack operations default to operating on on ST1.
2659 // For example, "fxch" -> "fxch %st(1)"
2660 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2661 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2662 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2663 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2664 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2665 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2666 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2667 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2668 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2669 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2670 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2671 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2672 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2673 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2674 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2676 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2677 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2678 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2680 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2681 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2682 (Inst RST:$op), EmitAlias>;
2683 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2684 (Inst ST0), EmitAlias>;
2687 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2688 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2689 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2690 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2691 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2692 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2693 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2694 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2695 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2696 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2697 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2698 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2699 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2700 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2701 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2702 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2705 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2706 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2707 // solely because gas supports it.
2708 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2709 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2710 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2711 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2712 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2713 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2715 // We accept "fnstsw %eax" even though it only writes %ax.
2716 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2717 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2718 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2720 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2721 // this is compatible with what GAS does.
2722 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2723 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2724 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2725 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2726 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2727 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2728 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2729 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2731 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst), 0>, Requires<[In64BitMode]>;
2732 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst), 0>, Requires<[In64BitMode]>;
2733 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst), 0>, Requires<[In32BitMode]>;
2734 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst), 0>, Requires<[In32BitMode]>;
2735 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2736 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2739 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2740 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2741 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2742 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2743 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2744 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2745 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2747 // inb %dx -> inb %al, %dx
2748 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2749 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2750 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2751 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2752 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2753 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2756 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2757 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2758 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2759 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2760 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2761 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2762 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2763 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2764 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2766 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2767 // the move. All segment/mem forms are equivalent, this has the shortest
2769 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2770 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2772 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2773 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2775 // Match 'movq GR64, MMX' as an alias for movd.
2776 def : InstAlias<"movq $src, $dst",
2777 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2778 def : InstAlias<"movq $src, $dst",
2779 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2782 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2783 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2784 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2785 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2786 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2787 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2788 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2791 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2792 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2793 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2794 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2795 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2796 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2797 // Note: No GR32->GR64 movzx form.
2799 // outb %dx -> outb %al, %dx
2800 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2801 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2802 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2803 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2804 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2805 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2807 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2808 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2809 // errors, since its encoding is the most compact.
2810 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2812 // shld/shrd op,op -> shld op, op, CL
2813 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2814 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2815 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2816 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2817 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2818 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2820 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2821 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2822 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2823 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2824 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2825 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2827 /* FIXME: This is disabled because the asm matcher is currently incapable of
2828 * matching a fixed immediate like $1.
2829 // "shl X, $1" is an alias for "shl X".
2830 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2831 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2832 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2833 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2834 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2835 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2836 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2837 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2838 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2839 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2840 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2841 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2842 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2843 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2844 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2845 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2846 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2849 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2850 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2851 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2852 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2855 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2856 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2857 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2858 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2859 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2860 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2861 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2862 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2863 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2865 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2866 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2867 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2868 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2869 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2870 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2871 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2872 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2873 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2875 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2876 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2877 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2878 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2879 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2880 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2881 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;