1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // *mem - Operand definitions for the funky X86 addressing mode operands.
19 class X86MemOperand<ValueType Ty> : Operand<Ty> {
20 let NumMIOperands = 4;
21 let PrintMethod = "printMemoryOperand";
24 def i8mem : X86MemOperand<i8>;
25 def i16mem : X86MemOperand<i16>;
26 def i32mem : X86MemOperand<i32>;
27 def i64mem : X86MemOperand<i64>;
28 def f32mem : X86MemOperand<f32>;
29 def f64mem : X86MemOperand<f64>;
30 def f80mem : X86MemOperand<f80>;
32 // PCRelative calls need special operand formatting.
33 let PrintMethod = "printCallOperand" in
34 def calltarget : Operand<i32>;
36 // Format specifies the encoding used by the instruction. This is part of the
37 // ad-hoc solution used to emit machine instruction encodings by our machine
39 class Format<bits<5> val> {
43 def Pseudo : Format<0>; def RawFrm : Format<1>;
44 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
45 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
46 def MRMSrcMem : Format<6>;
47 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
48 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
49 def MRM6r : Format<22>; def MRM7r : Format<23>;
50 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
51 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
52 def MRM6m : Format<30>; def MRM7m : Format<31>;
54 // ImmType - This specifies the immediate type used by an instruction. This is
55 // part of the ad-hoc solution used to emit machine instruction encodings by our
56 // machine code emitter.
57 class ImmType<bits<2> val> {
60 def NoImm : ImmType<0>;
61 def Imm8 : ImmType<1>;
62 def Imm16 : ImmType<2>;
63 def Imm32 : ImmType<3>;
65 // FPFormat - This specifies what form this FP instruction has. This is used by
66 // the Floating-Point stackifier pass.
67 class FPFormat<bits<3> val> {
70 def NotFP : FPFormat<0>;
71 def ZeroArgFP : FPFormat<1>;
72 def OneArgFP : FPFormat<2>;
73 def OneArgFPRW : FPFormat<3>;
74 def TwoArgFP : FPFormat<4>;
75 def CompareFP : FPFormat<5>;
76 def CondMovFP : FPFormat<6>;
77 def SpecialFP : FPFormat<7>;
80 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
82 let Namespace = "X86";
84 bits<8> Opcode = opcod;
86 bits<5> FormBits = Form.Value;
88 bits<2> ImmTypeBits = ImmT.Value;
90 dag OperandList = ops;
91 string AsmString = AsmStr;
94 // Attributes specific to X86 instructions...
96 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
98 bits<4> Prefix = 0; // Which prefix byte does this inst have?
99 FPFormat FPForm; // What flavor of FP instruction is this?
100 bits<3> FPFormBits = 0;
103 class Imp<list<Register> uses, list<Register> defs> {
104 list<Register> Uses = uses;
105 list<Register> Defs = defs;
109 // Prefix byte classes which are used to indicate to the ad-hoc machine code
110 // emitter that various prefix bytes are required.
111 class OpSize { bit hasOpSizePrefix = 1; }
112 class TB { bits<4> Prefix = 1; }
113 class REP { bits<4> Prefix = 2; }
114 class D8 { bits<4> Prefix = 3; }
115 class D9 { bits<4> Prefix = 4; }
116 class DA { bits<4> Prefix = 5; }
117 class DB { bits<4> Prefix = 6; }
118 class DC { bits<4> Prefix = 7; }
119 class DD { bits<4> Prefix = 8; }
120 class DE { bits<4> Prefix = 9; }
121 class DF { bits<4> Prefix = 10; }
122 class XD { bits<4> Prefix = 11; }
123 class XS { bits<4> Prefix = 12; }
126 //===----------------------------------------------------------------------===//
127 // Instruction templates...
129 class I<bits<8> o, Format f, dag ops, string asm>
130 : X86Inst<o, f, NoImm, ops, asm>;
131 class Ii8 <bits<8> o, Format f, dag ops, string asm>
132 : X86Inst<o, f, Imm8 , ops, asm>;
133 class Ii16<bits<8> o, Format f, dag ops, string asm>
134 : X86Inst<o, f, Imm16, ops, asm>;
135 class Ii32<bits<8> o, Format f, dag ops, string asm>
136 : X86Inst<o, f, Imm32, ops, asm>;
138 //===----------------------------------------------------------------------===//
139 // Instruction list...
142 def PHI : I<0, Pseudo, (ops), "PHINODE">; // PHI node.
143 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
145 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">;
146 def ADJCALLSTACKUP : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">;
147 def IMPLICIT_USE : I<0, Pseudo, (ops), "#IMPLICIT_USE">;
148 def IMPLICIT_DEF : I<0, Pseudo, (ops), "#IMPLICIT_DEF">;
149 let isTerminator = 1 in
150 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
151 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">;
153 //===----------------------------------------------------------------------===//
154 // Control Flow Instructions...
157 // Return instructions.
158 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
159 def RET : I<0xC3, RawFrm, (ops), "ret">;
160 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
161 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt">;
163 // All branches are RawFrm, Void, Branch, and Terminators
164 let isBranch = 1, isTerminator = 1 in
165 class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>;
168 def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
169 def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
170 def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
171 def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
172 def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
173 def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
174 def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
175 def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
176 def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
177 def JP : IBr<0x8A, (ops i32imm:$dst), "jp $dst">, TB;
178 def JNP : IBr<0x8B, (ops i32imm:$dst), "jnp $dst">, TB;
179 def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
180 def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
181 def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
182 def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
185 //===----------------------------------------------------------------------===//
186 // Call Instructions...
189 // All calls clobber the non-callee saved registers...
190 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
191 XMM0, XMM1, XMM2, XMM3] in {
192 def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">;
193 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst">;
194 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst">;
198 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
199 def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL">;
200 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
201 def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL">;
202 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
203 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp {*}$dst # TAIL CALL">;
205 // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
206 // way, except that it is marked as being a terminator. This causes the epilog
207 // inserter to insert reloads of callee saved registers BEFORE this. We need
208 // this until we have a more accurate way of tracking where the stack pointer is
209 // within a function.
210 let isTerminator = 1, isTwoAddress = 1 in
211 def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
212 "add{l} {$src2, $dst|$dst, $src2}">;
214 //===----------------------------------------------------------------------===//
215 // Miscellaneous Instructions...
217 def LEAVE : I<0xC9, RawFrm,
218 (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>;
219 def POP32r : I<0x58, AddRegFrm,
220 (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>;
222 let isTwoAddress = 1 in // R32 = bswap R32
223 def BSWAP32r : I<0xC8, AddRegFrm,
224 (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB;
226 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
227 (ops R8:$src1, R8:$src2),
228 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
229 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
230 (ops R16:$src1, R16:$src2),
231 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
232 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
233 (ops R32:$src1, R32:$src2),
234 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
236 def XCHG8mr : I<0x86, MRMDestMem,
237 (ops i8mem:$src1, R8:$src2),
238 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
239 def XCHG16mr : I<0x87, MRMDestMem,
240 (ops i16mem:$src1, R16:$src2),
241 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
242 def XCHG32mr : I<0x87, MRMDestMem,
243 (ops i32mem:$src1, R32:$src2),
244 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
245 def XCHG8rm : I<0x86, MRMSrcMem,
246 (ops R8:$src1, i8mem:$src2),
247 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
248 def XCHG16rm : I<0x87, MRMSrcMem,
249 (ops R16:$src1, i16mem:$src2),
250 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
251 def XCHG32rm : I<0x87, MRMSrcMem,
252 (ops R32:$src1, i32mem:$src2),
253 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
255 def LEA16r : I<0x8D, MRMSrcMem,
256 (ops R16:$dst, i32mem:$src),
257 "lea{w} {$src|$dst}, {$dst|$src}">, OpSize;
258 def LEA32r : I<0x8D, MRMSrcMem,
259 (ops R32:$dst, i32mem:$src),
260 "lea{l} {$src|$dst}, {$dst|$src}">;
263 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">,
264 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
265 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">,
266 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
267 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">,
268 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
270 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">,
271 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
272 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">,
273 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
274 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}">,
275 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
278 //===----------------------------------------------------------------------===//
279 // Input/Output Instructions...
281 def IN8rr : I<0xEC, RawFrm, (ops),
282 "in{b} {%dx, %al|%AL, %DX}">, Imp<[DX], [AL]>;
283 def IN16rr : I<0xED, RawFrm, (ops),
284 "in{w} {%dx, %ax|%AX, %DX}">, Imp<[DX], [AX]>, OpSize;
285 def IN32rr : I<0xED, RawFrm, (ops),
286 "in{l} {%dx, %eax|%EAX, %DX}">, Imp<[DX],[EAX]>;
288 def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
289 "in{b} {$port, %al|%AL, $port}">, Imp<[], [AL]>;
290 def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
291 "in{w} {$port, %ax|%AX, $port}">, Imp<[], [AX]>, OpSize;
292 def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
293 "in{l} {$port, %eax|%EAX, $port}">, Imp<[],[EAX]>;
295 def OUT8rr : I<0xEE, RawFrm, (ops),
296 "out{b} {%al, %dx|%DX, %AL}">, Imp<[DX, AL], []>;
297 def OUT16rr : I<0xEF, RawFrm, (ops),
298 "out{w} {%ax, %dx|%DX, %AX}">, Imp<[DX, AX], []>, OpSize;
299 def OUT32rr : I<0xEF, RawFrm, (ops),
300 "out{l} {%eax, %dx|%DX, %EAX}">, Imp<[DX, EAX], []>;
302 def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
303 "out{b} {%al, $port|$port, %AL}">, Imp<[AL], []>;
304 def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
305 "out{w} {%ax, $port|$port, %AX}">, Imp<[AX], []>, OpSize;
306 def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
307 "out{l} {%eax, $port|$port, %EAX}">, Imp<[EAX], []>;
309 //===----------------------------------------------------------------------===//
310 // Move Instructions...
312 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src),
313 "mov{b} {$src, $dst|$dst, $src}">;
314 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src),
315 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
316 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
317 "mov{l} {$src, $dst|$dst, $src}">;
318 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
319 "mov{b} {$src, $dst|$dst, $src}">;
320 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
321 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
322 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
323 "mov{l} {$src, $dst|$dst, $src}">;
324 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
325 "mov{b} {$src, $dst|$dst, $src}">;
326 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
327 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
328 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
329 "mov{l} {$src, $dst|$dst, $src}">;
331 def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
332 "mov{b} {$src, $dst|$dst, $src}">;
333 def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
334 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
335 def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
336 "mov{l} {$src, $dst|$dst, $src}">;
338 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
339 "mov{b} {$src, $dst|$dst, $src}">;
340 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
341 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
342 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
343 "mov{l} {$src, $dst|$dst, $src}">;
345 //===----------------------------------------------------------------------===//
346 // Fixed-Register Multiplication and Division Instructions...
349 // Extra precision multiplication
350 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">,
351 Imp<[AL],[AX]>; // AL,AH = AL*R8
352 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">,
353 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
354 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">,
355 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
356 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
357 "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
358 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
359 "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
360 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
361 "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
363 def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src">,
364 Imp<[AL],[AX]>; // AL,AH = AL*R8
365 def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src">,
366 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
367 def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src">,
368 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
369 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
370 "imul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
371 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
372 "imul{w} $src">, Imp<[AX],[AX,DX]>, OpSize;// AX,DX = AX*[mem16]
373 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
374 "imul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
376 // unsigned division/remainder
377 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH
378 "div{b} $src">, Imp<[AX],[AX]>;
379 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX
380 "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
381 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
382 "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
383 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
384 "div{b} $src">, Imp<[AX],[AX]>;
385 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
386 "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
387 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
388 "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
390 // Signed division/remainder.
391 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH
392 "idiv{b} $src">, Imp<[AX],[AX]>;
393 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX
394 "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
395 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
396 "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
397 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
398 "idiv{b} $src">, Imp<[AX],[AX]>;
399 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
400 "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
401 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
402 "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
404 // Sign-extenders for division.
405 def CBW : I<0x98, RawFrm, (ops),
406 "{cbtw|cbw}">, Imp<[AL],[AH]>; // AX = signext(AL)
407 def CWD : I<0x99, RawFrm, (ops),
408 "{cwtd|cwd}">, Imp<[AX],[DX]>; // DX:AX = signext(AX)
409 def CDQ : I<0x99, RawFrm, (ops),
410 "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
413 //===----------------------------------------------------------------------===//
414 // Two address Instructions...
416 let isTwoAddress = 1 in {
419 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16
420 (ops R16:$dst, R16:$src1, R16:$src2),
421 "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
422 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16]
423 (ops R16:$dst, R16:$src1, i16mem:$src2),
424 "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
425 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32
426 (ops R32:$dst, R32:$src1, R32:$src2),
427 "cmovb {$src2, $dst|$dst, $src2}">, TB;
428 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32]
429 (ops R32:$dst, R32:$src1, i32mem:$src2),
430 "cmovb {$src2, $dst|$dst, $src2}">, TB;
432 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16
433 (ops R16:$dst, R16:$src1, R16:$src2),
434 "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
435 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16]
436 (ops R16:$dst, R16:$src1, i16mem:$src2),
437 "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
438 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32
439 (ops R32:$dst, R32:$src1, R32:$src2),
440 "cmovae {$src2, $dst|$dst, $src2}">, TB;
441 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32]
442 (ops R32:$dst, R32:$src1, i32mem:$src2),
443 "cmovae {$src2, $dst|$dst, $src2}">, TB;
445 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16
446 (ops R16:$dst, R16:$src1, R16:$src2),
447 "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
448 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16]
449 (ops R16:$dst, R16:$src1, i16mem:$src2),
450 "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
451 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32
452 (ops R32:$dst, R32:$src1, R32:$src2),
453 "cmove {$src2, $dst|$dst, $src2}">, TB;
454 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32]
455 (ops R32:$dst, R32:$src1, i32mem:$src2),
456 "cmove {$src2, $dst|$dst, $src2}">, TB;
458 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16
459 (ops R16:$dst, R16:$src1, R16:$src2),
460 "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
461 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16]
462 (ops R16:$dst, R16:$src1, i16mem:$src2),
463 "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
464 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32
465 (ops R32:$dst, R32:$src1, R32:$src2),
466 "cmovne {$src2, $dst|$dst, $src2}">, TB;
467 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32]
468 (ops R32:$dst, R32:$src1, i32mem:$src2),
469 "cmovne {$src2, $dst|$dst, $src2}">, TB;
471 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16
472 (ops R16:$dst, R16:$src1, R16:$src2),
473 "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
474 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16]
475 (ops R16:$dst, R16:$src1, i16mem:$src2),
476 "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
477 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32
478 (ops R32:$dst, R32:$src1, R32:$src2),
479 "cmovbe {$src2, $dst|$dst, $src2}">, TB;
480 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32]
481 (ops R32:$dst, R32:$src1, i32mem:$src2),
482 "cmovbe {$src2, $dst|$dst, $src2}">, TB;
484 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16
485 (ops R16:$dst, R16:$src1, R16:$src2),
486 "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
487 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16]
488 (ops R16:$dst, R16:$src1, i16mem:$src2),
489 "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
490 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32
491 (ops R32:$dst, R32:$src1, R32:$src2),
492 "cmova {$src2, $dst|$dst, $src2}">, TB;
493 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32]
494 (ops R32:$dst, R32:$src1, i32mem:$src2),
495 "cmova {$src2, $dst|$dst, $src2}">, TB;
497 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16
498 (ops R16:$dst, R16:$src1, R16:$src2),
499 "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
500 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16]
501 (ops R16:$dst, R16:$src1, i16mem:$src2),
502 "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
503 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32
504 (ops R32:$dst, R32:$src1, R32:$src2),
505 "cmovs {$src2, $dst|$dst, $src2}">, TB;
506 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32]
507 (ops R32:$dst, R32:$src1, i32mem:$src2),
508 "cmovs {$src2, $dst|$dst, $src2}">, TB;
510 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16
511 (ops R16:$dst, R16:$src1, R16:$src2),
512 "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
513 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16]
514 (ops R16:$dst, R16:$src1, i16mem:$src2),
515 "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
516 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32
517 (ops R32:$dst, R32:$src1, R32:$src2),
518 "cmovns {$src2, $dst|$dst, $src2}">, TB;
519 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32]
520 (ops R32:$dst, R32:$src1, i32mem:$src2),
521 "cmovns {$src2, $dst|$dst, $src2}">, TB;
523 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16
524 (ops R16:$dst, R16:$src1, R16:$src2),
525 "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize;
526 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16]
527 (ops R16:$dst, R16:$src1, i16mem:$src2),
528 "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize;
529 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32
530 (ops R32:$dst, R32:$src1, R32:$src2),
531 "cmovp {$src2, $dst|$dst, $src2}">, TB;
532 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32]
533 (ops R32:$dst, R32:$src1, i32mem:$src2),
534 "cmovp {$src2, $dst|$dst, $src2}">, TB;
537 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16
538 (ops R16:$dst, R16:$src1, R16:$src2),
539 "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize;
540 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16]
541 (ops R16:$dst, R16:$src1, i16mem:$src2),
542 "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize;
543 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32
544 (ops R32:$dst, R32:$src1, R32:$src2),
545 "cmovnp {$src2, $dst|$dst, $src2}">, TB;
546 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32]
547 (ops R32:$dst, R32:$src1, i32mem:$src2),
548 "cmovnp {$src2, $dst|$dst, $src2}">, TB;
551 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16
552 (ops R16:$dst, R16:$src1, R16:$src2),
553 "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
554 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16]
555 (ops R16:$dst, R16:$src1, i16mem:$src2),
556 "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
557 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32
558 (ops R32:$dst, R32:$src1, R32:$src2),
559 "cmovl {$src2, $dst|$dst, $src2}">, TB;
560 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32]
561 (ops R32:$dst, R32:$src1, i32mem:$src2),
562 "cmovl {$src2, $dst|$dst, $src2}">, TB;
564 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16
565 (ops R16:$dst, R16:$src1, R16:$src2),
566 "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
567 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16]
568 (ops R16:$dst, R16:$src1, i16mem:$src2),
569 "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
570 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32
571 (ops R32:$dst, R32:$src1, R32:$src2),
572 "cmovge {$src2, $dst|$dst, $src2}">, TB;
573 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32]
574 (ops R32:$dst, R32:$src1, i32mem:$src2),
575 "cmovge {$src2, $dst|$dst, $src2}">, TB;
577 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16
578 (ops R16:$dst, R16:$src1, R16:$src2),
579 "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
580 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16]
581 (ops R16:$dst, R16:$src1, i16mem:$src2),
582 "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
583 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32
584 (ops R32:$dst, R32:$src1, R32:$src2),
585 "cmovle {$src2, $dst|$dst, $src2}">, TB;
586 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32]
587 (ops R32:$dst, R32:$src1, i32mem:$src2),
588 "cmovle {$src2, $dst|$dst, $src2}">, TB;
590 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16
591 (ops R16:$dst, R16:$src1, R16:$src2),
592 "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
593 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16]
594 (ops R16:$dst, R16:$src1, i16mem:$src2),
595 "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
596 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32
597 (ops R32:$dst, R32:$src1, R32:$src2),
598 "cmovg {$src2, $dst|$dst, $src2}">, TB;
599 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32]
600 (ops R32:$dst, R32:$src1, i32mem:$src2),
601 "cmovg {$src2, $dst|$dst, $src2}">, TB;
603 // unary instructions
604 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">;
605 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize;
606 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">;
607 let isTwoAddress = 0 in {
608 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">;
609 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize;
610 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">;
613 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">;
614 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize;
615 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">;
616 let isTwoAddress = 0 in {
617 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">;
618 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize;
619 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">;
622 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">;
623 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
624 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize;
625 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">;
627 let isTwoAddress = 0 in {
628 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">;
629 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize;
630 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">;
633 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">;
634 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
635 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize;
636 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">;
639 let isTwoAddress = 0 in {
640 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">;
641 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize;
642 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">;
645 // Logical operators...
646 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
647 def AND8rr : I<0x20, MRMDestReg,
648 (ops R8 :$dst, R8 :$src1, R8 :$src2),
649 "and{b} {$src2, $dst|$dst, $src2}">;
650 def AND16rr : I<0x21, MRMDestReg,
651 (ops R16:$dst, R16:$src1, R16:$src2),
652 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
653 def AND32rr : I<0x21, MRMDestReg,
654 (ops R32:$dst, R32:$src1, R32:$src2),
655 "and{l} {$src2, $dst|$dst, $src2}">;
658 def AND8rm : I<0x22, MRMSrcMem,
659 (ops R8 :$dst, R8 :$src1, i8mem :$src2),
660 "and{b} {$src2, $dst|$dst, $src2}">;
661 def AND16rm : I<0x23, MRMSrcMem,
662 (ops R16:$dst, R16:$src1, i16mem:$src2),
663 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
664 def AND32rm : I<0x23, MRMSrcMem,
665 (ops R32:$dst, R32:$src1, i32mem:$src2),
666 "and{l} {$src2, $dst|$dst, $src2}">;
668 def AND8ri : Ii8<0x80, MRM4r,
669 (ops R8 :$dst, R8 :$src1, i8imm :$src2),
670 "and{b} {$src2, $dst|$dst, $src2}">;
671 def AND16ri : Ii16<0x81, MRM4r,
672 (ops R16:$dst, R16:$src1, i16imm:$src2),
673 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
674 def AND32ri : Ii32<0x81, MRM4r,
675 (ops R32:$dst, R32:$src1, i32imm:$src2),
676 "and{l} {$src2, $dst|$dst, $src2}">;
677 def AND16ri8 : Ii8<0x83, MRM4r,
678 (ops R16:$dst, R16:$src1, i8imm:$src2),
679 "and{w} {$src2, $dst|$dst, $src2}" >, OpSize;
680 def AND32ri8 : Ii8<0x83, MRM4r,
681 (ops R32:$dst, R32:$src1, i8imm:$src2),
682 "and{l} {$src2, $dst|$dst, $src2}">;
684 let isTwoAddress = 0 in {
685 def AND8mr : I<0x20, MRMDestMem,
686 (ops i8mem :$dst, R8 :$src),
687 "and{b} {$src, $dst|$dst, $src}">;
688 def AND16mr : I<0x21, MRMDestMem,
689 (ops i16mem:$dst, R16:$src),
690 "and{w} {$src, $dst|$dst, $src}">, OpSize;
691 def AND32mr : I<0x21, MRMDestMem,
692 (ops i32mem:$dst, R32:$src),
693 "and{l} {$src, $dst|$dst, $src}">;
694 def AND8mi : Ii8<0x80, MRM4m,
695 (ops i8mem :$dst, i8imm :$src),
696 "and{b} {$src, $dst|$dst, $src}">;
697 def AND16mi : Ii16<0x81, MRM4m,
698 (ops i16mem:$dst, i16imm:$src),
699 "and{w} {$src, $dst|$dst, $src}">, OpSize;
700 def AND32mi : Ii32<0x81, MRM4m,
701 (ops i32mem:$dst, i32imm:$src),
702 "and{l} {$src, $dst|$dst, $src}">;
703 def AND16mi8 : Ii8<0x83, MRM4m,
704 (ops i16mem:$dst, i8imm :$src),
705 "and{w} {$src, $dst|$dst, $src}">, OpSize;
706 def AND32mi8 : Ii8<0x83, MRM4m,
707 (ops i32mem:$dst, i8imm :$src),
708 "and{l} {$src, $dst|$dst, $src}">;
712 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
713 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
714 "or{b} {$src2, $dst|$dst, $src2}">;
715 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
716 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
717 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
718 "or{l} {$src2, $dst|$dst, $src2}">;
720 def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
721 "or{b} {$src2, $dst|$dst, $src2}">;
722 def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
723 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
724 def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
725 "or{l} {$src2, $dst|$dst, $src2}">;
727 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
728 "or{b} {$src2, $dst|$dst, $src2}">;
729 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
730 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
731 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
732 "or{l} {$src2, $dst|$dst, $src2}">;
734 def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
735 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
736 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
737 "or{l} {$src2, $dst|$dst, $src2}">;
738 let isTwoAddress = 0 in {
739 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
740 "or{b} {$src, $dst|$dst, $src}">;
741 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
742 "or{w} {$src, $dst|$dst, $src}">, OpSize;
743 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
744 "or{l} {$src, $dst|$dst, $src}">;
745 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
746 "or{b} {$src, $dst|$dst, $src}">;
747 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
748 "or{w} {$src, $dst|$dst, $src}">, OpSize;
749 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
750 "or{l} {$src, $dst|$dst, $src}">;
751 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src),
752 "or{w} {$src, $dst|$dst, $src}">, OpSize;
753 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src),
754 "or{l} {$src, $dst|$dst, $src}">;
758 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
759 def XOR8rr : I<0x30, MRMDestReg,
760 (ops R8 :$dst, R8 :$src1, R8 :$src2),
761 "xor{b} {$src2, $dst|$dst, $src2}">;
762 def XOR16rr : I<0x31, MRMDestReg,
763 (ops R16:$dst, R16:$src1, R16:$src2),
764 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
765 def XOR32rr : I<0x31, MRMDestReg,
766 (ops R32:$dst, R32:$src1, R32:$src2),
767 "xor{l} {$src2, $dst|$dst, $src2}">;
770 def XOR8rm : I<0x32, MRMSrcMem ,
771 (ops R8 :$dst, R8:$src1, i8mem :$src2),
772 "xor{b} {$src2, $dst|$dst, $src2}">;
773 def XOR16rm : I<0x33, MRMSrcMem ,
774 (ops R16:$dst, R8:$src1, i16mem:$src2),
775 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
776 def XOR32rm : I<0x33, MRMSrcMem ,
777 (ops R32:$dst, R8:$src1, i32mem:$src2),
778 "xor{l} {$src2, $dst|$dst, $src2}">;
780 def XOR8ri : Ii8<0x80, MRM6r,
781 (ops R8:$dst, R8:$src1, i8imm:$src2),
782 "xor{b} {$src2, $dst|$dst, $src2}">;
783 def XOR16ri : Ii16<0x81, MRM6r,
784 (ops R16:$dst, R16:$src1, i16imm:$src2),
785 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
786 def XOR32ri : Ii32<0x81, MRM6r,
787 (ops R32:$dst, R32:$src1, i32imm:$src2),
788 "xor{l} {$src2, $dst|$dst, $src2}">;
789 def XOR16ri8 : Ii8<0x83, MRM6r,
790 (ops R16:$dst, R16:$src1, i8imm:$src2),
791 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
792 def XOR32ri8 : Ii8<0x83, MRM6r,
793 (ops R32:$dst, R32:$src1, i8imm:$src2),
794 "xor{l} {$src2, $dst|$dst, $src2}">;
795 let isTwoAddress = 0 in {
796 def XOR8mr : I<0x30, MRMDestMem,
797 (ops i8mem :$dst, R8 :$src),
798 "xor{b} {$src, $dst|$dst, $src}">;
799 def XOR16mr : I<0x31, MRMDestMem,
800 (ops i16mem:$dst, R16:$src),
801 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
802 def XOR32mr : I<0x31, MRMDestMem,
803 (ops i32mem:$dst, R32:$src),
804 "xor{l} {$src, $dst|$dst, $src}">;
805 def XOR8mi : Ii8<0x80, MRM6m,
806 (ops i8mem :$dst, i8imm :$src),
807 "xor{b} {$src, $dst|$dst, $src}">;
808 def XOR16mi : Ii16<0x81, MRM6m,
809 (ops i16mem:$dst, i16imm:$src),
810 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
811 def XOR32mi : Ii32<0x81, MRM6m,
812 (ops i32mem:$dst, i32imm:$src),
813 "xor{l} {$src, $dst|$dst, $src}">;
814 def XOR16mi8 : Ii8<0x83, MRM6m,
815 (ops i16mem:$dst, i8imm :$src),
816 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
817 def XOR32mi8 : Ii8<0x83, MRM6m,
818 (ops i32mem:$dst, i8imm :$src),
819 "xor{l} {$src, $dst|$dst, $src}">;
822 // Shift instructions
823 // FIXME: provide shorter instructions when imm8 == 1
824 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
825 "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
826 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
827 "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
828 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
829 "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
831 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
832 "shl{b} {$src2, $dst|$dst, $src2}">;
833 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
834 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
835 "shl{w} {$src2, $dst|$dst, $src2}">, OpSize;
836 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
837 "shl{l} {$src2, $dst|$dst, $src2}">;
840 let isTwoAddress = 0 in {
841 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
842 "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
843 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
844 "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
845 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
846 "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
847 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
848 "shl{b} {$src, $dst|$dst, $src}">;
849 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
850 "shl{w} {$src, $dst|$dst, $src}">, OpSize;
851 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
852 "shl{l} {$src, $dst|$dst, $src}">;
855 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
856 "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
857 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
858 "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
859 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
860 "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
862 def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
863 "shr{b} {$src2, $dst|$dst, $src2}">;
864 def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
865 "shr{w} {$src2, $dst|$dst, $src2}">, OpSize;
866 def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
867 "shr{l} {$src2, $dst|$dst, $src2}">;
869 let isTwoAddress = 0 in {
870 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
871 "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
872 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
873 "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
874 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
875 "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
876 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
877 "shr{b} {$src, $dst|$dst, $src}">;
878 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
879 "shr{w} {$src, $dst|$dst, $src}">, OpSize;
880 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
881 "shr{l} {$src, $dst|$dst, $src}">;
884 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
885 "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
886 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
887 "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
888 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
889 "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
891 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
892 "sar{b} {$src2, $dst|$dst, $src2}">;
893 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
894 "sar{w} {$src2, $dst|$dst, $src2}">, OpSize;
895 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
896 "sar{l} {$src2, $dst|$dst, $src2}">;
897 let isTwoAddress = 0 in {
898 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
899 "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
900 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
901 "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
902 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
903 "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
904 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
905 "sar{b} {$src, $dst|$dst, $src}">;
906 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
907 "sar{w} {$src, $dst|$dst, $src}">, OpSize;
908 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
909 "sar{l} {$src, $dst|$dst, $src}">;
912 // Rotate instructions
913 // FIXME: provide shorter instructions when imm8 == 1
914 def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
915 "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
916 def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
917 "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
918 def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
919 "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
921 def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
922 "rol{b} {$src2, $dst|$dst, $src2}">;
923 def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
924 "rol{w} {$src2, $dst|$dst, $src2}">, OpSize;
925 def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
926 "rol{l} {$src2, $dst|$dst, $src2}">;
928 let isTwoAddress = 0 in {
929 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
930 "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
931 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
932 "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
933 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
934 "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
935 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
936 "rol{b} {$src, $dst|$dst, $src}">;
937 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
938 "rol{w} {$src, $dst|$dst, $src}">, OpSize;
939 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
940 "rol{l} {$src, $dst|$dst, $src}">;
943 def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
944 "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
945 def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
946 "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
947 def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
948 "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
950 def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
951 "ror{b} {$src2, $dst|$dst, $src2}">;
952 def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2),
953 "ror{w} {$src2, $dst|$dst, $src2}">, OpSize;
954 def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
955 "ror{l} {$src2, $dst|$dst, $src2}">;
956 let isTwoAddress = 0 in {
957 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
958 "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
959 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
960 "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
961 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
962 "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
963 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
964 "ror{b} {$src, $dst|$dst, $src}">;
965 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
966 "ror{w} {$src, $dst|$dst, $src}">, OpSize;
967 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
968 "ror{l} {$src, $dst|$dst, $src}">;
973 // Double shift instructions (generalizations of rotate)
975 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
976 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
978 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
979 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
981 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
982 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
983 Imp<[CL],[]>, TB, OpSize;
984 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
985 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
986 Imp<[CL],[]>, TB, OpSize;
988 let isCommutable = 1 in { // These instructions commute to each other.
989 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
990 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
991 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
992 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
993 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
994 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
995 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
996 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
997 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
999 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1000 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
1001 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
1005 let isTwoAddress = 0 in {
1006 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1007 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1009 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1010 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1012 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1013 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1014 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
1015 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1016 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1017 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
1019 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1020 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1021 Imp<[CL],[]>, TB, OpSize;
1022 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1023 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
1024 Imp<[CL],[]>, TB, OpSize;
1025 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1026 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1027 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
1029 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1030 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1031 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">,
1037 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1038 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1039 "add{b} {$src2, $dst|$dst, $src2}">;
1040 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1041 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1042 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1043 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1044 "add{l} {$src2, $dst|$dst, $src2}">;
1045 } // end isConvertibleToThreeAddress
1046 } // end isCommutable
1047 def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1048 "add{b} {$src2, $dst|$dst, $src2}">;
1049 def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1050 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1051 def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1052 "add{l} {$src2, $dst|$dst, $src2}">;
1054 def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1055 "add{b} {$src2, $dst|$dst, $src2}">;
1057 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1058 def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1059 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1060 def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1061 "add{l} {$src2, $dst|$dst, $src2}">;
1064 def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1065 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1066 def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1067 "add{l} {$src2, $dst|$dst, $src2}">;
1069 let isTwoAddress = 0 in {
1070 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1071 "add{b} {$src2, $dst|$dst, $src2}">;
1072 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1073 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1074 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1075 "add{l} {$src2, $dst|$dst, $src2}">;
1076 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1077 "add{b} {$src2, $dst|$dst, $src2}">;
1078 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1079 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1080 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1081 "add{l} {$src2, $dst|$dst, $src2}">;
1082 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2),
1083 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
1084 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2),
1085 "add{l} {$src2, $dst|$dst, $src2}">;
1088 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1089 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1090 "adc{l} {$src2, $dst|$dst, $src2}">;
1092 def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
1093 "adc{l} {$src2, $dst|$dst, $src2}">;
1094 def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1095 "adc{l} {$src2, $dst|$dst, $src2}">;
1096 def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1097 "adc{l} {$src2, $dst|$dst, $src2}">;
1099 let isTwoAddress = 0 in {
1100 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1101 "adc{l} {$src2, $dst|$dst, $src2}">;
1102 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1103 "adc{l} {$src2, $dst|$dst, $src2}">;
1104 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2),
1105 "adc{l} {$src2, $dst|$dst, $src2}">;
1108 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1109 "sub{b} {$src2, $dst|$dst, $src2}">;
1110 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1111 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1112 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1113 "sub{l} {$src2, $dst|$dst, $src2}">;
1114 def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1115 "sub{b} {$src2, $dst|$dst, $src2}">;
1116 def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1117 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1118 def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1119 "sub{l} {$src2, $dst|$dst, $src2}">;
1121 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1122 "sub{b} {$src2, $dst|$dst, $src2}">;
1123 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1124 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1125 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1126 "sub{l} {$src2, $dst|$dst, $src2}">;
1127 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1128 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1129 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1130 "sub{l} {$src2, $dst|$dst, $src2}">;
1131 let isTwoAddress = 0 in {
1132 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1133 "sub{b} {$src2, $dst|$dst, $src2}">;
1134 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1135 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1136 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1137 "sub{l} {$src2, $dst|$dst, $src2}">;
1138 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1139 "sub{b} {$src2, $dst|$dst, $src2}">;
1140 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1141 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1142 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1143 "sub{l} {$src2, $dst|$dst, $src2}">;
1144 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2),
1145 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
1146 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i8imm :$src2),
1147 "sub{l} {$src2, $dst|$dst, $src2}">;
1150 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1151 "sbb{l} {$src2, $dst|$dst, $src2}">;
1153 let isTwoAddress = 0 in {
1154 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1155 "sbb{l} {$src2, $dst|$dst, $src2}">;
1156 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
1157 "sbb{b} {$src2, $dst|$dst, $src2}">;
1158 def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
1159 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1160 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
1161 "sbb{l} {$src2, $dst|$dst, $src2}">;
1162 def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2),
1163 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1164 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2),
1165 "sbb{l} {$src2, $dst|$dst, $src2}">;
1167 def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1168 "sbb{b} {$src2, $dst|$dst, $src2}">;
1169 def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1170 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1172 def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1173 "sbb{l} {$src2, $dst|$dst, $src2}">;
1174 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1175 "sbb{l} {$src2, $dst|$dst, $src2}">;
1177 def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1178 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
1179 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1180 "sbb{l} {$src2, $dst|$dst, $src2}">;
1182 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
1183 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
1184 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
1185 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
1186 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
1188 def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1189 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
1190 def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1191 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
1193 } // end Two Address instructions
1195 // Suprisingly enough, these are not two address instructions!
1196 def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16
1197 (ops R16:$dst, R16:$src1, i16imm:$src2),
1198 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">,
1200 def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
1201 (ops R32:$dst, R32:$src1, i32imm:$src2),
1202 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1203 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
1204 (ops R16:$dst, R16:$src1, i8imm:$src2),
1205 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1206 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
1207 (ops R32:$dst, R32:$src1, i8imm:$src2),
1208 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1210 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
1211 (ops R32:$dst, i16mem:$src1, i16imm:$src2),
1212 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1213 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
1214 (ops R32:$dst, i32mem:$src1, i32imm:$src2),
1215 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1216 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
1217 (ops R32:$dst, i16mem:$src1, i8imm :$src2),
1218 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
1220 (ops R32:$dst, i32mem:$src1, i8imm: $src2),
1221 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1223 //===----------------------------------------------------------------------===//
1224 // Test instructions are just like AND, except they don't generate a result.
1226 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1227 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
1228 "test{b} {$src2, $src1|$src1, $src2}">;
1229 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
1230 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1231 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
1232 "test{l} {$src2, $src1|$src1, $src2}">;
1234 def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
1235 "test{b} {$src2, $src1|$src1, $src2}">;
1236 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
1237 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1238 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
1239 "test{l} {$src2, $src1|$src1, $src2}">;
1240 def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
1241 "test{b} {$src2, $src1|$src1, $src2}">;
1242 def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
1243 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1244 def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
1245 "test{l} {$src2, $src1|$src1, $src2}">;
1247 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
1248 (ops R8:$src1, i8imm:$src2),
1249 "test{b} {$src2, $src1|$src1, $src2}">;
1250 def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
1251 (ops R16:$src1, i16imm:$src2),
1252 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1253 def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
1254 (ops R32:$src1, i32imm:$src2),
1255 "test{l} {$src2, $src1|$src1, $src2}">;
1256 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1257 (ops i32mem:$src1, i8imm:$src2),
1258 "test{b} {$src2, $src1|$src1, $src2}">;
1259 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1260 (ops i16mem:$src1, i16imm:$src2),
1261 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1262 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1263 (ops i32mem:$src1, i32imm:$src2),
1264 "test{l} {$src2, $src1|$src1, $src2}">;
1268 // Condition code ops, incl. set if equal/not equal/...
1269 def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH
1270 def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags
1272 def SETBr : I<0x92, MRM0r,
1273 (ops R8 :$dst), "setb $dst">, TB; // R8 = < unsign
1274 def SETBm : I<0x92, MRM0m,
1275 (ops i8mem:$dst), "setb $dst">, TB; // [mem8] = < unsign
1276 def SETAEr : I<0x93, MRM0r,
1277 (ops R8 :$dst), "setae $dst">, TB; // R8 = >= unsign
1278 def SETAEm : I<0x93, MRM0m,
1279 (ops i8mem:$dst), "setae $dst">, TB; // [mem8] = >= unsign
1280 def SETEr : I<0x94, MRM0r,
1281 (ops R8 :$dst), "sete $dst">, TB; // R8 = ==
1282 def SETEm : I<0x94, MRM0m,
1283 (ops i8mem:$dst), "sete $dst">, TB; // [mem8] = ==
1284 def SETNEr : I<0x95, MRM0r,
1285 (ops R8 :$dst), "setne $dst">, TB; // R8 = !=
1286 def SETNEm : I<0x95, MRM0m,
1287 (ops i8mem:$dst), "setne $dst">, TB; // [mem8] = !=
1288 def SETBEr : I<0x96, MRM0r,
1289 (ops R8 :$dst), "setbe $dst">, TB; // R8 = <= unsign
1290 def SETBEm : I<0x96, MRM0m,
1291 (ops i8mem:$dst), "setbe $dst">, TB; // [mem8] = <= unsign
1292 def SETAr : I<0x97, MRM0r,
1293 (ops R8 :$dst), "seta $dst">, TB; // R8 = > signed
1294 def SETAm : I<0x97, MRM0m,
1295 (ops i8mem:$dst), "seta $dst">, TB; // [mem8] = > signed
1296 def SETSr : I<0x98, MRM0r,
1297 (ops R8 :$dst), "sets $dst">, TB; // R8 = <sign bit>
1298 def SETSm : I<0x98, MRM0m,
1299 (ops i8mem:$dst), "sets $dst">, TB; // [mem8] = <sign bit>
1300 def SETNSr : I<0x99, MRM0r,
1301 (ops R8 :$dst), "setns $dst">, TB; // R8 = !<sign bit>
1302 def SETNSm : I<0x99, MRM0m,
1303 (ops i8mem:$dst), "setns $dst">, TB; // [mem8] = !<sign bit>
1304 def SETPr : I<0x9A, MRM0r,
1305 (ops R8 :$dst), "setp $dst">, TB; // R8 = parity
1306 def SETPm : I<0x9A, MRM0m,
1307 (ops i8mem:$dst), "setp $dst">, TB; // [mem8] = parity
1308 def SETNPr : I<0x9B, MRM0r,
1309 (ops R8 :$dst), "setnp $dst">, TB; // R8 = not parity
1310 def SETNPm : I<0x9B, MRM0m,
1311 (ops i8mem:$dst), "setnp $dst">, TB; // [mem8] = not parity
1312 def SETLr : I<0x9C, MRM0r,
1313 (ops R8 :$dst), "setl $dst">, TB; // R8 = < signed
1314 def SETLm : I<0x9C, MRM0m,
1315 (ops i8mem:$dst), "setl $dst">, TB; // [mem8] = < signed
1316 def SETGEr : I<0x9D, MRM0r,
1317 (ops R8 :$dst), "setge $dst">, TB; // R8 = >= signed
1318 def SETGEm : I<0x9D, MRM0m,
1319 (ops i8mem:$dst), "setge $dst">, TB; // [mem8] = >= signed
1320 def SETLEr : I<0x9E, MRM0r,
1321 (ops R8 :$dst), "setle $dst">, TB; // R8 = <= signed
1322 def SETLEm : I<0x9E, MRM0m,
1323 (ops i8mem:$dst), "setle $dst">, TB; // [mem8] = <= signed
1324 def SETGr : I<0x9F, MRM0r,
1325 (ops R8 :$dst), "setg $dst">, TB; // R8 = < signed
1326 def SETGm : I<0x9F, MRM0m,
1327 (ops i8mem:$dst), "setg $dst">, TB; // [mem8] = < signed
1329 // Integer comparisons
1330 def CMP8rr : I<0x38, MRMDestReg,
1331 (ops R8 :$src1, R8 :$src2),
1332 "cmp{b} {$src2, $src1|$src1, $src2}">;
1333 def CMP16rr : I<0x39, MRMDestReg,
1334 (ops R16:$src1, R16:$src2),
1335 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1336 def CMP32rr : I<0x39, MRMDestReg,
1337 (ops R32:$src1, R32:$src2),
1338 "cmp{l} {$src2, $src1|$src1, $src2}">;
1339 def CMP8mr : I<0x38, MRMDestMem,
1340 (ops i8mem :$src1, R8 :$src2),
1341 "cmp{b} {$src2, $src1|$src1, $src2}">;
1342 def CMP16mr : I<0x39, MRMDestMem,
1343 (ops i16mem:$src1, R16:$src2),
1344 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1345 def CMP32mr : I<0x39, MRMDestMem,
1346 (ops i32mem:$src1, R32:$src2),
1347 "cmp{l} {$src2, $src1|$src1, $src2}">;
1348 def CMP8rm : I<0x3A, MRMSrcMem,
1349 (ops R8 :$src1, i8mem :$src2),
1350 "cmp{b} {$src2, $src1|$src1, $src2}">;
1351 def CMP16rm : I<0x3B, MRMSrcMem,
1352 (ops R16:$src1, i16mem:$src2),
1353 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1354 def CMP32rm : I<0x3B, MRMSrcMem,
1355 (ops R32:$src1, i32mem:$src2),
1356 "cmp{l} {$src2, $src1|$src1, $src2}">;
1357 def CMP8ri : Ii8<0x80, MRM7r,
1358 (ops R16:$src1, i8imm:$src2),
1359 "cmp{b} {$src2, $src1|$src1, $src2}">;
1360 def CMP16ri : Ii16<0x81, MRM7r,
1361 (ops R16:$src1, i16imm:$src2),
1362 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1363 def CMP32ri : Ii32<0x81, MRM7r,
1364 (ops R32:$src1, i32imm:$src2),
1365 "cmp{l} {$src2, $src1|$src1, $src2}">;
1366 def CMP8mi : Ii8 <0x80, MRM7m,
1367 (ops i8mem :$src1, i8imm :$src2),
1368 "cmp{b} {$src2, $src1|$src1, $src2}">;
1369 def CMP16mi : Ii16<0x81, MRM7m,
1370 (ops i16mem:$src1, i16imm:$src2),
1371 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1372 def CMP32mi : Ii32<0x81, MRM7m,
1373 (ops i32mem:$src1, i32imm:$src2),
1374 "cmp{l} {$src2, $src1|$src1, $src2}">;
1376 // Sign/Zero extenders
1377 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
1378 "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1379 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1380 "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1381 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src),
1382 "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
1383 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1384 "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
1385 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src),
1386 "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
1387 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1388 "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
1390 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src),
1391 "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1392 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1393 "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1394 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src),
1395 "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
1396 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1397 "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
1398 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src),
1399 "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
1400 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1401 "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
1403 //===----------------------------------------------------------------------===//
1404 // XMM Floating point support (requires SSE2)
1405 //===----------------------------------------------------------------------===//
1407 def MOVSSrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1408 "movss {$src, $dst|$dst, $src}">, XS;
1409 def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
1410 "movss {$src, $dst|$dst, $src}">, XS;
1411 def MOVSDrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1412 "movsd {$src, $dst|$dst, $src}">, XD;
1413 def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
1414 "movsd {$src, $dst|$dst, $src}">, XD;
1415 def MOVAPSrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1416 "movaps {$src, $dst|$dst, $src}">, TB;
1417 def MOVAPSrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1418 "movaps {$src, $dst|$dst, $src}">, TB;
1419 def MOVAPSmr: I<0x29, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
1420 "movaps {$src, $dst|$dst, $src}">, TB;
1421 def MOVAPDrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1422 "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
1423 def MOVAPDrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1424 "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
1425 def MOVAPDmr: I<0x29, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
1426 "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
1428 def CVTSD2SIrr: I<0x2D, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1429 "cvtsd2si {$src, $dst|$dst, $src}">, XD;
1430 def CVTSD2SIrm: I<0x2D, MRMSrcMem, (ops R32:$dst, f64mem:$src),
1431 "cvtsd2si {$src, $dst|$dst, $src}">, XD;
1432 def CVTSS2SIrr: I<0x2D, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1433 "cvtss2si {$src, $dst|$dst, $src}">, XS;
1434 def CVTSS2SIrm: I<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
1435 "cvtss2si {$src, $dst|$dst, $src}">, XS;
1436 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1437 "cvtss2sd {$src, $dst|$dst, $src}">, XD;
1438 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops R32:$dst, f32mem:$src),
1439 "cvtss2sd {$src, $dst|$dst, $src}">, XD;
1440 def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1441 "cvtsi2ss {$src, $dst|$dst, $src}">, XS;
1442 def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f32mem:$src),
1443 "cvtsi2ss {$src, $dst|$dst, $src}">, XS;
1444 def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
1445 "cvtsi2sd {$src, $dst|$dst, $src}">, XD;
1446 def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f64mem:$src),
1447 "cvtsi2sd {$src, $dst|$dst, $src}">, XD;
1449 def SQRTSSrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1450 "subss {$src, $dst|$dst, $src}">, XS;
1451 def SQRTSSrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1452 "subss {$src, $dst|$dst, $src}">, XS;
1453 def SQRTSDrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1454 "subsd {$src, $dst|$dst, $src}">, XD;
1455 def SQRTSDrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1456 "subsd {$src, $dst|$dst, $src}">, XD;
1458 def UCOMISDrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1459 "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
1460 def UCOMISDrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
1461 "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
1462 def UCOMISSrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
1463 "ucomiss {$src, $dst|$dst, $src}">, TB;
1464 def UCOMISSrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
1465 "ucomiss {$src, $dst|$dst, $src}">, TB;
1467 let isTwoAddress = 1 in {
1468 let isCommutable = 1 in {
1469 def ADDSSrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1470 "addss {$src, $dst|$dst, $src}">, XS;
1471 def ADDSDrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1472 "addsd {$src, $dst|$dst, $src}">, XD;
1473 def ANDPSrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1474 "andps {$src, $dst|$dst, $src}">, TB;
1475 def ANDPDrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1476 "andpd {$src, $dst|$dst, $src}">, TB, OpSize;
1477 def MULSSrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1478 "mulss {$src, $dst|$dst, $src}">, XS;
1479 def MULSDrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1480 "mulsd {$src, $dst|$dst, $src}">, XD;
1481 def ORPSrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1482 "orps {$src, $dst|$dst, $src}">, TB;
1483 def ORPDrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1484 "orpd {$src, $dst|$dst, $src}">, TB, OpSize;
1486 def ANDNPSrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1487 "andnps {$src, $dst|$dst, $src}">, TB;
1488 def ANDNPDrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1489 "andnpd {$src, $dst|$dst, $src}">, TB, OpSize;
1490 def ADDSSrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1491 "addss {$src, $dst|$dst, $src}">, XS;
1492 def ADDSDrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1493 "addsd {$src, $dst|$dst, $src}">, XD;
1494 def MULSSrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1495 "mulss {$src, $dst|$dst, $src}">, XS;
1496 def MULSDrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1497 "mulsd {$src, $dst|$dst, $src}">, XD;
1499 def DIVSSrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1500 "divss {$src, $dst|$dst, $src}">, XS;
1501 def DIVSSrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1502 "divss {$src, $dst|$dst, $src}">, XS;
1503 def DIVSDrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1504 "divsd {$src, $dst|$dst, $src}">, XD;
1505 def DIVSDrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1506 "divsd {$src, $dst|$dst, $src}">, XD;
1508 def SUBSSrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
1509 "subss {$src, $dst|$dst, $src}">, XS;
1510 def SUBSSrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1511 "subss {$src, $dst|$dst, $src}">, XS;
1512 def SUBSDrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
1513 "subsd {$src, $dst|$dst, $src}">, XD;
1514 def SUBSDrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
1515 "subsd {$src, $dst|$dst, $src}">, XD;
1517 def CMPSSrr : I<0xC2, MRMSrcReg,
1518 (ops RXMM:$dst, RXMM:$src1, RXMM:$src, i8imm:$pred),
1519 "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XS;
1520 def CMPSSrm : I<0xC2, MRMSrcMem,
1521 (ops RXMM:$dst, RXMM:$src1, f32mem:$src, i8imm:$pred),
1522 "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XS;
1523 def CMPSDrr : I<0xC2, MRMSrcReg,
1524 (ops RXMM:$dst, RXMM:$src1, RXMM:$src, i8imm:$pred),
1525 "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XD;
1526 def CMPSDrm : I<0xC2, MRMSrcMem,
1527 (ops RXMM:$dst, RXMM:$src1, f64mem:$src, i8imm:$pred),
1528 "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XD;
1531 //===----------------------------------------------------------------------===//
1532 // Stack-based Floating point support
1533 //===----------------------------------------------------------------------===//
1535 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
1537 // Floating point instruction template
1538 class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm>
1539 : X86Inst<o, F, NoImm, ops, asm> {
1540 let FPForm = fp; let FPFormBits = FPForm.Value;
1543 // Pseudo instructions for floating point. We use these pseudo instructions
1544 // because they can be expanded by the fp spackifier into one of many different
1545 // forms of instructions for doing these operations. Until the stackifier runs,
1546 // we prefer to be abstract.
1547 def FpMOV : FPI<0, Pseudo, SpecialFP,
1548 (ops RFP, RFP), "">; // f1 = fmov f2
1549 def FpADD : FPI<0, Pseudo, TwoArgFP ,
1550 (ops RFP, RFP, RFP), "">; // f1 = fadd f2, f3
1551 def FpSUB : FPI<0, Pseudo, TwoArgFP ,
1552 (ops RFP, RFP, RFP), "">; // f1 = fsub f2, f3
1553 def FpMUL : FPI<0, Pseudo, TwoArgFP ,
1554 (ops RFP, RFP, RFP), "">; // f1 = fmul f2, f3
1555 def FpDIV : FPI<0, Pseudo, TwoArgFP ,
1556 (ops RFP, RFP, RFP), "">; // f1 = fdiv f2, f3
1558 def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">,
1559 Imp<[ST0], []>; // FPR = ST(0)
1561 def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">,
1562 Imp<[], [ST0]>; // ST(0) = FPR
1564 // FADD reg, mem: Before stackification, these are represented by:
1565 // R1 = FADD* R2, [mem]
1566 def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real]
1567 (ops f32mem:$src), "fadd{s} $src">;
1568 def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real]
1569 (ops f64mem:$src), "fadd{l} $src">;
1570 //def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
1571 //def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
1573 // FMUL reg, mem: Before stackification, these are represented by:
1574 // R1 = FMUL* R2, [mem]
1575 def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real]
1576 (ops f32mem:$src), "fmul{s} $src">;
1577 def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real]
1578 (ops f64mem:$src), "fmul{l} $src">;
1579 // ST(0) = ST(0) * [mem16int]
1580 //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>;
1581 // ST(0) = ST(0) * [mem32int]
1582 //def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>;
1584 // FSUB reg, mem: Before stackification, these are represented by:
1585 // R1 = FSUB* R2, [mem]
1586 def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real]
1587 (ops f32mem:$src), "fsub{s} $src">;
1588 def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real]
1589 (ops f64mem:$src), "fsub{l} $src">;
1590 // ST(0) = ST(0) - [mem16int]
1591 //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>;
1592 // ST(0) = ST(0) - [mem32int]
1593 //def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>;
1595 // FSUBR reg, mem: Before stackification, these are represented by:
1596 // R1 = FSUBR* R2, [mem]
1598 // Note that the order of operands does not reflect the operation being
1600 def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0)
1601 (ops f32mem:$src), "fsubr{s} $src">;
1602 def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0)
1603 (ops f64mem:$src), "fsubr{l} $src">;
1604 // ST(0) = [mem16int] - ST(0)
1605 //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>;
1606 // ST(0) = [mem32int] - ST(0)
1607 //def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>;
1609 // FDIV reg, mem: Before stackification, these are represented by:
1610 // R1 = FDIV* R2, [mem]
1611 def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real]
1612 (ops f32mem:$src), "fdiv{s} $src">;
1613 def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real]
1614 (ops f64mem:$src), "fdiv{l} $src">;
1615 // ST(0) = ST(0) / [mem16int]
1616 //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>;
1617 // ST(0) = ST(0) / [mem32int]
1618 //def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>;
1620 // FDIVR reg, mem: Before stackification, these are represented by:
1621 // R1 = FDIVR* R2, [mem]
1622 // Note that the order of operands does not reflect the operation being
1624 def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0)
1625 (ops f32mem:$src), "fdivr{s} $src">;
1626 def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0)
1627 (ops f64mem:$src), "fdivr{l} $src">;
1628 // ST(0) = [mem16int] / ST(0)
1629 //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>;
1630 // ST(0) = [mem32int] / ST(0)
1631 //def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>;
1634 // Floating point cmovs...
1635 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
1636 def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP,
1637 (ops RST:$op), "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
1638 def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
1639 (ops RST:$op), "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
1640 def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP,
1641 (ops RST:$op), "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
1642 def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP,
1643 (ops RST:$op), "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
1644 def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
1645 (ops RST:$op), "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
1646 def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP,
1647 (ops RST:$op), "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
1648 def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
1649 (ops RST:$op), "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
1650 def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP,
1651 (ops RST:$op), "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
1654 // Floating point loads & stores...
1655 def FLDrr : FPI<0xC0, AddRegFrm, NotFP, (ops RST:$src), "fld $src">, D9;
1656 def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP, (ops f32mem:$src), "fld{s} $src">;
1657 def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP, (ops f64mem:$src), "fld{l} $src">;
1658 def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP, (ops f80mem:$src), "fld{t} $src">;
1659 def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP, (ops i16mem:$src), "fild{s} $src">;
1660 def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP, (ops i32mem:$src), "fild{l} $src">;
1661 def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP, (ops i64mem:$src), "fild{ll} $src">;
1663 def FSTrr : FPI<0xD0, AddRegFrm, NotFP, (ops RST:$op), "fst $op">, DD;
1664 def FSTPrr : FPI<0xD8, AddRegFrm, NotFP, (ops RST:$op), "fstp $op">, DD;
1665 def FST32m : FPI<0xD9, MRM2m, OneArgFP, (ops f32mem:$op), "fst{s} $op">;
1666 def FST64m : FPI<0xDD, MRM2m, OneArgFP, (ops f64mem:$op), "fst{l} $op">;
1667 def FSTP32m : FPI<0xD9, MRM3m, OneArgFP, (ops f32mem:$op), "fstp{s} $op">;
1668 def FSTP64m : FPI<0xDD, MRM3m, OneArgFP, (ops f64mem:$op), "fstp{l} $op">;
1669 def FSTP80m : FPI<0xDB, MRM7m, OneArgFP, (ops f80mem:$op), "fstp{t} $op">;
1671 def FIST16m : FPI<0xDF, MRM2m , OneArgFP, (ops i16mem:$op), "fist{s} $op">;
1672 def FIST32m : FPI<0xDB, MRM2m , OneArgFP, (ops i32mem:$op), "fist{l} $op">;
1673 def FISTP16m : FPI<0xDF, MRM3m , NotFP , (ops i16mem:$op), "fistp{s} $op">;
1674 def FISTP32m : FPI<0xDB, MRM3m , NotFP , (ops i32mem:$op), "fistp{l} $op">;
1675 def FISTP64m : FPI<0xDF, MRM7m , OneArgFP, (ops i64mem:$op), "fistp{ll} $op">;
1677 def FXCH : FPI<0xC8, AddRegFrm, NotFP,
1678 (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
1680 // Floating point constant loads...
1681 def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops), "fldz">, D9;
1682 def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops), "fld1">, D9;
1685 // Unary operations...
1686 def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, (ops), "fchs" >, D9; // f1 = fchs f2
1687 def FABS : FPI<0xE1, RawFrm, OneArgFPRW, (ops), "fabs" >, D9; // f1 = fabs f2
1688 def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, (ops), "fsqrt">, D9; // fsqrt ST(0)
1689 def FSIN : FPI<0xFE, RawFrm, OneArgFPRW, (ops), "fsin" >, D9; // fsin ST(0)
1690 def FCOS : FPI<0xFF, RawFrm, OneArgFPRW, (ops), "fcos" >, D9; // fcos ST(0)
1691 def FTST : FPI<0xE4, RawFrm, OneArgFP , (ops), "ftst" >, D9; // ftst ST(0)
1693 // Binary arithmetic operations...
1694 class FPST0rInst<bits<8> o, dag ops, string asm>
1695 : I<o, AddRegFrm, ops, asm>, D8 {
1696 list<Register> Uses = [ST0];
1697 list<Register> Defs = [ST0];
1699 class FPrST0Inst<bits<8> o, dag ops, string asm>
1700 : I<o, AddRegFrm, ops, asm>, DC {
1701 list<Register> Uses = [ST0];
1703 class FPrST0PInst<bits<8> o, dag ops, string asm>
1704 : I<o, AddRegFrm, ops, asm>, DE {
1705 list<Register> Uses = [ST0];
1708 def FADDST0r : FPST0rInst <0xC0, (ops RST:$op),
1710 def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op),
1711 "fadd {%ST(0), $op|$op, %ST(0)}">;
1712 def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op),
1715 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
1716 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
1717 // we have to put some 'r's in and take them out of weird places.
1718 def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op),
1720 def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op),
1721 "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
1722 def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op),
1725 def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op),
1727 def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op),
1728 "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
1729 def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op),
1732 def FMULST0r : FPST0rInst <0xC8, (ops RST:$op),
1734 def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op),
1735 "fmul {%ST(0), $op|$op, %ST(0)}">;
1736 def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op),
1739 def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op),
1741 def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op),
1742 "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
1743 def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op),
1746 def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i)
1748 def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i)
1749 "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
1750 def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop
1753 // Floating point compares
1754 def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i)
1756 "fucom $reg">, DD, Imp<[ST0],[]>;
1757 def FUCOMPr : I<0xE8, AddRegFrm,
1758 (ops RST:$reg), // FPSW = cmp ST(0) with ST(i), pop
1759 "fucomp $reg">, DD, Imp<[ST0],[]>;
1760 def FUCOMPPr : I<0xE9, RawFrm,
1761 (ops), // cmp ST(0) with ST(1), pop, pop
1762 "fucompp">, DA, Imp<[ST0],[]>;
1764 def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i)
1766 "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
1767 def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
1769 "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
1772 // Floating point flag ops
1773 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
1774 (ops), "fnstsw">, DF, Imp<[],[AX]>;
1776 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
1777 (ops i16mem:$dst), "fnstcw $dst">;
1778 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
1779 (ops i16mem:$dst), "fldcw $dst">;