1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
79 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
83 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
84 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
85 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
86 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
88 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
89 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
91 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
92 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
94 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
95 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
97 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
100 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
101 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
103 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
119 [SDNPHasChain, SDNPMayStore,
120 SDNPMayLoad, SDNPMemOperand]>;
121 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
122 [SDNPHasChain, SDNPMayStore,
123 SDNPMayLoad, SDNPMemOperand]>;
124 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
125 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
127 def X86vastart_save_xmm_regs :
128 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
129 SDT_X86VASTART_SAVE_XMM_REGS,
130 [SDNPHasChain, SDNPVariadic]>;
132 def X86callseq_start :
133 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
134 [SDNPHasChain, SDNPOutFlag]>;
136 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
137 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
139 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
140 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
143 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
145 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
146 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
149 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
150 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
152 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
153 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
155 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
156 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
157 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
158 SDT_X86SegmentBaseAddress, []>;
160 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
163 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
164 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
166 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
168 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
169 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
171 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
174 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
175 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
176 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
178 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
180 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
183 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
185 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
186 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
188 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
191 //===----------------------------------------------------------------------===//
192 // X86 Operand Definitions.
195 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
196 // the index operand of an address, to conform to x86 encoding restrictions.
197 def ptr_rc_nosp : PointerLikeRegClass<1>;
199 // *mem - Operand definitions for the funky X86 addressing mode operands.
201 def X86MemAsmOperand : AsmOperandClass {
203 let SuperClasses = [];
205 def X86NoSegMemAsmOperand : AsmOperandClass {
206 let Name = "NoSegMem";
207 let SuperClasses = [X86MemAsmOperand];
209 def X86AbsMemAsmOperand : AsmOperandClass {
211 let SuperClasses = [X86NoSegMemAsmOperand];
213 class X86MemOperand<string printMethod> : Operand<iPTR> {
214 let PrintMethod = printMethod;
215 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
216 let ParserMatchClass = X86MemAsmOperand;
219 def opaque32mem : X86MemOperand<"printopaquemem">;
220 def opaque48mem : X86MemOperand<"printopaquemem">;
221 def opaque80mem : X86MemOperand<"printopaquemem">;
222 def opaque512mem : X86MemOperand<"printopaquemem">;
224 def i8mem : X86MemOperand<"printi8mem">;
225 def i16mem : X86MemOperand<"printi16mem">;
226 def i32mem : X86MemOperand<"printi32mem">;
227 def i64mem : X86MemOperand<"printi64mem">;
228 def i128mem : X86MemOperand<"printi128mem">;
229 //def i256mem : X86MemOperand<"printi256mem">;
230 def f32mem : X86MemOperand<"printf32mem">;
231 def f64mem : X86MemOperand<"printf64mem">;
232 def f80mem : X86MemOperand<"printf80mem">;
233 def f128mem : X86MemOperand<"printf128mem">;
234 //def f256mem : X86MemOperand<"printf256mem">;
236 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
237 // plain GR64, so that it doesn't potentially require a REX prefix.
238 def i8mem_NOREX : Operand<i64> {
239 let PrintMethod = "printi8mem";
240 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
241 let ParserMatchClass = X86MemAsmOperand;
244 // Special i32mem for addresses of load folding tail calls. These are not
245 // allowed to use callee-saved registers since they must be scheduled
246 // after callee-saved register are popped.
247 def i32mem_TC : Operand<i32> {
248 let PrintMethod = "printi32mem";
249 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
250 let ParserMatchClass = X86MemAsmOperand;
253 def lea32mem : Operand<i32> {
254 let PrintMethod = "printlea32mem";
255 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
256 let ParserMatchClass = X86NoSegMemAsmOperand;
259 let ParserMatchClass = X86AbsMemAsmOperand,
260 PrintMethod = "print_pcrel_imm" in {
261 def i32imm_pcrel : Operand<i32>;
263 def offset8 : Operand<i64>;
264 def offset16 : Operand<i64>;
265 def offset32 : Operand<i64>;
266 def offset64 : Operand<i64>;
268 // Branch targets have OtherVT type and print as pc-relative values.
269 def brtarget : Operand<OtherVT>;
270 def brtarget8 : Operand<OtherVT>;
274 def SSECC : Operand<i8> {
275 let PrintMethod = "printSSECC";
278 class ImmSExtAsmOperandClass : AsmOperandClass {
279 let SuperClasses = [ImmAsmOperand];
280 let RenderMethod = "addImmOperands";
283 // Sign-extended immediate classes. We don't need to define the full lattice
284 // here because there is no instruction with an ambiguity between ImmSExti64i32
287 // The strange ranges come from the fact that the assembler always works with
288 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
289 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
291 // [0, 0x7FFFFFFF] | [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
292 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
293 let Name = "ImmSExti64i32";
296 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
297 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
298 let Name = "ImmSExti16i8";
299 let SuperClasses = [ImmSExti64i32AsmOperand];
302 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
303 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
304 let Name = "ImmSExti32i8";
307 // [0, 0x0000007F] | [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
308 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
309 let Name = "ImmSExti64i8";
310 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, ImmSExti64i32AsmOperand];
313 // A couple of more descriptive operand definitions.
314 // 16-bits but only 8 bits are significant.
315 def i16i8imm : Operand<i16> {
316 let ParserMatchClass = ImmSExti16i8AsmOperand;
318 // 32-bits but only 8 bits are significant.
319 def i32i8imm : Operand<i32> {
320 let ParserMatchClass = ImmSExti32i8AsmOperand;
323 //===----------------------------------------------------------------------===//
324 // X86 Complex Pattern Definitions.
327 // Define X86 specific addressing mode.
328 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
329 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
330 [add, sub, mul, X86mul_imm, shl, or, frameindex],
332 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
333 [tglobaltlsaddr], []>;
335 //===----------------------------------------------------------------------===//
336 // X86 Instruction Predicate Definitions.
337 def HasCMov : Predicate<"Subtarget->hasCMov()">;
338 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
339 def HasMMX : Predicate<"Subtarget->hasMMX()">;
340 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
341 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
342 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
343 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
344 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
345 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
346 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
347 def HasAVX : Predicate<"Subtarget->hasAVX()">;
348 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
349 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
350 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
351 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
352 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
353 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
354 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
355 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
356 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
357 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
358 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
359 "TM.getCodeModel() != CodeModel::Kernel">;
360 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
361 "TM.getCodeModel() == CodeModel::Kernel">;
362 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
363 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
364 def OptForSize : Predicate<"OptForSize">;
365 def OptForSpeed : Predicate<"!OptForSize">;
366 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
367 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
368 def HasAES : Predicate<"Subtarget->hasAES()">;
370 //===----------------------------------------------------------------------===//
371 // X86 Instruction Format Definitions.
374 include "X86InstrFormats.td"
376 //===----------------------------------------------------------------------===//
377 // Pattern fragments...
380 // X86 specific condition code. These correspond to CondCode in
381 // X86InstrInfo.h. They must be kept in synch.
382 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
383 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
384 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
385 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
386 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
387 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
388 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
389 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
390 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
391 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
392 def X86_COND_NO : PatLeaf<(i8 10)>;
393 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
394 def X86_COND_NS : PatLeaf<(i8 12)>;
395 def X86_COND_O : PatLeaf<(i8 13)>;
396 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
397 def X86_COND_S : PatLeaf<(i8 15)>;
399 def immSext8 : PatLeaf<(imm), [{
400 return N->getSExtValue() == (int8_t)N->getSExtValue();
403 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
404 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
406 /// Load patterns: these constraint the match to the right address space.
407 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
408 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
409 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
410 if (PT->getAddressSpace() > 255)
415 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
417 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
418 return PT->getAddressSpace() == 256;
422 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
423 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
424 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
425 return PT->getAddressSpace() == 257;
430 // Helper fragments for loads.
431 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
432 // known to be 32-bit aligned or better. Ditto for i8 to i16.
433 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
434 LoadSDNode *LD = cast<LoadSDNode>(N);
435 if (const Value *Src = LD->getSrcValue())
436 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
437 if (PT->getAddressSpace() > 255)
439 ISD::LoadExtType ExtType = LD->getExtensionType();
440 if (ExtType == ISD::NON_EXTLOAD)
442 if (ExtType == ISD::EXTLOAD)
443 return LD->getAlignment() >= 2 && !LD->isVolatile();
447 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
448 LoadSDNode *LD = cast<LoadSDNode>(N);
449 if (const Value *Src = LD->getSrcValue())
450 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
451 if (PT->getAddressSpace() > 255)
453 ISD::LoadExtType ExtType = LD->getExtensionType();
454 if (ExtType == ISD::EXTLOAD)
455 return LD->getAlignment() >= 2 && !LD->isVolatile();
459 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
460 LoadSDNode *LD = cast<LoadSDNode>(N);
461 if (const Value *Src = LD->getSrcValue())
462 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
463 if (PT->getAddressSpace() > 255)
465 ISD::LoadExtType ExtType = LD->getExtensionType();
466 if (ExtType == ISD::NON_EXTLOAD)
468 if (ExtType == ISD::EXTLOAD)
469 return LD->getAlignment() >= 4 && !LD->isVolatile();
473 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
474 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
475 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
476 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
477 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
479 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
480 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
481 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
483 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
484 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
485 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
486 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
487 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
488 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
490 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
491 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
492 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
493 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
494 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
495 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
498 // An 'and' node with a single use.
499 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
500 return N->hasOneUse();
502 // An 'srl' node with a single use.
503 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
504 return N->hasOneUse();
506 // An 'trunc' node with a single use.
507 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
508 return N->hasOneUse();
511 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
512 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
513 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
514 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
516 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
517 APInt Mask = APInt::getAllOnesValue(BitWidth);
518 APInt KnownZero0, KnownOne0;
519 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
520 APInt KnownZero1, KnownOne1;
521 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
522 return (~KnownZero0 & ~KnownZero1) == 0;
525 //===----------------------------------------------------------------------===//
526 // Instruction list...
529 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
530 // a stack adjustment and the codegen must know that they may modify the stack
531 // pointer before prolog-epilog rewriting occurs.
532 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
533 // sub / add which can clobber EFLAGS.
534 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
535 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
537 [(X86callseq_start timm:$amt)]>,
538 Requires<[In32BitMode]>;
539 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
541 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
542 Requires<[In32BitMode]>;
545 // x86-64 va_start lowering magic.
546 let usesCustomInserter = 1 in {
547 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
550 i64imm:$regsavefi, i64imm:$offset,
552 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
553 [(X86vastart_save_xmm_regs GR8:$al,
557 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
558 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
559 // one go. Touching the stack at 4K increments is necessary to ensure that the
560 // guard pages used by the OS virtual memory manager are allocated in correct
562 // The main point of having separate instruction are extra unmodelled effects
563 // (compared to ordinary calls) like stack pointer change.
565 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
566 "# dynamic stack allocation",
571 let neverHasSideEffects = 1 in {
572 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
573 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
574 "nop{w}\t$zero", []>, TB, OpSize;
575 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
576 "nop{l}\t$zero", []>, TB;
580 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
581 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", []>;
582 // FIXME: need to make sure that "int $3" matches int3
583 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
584 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
585 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
587 // PIC base construction. This expands to code that looks like this:
590 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
591 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
594 //===----------------------------------------------------------------------===//
595 // Control Flow Instructions.
598 // Return instructions.
599 let isTerminator = 1, isReturn = 1, isBarrier = 1,
600 hasCtrlDep = 1, FPForm = SpecialFP in {
601 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
604 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
606 [(X86retflag timm:$amt)]>;
607 def LRET : I <0xCB, RawFrm, (outs), (ins),
609 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
613 // Unconditional branches.
614 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
615 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
616 "jmp\t$dst", [(br bb:$dst)]>;
617 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
621 // Conditional Branches.
622 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
623 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
624 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
625 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
626 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
630 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
631 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
632 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
633 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
634 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
635 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
636 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
637 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
638 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
639 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
640 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
641 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
642 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
643 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
644 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
645 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
647 // FIXME: What about the CX/RCX versions of this instruction?
648 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
649 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
654 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
655 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
656 [(brind GR32:$dst)]>;
657 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
658 [(brind (loadi32 addr:$dst))]>;
660 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
661 (ins i16imm:$seg, i16imm:$off),
662 "ljmp{w}\t$seg, $off", []>, OpSize;
663 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
664 (ins i16imm:$seg, i32imm:$off),
665 "ljmp{l}\t$seg, $off", []>;
667 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
668 "ljmp{w}\t{*}$dst", []>, OpSize;
669 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
670 "ljmp{l}\t{*}$dst", []>;
676 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
677 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
678 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
680 //===----------------------------------------------------------------------===//
681 // Call Instructions...
684 // All calls clobber the non-callee saved registers. ESP is marked as
685 // a use to prevent stack-pointer assignments that appear immediately
686 // before calls from potentially appearing dead. Uses for argument
687 // registers are added manually.
688 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
689 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
690 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
691 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
693 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
694 (outs), (ins i32imm_pcrel:$dst,variable_ops),
696 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
697 "call\t{*}$dst", [(X86call GR32:$dst)]>;
698 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
699 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
701 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
702 (ins i16imm:$seg, i16imm:$off),
703 "lcall{w}\t$seg, $off", []>, OpSize;
704 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
705 (ins i16imm:$seg, i32imm:$off),
706 "lcall{l}\t$seg, $off", []>;
708 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
709 "lcall{w}\t{*}$dst", []>, OpSize;
710 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
711 "lcall{l}\t{*}$dst", []>;
714 // Constructing a stack frame.
716 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
717 "enter\t$len, $lvl", []>;
721 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
722 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
723 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
724 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
725 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
727 def TCRETURNdi : I<0, Pseudo, (outs),
728 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
729 "#TC_RETURN $dst $offset", []>;
730 def TCRETURNri : I<0, Pseudo, (outs),
731 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
732 "#TC_RETURN $dst $offset", []>;
734 def TCRETURNmi : I<0, Pseudo, (outs),
735 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
736 "#TC_RETURN $dst $offset", []>;
738 // FIXME: The should be pseudo instructions that are lowered when going to
740 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
741 (ins i32imm_pcrel:$dst, variable_ops),
742 "jmp\t$dst # TAILCALL",
744 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
745 "jmp{l}\t{*}$dst # TAILCALL",
748 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
749 "jmp{l}\t{*}$dst # TAILCALL", []>;
751 // FIXME: This is a hack so that MCInst lowering can preserve the TAILCALL
752 // marker on instructions, while still being able to relax.
753 let isCodeGenOnly = 1 in {
754 def TAILJMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
755 "jmp\t$dst # TAILCALL", []>;
759 //===----------------------------------------------------------------------===//
760 // Miscellaneous Instructions...
762 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
763 def LEAVE : I<0xC9, RawFrm,
764 (outs), (ins), "leave", []>;
766 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
767 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
769 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
770 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
771 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
772 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
774 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
775 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
777 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
779 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
781 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
782 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
784 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
786 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
787 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
790 let mayStore = 1 in {
791 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
793 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
794 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
796 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
798 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
799 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
803 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
804 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
805 "push{l}\t$imm", []>;
806 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
807 "push{w}\t$imm", []>, OpSize;
808 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
809 "push{l}\t$imm", []>;
812 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
813 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
814 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
815 Requires<[In32BitMode]>;
817 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
818 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
819 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
820 Requires<[In32BitMode]>;
823 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
824 def BSWAP32r : I<0xC8, AddRegFrm,
825 (outs GR32:$dst), (ins GR32:$src),
827 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
830 // Bit scan instructions.
831 let Defs = [EFLAGS] in {
832 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
833 "bsf{w}\t{$src, $dst|$dst, $src}",
834 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
835 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
836 "bsf{w}\t{$src, $dst|$dst, $src}",
837 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
839 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
840 "bsf{l}\t{$src, $dst|$dst, $src}",
841 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
842 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
843 "bsf{l}\t{$src, $dst|$dst, $src}",
844 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
846 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
847 "bsr{w}\t{$src, $dst|$dst, $src}",
848 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
849 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
850 "bsr{w}\t{$src, $dst|$dst, $src}",
851 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
853 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
854 "bsr{l}\t{$src, $dst|$dst, $src}",
855 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
856 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
857 "bsr{l}\t{$src, $dst|$dst, $src}",
858 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
861 let neverHasSideEffects = 1 in
862 def LEA16r : I<0x8D, MRMSrcMem,
863 (outs GR16:$dst), (ins lea32mem:$src),
864 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
865 let isReMaterializable = 1 in
866 def LEA32r : I<0x8D, MRMSrcMem,
867 (outs GR32:$dst), (ins lea32mem:$src),
868 "lea{l}\t{$src|$dst}, {$dst|$src}",
869 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
871 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
872 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
873 [(X86rep_movs i8)]>, REP;
874 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
875 [(X86rep_movs i16)]>, REP, OpSize;
876 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
877 [(X86rep_movs i32)]>, REP;
880 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
881 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
882 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
883 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
884 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
887 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
888 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
889 [(X86rep_stos i8)]>, REP;
890 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
891 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
892 [(X86rep_stos i16)]>, REP, OpSize;
893 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
894 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
895 [(X86rep_stos i32)]>, REP;
897 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
898 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
899 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
900 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
901 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
902 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
903 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
905 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
906 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
907 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
909 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
910 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
911 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
913 let Defs = [RAX, RDX] in
914 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
917 let Defs = [RAX, RCX, RDX] in
918 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
920 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
921 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
924 def SYSCALL : I<0x05, RawFrm,
925 (outs), (ins), "syscall", []>, TB;
926 def SYSRET : I<0x07, RawFrm,
927 (outs), (ins), "sysret", []>, TB;
928 def SYSENTER : I<0x34, RawFrm,
929 (outs), (ins), "sysenter", []>, TB;
930 def SYSEXIT : I<0x35, RawFrm,
931 (outs), (ins), "sysexit", []>, TB;
933 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
936 //===----------------------------------------------------------------------===//
937 // Input/Output Instructions...
939 let Defs = [AL], Uses = [DX] in
940 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
941 "in{b}\t{%dx, %al|%AL, %DX}", []>;
942 let Defs = [AX], Uses = [DX] in
943 def IN16rr : I<0xED, RawFrm, (outs), (ins),
944 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
945 let Defs = [EAX], Uses = [DX] in
946 def IN32rr : I<0xED, RawFrm, (outs), (ins),
947 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
950 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
951 "in{b}\t{$port, %al|%AL, $port}", []>;
953 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
954 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
956 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
957 "in{l}\t{$port, %eax|%EAX, $port}", []>;
959 let Uses = [DX, AL] in
960 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
961 "out{b}\t{%al, %dx|%DX, %AL}", []>;
962 let Uses = [DX, AX] in
963 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
964 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
965 let Uses = [DX, EAX] in
966 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
967 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
970 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
971 "out{b}\t{%al, $port|$port, %AL}", []>;
973 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
974 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
976 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
977 "out{l}\t{%eax, $port|$port, %EAX}", []>;
979 def IN8 : I<0x6C, RawFrm, (outs), (ins),
981 def IN16 : I<0x6D, RawFrm, (outs), (ins),
982 "ins{w}", []>, OpSize;
983 def IN32 : I<0x6D, RawFrm, (outs), (ins),
986 //===----------------------------------------------------------------------===//
987 // Move Instructions...
989 let neverHasSideEffects = 1 in {
990 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
991 "mov{b}\t{$src, $dst|$dst, $src}", []>;
992 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
993 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
994 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
995 "mov{l}\t{$src, $dst|$dst, $src}", []>;
997 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
998 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
999 "mov{b}\t{$src, $dst|$dst, $src}",
1000 [(set GR8:$dst, imm:$src)]>;
1001 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1002 "mov{w}\t{$src, $dst|$dst, $src}",
1003 [(set GR16:$dst, imm:$src)]>, OpSize;
1004 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1005 "mov{l}\t{$src, $dst|$dst, $src}",
1006 [(set GR32:$dst, imm:$src)]>;
1009 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1010 "mov{b}\t{$src, $dst|$dst, $src}",
1011 [(store (i8 imm:$src), addr:$dst)]>;
1012 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1013 "mov{w}\t{$src, $dst|$dst, $src}",
1014 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1015 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1016 "mov{l}\t{$src, $dst|$dst, $src}",
1017 [(store (i32 imm:$src), addr:$dst)]>;
1019 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1020 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1021 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1022 "mov{b}\t{$src, %al|%al, $src}", []>;
1023 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1024 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1025 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1026 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1027 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1028 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1029 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1030 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1031 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1032 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1034 // Moves to and from segment registers
1035 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1036 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1037 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
1038 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1039 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1040 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1041 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
1042 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1043 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1044 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1045 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
1046 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1047 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1048 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1049 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
1050 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1052 let isCodeGenOnly = 1 in {
1053 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1054 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1055 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1056 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1057 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1058 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1061 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1062 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1063 "mov{b}\t{$src, $dst|$dst, $src}",
1064 [(set GR8:$dst, (loadi8 addr:$src))]>;
1065 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1066 "mov{w}\t{$src, $dst|$dst, $src}",
1067 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1068 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1069 "mov{l}\t{$src, $dst|$dst, $src}",
1070 [(set GR32:$dst, (loadi32 addr:$src))]>;
1073 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1074 "mov{b}\t{$src, $dst|$dst, $src}",
1075 [(store GR8:$src, addr:$dst)]>;
1076 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1077 "mov{w}\t{$src, $dst|$dst, $src}",
1078 [(store GR16:$src, addr:$dst)]>, OpSize;
1079 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1080 "mov{l}\t{$src, $dst|$dst, $src}",
1081 [(store GR32:$src, addr:$dst)]>;
1083 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1084 let neverHasSideEffects = 1 in
1085 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1086 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1089 canFoldAsLoad = 1, isReMaterializable = 1 in
1090 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1091 "mov{l}\t{$src, $dst|$dst, $src}",
1095 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1096 "mov{l}\t{$src, $dst|$dst, $src}",
1099 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1100 // that they can be used for copying and storing h registers, which can't be
1101 // encoded when a REX prefix is present.
1102 let neverHasSideEffects = 1 in
1103 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1104 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1105 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1107 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1108 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1109 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1111 canFoldAsLoad = 1, isReMaterializable = 1 in
1112 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1113 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1114 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1116 // Moves to and from debug registers
1117 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1118 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1119 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1120 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1122 // Moves to and from control registers
1123 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1124 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1125 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1126 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1128 //===----------------------------------------------------------------------===//
1129 // Fixed-Register Multiplication and Division Instructions...
1132 // Extra precision multiplication
1134 // AL is really implied by AX, by the registers in Defs must match the
1135 // SDNode results (i8, i32).
1136 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1137 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1138 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1139 // This probably ought to be moved to a def : Pat<> if the
1140 // syntax can be accepted.
1141 [(set AL, (mul AL, GR8:$src)),
1142 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1144 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1145 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1147 []>, OpSize; // AX,DX = AX*GR16
1149 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1150 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1152 []>; // EAX,EDX = EAX*GR32
1154 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1155 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1157 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1158 // This probably ought to be moved to a def : Pat<> if the
1159 // syntax can be accepted.
1160 [(set AL, (mul AL, (loadi8 addr:$src))),
1161 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1163 let mayLoad = 1, neverHasSideEffects = 1 in {
1164 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1165 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1167 []>, OpSize; // AX,DX = AX*[mem16]
1169 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1170 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1172 []>; // EAX,EDX = EAX*[mem32]
1175 let neverHasSideEffects = 1 in {
1176 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1177 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1179 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1180 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1181 OpSize; // AX,DX = AX*GR16
1182 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1183 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1184 // EAX,EDX = EAX*GR32
1185 let mayLoad = 1 in {
1186 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1187 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1188 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1189 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1190 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1191 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1192 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1193 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1194 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1196 } // neverHasSideEffects
1198 // unsigned division/remainder
1199 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1200 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1201 "div{b}\t$src", []>;
1202 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1203 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1204 "div{w}\t$src", []>, OpSize;
1205 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1206 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1207 "div{l}\t$src", []>;
1208 let mayLoad = 1 in {
1209 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1210 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1211 "div{b}\t$src", []>;
1212 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1213 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1214 "div{w}\t$src", []>, OpSize;
1215 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1216 // EDX:EAX/[mem32] = EAX,EDX
1217 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1218 "div{l}\t$src", []>;
1221 // Signed division/remainder.
1222 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1223 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1224 "idiv{b}\t$src", []>;
1225 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1226 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1227 "idiv{w}\t$src", []>, OpSize;
1228 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1229 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1230 "idiv{l}\t$src", []>;
1231 let mayLoad = 1, mayLoad = 1 in {
1232 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1233 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1234 "idiv{b}\t$src", []>;
1235 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1236 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1237 "idiv{w}\t$src", []>, OpSize;
1238 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1239 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1240 // EDX:EAX/[mem32] = EAX,EDX
1241 "idiv{l}\t$src", []>;
1244 //===----------------------------------------------------------------------===//
1245 // Two address Instructions.
1247 let Constraints = "$src1 = $dst" in {
1249 // Conditional moves
1250 let Uses = [EFLAGS] in {
1252 let Predicates = [HasCMov] in {
1253 let isCommutable = 1 in {
1254 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1255 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1256 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1258 X86_COND_B, EFLAGS))]>,
1260 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1261 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1262 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1264 X86_COND_B, EFLAGS))]>,
1266 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1267 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1268 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1269 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1270 X86_COND_AE, EFLAGS))]>,
1272 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1273 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1274 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1275 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1276 X86_COND_AE, EFLAGS))]>,
1278 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1279 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1280 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1281 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1282 X86_COND_E, EFLAGS))]>,
1284 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1285 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1286 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1287 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1288 X86_COND_E, EFLAGS))]>,
1290 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1291 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1292 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1293 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1294 X86_COND_NE, EFLAGS))]>,
1296 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1297 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1298 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1299 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1300 X86_COND_NE, EFLAGS))]>,
1302 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1303 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1304 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1305 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1306 X86_COND_BE, EFLAGS))]>,
1308 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1309 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1310 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1311 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1312 X86_COND_BE, EFLAGS))]>,
1314 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1315 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1316 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1318 X86_COND_A, EFLAGS))]>,
1320 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1321 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1322 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1324 X86_COND_A, EFLAGS))]>,
1326 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1327 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1328 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1329 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1330 X86_COND_L, EFLAGS))]>,
1332 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1333 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1334 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1335 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1336 X86_COND_L, EFLAGS))]>,
1338 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1339 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1340 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1342 X86_COND_GE, EFLAGS))]>,
1344 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1345 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1346 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1347 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1348 X86_COND_GE, EFLAGS))]>,
1350 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1351 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1352 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1354 X86_COND_LE, EFLAGS))]>,
1356 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1357 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1358 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1360 X86_COND_LE, EFLAGS))]>,
1362 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1363 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1364 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1366 X86_COND_G, EFLAGS))]>,
1368 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1369 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1370 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1371 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1372 X86_COND_G, EFLAGS))]>,
1374 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1375 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1376 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1377 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1378 X86_COND_S, EFLAGS))]>,
1380 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1381 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1382 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1384 X86_COND_S, EFLAGS))]>,
1386 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1387 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1388 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1389 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1390 X86_COND_NS, EFLAGS))]>,
1392 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1393 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1394 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1396 X86_COND_NS, EFLAGS))]>,
1398 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1399 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1400 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1401 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1402 X86_COND_P, EFLAGS))]>,
1404 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1405 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1406 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1408 X86_COND_P, EFLAGS))]>,
1410 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1411 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1412 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1413 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1414 X86_COND_NP, EFLAGS))]>,
1416 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1417 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1418 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1419 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1420 X86_COND_NP, EFLAGS))]>,
1422 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1423 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1424 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1426 X86_COND_O, EFLAGS))]>,
1428 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1429 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1430 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1431 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1432 X86_COND_O, EFLAGS))]>,
1434 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1435 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1436 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1438 X86_COND_NO, EFLAGS))]>,
1440 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1441 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1442 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1443 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1444 X86_COND_NO, EFLAGS))]>,
1446 } // isCommutable = 1
1448 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1449 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1450 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1452 X86_COND_B, EFLAGS))]>,
1454 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1455 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1456 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1458 X86_COND_B, EFLAGS))]>,
1460 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1461 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1462 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1464 X86_COND_AE, EFLAGS))]>,
1466 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1467 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1468 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1470 X86_COND_AE, EFLAGS))]>,
1472 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1473 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1474 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1476 X86_COND_E, EFLAGS))]>,
1478 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1479 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1480 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1481 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1482 X86_COND_E, EFLAGS))]>,
1484 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1485 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1486 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1487 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1488 X86_COND_NE, EFLAGS))]>,
1490 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1491 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1492 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1494 X86_COND_NE, EFLAGS))]>,
1496 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1497 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1498 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1499 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1500 X86_COND_BE, EFLAGS))]>,
1502 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1503 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1504 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1505 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1506 X86_COND_BE, EFLAGS))]>,
1508 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1509 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1510 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1512 X86_COND_A, EFLAGS))]>,
1514 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1515 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1516 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1517 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1518 X86_COND_A, EFLAGS))]>,
1520 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1521 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1522 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1523 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1524 X86_COND_L, EFLAGS))]>,
1526 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1527 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1528 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1529 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1530 X86_COND_L, EFLAGS))]>,
1532 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1533 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1534 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1536 X86_COND_GE, EFLAGS))]>,
1538 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1539 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1540 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1542 X86_COND_GE, EFLAGS))]>,
1544 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1545 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1546 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1547 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1548 X86_COND_LE, EFLAGS))]>,
1550 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1551 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1552 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1553 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1554 X86_COND_LE, EFLAGS))]>,
1556 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1557 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1558 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1560 X86_COND_G, EFLAGS))]>,
1562 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1563 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1564 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1565 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1566 X86_COND_G, EFLAGS))]>,
1568 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1569 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1570 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1571 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1572 X86_COND_S, EFLAGS))]>,
1574 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1575 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1576 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1577 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1578 X86_COND_S, EFLAGS))]>,
1580 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1581 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1582 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1583 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1584 X86_COND_NS, EFLAGS))]>,
1586 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1587 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1588 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1589 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1590 X86_COND_NS, EFLAGS))]>,
1592 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1593 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1594 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1596 X86_COND_P, EFLAGS))]>,
1598 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1599 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1600 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1601 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1602 X86_COND_P, EFLAGS))]>,
1604 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1605 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1606 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1607 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1608 X86_COND_NP, EFLAGS))]>,
1610 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1611 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1612 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1613 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1614 X86_COND_NP, EFLAGS))]>,
1616 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1617 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1618 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1619 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1620 X86_COND_O, EFLAGS))]>,
1622 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1623 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1624 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1625 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1626 X86_COND_O, EFLAGS))]>,
1628 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1629 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1630 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1631 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1632 X86_COND_NO, EFLAGS))]>,
1634 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1635 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1636 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1637 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1638 X86_COND_NO, EFLAGS))]>,
1640 } // Predicates = [HasCMov]
1642 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1643 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1644 // however that requires promoting the operands, and can induce additional
1645 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1646 // clobber EFLAGS, because if one of the operands is zero, the expansion
1647 // could involve an xor.
1648 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1649 def CMOV_GR8 : I<0, Pseudo,
1650 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1651 "#CMOV_GR8 PSEUDO!",
1652 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1653 imm:$cond, EFLAGS))]>;
1655 let Predicates = [NoCMov] in {
1656 def CMOV_GR32 : I<0, Pseudo,
1657 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1658 "#CMOV_GR32* PSEUDO!",
1660 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1661 def CMOV_GR16 : I<0, Pseudo,
1662 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1663 "#CMOV_GR16* PSEUDO!",
1665 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1666 def CMOV_RFP32 : I<0, Pseudo,
1668 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1669 "#CMOV_RFP32 PSEUDO!",
1671 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1673 def CMOV_RFP64 : I<0, Pseudo,
1675 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1676 "#CMOV_RFP64 PSEUDO!",
1678 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1680 def CMOV_RFP80 : I<0, Pseudo,
1682 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1683 "#CMOV_RFP80 PSEUDO!",
1685 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1687 } // Predicates = [NoCMov]
1688 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1689 } // Uses = [EFLAGS]
1692 // unary instructions
1693 let CodeSize = 2 in {
1694 let Defs = [EFLAGS] in {
1695 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1697 [(set GR8:$dst, (ineg GR8:$src1)),
1698 (implicit EFLAGS)]>;
1699 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1701 [(set GR16:$dst, (ineg GR16:$src1)),
1702 (implicit EFLAGS)]>, OpSize;
1703 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1705 [(set GR32:$dst, (ineg GR32:$src1)),
1706 (implicit EFLAGS)]>;
1708 let Constraints = "" in {
1709 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1711 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1712 (implicit EFLAGS)]>;
1713 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1715 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1716 (implicit EFLAGS)]>, OpSize;
1717 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1719 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1720 (implicit EFLAGS)]>;
1721 } // Constraints = ""
1722 } // Defs = [EFLAGS]
1724 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1725 let AddedComplexity = 15 in {
1726 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1728 [(set GR8:$dst, (not GR8:$src1))]>;
1729 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1731 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1732 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1734 [(set GR32:$dst, (not GR32:$src1))]>;
1736 let Constraints = "" in {
1737 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1739 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1740 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1742 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1743 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1745 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1746 } // Constraints = ""
1749 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1750 let Defs = [EFLAGS] in {
1752 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1754 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1756 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1757 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1759 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1760 OpSize, Requires<[In32BitMode]>;
1761 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1763 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1764 Requires<[In32BitMode]>;
1766 let Constraints = "", CodeSize = 2 in {
1767 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1768 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1769 (implicit EFLAGS)]>;
1770 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1771 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1772 (implicit EFLAGS)]>,
1773 OpSize, Requires<[In32BitMode]>;
1774 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1775 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1776 (implicit EFLAGS)]>,
1777 Requires<[In32BitMode]>;
1778 } // Constraints = "", CodeSize = 2
1781 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1783 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1784 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1785 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1787 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1788 OpSize, Requires<[In32BitMode]>;
1789 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1791 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1792 Requires<[In32BitMode]>;
1795 let Constraints = "", CodeSize = 2 in {
1796 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1797 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1798 (implicit EFLAGS)]>;
1799 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1800 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1801 (implicit EFLAGS)]>,
1802 OpSize, Requires<[In32BitMode]>;
1803 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1804 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1805 (implicit EFLAGS)]>,
1806 Requires<[In32BitMode]>;
1807 } // Constraints = "", CodeSize = 2
1808 } // Defs = [EFLAGS]
1810 // Logical operators...
1811 let Defs = [EFLAGS] in {
1812 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1813 def AND8rr : I<0x20, MRMDestReg,
1814 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1815 "and{b}\t{$src2, $dst|$dst, $src2}",
1816 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1817 def AND16rr : I<0x21, MRMDestReg,
1818 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1819 "and{w}\t{$src2, $dst|$dst, $src2}",
1820 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1821 GR16:$src2))]>, OpSize;
1822 def AND32rr : I<0x21, MRMDestReg,
1823 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1824 "and{l}\t{$src2, $dst|$dst, $src2}",
1825 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1829 // AND instructions with the destination register in REG and the source register
1830 // in R/M. Included for the disassembler.
1831 let isCodeGenOnly = 1 in {
1832 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1833 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1834 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1835 (ins GR16:$src1, GR16:$src2),
1836 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1837 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1838 (ins GR32:$src1, GR32:$src2),
1839 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1842 def AND8rm : I<0x22, MRMSrcMem,
1843 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1844 "and{b}\t{$src2, $dst|$dst, $src2}",
1845 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1846 (loadi8 addr:$src2)))]>;
1847 def AND16rm : I<0x23, MRMSrcMem,
1848 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1849 "and{w}\t{$src2, $dst|$dst, $src2}",
1850 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1851 (loadi16 addr:$src2)))]>,
1853 def AND32rm : I<0x23, MRMSrcMem,
1854 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1855 "and{l}\t{$src2, $dst|$dst, $src2}",
1856 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1857 (loadi32 addr:$src2)))]>;
1859 def AND8ri : Ii8<0x80, MRM4r,
1860 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1861 "and{b}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1864 def AND16ri : Ii16<0x81, MRM4r,
1865 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1866 "and{w}\t{$src2, $dst|$dst, $src2}",
1867 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1868 imm:$src2))]>, OpSize;
1869 def AND32ri : Ii32<0x81, MRM4r,
1870 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1871 "and{l}\t{$src2, $dst|$dst, $src2}",
1872 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1874 def AND16ri8 : Ii8<0x83, MRM4r,
1875 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1876 "and{w}\t{$src2, $dst|$dst, $src2}",
1877 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1878 i16immSExt8:$src2))]>,
1880 def AND32ri8 : Ii8<0x83, MRM4r,
1881 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1882 "and{l}\t{$src2, $dst|$dst, $src2}",
1883 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1884 i32immSExt8:$src2))]>;
1886 let Constraints = "" in {
1887 def AND8mr : I<0x20, MRMDestMem,
1888 (outs), (ins i8mem :$dst, GR8 :$src),
1889 "and{b}\t{$src, $dst|$dst, $src}",
1890 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1891 (implicit EFLAGS)]>;
1892 def AND16mr : I<0x21, MRMDestMem,
1893 (outs), (ins i16mem:$dst, GR16:$src),
1894 "and{w}\t{$src, $dst|$dst, $src}",
1895 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1896 (implicit EFLAGS)]>,
1898 def AND32mr : I<0x21, MRMDestMem,
1899 (outs), (ins i32mem:$dst, GR32:$src),
1900 "and{l}\t{$src, $dst|$dst, $src}",
1901 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1902 (implicit EFLAGS)]>;
1903 def AND8mi : Ii8<0x80, MRM4m,
1904 (outs), (ins i8mem :$dst, i8imm :$src),
1905 "and{b}\t{$src, $dst|$dst, $src}",
1906 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1907 (implicit EFLAGS)]>;
1908 def AND16mi : Ii16<0x81, MRM4m,
1909 (outs), (ins i16mem:$dst, i16imm:$src),
1910 "and{w}\t{$src, $dst|$dst, $src}",
1911 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1912 (implicit EFLAGS)]>,
1914 def AND32mi : Ii32<0x81, MRM4m,
1915 (outs), (ins i32mem:$dst, i32imm:$src),
1916 "and{l}\t{$src, $dst|$dst, $src}",
1917 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1918 (implicit EFLAGS)]>;
1919 def AND16mi8 : Ii8<0x83, MRM4m,
1920 (outs), (ins i16mem:$dst, i16i8imm :$src),
1921 "and{w}\t{$src, $dst|$dst, $src}",
1922 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1923 (implicit EFLAGS)]>,
1925 def AND32mi8 : Ii8<0x83, MRM4m,
1926 (outs), (ins i32mem:$dst, i32i8imm :$src),
1927 "and{l}\t{$src, $dst|$dst, $src}",
1928 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1929 (implicit EFLAGS)]>;
1931 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1932 "and{b}\t{$src, %al|%al, $src}", []>;
1933 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1934 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1935 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1936 "and{l}\t{$src, %eax|%eax, $src}", []>;
1938 } // Constraints = ""
1941 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1942 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1943 (ins GR8 :$src1, GR8 :$src2),
1944 "or{b}\t{$src2, $dst|$dst, $src2}",
1945 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1946 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1947 (ins GR16:$src1, GR16:$src2),
1948 "or{w}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1951 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1952 (ins GR32:$src1, GR32:$src2),
1953 "or{l}\t{$src2, $dst|$dst, $src2}",
1954 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1957 // OR instructions with the destination register in REG and the source register
1958 // in R/M. Included for the disassembler.
1959 let isCodeGenOnly = 1 in {
1960 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1961 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1962 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1963 (ins GR16:$src1, GR16:$src2),
1964 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1965 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1966 (ins GR32:$src1, GR32:$src2),
1967 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1970 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1971 (ins GR8 :$src1, i8mem :$src2),
1972 "or{b}\t{$src2, $dst|$dst, $src2}",
1973 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1974 (load addr:$src2)))]>;
1975 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1976 (ins GR16:$src1, i16mem:$src2),
1977 "or{w}\t{$src2, $dst|$dst, $src2}",
1978 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1979 (load addr:$src2)))]>,
1981 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1982 (ins GR32:$src1, i32mem:$src2),
1983 "or{l}\t{$src2, $dst|$dst, $src2}",
1984 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1985 (load addr:$src2)))]>;
1987 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1988 (ins GR8 :$src1, i8imm:$src2),
1989 "or{b}\t{$src2, $dst|$dst, $src2}",
1990 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1991 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1992 (ins GR16:$src1, i16imm:$src2),
1993 "or{w}\t{$src2, $dst|$dst, $src2}",
1994 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1995 imm:$src2))]>, OpSize;
1996 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1997 (ins GR32:$src1, i32imm:$src2),
1998 "or{l}\t{$src2, $dst|$dst, $src2}",
1999 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2002 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
2003 (ins GR16:$src1, i16i8imm:$src2),
2004 "or{w}\t{$src2, $dst|$dst, $src2}",
2005 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2006 i16immSExt8:$src2))]>, OpSize;
2007 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
2008 (ins GR32:$src1, i32i8imm:$src2),
2009 "or{l}\t{$src2, $dst|$dst, $src2}",
2010 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2011 i32immSExt8:$src2))]>;
2012 let Constraints = "" in {
2013 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2014 "or{b}\t{$src, $dst|$dst, $src}",
2015 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
2016 (implicit EFLAGS)]>;
2017 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2018 "or{w}\t{$src, $dst|$dst, $src}",
2019 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
2020 (implicit EFLAGS)]>, OpSize;
2021 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2022 "or{l}\t{$src, $dst|$dst, $src}",
2023 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
2024 (implicit EFLAGS)]>;
2025 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2026 "or{b}\t{$src, $dst|$dst, $src}",
2027 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
2028 (implicit EFLAGS)]>;
2029 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
2030 "or{w}\t{$src, $dst|$dst, $src}",
2031 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
2032 (implicit EFLAGS)]>,
2034 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
2035 "or{l}\t{$src, $dst|$dst, $src}",
2036 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
2037 (implicit EFLAGS)]>;
2038 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
2039 "or{w}\t{$src, $dst|$dst, $src}",
2040 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2041 (implicit EFLAGS)]>,
2043 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2044 "or{l}\t{$src, $dst|$dst, $src}",
2045 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2046 (implicit EFLAGS)]>;
2048 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2049 "or{b}\t{$src, %al|%al, $src}", []>;
2050 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2051 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2052 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2053 "or{l}\t{$src, %eax|%eax, $src}", []>;
2054 } // Constraints = ""
2057 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2058 def XOR8rr : I<0x30, MRMDestReg,
2059 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2060 "xor{b}\t{$src2, $dst|$dst, $src2}",
2061 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2063 def XOR16rr : I<0x31, MRMDestReg,
2064 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2065 "xor{w}\t{$src2, $dst|$dst, $src2}",
2066 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2067 GR16:$src2))]>, OpSize;
2068 def XOR32rr : I<0x31, MRMDestReg,
2069 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2070 "xor{l}\t{$src2, $dst|$dst, $src2}",
2071 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2073 } // isCommutable = 1
2075 // XOR instructions with the destination register in REG and the source register
2076 // in R/M. Included for the disassembler.
2077 let isCodeGenOnly = 1 in {
2078 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2079 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2080 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2081 (ins GR16:$src1, GR16:$src2),
2082 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2083 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2084 (ins GR32:$src1, GR32:$src2),
2085 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2088 def XOR8rm : I<0x32, MRMSrcMem,
2089 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2090 "xor{b}\t{$src2, $dst|$dst, $src2}",
2091 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2092 (load addr:$src2)))]>;
2093 def XOR16rm : I<0x33, MRMSrcMem,
2094 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2095 "xor{w}\t{$src2, $dst|$dst, $src2}",
2096 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2097 (load addr:$src2)))]>,
2099 def XOR32rm : I<0x33, MRMSrcMem,
2100 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2101 "xor{l}\t{$src2, $dst|$dst, $src2}",
2102 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2103 (load addr:$src2)))]>;
2105 def XOR8ri : Ii8<0x80, MRM6r,
2106 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2107 "xor{b}\t{$src2, $dst|$dst, $src2}",
2108 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2109 def XOR16ri : Ii16<0x81, MRM6r,
2110 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2111 "xor{w}\t{$src2, $dst|$dst, $src2}",
2112 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2113 imm:$src2))]>, OpSize;
2114 def XOR32ri : Ii32<0x81, MRM6r,
2115 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2116 "xor{l}\t{$src2, $dst|$dst, $src2}",
2117 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2119 def XOR16ri8 : Ii8<0x83, MRM6r,
2120 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2121 "xor{w}\t{$src2, $dst|$dst, $src2}",
2122 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2123 i16immSExt8:$src2))]>,
2125 def XOR32ri8 : Ii8<0x83, MRM6r,
2126 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2127 "xor{l}\t{$src2, $dst|$dst, $src2}",
2128 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2129 i32immSExt8:$src2))]>;
2131 let Constraints = "" in {
2132 def XOR8mr : I<0x30, MRMDestMem,
2133 (outs), (ins i8mem :$dst, GR8 :$src),
2134 "xor{b}\t{$src, $dst|$dst, $src}",
2135 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2136 (implicit EFLAGS)]>;
2137 def XOR16mr : I<0x31, MRMDestMem,
2138 (outs), (ins i16mem:$dst, GR16:$src),
2139 "xor{w}\t{$src, $dst|$dst, $src}",
2140 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2141 (implicit EFLAGS)]>,
2143 def XOR32mr : I<0x31, MRMDestMem,
2144 (outs), (ins i32mem:$dst, GR32:$src),
2145 "xor{l}\t{$src, $dst|$dst, $src}",
2146 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2147 (implicit EFLAGS)]>;
2148 def XOR8mi : Ii8<0x80, MRM6m,
2149 (outs), (ins i8mem :$dst, i8imm :$src),
2150 "xor{b}\t{$src, $dst|$dst, $src}",
2151 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2152 (implicit EFLAGS)]>;
2153 def XOR16mi : Ii16<0x81, MRM6m,
2154 (outs), (ins i16mem:$dst, i16imm:$src),
2155 "xor{w}\t{$src, $dst|$dst, $src}",
2156 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2157 (implicit EFLAGS)]>,
2159 def XOR32mi : Ii32<0x81, MRM6m,
2160 (outs), (ins i32mem:$dst, i32imm:$src),
2161 "xor{l}\t{$src, $dst|$dst, $src}",
2162 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2163 (implicit EFLAGS)]>;
2164 def XOR16mi8 : Ii8<0x83, MRM6m,
2165 (outs), (ins i16mem:$dst, i16i8imm :$src),
2166 "xor{w}\t{$src, $dst|$dst, $src}",
2167 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2168 (implicit EFLAGS)]>,
2170 def XOR32mi8 : Ii8<0x83, MRM6m,
2171 (outs), (ins i32mem:$dst, i32i8imm :$src),
2172 "xor{l}\t{$src, $dst|$dst, $src}",
2173 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2174 (implicit EFLAGS)]>;
2176 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2177 "xor{b}\t{$src, %al|%al, $src}", []>;
2178 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2179 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2180 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2181 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2182 } // Constraints = ""
2183 } // Defs = [EFLAGS]
2185 // Shift instructions
2186 let Defs = [EFLAGS] in {
2187 let Uses = [CL] in {
2188 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2189 "shl{b}\t{%cl, $dst|$dst, CL}",
2190 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
2191 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2192 "shl{w}\t{%cl, $dst|$dst, CL}",
2193 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
2194 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2195 "shl{l}\t{%cl, $dst|$dst, CL}",
2196 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
2199 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2200 "shl{b}\t{$src2, $dst|$dst, $src2}",
2201 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2203 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2204 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2205 "shl{w}\t{$src2, $dst|$dst, $src2}",
2206 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2207 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2208 "shl{l}\t{$src2, $dst|$dst, $src2}",
2209 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2211 // NOTE: We don't include patterns for shifts of a register by one, because
2212 // 'add reg,reg' is cheaper.
2214 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2215 "shl{b}\t$dst", []>;
2216 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2217 "shl{w}\t$dst", []>, OpSize;
2218 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2219 "shl{l}\t$dst", []>;
2221 } // isConvertibleToThreeAddress = 1
2223 let Constraints = "" in {
2224 let Uses = [CL] in {
2225 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2226 "shl{b}\t{%cl, $dst|$dst, CL}",
2227 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2228 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2229 "shl{w}\t{%cl, $dst|$dst, CL}",
2230 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2231 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2232 "shl{l}\t{%cl, $dst|$dst, CL}",
2233 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2235 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2236 "shl{b}\t{$src, $dst|$dst, $src}",
2237 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2238 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2239 "shl{w}\t{$src, $dst|$dst, $src}",
2240 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2242 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2243 "shl{l}\t{$src, $dst|$dst, $src}",
2244 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2247 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2249 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2250 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2252 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2254 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2256 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2257 } // Constraints = ""
2259 let Uses = [CL] in {
2260 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
2261 "shr{b}\t{%cl, $dst|$dst, CL}",
2262 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
2263 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2264 "shr{w}\t{%cl, $dst|$dst, CL}",
2265 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
2266 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2267 "shr{l}\t{%cl, $dst|$dst, CL}",
2268 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
2271 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2272 "shr{b}\t{$src2, $dst|$dst, $src2}",
2273 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2274 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2275 "shr{w}\t{$src2, $dst|$dst, $src2}",
2276 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2277 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2278 "shr{l}\t{$src2, $dst|$dst, $src2}",
2279 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2282 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2284 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2285 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2287 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2288 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2290 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2292 let Constraints = "" in {
2293 let Uses = [CL] in {
2294 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2295 "shr{b}\t{%cl, $dst|$dst, CL}",
2296 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2297 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2298 "shr{w}\t{%cl, $dst|$dst, CL}",
2299 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2301 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2302 "shr{l}\t{%cl, $dst|$dst, CL}",
2303 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2305 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2306 "shr{b}\t{$src, $dst|$dst, $src}",
2307 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2308 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2309 "shr{w}\t{$src, $dst|$dst, $src}",
2310 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2312 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2313 "shr{l}\t{$src, $dst|$dst, $src}",
2314 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2317 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2319 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2320 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2322 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2323 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2325 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2326 } // Constraints = ""
2328 let Uses = [CL] in {
2329 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2330 "sar{b}\t{%cl, $dst|$dst, CL}",
2331 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2332 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2333 "sar{w}\t{%cl, $dst|$dst, CL}",
2334 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2335 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2336 "sar{l}\t{%cl, $dst|$dst, CL}",
2337 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2340 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2341 "sar{b}\t{$src2, $dst|$dst, $src2}",
2342 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2343 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2344 "sar{w}\t{$src2, $dst|$dst, $src2}",
2345 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2347 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2348 "sar{l}\t{$src2, $dst|$dst, $src2}",
2349 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2352 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2354 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2355 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2357 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2358 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2360 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2362 let Constraints = "" in {
2363 let Uses = [CL] in {
2364 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2365 "sar{b}\t{%cl, $dst|$dst, CL}",
2366 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2367 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2368 "sar{w}\t{%cl, $dst|$dst, CL}",
2369 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2370 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2371 "sar{l}\t{%cl, $dst|$dst, CL}",
2372 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2374 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2375 "sar{b}\t{$src, $dst|$dst, $src}",
2376 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2377 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2378 "sar{w}\t{$src, $dst|$dst, $src}",
2379 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2381 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2382 "sar{l}\t{$src, $dst|$dst, $src}",
2383 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2386 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2388 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2389 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2391 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2393 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2395 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2396 } // Constraints = ""
2398 // Rotate instructions
2400 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2401 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2402 let Uses = [CL] in {
2403 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2404 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2406 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2407 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2409 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2410 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2411 let Uses = [CL] in {
2412 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2413 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2415 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2416 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2418 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2419 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2420 let Uses = [CL] in {
2421 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2422 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2424 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2425 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2427 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2428 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2429 let Uses = [CL] in {
2430 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2431 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2433 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2434 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2436 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2437 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2438 let Uses = [CL] in {
2439 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2440 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2442 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2443 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2445 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2446 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2447 let Uses = [CL] in {
2448 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2449 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2451 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2452 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2454 let Constraints = "" in {
2455 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2456 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2457 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2458 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2459 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2460 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2461 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2462 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2463 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2464 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2465 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2466 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2467 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2468 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2469 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2470 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2471 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2472 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2473 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2474 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2475 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2476 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2477 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2478 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2480 let Uses = [CL] in {
2481 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2482 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2483 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2484 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2485 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2486 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2487 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2488 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2489 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2490 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2491 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2492 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2494 } // Constraints = ""
2496 // FIXME: provide shorter instructions when imm8 == 1
2497 let Uses = [CL] in {
2498 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2499 "rol{b}\t{%cl, $dst|$dst, CL}",
2500 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2501 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2502 "rol{w}\t{%cl, $dst|$dst, CL}",
2503 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2504 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2505 "rol{l}\t{%cl, $dst|$dst, CL}",
2506 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2509 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2510 "rol{b}\t{$src2, $dst|$dst, $src2}",
2511 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2512 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2513 "rol{w}\t{$src2, $dst|$dst, $src2}",
2514 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2516 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2517 "rol{l}\t{$src2, $dst|$dst, $src2}",
2518 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2521 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2523 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2524 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2526 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2527 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2529 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2531 let Constraints = "" in {
2532 let Uses = [CL] in {
2533 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2534 "rol{b}\t{%cl, $dst|$dst, CL}",
2535 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2536 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2537 "rol{w}\t{%cl, $dst|$dst, CL}",
2538 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2539 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2540 "rol{l}\t{%cl, $dst|$dst, CL}",
2541 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2543 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2544 "rol{b}\t{$src, $dst|$dst, $src}",
2545 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2546 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2547 "rol{w}\t{$src, $dst|$dst, $src}",
2548 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2550 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2551 "rol{l}\t{$src, $dst|$dst, $src}",
2552 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2555 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2557 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2558 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2560 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2562 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2564 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2565 } // Constraints = ""
2567 let Uses = [CL] in {
2568 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2569 "ror{b}\t{%cl, $dst|$dst, CL}",
2570 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2571 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2572 "ror{w}\t{%cl, $dst|$dst, CL}",
2573 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2574 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2575 "ror{l}\t{%cl, $dst|$dst, CL}",
2576 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2579 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2580 "ror{b}\t{$src2, $dst|$dst, $src2}",
2581 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2582 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2583 "ror{w}\t{$src2, $dst|$dst, $src2}",
2584 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2586 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2587 "ror{l}\t{$src2, $dst|$dst, $src2}",
2588 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2591 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2593 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2594 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2596 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2597 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2599 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2601 let Constraints = "" in {
2602 let Uses = [CL] in {
2603 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2604 "ror{b}\t{%cl, $dst|$dst, CL}",
2605 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2606 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2607 "ror{w}\t{%cl, $dst|$dst, CL}",
2608 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2609 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2610 "ror{l}\t{%cl, $dst|$dst, CL}",
2611 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2613 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2614 "ror{b}\t{$src, $dst|$dst, $src}",
2615 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2616 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2617 "ror{w}\t{$src, $dst|$dst, $src}",
2618 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2620 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2621 "ror{l}\t{$src, $dst|$dst, $src}",
2622 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2625 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2627 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2628 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2630 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2632 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2634 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2635 } // Constraints = ""
2638 // Double shift instructions (generalizations of rotate)
2639 let Uses = [CL] in {
2640 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2641 (ins GR32:$src1, GR32:$src2),
2642 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2643 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2644 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2645 (ins GR32:$src1, GR32:$src2),
2646 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2647 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2648 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2649 (ins GR16:$src1, GR16:$src2),
2650 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2651 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2653 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2654 (ins GR16:$src1, GR16:$src2),
2655 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2656 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2660 let isCommutable = 1 in { // These instructions commute to each other.
2661 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2663 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2664 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2665 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2668 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2670 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2671 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2672 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2675 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2677 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2678 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2679 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2682 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2684 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2685 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2686 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2691 let Constraints = "" in {
2692 let Uses = [CL] in {
2693 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2694 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2695 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2697 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2698 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2699 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2702 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2703 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2704 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2705 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2706 (i8 imm:$src3)), addr:$dst)]>,
2708 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2709 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2710 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2711 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2712 (i8 imm:$src3)), addr:$dst)]>,
2715 let Uses = [CL] in {
2716 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2717 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2718 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2719 addr:$dst)]>, TB, OpSize;
2720 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2721 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2722 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2723 addr:$dst)]>, TB, OpSize;
2725 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2726 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2727 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2728 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2729 (i8 imm:$src3)), addr:$dst)]>,
2731 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2732 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2733 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2734 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2735 (i8 imm:$src3)), addr:$dst)]>,
2737 } // Constraints = ""
2738 } // Defs = [EFLAGS]
2742 let Defs = [EFLAGS] in {
2743 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2744 // Register-Register Addition
2745 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2746 (ins GR8 :$src1, GR8 :$src2),
2747 "add{b}\t{$src2, $dst|$dst, $src2}",
2748 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2750 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2751 // Register-Register Addition
2752 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2753 (ins GR16:$src1, GR16:$src2),
2754 "add{w}\t{$src2, $dst|$dst, $src2}",
2755 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2756 GR16:$src2))]>, OpSize;
2757 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2758 (ins GR32:$src1, GR32:$src2),
2759 "add{l}\t{$src2, $dst|$dst, $src2}",
2760 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2762 } // end isConvertibleToThreeAddress
2763 } // end isCommutable
2765 // These are alternate spellings for use by the disassembler, we mark them as
2766 // code gen only to ensure they aren't matched by the assembler.
2767 let isCodeGenOnly = 1 in {
2768 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2769 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2770 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2771 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2772 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2773 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2776 // Register-Memory Addition
2777 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2778 (ins GR8 :$src1, i8mem :$src2),
2779 "add{b}\t{$src2, $dst|$dst, $src2}",
2780 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2781 (load addr:$src2)))]>;
2782 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2783 (ins GR16:$src1, i16mem:$src2),
2784 "add{w}\t{$src2, $dst|$dst, $src2}",
2785 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2786 (load addr:$src2)))]>, OpSize;
2787 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2788 (ins GR32:$src1, i32mem:$src2),
2789 "add{l}\t{$src2, $dst|$dst, $src2}",
2790 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2791 (load addr:$src2)))]>;
2793 // Register-Integer Addition
2794 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2795 "add{b}\t{$src2, $dst|$dst, $src2}",
2796 [(set GR8:$dst, EFLAGS,
2797 (X86add_flag GR8:$src1, imm:$src2))]>;
2799 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2800 // Register-Integer Addition
2801 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2802 (ins GR16:$src1, i16imm:$src2),
2803 "add{w}\t{$src2, $dst|$dst, $src2}",
2804 [(set GR16:$dst, EFLAGS,
2805 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2806 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2807 (ins GR32:$src1, i32imm:$src2),
2808 "add{l}\t{$src2, $dst|$dst, $src2}",
2809 [(set GR32:$dst, EFLAGS,
2810 (X86add_flag GR32:$src1, imm:$src2))]>;
2811 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2812 (ins GR16:$src1, i16i8imm:$src2),
2813 "add{w}\t{$src2, $dst|$dst, $src2}",
2814 [(set GR16:$dst, EFLAGS,
2815 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2816 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2817 (ins GR32:$src1, i32i8imm:$src2),
2818 "add{l}\t{$src2, $dst|$dst, $src2}",
2819 [(set GR32:$dst, EFLAGS,
2820 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2823 let Constraints = "" in {
2824 // Memory-Register Addition
2825 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2826 "add{b}\t{$src2, $dst|$dst, $src2}",
2827 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2828 (implicit EFLAGS)]>;
2829 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2830 "add{w}\t{$src2, $dst|$dst, $src2}",
2831 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2832 (implicit EFLAGS)]>, OpSize;
2833 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2834 "add{l}\t{$src2, $dst|$dst, $src2}",
2835 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2836 (implicit EFLAGS)]>;
2837 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2838 "add{b}\t{$src2, $dst|$dst, $src2}",
2839 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2840 (implicit EFLAGS)]>;
2841 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2842 "add{w}\t{$src2, $dst|$dst, $src2}",
2843 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2844 (implicit EFLAGS)]>, OpSize;
2845 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2846 "add{l}\t{$src2, $dst|$dst, $src2}",
2847 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2848 (implicit EFLAGS)]>;
2849 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2850 "add{w}\t{$src2, $dst|$dst, $src2}",
2851 [(store (add (load addr:$dst), i16immSExt8:$src2),
2853 (implicit EFLAGS)]>, OpSize;
2854 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2855 "add{l}\t{$src2, $dst|$dst, $src2}",
2856 [(store (add (load addr:$dst), i32immSExt8:$src2),
2858 (implicit EFLAGS)]>;
2861 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2862 "add{b}\t{$src, %al|%al, $src}", []>;
2863 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2864 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2865 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2866 "add{l}\t{$src, %eax|%eax, $src}", []>;
2867 } // Constraints = ""
2869 let Uses = [EFLAGS] in {
2870 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2871 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2872 "adc{b}\t{$src2, $dst|$dst, $src2}",
2873 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2874 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2875 (ins GR16:$src1, GR16:$src2),
2876 "adc{w}\t{$src2, $dst|$dst, $src2}",
2877 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2878 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2879 (ins GR32:$src1, GR32:$src2),
2880 "adc{l}\t{$src2, $dst|$dst, $src2}",
2881 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2884 let isCodeGenOnly = 1 in {
2885 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2886 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2887 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2888 (ins GR16:$src1, GR16:$src2),
2889 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2890 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2891 (ins GR32:$src1, GR32:$src2),
2892 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2895 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2896 (ins GR8:$src1, i8mem:$src2),
2897 "adc{b}\t{$src2, $dst|$dst, $src2}",
2898 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2899 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2900 (ins GR16:$src1, i16mem:$src2),
2901 "adc{w}\t{$src2, $dst|$dst, $src2}",
2902 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2904 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2905 (ins GR32:$src1, i32mem:$src2),
2906 "adc{l}\t{$src2, $dst|$dst, $src2}",
2907 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2908 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2909 "adc{b}\t{$src2, $dst|$dst, $src2}",
2910 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2911 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2912 (ins GR16:$src1, i16imm:$src2),
2913 "adc{w}\t{$src2, $dst|$dst, $src2}",
2914 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2915 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2916 (ins GR16:$src1, i16i8imm:$src2),
2917 "adc{w}\t{$src2, $dst|$dst, $src2}",
2918 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2920 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2921 (ins GR32:$src1, i32imm:$src2),
2922 "adc{l}\t{$src2, $dst|$dst, $src2}",
2923 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2924 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2925 (ins GR32:$src1, i32i8imm:$src2),
2926 "adc{l}\t{$src2, $dst|$dst, $src2}",
2927 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2929 let Constraints = "" in {
2930 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2931 "adc{b}\t{$src2, $dst|$dst, $src2}",
2932 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2933 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2934 "adc{w}\t{$src2, $dst|$dst, $src2}",
2935 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2937 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2938 "adc{l}\t{$src2, $dst|$dst, $src2}",
2939 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2940 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2941 "adc{b}\t{$src2, $dst|$dst, $src2}",
2942 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2943 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2944 "adc{w}\t{$src2, $dst|$dst, $src2}",
2945 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2947 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2948 "adc{w}\t{$src2, $dst|$dst, $src2}",
2949 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2951 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2952 "adc{l}\t{$src2, $dst|$dst, $src2}",
2953 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2954 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2955 "adc{l}\t{$src2, $dst|$dst, $src2}",
2956 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2958 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2959 "adc{b}\t{$src, %al|%al, $src}", []>;
2960 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2961 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2962 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2963 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2964 } // Constraints = ""
2965 } // Uses = [EFLAGS]
2967 // Register-Register Subtraction
2968 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2969 "sub{b}\t{$src2, $dst|$dst, $src2}",
2970 [(set GR8:$dst, EFLAGS,
2971 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2972 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2973 "sub{w}\t{$src2, $dst|$dst, $src2}",
2974 [(set GR16:$dst, EFLAGS,
2975 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2976 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2977 "sub{l}\t{$src2, $dst|$dst, $src2}",
2978 [(set GR32:$dst, EFLAGS,
2979 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2981 let isCodeGenOnly = 1 in {
2982 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2983 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2984 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2985 (ins GR16:$src1, GR16:$src2),
2986 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2987 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2988 (ins GR32:$src1, GR32:$src2),
2989 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2992 // Register-Memory Subtraction
2993 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2994 (ins GR8 :$src1, i8mem :$src2),
2995 "sub{b}\t{$src2, $dst|$dst, $src2}",
2996 [(set GR8:$dst, EFLAGS,
2997 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2998 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2999 (ins GR16:$src1, i16mem:$src2),
3000 "sub{w}\t{$src2, $dst|$dst, $src2}",
3001 [(set GR16:$dst, EFLAGS,
3002 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
3003 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
3004 (ins GR32:$src1, i32mem:$src2),
3005 "sub{l}\t{$src2, $dst|$dst, $src2}",
3006 [(set GR32:$dst, EFLAGS,
3007 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
3009 // Register-Integer Subtraction
3010 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
3011 (ins GR8:$src1, i8imm:$src2),
3012 "sub{b}\t{$src2, $dst|$dst, $src2}",
3013 [(set GR8:$dst, EFLAGS,
3014 (X86sub_flag GR8:$src1, imm:$src2))]>;
3015 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
3016 (ins GR16:$src1, i16imm:$src2),
3017 "sub{w}\t{$src2, $dst|$dst, $src2}",
3018 [(set GR16:$dst, EFLAGS,
3019 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
3020 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
3021 (ins GR32:$src1, i32imm:$src2),
3022 "sub{l}\t{$src2, $dst|$dst, $src2}",
3023 [(set GR32:$dst, EFLAGS,
3024 (X86sub_flag GR32:$src1, imm:$src2))]>;
3025 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
3026 (ins GR16:$src1, i16i8imm:$src2),
3027 "sub{w}\t{$src2, $dst|$dst, $src2}",
3028 [(set GR16:$dst, EFLAGS,
3029 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
3030 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
3031 (ins GR32:$src1, i32i8imm:$src2),
3032 "sub{l}\t{$src2, $dst|$dst, $src2}",
3033 [(set GR32:$dst, EFLAGS,
3034 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
3036 let Constraints = "" in {
3037 // Memory-Register Subtraction
3038 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3039 "sub{b}\t{$src2, $dst|$dst, $src2}",
3040 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
3041 (implicit EFLAGS)]>;
3042 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3043 "sub{w}\t{$src2, $dst|$dst, $src2}",
3044 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
3045 (implicit EFLAGS)]>, OpSize;
3046 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3047 "sub{l}\t{$src2, $dst|$dst, $src2}",
3048 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3049 (implicit EFLAGS)]>;
3051 // Memory-Integer Subtraction
3052 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3053 "sub{b}\t{$src2, $dst|$dst, $src2}",
3054 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3055 (implicit EFLAGS)]>;
3056 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3057 "sub{w}\t{$src2, $dst|$dst, $src2}",
3058 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3059 (implicit EFLAGS)]>, OpSize;
3060 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3061 "sub{l}\t{$src2, $dst|$dst, $src2}",
3062 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3063 (implicit EFLAGS)]>;
3064 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3065 "sub{w}\t{$src2, $dst|$dst, $src2}",
3066 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3068 (implicit EFLAGS)]>, OpSize;
3069 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3070 "sub{l}\t{$src2, $dst|$dst, $src2}",
3071 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3073 (implicit EFLAGS)]>;
3075 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3076 "sub{b}\t{$src, %al|%al, $src}", []>;
3077 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3078 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3079 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3080 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3081 } // Constraints = ""
3083 let Uses = [EFLAGS] in {
3084 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3085 (ins GR8:$src1, GR8:$src2),
3086 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3087 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3088 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3089 (ins GR16:$src1, GR16:$src2),
3090 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3091 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3092 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3093 (ins GR32:$src1, GR32:$src2),
3094 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3095 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3097 let Constraints = "" in {
3098 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3099 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3100 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3101 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3102 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3103 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3105 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3106 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3107 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3108 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3109 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3110 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3111 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3112 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3113 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3115 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3116 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3117 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3119 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3120 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3121 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3122 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3123 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3124 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3126 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3127 "sbb{b}\t{$src, %al|%al, $src}", []>;
3128 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3129 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3130 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3131 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3132 } // Constraints = ""
3134 let isCodeGenOnly = 1 in {
3135 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3136 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3137 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3138 (ins GR16:$src1, GR16:$src2),
3139 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3140 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3141 (ins GR32:$src1, GR32:$src2),
3142 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3145 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3146 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3147 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3148 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3149 (ins GR16:$src1, i16mem:$src2),
3150 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3151 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3153 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3154 (ins GR32:$src1, i32mem:$src2),
3155 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3156 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3157 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3158 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3159 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3160 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3161 (ins GR16:$src1, i16imm:$src2),
3162 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3163 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3164 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3165 (ins GR16:$src1, i16i8imm:$src2),
3166 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3167 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3169 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3170 (ins GR32:$src1, i32imm:$src2),
3171 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3172 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3173 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3174 (ins GR32:$src1, i32i8imm:$src2),
3175 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3176 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3177 } // Uses = [EFLAGS]
3178 } // Defs = [EFLAGS]
3180 let Defs = [EFLAGS] in {
3181 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3182 // Register-Register Signed Integer Multiply
3183 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3184 "imul{w}\t{$src2, $dst|$dst, $src2}",
3185 [(set GR16:$dst, EFLAGS,
3186 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3187 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3188 "imul{l}\t{$src2, $dst|$dst, $src2}",
3189 [(set GR32:$dst, EFLAGS,
3190 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3193 // Register-Memory Signed Integer Multiply
3194 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3195 (ins GR16:$src1, i16mem:$src2),
3196 "imul{w}\t{$src2, $dst|$dst, $src2}",
3197 [(set GR16:$dst, EFLAGS,
3198 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3200 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3201 (ins GR32:$src1, i32mem:$src2),
3202 "imul{l}\t{$src2, $dst|$dst, $src2}",
3203 [(set GR32:$dst, EFLAGS,
3204 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3205 } // Defs = [EFLAGS]
3206 } // end Two Address instructions
3208 // Suprisingly enough, these are not two address instructions!
3209 let Defs = [EFLAGS] in {
3210 // Register-Integer Signed Integer Multiply
3211 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3212 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3213 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3214 [(set GR16:$dst, EFLAGS,
3215 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3216 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3217 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3218 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3219 [(set GR32:$dst, EFLAGS,
3220 (X86smul_flag GR32:$src1, imm:$src2))]>;
3221 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3222 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3223 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3224 [(set GR16:$dst, EFLAGS,
3225 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3227 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3228 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3229 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3230 [(set GR32:$dst, EFLAGS,
3231 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3233 // Memory-Integer Signed Integer Multiply
3234 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3235 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3236 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3237 [(set GR16:$dst, EFLAGS,
3238 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3240 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3241 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3242 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3243 [(set GR32:$dst, EFLAGS,
3244 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3245 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3246 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3247 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3248 [(set GR16:$dst, EFLAGS,
3249 (X86smul_flag (load addr:$src1),
3250 i16immSExt8:$src2))]>, OpSize;
3251 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3252 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3253 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3254 [(set GR32:$dst, EFLAGS,
3255 (X86smul_flag (load addr:$src1),
3256 i32immSExt8:$src2))]>;
3257 } // Defs = [EFLAGS]
3259 //===----------------------------------------------------------------------===//
3260 // Test instructions are just like AND, except they don't generate a result.
3262 let Defs = [EFLAGS] in {
3263 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3264 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3265 "test{b}\t{$src2, $src1|$src1, $src2}",
3266 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3267 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3268 "test{w}\t{$src2, $src1|$src1, $src2}",
3269 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3272 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3273 "test{l}\t{$src2, $src1|$src1, $src2}",
3274 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3278 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3279 "test{b}\t{$src, %al|%al, $src}", []>;
3280 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3281 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3282 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3283 "test{l}\t{$src, %eax|%eax, $src}", []>;
3285 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3286 "test{b}\t{$src2, $src1|$src1, $src2}",
3287 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3289 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3290 "test{w}\t{$src2, $src1|$src1, $src2}",
3291 [(set EFLAGS, (X86cmp (and GR16:$src1,
3292 (loadi16 addr:$src2)), 0))]>, OpSize;
3293 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3294 "test{l}\t{$src2, $src1|$src1, $src2}",
3295 [(set EFLAGS, (X86cmp (and GR32:$src1,
3296 (loadi32 addr:$src2)), 0))]>;
3298 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3299 (outs), (ins GR8:$src1, i8imm:$src2),
3300 "test{b}\t{$src2, $src1|$src1, $src2}",
3301 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3302 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3303 (outs), (ins GR16:$src1, i16imm:$src2),
3304 "test{w}\t{$src2, $src1|$src1, $src2}",
3305 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3307 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3308 (outs), (ins GR32:$src1, i32imm:$src2),
3309 "test{l}\t{$src2, $src1|$src1, $src2}",
3310 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3312 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3313 (outs), (ins i8mem:$src1, i8imm:$src2),
3314 "test{b}\t{$src2, $src1|$src1, $src2}",
3315 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3317 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3318 (outs), (ins i16mem:$src1, i16imm:$src2),
3319 "test{w}\t{$src2, $src1|$src1, $src2}",
3320 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3322 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3323 (outs), (ins i32mem:$src1, i32imm:$src2),
3324 "test{l}\t{$src2, $src1|$src1, $src2}",
3325 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3327 } // Defs = [EFLAGS]
3330 // Condition code ops, incl. set if equal/not equal/...
3331 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3332 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3333 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3334 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3336 let Uses = [EFLAGS] in {
3337 // Use sbb to materialize carry bit.
3338 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3339 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3340 // However, Pat<> can't replicate the destination reg into the inputs of the
3342 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3344 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3345 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3346 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3347 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3349 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3350 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3353 def SETEr : I<0x94, MRM0r,
3354 (outs GR8 :$dst), (ins),
3356 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3358 def SETEm : I<0x94, MRM0m,
3359 (outs), (ins i8mem:$dst),
3361 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3364 def SETNEr : I<0x95, MRM0r,
3365 (outs GR8 :$dst), (ins),
3367 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3369 def SETNEm : I<0x95, MRM0m,
3370 (outs), (ins i8mem:$dst),
3372 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3375 def SETLr : I<0x9C, MRM0r,
3376 (outs GR8 :$dst), (ins),
3378 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3379 TB; // GR8 = < signed
3380 def SETLm : I<0x9C, MRM0m,
3381 (outs), (ins i8mem:$dst),
3383 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3384 TB; // [mem8] = < signed
3386 def SETGEr : I<0x9D, MRM0r,
3387 (outs GR8 :$dst), (ins),
3389 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3390 TB; // GR8 = >= signed
3391 def SETGEm : I<0x9D, MRM0m,
3392 (outs), (ins i8mem:$dst),
3394 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3395 TB; // [mem8] = >= signed
3397 def SETLEr : I<0x9E, MRM0r,
3398 (outs GR8 :$dst), (ins),
3400 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3401 TB; // GR8 = <= signed
3402 def SETLEm : I<0x9E, MRM0m,
3403 (outs), (ins i8mem:$dst),
3405 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3406 TB; // [mem8] = <= signed
3408 def SETGr : I<0x9F, MRM0r,
3409 (outs GR8 :$dst), (ins),
3411 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3412 TB; // GR8 = > signed
3413 def SETGm : I<0x9F, MRM0m,
3414 (outs), (ins i8mem:$dst),
3416 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3417 TB; // [mem8] = > signed
3419 def SETBr : I<0x92, MRM0r,
3420 (outs GR8 :$dst), (ins),
3422 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3423 TB; // GR8 = < unsign
3424 def SETBm : I<0x92, MRM0m,
3425 (outs), (ins i8mem:$dst),
3427 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3428 TB; // [mem8] = < unsign
3430 def SETAEr : I<0x93, MRM0r,
3431 (outs GR8 :$dst), (ins),
3433 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3434 TB; // GR8 = >= unsign
3435 def SETAEm : I<0x93, MRM0m,
3436 (outs), (ins i8mem:$dst),
3438 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3439 TB; // [mem8] = >= unsign
3441 def SETBEr : I<0x96, MRM0r,
3442 (outs GR8 :$dst), (ins),
3444 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3445 TB; // GR8 = <= unsign
3446 def SETBEm : I<0x96, MRM0m,
3447 (outs), (ins i8mem:$dst),
3449 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3450 TB; // [mem8] = <= unsign
3452 def SETAr : I<0x97, MRM0r,
3453 (outs GR8 :$dst), (ins),
3455 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3456 TB; // GR8 = > signed
3457 def SETAm : I<0x97, MRM0m,
3458 (outs), (ins i8mem:$dst),
3460 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3461 TB; // [mem8] = > signed
3463 def SETSr : I<0x98, MRM0r,
3464 (outs GR8 :$dst), (ins),
3466 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3467 TB; // GR8 = <sign bit>
3468 def SETSm : I<0x98, MRM0m,
3469 (outs), (ins i8mem:$dst),
3471 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3472 TB; // [mem8] = <sign bit>
3473 def SETNSr : I<0x99, MRM0r,
3474 (outs GR8 :$dst), (ins),
3476 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3477 TB; // GR8 = !<sign bit>
3478 def SETNSm : I<0x99, MRM0m,
3479 (outs), (ins i8mem:$dst),
3481 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3482 TB; // [mem8] = !<sign bit>
3484 def SETPr : I<0x9A, MRM0r,
3485 (outs GR8 :$dst), (ins),
3487 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3489 def SETPm : I<0x9A, MRM0m,
3490 (outs), (ins i8mem:$dst),
3492 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3493 TB; // [mem8] = parity
3494 def SETNPr : I<0x9B, MRM0r,
3495 (outs GR8 :$dst), (ins),
3497 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3498 TB; // GR8 = not parity
3499 def SETNPm : I<0x9B, MRM0m,
3500 (outs), (ins i8mem:$dst),
3502 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3503 TB; // [mem8] = not parity
3505 def SETOr : I<0x90, MRM0r,
3506 (outs GR8 :$dst), (ins),
3508 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3509 TB; // GR8 = overflow
3510 def SETOm : I<0x90, MRM0m,
3511 (outs), (ins i8mem:$dst),
3513 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3514 TB; // [mem8] = overflow
3515 def SETNOr : I<0x91, MRM0r,
3516 (outs GR8 :$dst), (ins),
3518 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3519 TB; // GR8 = not overflow
3520 def SETNOm : I<0x91, MRM0m,
3521 (outs), (ins i8mem:$dst),
3523 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3524 TB; // [mem8] = not overflow
3525 } // Uses = [EFLAGS]
3528 // Integer comparisons
3529 let Defs = [EFLAGS] in {
3530 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3531 "cmp{b}\t{$src, %al|%al, $src}", []>;
3532 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3533 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3534 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3535 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3537 def CMP8rr : I<0x38, MRMDestReg,
3538 (outs), (ins GR8 :$src1, GR8 :$src2),
3539 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3540 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3541 def CMP16rr : I<0x39, MRMDestReg,
3542 (outs), (ins GR16:$src1, GR16:$src2),
3543 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3544 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3545 def CMP32rr : I<0x39, MRMDestReg,
3546 (outs), (ins GR32:$src1, GR32:$src2),
3547 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3548 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3549 def CMP8mr : I<0x38, MRMDestMem,
3550 (outs), (ins i8mem :$src1, GR8 :$src2),
3551 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3552 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3553 def CMP16mr : I<0x39, MRMDestMem,
3554 (outs), (ins i16mem:$src1, GR16:$src2),
3555 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3556 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3558 def CMP32mr : I<0x39, MRMDestMem,
3559 (outs), (ins i32mem:$src1, GR32:$src2),
3560 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3561 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3562 def CMP8rm : I<0x3A, MRMSrcMem,
3563 (outs), (ins GR8 :$src1, i8mem :$src2),
3564 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3565 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3566 def CMP16rm : I<0x3B, MRMSrcMem,
3567 (outs), (ins GR16:$src1, i16mem:$src2),
3568 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3569 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3571 def CMP32rm : I<0x3B, MRMSrcMem,
3572 (outs), (ins GR32:$src1, i32mem:$src2),
3573 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3574 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3576 // These are alternate spellings for use by the disassembler, we mark them as
3577 // code gen only to ensure they aren't matched by the assembler.
3578 let isCodeGenOnly = 1 in {
3579 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3580 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3581 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3582 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3583 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3584 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3587 def CMP8ri : Ii8<0x80, MRM7r,
3588 (outs), (ins GR8:$src1, i8imm:$src2),
3589 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3590 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3591 def CMP16ri : Ii16<0x81, MRM7r,
3592 (outs), (ins GR16:$src1, i16imm:$src2),
3593 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3594 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3595 def CMP32ri : Ii32<0x81, MRM7r,
3596 (outs), (ins GR32:$src1, i32imm:$src2),
3597 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3598 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3599 def CMP8mi : Ii8 <0x80, MRM7m,
3600 (outs), (ins i8mem :$src1, i8imm :$src2),
3601 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3602 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3603 def CMP16mi : Ii16<0x81, MRM7m,
3604 (outs), (ins i16mem:$src1, i16imm:$src2),
3605 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3606 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3608 def CMP32mi : Ii32<0x81, MRM7m,
3609 (outs), (ins i32mem:$src1, i32imm:$src2),
3610 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3611 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3612 def CMP16ri8 : Ii8<0x83, MRM7r,
3613 (outs), (ins GR16:$src1, i16i8imm:$src2),
3614 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3615 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3617 def CMP16mi8 : Ii8<0x83, MRM7m,
3618 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3619 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3620 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3621 i16immSExt8:$src2))]>, OpSize;
3622 def CMP32mi8 : Ii8<0x83, MRM7m,
3623 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3624 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3625 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3626 i32immSExt8:$src2))]>;
3627 def CMP32ri8 : Ii8<0x83, MRM7r,
3628 (outs), (ins GR32:$src1, i32i8imm:$src2),
3629 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3630 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3631 } // Defs = [EFLAGS]
3634 // TODO: BTC, BTR, and BTS
3635 let Defs = [EFLAGS] in {
3636 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3637 "bt{w}\t{$src2, $src1|$src1, $src2}",
3638 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3639 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3640 "bt{l}\t{$src2, $src1|$src1, $src2}",
3641 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3643 // Unlike with the register+register form, the memory+register form of the
3644 // bt instruction does not ignore the high bits of the index. From ISel's
3645 // perspective, this is pretty bizarre. Make these instructions disassembly
3648 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3649 "bt{w}\t{$src2, $src1|$src1, $src2}",
3650 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3651 // (implicit EFLAGS)]
3653 >, OpSize, TB, Requires<[FastBTMem]>;
3654 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3655 "bt{l}\t{$src2, $src1|$src1, $src2}",
3656 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3657 // (implicit EFLAGS)]
3659 >, TB, Requires<[FastBTMem]>;
3661 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3662 "bt{w}\t{$src2, $src1|$src1, $src2}",
3663 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3665 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3666 "bt{l}\t{$src2, $src1|$src1, $src2}",
3667 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3668 // Note that these instructions don't need FastBTMem because that
3669 // only applies when the other operand is in a register. When it's
3670 // an immediate, bt is still fast.
3671 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3672 "bt{w}\t{$src2, $src1|$src1, $src2}",
3673 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3675 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3676 "bt{l}\t{$src2, $src1|$src1, $src2}",
3677 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3680 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3681 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3682 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3683 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3684 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3685 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3686 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3687 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3688 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3689 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3690 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3691 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3692 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3693 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3694 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3695 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3697 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3698 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3699 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3700 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3701 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3702 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3703 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3704 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3705 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3706 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3707 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3708 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3709 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3710 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3711 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3712 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3714 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3715 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3716 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3717 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3718 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3719 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3720 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3721 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3722 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3723 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3724 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3725 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3726 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3727 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3728 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3729 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3730 } // Defs = [EFLAGS]
3732 // Sign/Zero extenders
3733 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3734 // of the register here. This has a smaller encoding and avoids a
3735 // partial-register update. Actual movsbw included for the disassembler.
3736 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3737 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3738 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3739 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3740 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3741 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3742 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3743 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3744 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3745 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3746 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3747 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3748 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3749 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3750 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3751 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3752 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3753 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3754 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3755 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3757 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3758 // of the register here. This has a smaller encoding and avoids a
3759 // partial-register update. Actual movzbw included for the disassembler.
3760 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3761 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3762 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3763 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3764 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3765 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3766 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3767 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3768 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3769 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3770 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3771 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3772 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3773 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3774 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3775 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3776 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3777 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3778 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3779 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3781 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3782 // except that they use GR32_NOREX for the output operand register class
3783 // instead of GR32. This allows them to operate on h registers on x86-64.
3784 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3785 (outs GR32_NOREX:$dst), (ins GR8:$src),
3786 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3789 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3790 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3791 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3794 let neverHasSideEffects = 1 in {
3795 let Defs = [AX], Uses = [AL] in
3796 def CBW : I<0x98, RawFrm, (outs), (ins),
3797 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3798 let Defs = [EAX], Uses = [AX] in
3799 def CWDE : I<0x98, RawFrm, (outs), (ins),
3800 "{cwtl|cwde}", []>; // EAX = signext(AX)
3802 let Defs = [AX,DX], Uses = [AX] in
3803 def CWD : I<0x99, RawFrm, (outs), (ins),
3804 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3805 let Defs = [EAX,EDX], Uses = [EAX] in
3806 def CDQ : I<0x99, RawFrm, (outs), (ins),
3807 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3810 //===----------------------------------------------------------------------===//
3811 // Alias Instructions
3812 //===----------------------------------------------------------------------===//
3814 // Alias instructions that map movr0 to xor.
3815 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3816 // FIXME: Set encoding to pseudo.
3817 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3818 isCodeGenOnly = 1 in {
3819 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3820 [(set GR8:$dst, 0)]>;
3822 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3823 // encoding and avoids a partial-register update sometimes, but doing so
3824 // at isel time interferes with rematerialization in the current register
3825 // allocator. For now, this is rewritten when the instruction is lowered
3827 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3829 [(set GR16:$dst, 0)]>, OpSize;
3831 // FIXME: Set encoding to pseudo.
3832 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3833 [(set GR32:$dst, 0)]>;
3836 //===----------------------------------------------------------------------===//
3837 // Thread Local Storage Instructions
3840 // All calls clobber the non-callee saved registers. ESP is marked as
3841 // a use to prevent stack-pointer assignments that appear immediately
3842 // before calls from potentially appearing dead.
3843 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3844 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3845 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3846 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3848 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3849 "leal\t$sym, %eax; "
3850 "call\t___tls_get_addr@PLT",
3851 [(X86tlsaddr tls32addr:$sym)]>,
3852 Requires<[In32BitMode]>;
3854 // For i386, the address of the thunk is passed on the stack, on return the
3855 // address of the variable is in %eax. %ecx is trashed during the function
3856 // call. %edx is preserved.
3859 usesCustomInserter = 1 in
3860 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3861 "# Fixme into a call",
3862 [(X86TLSCall addr:$sym)]>,
3863 Requires<[In32BitMode]>;
3865 let AddedComplexity = 5, isCodeGenOnly = 1 in
3866 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3867 "movl\t%gs:$src, $dst",
3868 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3870 let AddedComplexity = 5, isCodeGenOnly = 1 in
3871 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3872 "movl\t%fs:$src, $dst",
3873 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3875 //===----------------------------------------------------------------------===//
3876 // EH Pseudo Instructions
3878 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3879 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3880 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3881 "ret\t#eh_return, addr: $addr",
3882 [(X86ehret GR32:$addr)]>;
3886 //===----------------------------------------------------------------------===//
3890 // Atomic swap. These are just normal xchg instructions. But since a memory
3891 // operand is referenced, the atomicity is ensured.
3892 let Constraints = "$val = $dst" in {
3893 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3894 (ins GR32:$val, i32mem:$ptr),
3895 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3896 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3897 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3898 (ins GR16:$val, i16mem:$ptr),
3899 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3900 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3902 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3903 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3904 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3906 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3907 "xchg{l}\t{$val, $src|$src, $val}", []>;
3908 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3909 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3910 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3911 "xchg{b}\t{$val, $src|$src, $val}", []>;
3914 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3915 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3916 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3917 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3919 // Atomic compare and swap.
3920 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3921 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3923 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3924 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3926 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3927 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3930 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3933 let Defs = [AX, EFLAGS], Uses = [AX] in {
3934 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3936 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3937 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3939 let Defs = [AL, EFLAGS], Uses = [AL] in {
3940 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3942 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3943 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3946 // Atomic exchange and add
3947 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3948 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3950 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3951 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3953 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3955 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3956 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3958 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3960 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3961 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3965 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3966 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3967 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3968 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3969 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3970 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3972 let mayLoad = 1, mayStore = 1 in {
3973 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3974 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3975 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3976 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3977 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3978 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3981 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3982 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3983 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3984 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3985 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3986 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3988 let mayLoad = 1, mayStore = 1 in {
3989 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3990 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3991 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3992 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3993 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3994 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3997 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3998 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3999 "cmpxchg8b\t$dst", []>, TB;
4001 // Optimized codegen when the non-memory output is not used.
4002 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
4003 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
4004 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
4006 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4007 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4009 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4010 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4012 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4013 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
4015 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4016 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
4018 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4019 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
4021 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4022 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4024 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4025 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4027 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4029 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
4031 "inc{b}\t$dst", []>, LOCK;
4032 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
4034 "inc{w}\t$dst", []>, OpSize, LOCK;
4035 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
4037 "inc{l}\t$dst", []>, LOCK;
4039 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
4041 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4042 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4044 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4045 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4047 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4048 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
4050 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4051 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
4053 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4054 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
4056 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4057 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4059 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4060 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4062 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4064 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4066 "dec{b}\t$dst", []>, LOCK;
4067 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4069 "dec{w}\t$dst", []>, OpSize, LOCK;
4070 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4072 "dec{l}\t$dst", []>, LOCK;
4075 // Atomic exchange, and, or, xor
4076 let Constraints = "$val = $dst", Defs = [EFLAGS],
4077 usesCustomInserter = 1 in {
4078 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4079 "#ATOMAND32 PSEUDO!",
4080 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4081 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4082 "#ATOMOR32 PSEUDO!",
4083 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4084 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4085 "#ATOMXOR32 PSEUDO!",
4086 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4087 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4088 "#ATOMNAND32 PSEUDO!",
4089 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4090 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4091 "#ATOMMIN32 PSEUDO!",
4092 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4093 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4094 "#ATOMMAX32 PSEUDO!",
4095 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4096 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4097 "#ATOMUMIN32 PSEUDO!",
4098 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4099 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4100 "#ATOMUMAX32 PSEUDO!",
4101 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4103 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4104 "#ATOMAND16 PSEUDO!",
4105 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4106 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4107 "#ATOMOR16 PSEUDO!",
4108 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4109 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4110 "#ATOMXOR16 PSEUDO!",
4111 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4112 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4113 "#ATOMNAND16 PSEUDO!",
4114 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4115 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4116 "#ATOMMIN16 PSEUDO!",
4117 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4118 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4119 "#ATOMMAX16 PSEUDO!",
4120 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4121 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4122 "#ATOMUMIN16 PSEUDO!",
4123 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4124 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4125 "#ATOMUMAX16 PSEUDO!",
4126 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4128 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4129 "#ATOMAND8 PSEUDO!",
4130 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4131 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4133 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4134 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4135 "#ATOMXOR8 PSEUDO!",
4136 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4137 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4138 "#ATOMNAND8 PSEUDO!",
4139 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4142 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4143 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4144 Uses = [EAX, EBX, ECX, EDX],
4145 mayLoad = 1, mayStore = 1,
4146 usesCustomInserter = 1 in {
4147 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4148 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4149 "#ATOMAND6432 PSEUDO!", []>;
4150 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4151 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4152 "#ATOMOR6432 PSEUDO!", []>;
4153 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4154 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4155 "#ATOMXOR6432 PSEUDO!", []>;
4156 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4157 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4158 "#ATOMNAND6432 PSEUDO!", []>;
4159 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4160 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4161 "#ATOMADD6432 PSEUDO!", []>;
4162 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4163 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4164 "#ATOMSUB6432 PSEUDO!", []>;
4165 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4166 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4167 "#ATOMSWAP6432 PSEUDO!", []>;
4170 // Segmentation support instructions.
4172 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4173 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4174 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4175 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4177 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4178 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4179 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4180 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4181 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4183 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4184 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4185 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4186 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4187 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4188 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4189 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4190 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4192 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4194 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4195 "str{w}\t{$dst}", []>, TB;
4196 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4197 "str{w}\t{$dst}", []>, TB;
4198 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4199 "ltr{w}\t{$src}", []>, TB;
4200 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4201 "ltr{w}\t{$src}", []>, TB;
4203 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4204 "push{w}\t%fs", []>, OpSize, TB;
4205 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4206 "push{l}\t%fs", []>, TB;
4207 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4208 "push{w}\t%gs", []>, OpSize, TB;
4209 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4210 "push{l}\t%gs", []>, TB;
4212 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4213 "pop{w}\t%fs", []>, OpSize, TB;
4214 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4215 "pop{l}\t%fs", []>, TB;
4216 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4217 "pop{w}\t%gs", []>, OpSize, TB;
4218 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4219 "pop{l}\t%gs", []>, TB;
4221 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4222 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4223 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4224 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4225 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4226 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4227 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4228 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4229 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4230 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4231 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4232 "les{l}\t{$src, $dst|$dst, $src}", []>;
4233 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4234 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4235 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4236 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4237 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4238 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4239 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4240 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4242 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4243 "verr\t$seg", []>, TB;
4244 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4245 "verr\t$seg", []>, TB;
4246 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4247 "verw\t$seg", []>, TB;
4248 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4249 "verw\t$seg", []>, TB;
4251 // Descriptor-table support instructions
4253 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4254 "sgdt\t$dst", []>, TB;
4255 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4256 "sidt\t$dst", []>, TB;
4257 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4258 "sldt{w}\t$dst", []>, TB;
4259 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4260 "sldt{w}\t$dst", []>, TB;
4261 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4262 "lgdt\t$src", []>, TB;
4263 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4264 "lidt\t$src", []>, TB;
4265 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4266 "lldt{w}\t$src", []>, TB;
4267 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4268 "lldt{w}\t$src", []>, TB;
4270 // Lock instruction prefix
4271 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4273 // Repeat string operation instruction prefixes
4274 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4275 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4276 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4277 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4278 // Repeat while not equal (used with CMPS and SCAS)
4279 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4282 // Segment override instruction prefixes
4283 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4284 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4285 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4286 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4287 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4288 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4290 // String manipulation instructions
4292 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4293 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4294 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4296 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4297 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4298 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4300 // CPU flow control instructions
4302 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4303 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4305 // FPU control instructions
4307 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4309 // Flag instructions
4311 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4312 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4313 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4314 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4315 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4316 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4317 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4319 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4321 // Table lookup instructions
4323 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4325 // Specialized register support
4327 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4328 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4329 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4331 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4332 "smsw{w}\t$dst", []>, OpSize, TB;
4333 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4334 "smsw{l}\t$dst", []>, TB;
4335 // For memory operands, there is only a 16-bit form
4336 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4337 "smsw{w}\t$dst", []>, TB;
4339 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4340 "lmsw{w}\t$src", []>, TB;
4341 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4342 "lmsw{w}\t$src", []>, TB;
4344 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4346 // Cache instructions
4348 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4349 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4354 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4356 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4358 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4359 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4360 "vmclear\t$vmcs", []>, OpSize, TB;
4362 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4364 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4365 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4366 "vmptrld\t$vmcs", []>, TB;
4367 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4368 "vmptrst\t$vmcs", []>, TB;
4369 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4370 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4371 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4372 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4373 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4374 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4375 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4376 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4377 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4378 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4379 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4380 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4381 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4382 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4383 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4384 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4386 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4387 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4388 "vmxon\t{$vmxon}", []>, XS;
4390 //===----------------------------------------------------------------------===//
4391 // Non-Instruction Patterns
4392 //===----------------------------------------------------------------------===//
4394 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4395 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4396 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4397 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4398 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4399 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4400 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4402 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4403 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4404 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4405 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4406 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4407 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4408 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4409 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4410 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4411 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4413 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4414 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4415 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4416 (MOV32mi addr:$dst, texternalsym:$src)>;
4417 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4418 (MOV32mi addr:$dst, tblockaddress:$src)>;
4422 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4423 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4424 Requires<[In32BitMode]>;
4426 // FIXME: This is disabled for 32-bit PIC mode because the global base
4427 // register which is part of the address mode may be assigned a
4428 // callee-saved register.
4429 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4430 (TCRETURNmi addr:$dst, imm:$off)>,
4431 Requires<[In32BitMode, IsNotPIC]>;
4433 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4434 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4435 Requires<[In32BitMode]>;
4437 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4438 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4439 Requires<[In32BitMode]>;
4441 // Normal calls, with various flavors of addresses.
4442 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4443 (CALLpcrel32 tglobaladdr:$dst)>;
4444 def : Pat<(X86call (i32 texternalsym:$dst)),
4445 (CALLpcrel32 texternalsym:$dst)>;
4446 def : Pat<(X86call (i32 imm:$dst)),
4447 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4449 // X86 specific add which produces a flag.
4450 def : Pat<(addc GR32:$src1, GR32:$src2),
4451 (ADD32rr GR32:$src1, GR32:$src2)>;
4452 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4453 (ADD32rm GR32:$src1, addr:$src2)>;
4454 def : Pat<(addc GR32:$src1, imm:$src2),
4455 (ADD32ri GR32:$src1, imm:$src2)>;
4456 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4457 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4459 def : Pat<(subc GR32:$src1, GR32:$src2),
4460 (SUB32rr GR32:$src1, GR32:$src2)>;
4461 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4462 (SUB32rm GR32:$src1, addr:$src2)>;
4463 def : Pat<(subc GR32:$src1, imm:$src2),
4464 (SUB32ri GR32:$src1, imm:$src2)>;
4465 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4466 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4470 // TEST R,R is smaller than CMP R,0
4471 def : Pat<(X86cmp GR8:$src1, 0),
4472 (TEST8rr GR8:$src1, GR8:$src1)>;
4473 def : Pat<(X86cmp GR16:$src1, 0),
4474 (TEST16rr GR16:$src1, GR16:$src1)>;
4475 def : Pat<(X86cmp GR32:$src1, 0),
4476 (TEST32rr GR32:$src1, GR32:$src1)>;
4478 // Conditional moves with folded loads with operands swapped and conditions
4480 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4481 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4482 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4483 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4484 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4485 (CMOVB16rm GR16:$src2, addr:$src1)>;
4486 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4487 (CMOVB32rm GR32:$src2, addr:$src1)>;
4488 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4489 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4490 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4491 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4492 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4493 (CMOVE16rm GR16:$src2, addr:$src1)>;
4494 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4495 (CMOVE32rm GR32:$src2, addr:$src1)>;
4496 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4497 (CMOVA16rm GR16:$src2, addr:$src1)>;
4498 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4499 (CMOVA32rm GR32:$src2, addr:$src1)>;
4500 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4501 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4502 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4503 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4504 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4505 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4506 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4507 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4508 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4509 (CMOVL16rm GR16:$src2, addr:$src1)>;
4510 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4511 (CMOVL32rm GR32:$src2, addr:$src1)>;
4512 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4513 (CMOVG16rm GR16:$src2, addr:$src1)>;
4514 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4515 (CMOVG32rm GR32:$src2, addr:$src1)>;
4516 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4517 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4518 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4519 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4520 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4521 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4522 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4523 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4524 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4525 (CMOVP16rm GR16:$src2, addr:$src1)>;
4526 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4527 (CMOVP32rm GR32:$src2, addr:$src1)>;
4528 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4529 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4530 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4531 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4532 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4533 (CMOVS16rm GR16:$src2, addr:$src1)>;
4534 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4535 (CMOVS32rm GR32:$src2, addr:$src1)>;
4536 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4537 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4538 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4539 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4540 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4541 (CMOVO16rm GR16:$src2, addr:$src1)>;
4542 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4543 (CMOVO32rm GR32:$src2, addr:$src1)>;
4545 // zextload bool -> zextload byte
4546 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4547 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4548 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4550 // extload bool -> extload byte
4551 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4552 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4553 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4554 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4555 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4556 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4558 // anyext. Define these to do an explicit zero-extend to
4559 // avoid partial-register updates.
4560 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4561 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4563 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4564 def : Pat<(i32 (anyext GR16:$src)),
4565 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4568 //===----------------------------------------------------------------------===//
4570 //===----------------------------------------------------------------------===//
4572 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4573 // +128 doesn't, so in this special case use a sub instead of an add.
4574 def : Pat<(add GR16:$src1, 128),
4575 (SUB16ri8 GR16:$src1, -128)>;
4576 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4577 (SUB16mi8 addr:$dst, -128)>;
4578 def : Pat<(add GR32:$src1, 128),
4579 (SUB32ri8 GR32:$src1, -128)>;
4580 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4581 (SUB32mi8 addr:$dst, -128)>;
4583 // r & (2^16-1) ==> movz
4584 def : Pat<(and GR32:$src1, 0xffff),
4585 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4586 // r & (2^8-1) ==> movz
4587 def : Pat<(and GR32:$src1, 0xff),
4588 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4591 Requires<[In32BitMode]>;
4592 // r & (2^8-1) ==> movz
4593 def : Pat<(and GR16:$src1, 0xff),
4594 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4597 Requires<[In32BitMode]>;
4599 // sext_inreg patterns
4600 def : Pat<(sext_inreg GR32:$src, i16),
4601 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4602 def : Pat<(sext_inreg GR32:$src, i8),
4603 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4606 Requires<[In32BitMode]>;
4607 def : Pat<(sext_inreg GR16:$src, i8),
4608 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4611 Requires<[In32BitMode]>;
4614 def : Pat<(i16 (trunc GR32:$src)),
4615 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4616 def : Pat<(i8 (trunc GR32:$src)),
4617 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4619 Requires<[In32BitMode]>;
4620 def : Pat<(i8 (trunc GR16:$src)),
4621 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4623 Requires<[In32BitMode]>;
4625 // h-register tricks
4626 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4627 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4629 Requires<[In32BitMode]>;
4630 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4631 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4633 Requires<[In32BitMode]>;
4634 def : Pat<(srl GR16:$src, (i8 8)),
4637 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4640 Requires<[In32BitMode]>;
4641 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4642 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4645 Requires<[In32BitMode]>;
4646 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4647 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4650 Requires<[In32BitMode]>;
4651 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4652 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4655 Requires<[In32BitMode]>;
4656 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4657 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4660 Requires<[In32BitMode]>;
4662 // (shl x, 1) ==> (add x, x)
4663 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4664 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4665 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4667 // (shl x (and y, 31)) ==> (shl x, y)
4668 def : Pat<(shl GR8:$src1, (and CL, 31)),
4669 (SHL8rCL GR8:$src1)>;
4670 def : Pat<(shl GR16:$src1, (and CL, 31)),
4671 (SHL16rCL GR16:$src1)>;
4672 def : Pat<(shl GR32:$src1, (and CL, 31)),
4673 (SHL32rCL GR32:$src1)>;
4674 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4675 (SHL8mCL addr:$dst)>;
4676 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4677 (SHL16mCL addr:$dst)>;
4678 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4679 (SHL32mCL addr:$dst)>;
4681 def : Pat<(srl GR8:$src1, (and CL, 31)),
4682 (SHR8rCL GR8:$src1)>;
4683 def : Pat<(srl GR16:$src1, (and CL, 31)),
4684 (SHR16rCL GR16:$src1)>;
4685 def : Pat<(srl GR32:$src1, (and CL, 31)),
4686 (SHR32rCL GR32:$src1)>;
4687 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4688 (SHR8mCL addr:$dst)>;
4689 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4690 (SHR16mCL addr:$dst)>;
4691 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4692 (SHR32mCL addr:$dst)>;
4694 def : Pat<(sra GR8:$src1, (and CL, 31)),
4695 (SAR8rCL GR8:$src1)>;
4696 def : Pat<(sra GR16:$src1, (and CL, 31)),
4697 (SAR16rCL GR16:$src1)>;
4698 def : Pat<(sra GR32:$src1, (and CL, 31)),
4699 (SAR32rCL GR32:$src1)>;
4700 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4701 (SAR8mCL addr:$dst)>;
4702 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4703 (SAR16mCL addr:$dst)>;
4704 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4705 (SAR32mCL addr:$dst)>;
4707 // (anyext (setcc_carry)) -> (setcc_carry)
4708 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4710 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4712 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4715 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4716 let AddedComplexity = 5 in { // Try this before the selecting to OR
4717 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4718 (ADD16ri GR16:$src1, imm:$src2)>;
4719 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4720 (ADD32ri GR32:$src1, imm:$src2)>;
4721 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4722 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4723 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4724 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4725 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4726 (ADD16rr GR16:$src1, GR16:$src2)>;
4727 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4728 (ADD32rr GR32:$src1, GR32:$src2)>;
4729 } // AddedComplexity
4731 //===----------------------------------------------------------------------===//
4732 // EFLAGS-defining Patterns
4733 //===----------------------------------------------------------------------===//
4736 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4737 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4738 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4741 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4742 (ADD8rm GR8:$src1, addr:$src2)>;
4743 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4744 (ADD16rm GR16:$src1, addr:$src2)>;
4745 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4746 (ADD32rm GR32:$src1, addr:$src2)>;
4749 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4750 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4751 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4752 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4753 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4754 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4755 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4758 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4759 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4760 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4763 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4764 (SUB8rm GR8:$src1, addr:$src2)>;
4765 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4766 (SUB16rm GR16:$src1, addr:$src2)>;
4767 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4768 (SUB32rm GR32:$src1, addr:$src2)>;
4771 def : Pat<(sub GR8:$src1, imm:$src2),
4772 (SUB8ri GR8:$src1, imm:$src2)>;
4773 def : Pat<(sub GR16:$src1, imm:$src2),
4774 (SUB16ri GR16:$src1, imm:$src2)>;
4775 def : Pat<(sub GR32:$src1, imm:$src2),
4776 (SUB32ri GR32:$src1, imm:$src2)>;
4777 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4778 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4779 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4780 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4783 def : Pat<(mul GR16:$src1, GR16:$src2),
4784 (IMUL16rr GR16:$src1, GR16:$src2)>;
4785 def : Pat<(mul GR32:$src1, GR32:$src2),
4786 (IMUL32rr GR32:$src1, GR32:$src2)>;
4789 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4790 (IMUL16rm GR16:$src1, addr:$src2)>;
4791 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4792 (IMUL32rm GR32:$src1, addr:$src2)>;
4795 def : Pat<(mul GR16:$src1, imm:$src2),
4796 (IMUL16rri GR16:$src1, imm:$src2)>;
4797 def : Pat<(mul GR32:$src1, imm:$src2),
4798 (IMUL32rri GR32:$src1, imm:$src2)>;
4799 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4800 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4801 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4802 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4804 // reg = mul mem, imm
4805 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4806 (IMUL16rmi addr:$src1, imm:$src2)>;
4807 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4808 (IMUL32rmi addr:$src1, imm:$src2)>;
4809 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4810 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4811 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4812 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4814 // Optimize multiply by 2 with EFLAGS result.
4815 let AddedComplexity = 2 in {
4816 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4817 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4820 // Patterns for nodes that do not produce flags, for instructions that do.
4823 def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
4824 def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
4825 def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
4828 def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
4829 def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
4830 def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
4833 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4834 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4835 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4838 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4839 (OR8rm GR8:$src1, addr:$src2)>;
4840 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4841 (OR16rm GR16:$src1, addr:$src2)>;
4842 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4843 (OR32rm GR32:$src1, addr:$src2)>;
4846 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4847 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4848 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4849 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4850 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4851 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4852 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4855 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4856 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4857 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4860 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4861 (XOR8rm GR8:$src1, addr:$src2)>;
4862 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4863 (XOR16rm GR16:$src1, addr:$src2)>;
4864 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4865 (XOR32rm GR32:$src1, addr:$src2)>;
4868 def : Pat<(xor GR8:$src1, imm:$src2),
4869 (XOR8ri GR8:$src1, imm:$src2)>;
4870 def : Pat<(xor GR16:$src1, imm:$src2),
4871 (XOR16ri GR16:$src1, imm:$src2)>;
4872 def : Pat<(xor GR32:$src1, imm:$src2),
4873 (XOR32ri GR32:$src1, imm:$src2)>;
4874 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4875 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4876 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4877 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4880 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4881 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4882 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4885 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4886 (AND8rm GR8:$src1, addr:$src2)>;
4887 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4888 (AND16rm GR16:$src1, addr:$src2)>;
4889 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4890 (AND32rm GR32:$src1, addr:$src2)>;
4893 def : Pat<(and GR8:$src1, imm:$src2),
4894 (AND8ri GR8:$src1, imm:$src2)>;
4895 def : Pat<(and GR16:$src1, imm:$src2),
4896 (AND16ri GR16:$src1, imm:$src2)>;
4897 def : Pat<(and GR32:$src1, imm:$src2),
4898 (AND32ri GR32:$src1, imm:$src2)>;
4899 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4900 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4901 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4902 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4904 //===----------------------------------------------------------------------===//
4905 // Floating Point Stack Support
4906 //===----------------------------------------------------------------------===//
4908 include "X86InstrFPStack.td"
4910 //===----------------------------------------------------------------------===//
4912 //===----------------------------------------------------------------------===//
4914 include "X86Instr64bit.td"
4916 //===----------------------------------------------------------------------===//
4917 // SIMD support (SSE, MMX and AVX)
4918 //===----------------------------------------------------------------------===//
4920 include "X86InstrFragmentsSIMD.td"
4922 //===----------------------------------------------------------------------===//
4923 // XMM Floating point support (requires SSE / SSE2)
4924 //===----------------------------------------------------------------------===//
4926 include "X86InstrSSE.td"
4928 //===----------------------------------------------------------------------===//
4929 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4930 //===----------------------------------------------------------------------===//
4932 include "X86InstrMMX.td"