1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
252 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
253 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
254 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
255 def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
256 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
258 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
260 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
261 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
263 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
266 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
267 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
269 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
270 [SDNPHasChain, SDNPOutGlue]>;
272 //===----------------------------------------------------------------------===//
273 // X86 Operand Definitions.
276 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
277 // the index operand of an address, to conform to x86 encoding restrictions.
278 def ptr_rc_nosp : PointerLikeRegClass<1>;
280 // *mem - Operand definitions for the funky X86 addressing mode operands.
282 def X86MemAsmOperand : AsmOperandClass {
285 def X86Mem8AsmOperand : AsmOperandClass {
286 let Name = "Mem8"; let RenderMethod = "addMemOperands";
288 def X86Mem16AsmOperand : AsmOperandClass {
289 let Name = "Mem16"; let RenderMethod = "addMemOperands";
291 def X86Mem32AsmOperand : AsmOperandClass {
292 let Name = "Mem32"; let RenderMethod = "addMemOperands";
294 def X86Mem64AsmOperand : AsmOperandClass {
295 let Name = "Mem64"; let RenderMethod = "addMemOperands";
297 def X86Mem80AsmOperand : AsmOperandClass {
298 let Name = "Mem80"; let RenderMethod = "addMemOperands";
300 def X86Mem128AsmOperand : AsmOperandClass {
301 let Name = "Mem128"; let RenderMethod = "addMemOperands";
303 def X86Mem256AsmOperand : AsmOperandClass {
304 let Name = "Mem256"; let RenderMethod = "addMemOperands";
306 def X86Mem512AsmOperand : AsmOperandClass {
307 let Name = "Mem512"; let RenderMethod = "addMemOperands";
310 // Gather mem operands
311 def X86MemVX32Operand : AsmOperandClass {
312 let Name = "MemVX32"; let RenderMethod = "addMemOperands";
314 def X86MemVY32Operand : AsmOperandClass {
315 let Name = "MemVY32"; let RenderMethod = "addMemOperands";
317 def X86MemVZ32Operand : AsmOperandClass {
318 let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
320 def X86MemVX64Operand : AsmOperandClass {
321 let Name = "MemVX64"; let RenderMethod = "addMemOperands";
323 def X86MemVY64Operand : AsmOperandClass {
324 let Name = "MemVY64"; let RenderMethod = "addMemOperands";
326 def X86MemVZ64Operand : AsmOperandClass {
327 let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
330 def X86AbsMemAsmOperand : AsmOperandClass {
332 let SuperClasses = [X86MemAsmOperand];
334 class X86MemOperand<string printMethod> : Operand<iPTR> {
335 let PrintMethod = printMethod;
336 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
337 let ParserMatchClass = X86MemAsmOperand;
340 let OperandType = "OPERAND_MEMORY" in {
341 def opaque32mem : X86MemOperand<"printopaquemem">;
342 def opaque48mem : X86MemOperand<"printopaquemem">;
343 def opaque80mem : X86MemOperand<"printopaquemem">;
344 def opaque512mem : X86MemOperand<"printopaquemem">;
346 def i8mem : X86MemOperand<"printi8mem"> {
347 let ParserMatchClass = X86Mem8AsmOperand; }
348 def i16mem : X86MemOperand<"printi16mem"> {
349 let ParserMatchClass = X86Mem16AsmOperand; }
350 def i32mem : X86MemOperand<"printi32mem"> {
351 let ParserMatchClass = X86Mem32AsmOperand; }
352 def i64mem : X86MemOperand<"printi64mem"> {
353 let ParserMatchClass = X86Mem64AsmOperand; }
354 def i128mem : X86MemOperand<"printi128mem"> {
355 let ParserMatchClass = X86Mem128AsmOperand; }
356 def i256mem : X86MemOperand<"printi256mem"> {
357 let ParserMatchClass = X86Mem256AsmOperand; }
358 def i512mem : X86MemOperand<"printi512mem"> {
359 let ParserMatchClass = X86Mem512AsmOperand; }
360 def f32mem : X86MemOperand<"printf32mem"> {
361 let ParserMatchClass = X86Mem32AsmOperand; }
362 def f64mem : X86MemOperand<"printf64mem"> {
363 let ParserMatchClass = X86Mem64AsmOperand; }
364 def f80mem : X86MemOperand<"printf80mem"> {
365 let ParserMatchClass = X86Mem80AsmOperand; }
366 def f128mem : X86MemOperand<"printf128mem"> {
367 let ParserMatchClass = X86Mem128AsmOperand; }
368 def f256mem : X86MemOperand<"printf256mem">{
369 let ParserMatchClass = X86Mem256AsmOperand; }
370 def f512mem : X86MemOperand<"printf512mem">{
371 let ParserMatchClass = X86Mem512AsmOperand; }
372 def v512mem : Operand<iPTR> {
373 let PrintMethod = "printf512mem";
374 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
375 let ParserMatchClass = X86Mem512AsmOperand; }
377 // Gather mem operands
378 def vx32mem : X86MemOperand<"printi32mem">{
379 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
380 let ParserMatchClass = X86MemVX32Operand; }
381 def vy32mem : X86MemOperand<"printi32mem">{
382 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
383 let ParserMatchClass = X86MemVY32Operand; }
384 def vx64mem : X86MemOperand<"printi64mem">{
385 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
386 let ParserMatchClass = X86MemVX64Operand; }
387 def vy64mem : X86MemOperand<"printi64mem">{
388 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
389 let ParserMatchClass = X86MemVY64Operand; }
390 def vy64xmem : X86MemOperand<"printi64mem">{
391 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
392 let ParserMatchClass = X86MemVY64Operand; }
393 def vz32mem : X86MemOperand<"printi32mem">{
394 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
395 let ParserMatchClass = X86MemVZ32Operand; }
396 def vz64mem : X86MemOperand<"printi64mem">{
397 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
398 let ParserMatchClass = X86MemVZ64Operand; }
401 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
402 // plain GR64, so that it doesn't potentially require a REX prefix.
403 def i8mem_NOREX : Operand<i64> {
404 let PrintMethod = "printi8mem";
405 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
406 let ParserMatchClass = X86Mem8AsmOperand;
407 let OperandType = "OPERAND_MEMORY";
410 // GPRs available for tailcall.
411 // It represents GR32_TC, GR64_TC or GR64_TCW64.
412 def ptr_rc_tailcall : PointerLikeRegClass<2>;
414 // Special i32mem for addresses of load folding tail calls. These are not
415 // allowed to use callee-saved registers since they must be scheduled
416 // after callee-saved register are popped.
417 def i32mem_TC : Operand<i32> {
418 let PrintMethod = "printi32mem";
419 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
421 let ParserMatchClass = X86Mem32AsmOperand;
422 let OperandType = "OPERAND_MEMORY";
425 // Special i64mem for addresses of load folding tail calls. These are not
426 // allowed to use callee-saved registers since they must be scheduled
427 // after callee-saved register are popped.
428 def i64mem_TC : Operand<i64> {
429 let PrintMethod = "printi64mem";
430 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
431 ptr_rc_tailcall, i32imm, i8imm);
432 let ParserMatchClass = X86Mem64AsmOperand;
433 let OperandType = "OPERAND_MEMORY";
436 let OperandType = "OPERAND_PCREL",
437 ParserMatchClass = X86AbsMemAsmOperand,
438 PrintMethod = "printPCRelImm" in {
439 def i32imm_pcrel : Operand<i32>;
440 def i16imm_pcrel : Operand<i16>;
442 // Branch targets have OtherVT type and print as pc-relative values.
443 def brtarget : Operand<OtherVT>;
444 def brtarget8 : Operand<OtherVT>;
448 def X86MemOffs8AsmOperand : AsmOperandClass {
449 let Name = "MemOffs8";
450 let RenderMethod = "addMemOffsOperands";
451 let SuperClasses = [X86Mem8AsmOperand];
453 def X86MemOffs16AsmOperand : AsmOperandClass {
454 let Name = "MemOffs16";
455 let RenderMethod = "addMemOffsOperands";
456 let SuperClasses = [X86Mem16AsmOperand];
458 def X86MemOffs32AsmOperand : AsmOperandClass {
459 let Name = "MemOffs32";
460 let RenderMethod = "addMemOffsOperands";
461 let SuperClasses = [X86Mem32AsmOperand];
463 def X86MemOffs64AsmOperand : AsmOperandClass {
464 let Name = "MemOffs64";
465 let RenderMethod = "addMemOffsOperands";
466 let SuperClasses = [X86Mem64AsmOperand];
469 let OperandType = "OPERAND_MEMORY" in {
470 def offset8 : Operand<i64> {
471 let ParserMatchClass = X86MemOffs8AsmOperand;
472 let PrintMethod = "printMemOffs8"; }
473 def offset16 : Operand<i64> {
474 let ParserMatchClass = X86MemOffs16AsmOperand;
475 let PrintMethod = "printMemOffs16"; }
476 def offset32 : Operand<i64> {
477 let ParserMatchClass = X86MemOffs32AsmOperand;
478 let PrintMethod = "printMemOffs32"; }
479 def offset64 : Operand<i64> {
480 let ParserMatchClass = X86MemOffs64AsmOperand;
481 let PrintMethod = "printMemOffs64"; }
485 def SSECC : Operand<i8> {
486 let PrintMethod = "printSSECC";
487 let OperandType = "OPERAND_IMMEDIATE";
490 def AVXCC : Operand<i8> {
491 let PrintMethod = "printAVXCC";
492 let OperandType = "OPERAND_IMMEDIATE";
495 class ImmSExtAsmOperandClass : AsmOperandClass {
496 let SuperClasses = [ImmAsmOperand];
497 let RenderMethod = "addImmOperands";
500 class ImmZExtAsmOperandClass : AsmOperandClass {
501 let SuperClasses = [ImmAsmOperand];
502 let RenderMethod = "addImmOperands";
505 def X86GR32orGR64AsmOperand : AsmOperandClass {
506 let Name = "GR32orGR64";
509 def GR32orGR64 : RegisterOperand<GR32> {
510 let ParserMatchClass = X86GR32orGR64AsmOperand;
513 def AVX512RC : Operand<i32> {
514 let PrintMethod = "printRoundingControl";
515 let OperandType = "OPERAND_IMMEDIATE";
517 // Sign-extended immediate classes. We don't need to define the full lattice
518 // here because there is no instruction with an ambiguity between ImmSExti64i32
521 // The strange ranges come from the fact that the assembler always works with
522 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
523 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
526 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
527 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
528 let Name = "ImmSExti64i32";
531 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
532 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
533 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
534 let Name = "ImmSExti16i8";
535 let SuperClasses = [ImmSExti64i32AsmOperand];
538 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
539 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
540 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
541 let Name = "ImmSExti32i8";
545 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
546 let Name = "ImmZExtu32u8";
551 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
552 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
553 let Name = "ImmSExti64i8";
554 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
555 ImmSExti64i32AsmOperand];
558 // A couple of more descriptive operand definitions.
559 // 16-bits but only 8 bits are significant.
560 def i16i8imm : Operand<i16> {
561 let ParserMatchClass = ImmSExti16i8AsmOperand;
562 let OperandType = "OPERAND_IMMEDIATE";
564 // 32-bits but only 8 bits are significant.
565 def i32i8imm : Operand<i32> {
566 let ParserMatchClass = ImmSExti32i8AsmOperand;
567 let OperandType = "OPERAND_IMMEDIATE";
569 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
570 def u32u8imm : Operand<i32> {
571 let ParserMatchClass = ImmZExtu32u8AsmOperand;
572 let OperandType = "OPERAND_IMMEDIATE";
575 // 64-bits but only 32 bits are significant.
576 def i64i32imm : Operand<i64> {
577 let ParserMatchClass = ImmSExti64i32AsmOperand;
578 let OperandType = "OPERAND_IMMEDIATE";
581 // 64-bits but only 32 bits are significant, and those bits are treated as being
583 def i64i32imm_pcrel : Operand<i64> {
584 let PrintMethod = "printPCRelImm";
585 let ParserMatchClass = X86AbsMemAsmOperand;
586 let OperandType = "OPERAND_PCREL";
589 // 64-bits but only 8 bits are significant.
590 def i64i8imm : Operand<i64> {
591 let ParserMatchClass = ImmSExti64i8AsmOperand;
592 let OperandType = "OPERAND_IMMEDIATE";
595 def lea64_32mem : Operand<i32> {
596 let PrintMethod = "printi32mem";
597 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
598 let ParserMatchClass = X86MemAsmOperand;
601 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
602 def lea64mem : Operand<i64> {
603 let PrintMethod = "printi64mem";
604 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
605 let ParserMatchClass = X86MemAsmOperand;
609 //===----------------------------------------------------------------------===//
610 // X86 Complex Pattern Definitions.
613 // Define X86 specific addressing mode.
614 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
615 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
616 [add, sub, mul, X86mul_imm, shl, or, frameindex],
618 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
619 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
620 [add, sub, mul, X86mul_imm, shl, or,
621 frameindex, X86WrapperRIP],
624 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
625 [tglobaltlsaddr], []>;
627 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
628 [tglobaltlsaddr], []>;
630 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
631 [add, sub, mul, X86mul_imm, shl, or, frameindex,
634 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
635 [tglobaltlsaddr], []>;
637 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
638 [tglobaltlsaddr], []>;
640 //===----------------------------------------------------------------------===//
641 // X86 Instruction Predicate Definitions.
642 def HasCMov : Predicate<"Subtarget->hasCMov()">;
643 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
645 def HasMMX : Predicate<"Subtarget->hasMMX()">;
646 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
647 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
648 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
649 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
650 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
651 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
652 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
653 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
654 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
655 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
656 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
657 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
658 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
659 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
660 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
661 def HasAVX : Predicate<"Subtarget->hasAVX()">;
662 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
663 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
664 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
665 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
666 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
667 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
668 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
669 def HasCDI : Predicate<"Subtarget->hasCDI()">;
670 def HasPFI : Predicate<"Subtarget->hasPFI()">;
671 def HasERI : Predicate<"Subtarget->hasERI()">;
673 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
674 def HasAES : Predicate<"Subtarget->hasAES()">;
675 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
676 def HasFMA : Predicate<"Subtarget->hasFMA()">;
677 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
678 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
679 def HasXOP : Predicate<"Subtarget->hasXOP()">;
680 def HasTBM : Predicate<"Subtarget->hasTBM()">;
681 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
682 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
683 def HasF16C : Predicate<"Subtarget->hasF16C()">;
684 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
685 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
686 def HasBMI : Predicate<"Subtarget->hasBMI()">;
687 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
688 def HasRTM : Predicate<"Subtarget->hasRTM()">;
689 def HasHLE : Predicate<"Subtarget->hasHLE()">;
690 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
691 def HasADX : Predicate<"Subtarget->hasADX()">;
692 def HasSHA : Predicate<"Subtarget->hasSHA()">;
693 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
694 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
695 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
696 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
697 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
698 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
699 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
700 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
701 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
702 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
703 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
704 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
705 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
706 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
707 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
708 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
709 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
710 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
711 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
712 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
713 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
714 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
715 "TM.getCodeModel() != CodeModel::Kernel">;
716 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
717 "TM.getCodeModel() == CodeModel::Kernel">;
718 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
719 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
720 def OptForSize : Predicate<"OptForSize">;
721 def OptForSpeed : Predicate<"!OptForSize">;
722 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
723 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
724 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
726 //===----------------------------------------------------------------------===//
727 // X86 Instruction Format Definitions.
730 include "X86InstrFormats.td"
732 //===----------------------------------------------------------------------===//
733 // Pattern fragments.
736 // X86 specific condition code. These correspond to CondCode in
737 // X86InstrInfo.h. They must be kept in synch.
738 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
739 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
740 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
741 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
742 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
743 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
744 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
745 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
746 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
747 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
748 def X86_COND_NO : PatLeaf<(i8 10)>;
749 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
750 def X86_COND_NS : PatLeaf<(i8 12)>;
751 def X86_COND_O : PatLeaf<(i8 13)>;
752 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
753 def X86_COND_S : PatLeaf<(i8 15)>;
755 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
756 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
757 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
758 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
761 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
764 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
766 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
768 def i64immZExt32SExt8 : ImmLeaf<i64, [{
769 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
772 // Helper fragments for loads.
773 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
774 // known to be 32-bit aligned or better. Ditto for i8 to i16.
775 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
776 LoadSDNode *LD = cast<LoadSDNode>(N);
777 ISD::LoadExtType ExtType = LD->getExtensionType();
778 if (ExtType == ISD::NON_EXTLOAD)
780 if (ExtType == ISD::EXTLOAD)
781 return LD->getAlignment() >= 2 && !LD->isVolatile();
785 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
786 LoadSDNode *LD = cast<LoadSDNode>(N);
787 ISD::LoadExtType ExtType = LD->getExtensionType();
788 if (ExtType == ISD::EXTLOAD)
789 return LD->getAlignment() >= 2 && !LD->isVolatile();
793 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
794 LoadSDNode *LD = cast<LoadSDNode>(N);
795 ISD::LoadExtType ExtType = LD->getExtensionType();
796 if (ExtType == ISD::NON_EXTLOAD)
798 if (ExtType == ISD::EXTLOAD)
799 return LD->getAlignment() >= 4 && !LD->isVolatile();
803 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
804 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
805 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
806 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
807 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
809 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
810 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
811 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
812 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
813 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
814 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
816 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
817 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
818 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
819 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
820 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
821 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
822 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
823 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
824 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
825 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
827 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
828 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
829 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
830 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
831 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
832 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
833 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
834 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
835 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
836 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
839 // An 'and' node with a single use.
840 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
841 return N->hasOneUse();
843 // An 'srl' node with a single use.
844 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
845 return N->hasOneUse();
847 // An 'trunc' node with a single use.
848 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
849 return N->hasOneUse();
852 //===----------------------------------------------------------------------===//
857 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
858 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
859 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
860 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
861 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
862 "nop{l}\t$zero", [], IIC_NOP>, TB;
866 // Constructing a stack frame.
867 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
868 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
870 let SchedRW = [WriteALU] in {
871 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
872 def LEAVE : I<0xC9, RawFrm,
873 (outs), (ins), "leave", [], IIC_LEAVE>,
874 Requires<[Not64BitMode]>;
876 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
877 def LEAVE64 : I<0xC9, RawFrm,
878 (outs), (ins), "leave", [], IIC_LEAVE>,
879 Requires<[In64BitMode]>;
882 //===----------------------------------------------------------------------===//
883 // Miscellaneous Instructions.
886 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
887 let mayLoad = 1, SchedRW = [WriteLoad] in {
888 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
889 IIC_POP_REG16>, OpSize;
890 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
891 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
892 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
893 IIC_POP_REG>, OpSize;
894 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
895 IIC_POP_MEM>, OpSize;
896 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
897 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
898 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
899 IIC_POP_MEM>, Requires<[Not64BitMode]>;
901 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
902 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
903 OpSize16, Requires<[Not64BitMode]>;
904 } // mayLoad, SchedRW
906 let mayStore = 1, SchedRW = [WriteStore] in {
907 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
908 IIC_PUSH_REG>, OpSize;
909 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
910 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
911 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
912 IIC_PUSH_REG>, OpSize;
913 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
914 IIC_PUSH_MEM>, OpSize;
915 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
916 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
917 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
918 IIC_PUSH_MEM>, OpSize16, Requires<[Not64BitMode]>;
920 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
921 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
922 Requires<[Not64BitMode]>;
923 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
924 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
925 Requires<[Not64BitMode]>;
926 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
927 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
928 Requires<[Not64BitMode]>;
929 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
930 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
931 Requires<[Not64BitMode]>;
933 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
935 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
936 OpSize16, Requires<[Not64BitMode]>;
938 } // mayStore, SchedRW
941 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
942 let mayLoad = 1, SchedRW = [WriteLoad] in {
943 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
944 IIC_POP_REG>, Requires<[In64BitMode]>;
945 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
946 IIC_POP_REG>, Requires<[In64BitMode]>;
947 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
948 IIC_POP_MEM>, Requires<[In64BitMode]>;
949 } // mayLoad, SchedRW
950 let mayStore = 1, SchedRW = [WriteStore] in {
951 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
952 IIC_PUSH_REG>, Requires<[In64BitMode]>;
953 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
954 IIC_PUSH_REG>, Requires<[In64BitMode]>;
955 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
956 IIC_PUSH_MEM>, Requires<[In64BitMode]>;
957 } // mayStore, SchedRW
960 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
961 SchedRW = [WriteStore] in {
962 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
963 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
964 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
965 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
966 Requires<[In64BitMode]>;
967 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
968 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
971 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
972 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
973 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
974 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
975 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
976 Requires<[In64BitMode]>, Sched<[WriteStore]>;
978 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
979 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
980 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
981 OpSize16, Requires<[Not64BitMode]>;
982 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
983 OpSize, Requires<[Not64BitMode]>;
985 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
986 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
987 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
988 OpSize16, Requires<[Not64BitMode]>;
989 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
990 OpSize, Requires<[Not64BitMode]>;
993 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
995 def BSWAP32r : I<0xC8, AddRegFrm,
996 (outs GR32:$dst), (ins GR32:$src),
998 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;
1000 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1002 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1003 } // Constraints = "$src = $dst", SchedRW
1005 // Bit scan instructions.
1006 let Defs = [EFLAGS] in {
1007 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1008 "bsf{w}\t{$src, $dst|$dst, $src}",
1009 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1010 IIC_BIT_SCAN_REG>, TB, OpSize, Sched<[WriteShift]>;
1011 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1012 "bsf{w}\t{$src, $dst|$dst, $src}",
1013 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1014 IIC_BIT_SCAN_MEM>, TB, OpSize, Sched<[WriteShiftLd]>;
1015 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1016 "bsf{l}\t{$src, $dst|$dst, $src}",
1017 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1018 IIC_BIT_SCAN_REG>, TB, OpSize16,
1019 Sched<[WriteShift]>;
1020 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1021 "bsf{l}\t{$src, $dst|$dst, $src}",
1022 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1023 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1024 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1025 "bsf{q}\t{$src, $dst|$dst, $src}",
1026 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1027 IIC_BIT_SCAN_REG>, TB, Sched<[WriteShift]>;
1028 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1029 "bsf{q}\t{$src, $dst|$dst, $src}",
1030 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1031 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1033 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1034 "bsr{w}\t{$src, $dst|$dst, $src}",
1035 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1037 TB, OpSize, Sched<[WriteShift]>;
1038 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1039 "bsr{w}\t{$src, $dst|$dst, $src}",
1040 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1041 IIC_BIT_SCAN_MEM>, TB,
1042 OpSize, Sched<[WriteShiftLd]>;
1043 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1044 "bsr{l}\t{$src, $dst|$dst, $src}",
1045 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1046 IIC_BIT_SCAN_REG>, TB, OpSize16,
1047 Sched<[WriteShift]>;
1048 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1049 "bsr{l}\t{$src, $dst|$dst, $src}",
1050 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1051 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1052 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1053 "bsr{q}\t{$src, $dst|$dst, $src}",
1054 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
1055 Sched<[WriteShift]>;
1056 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1057 "bsr{q}\t{$src, $dst|$dst, $src}",
1058 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1059 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1060 } // Defs = [EFLAGS]
1062 let SchedRW = [WriteMicrocoded] in {
1063 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1064 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1065 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
1066 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
1067 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>, OpSize16;
1068 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
1071 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1072 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1073 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
1074 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1075 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
1076 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1077 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>, OpSize16;
1078 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1079 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
1081 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
1082 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
1083 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>,
1085 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
1087 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
1088 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
1089 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>,
1091 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
1094 //===----------------------------------------------------------------------===//
1095 // Move Instructions.
1097 let SchedRW = [WriteMove] in {
1098 let neverHasSideEffects = 1 in {
1099 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1100 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1101 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1102 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1103 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1104 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1105 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1106 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1109 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1110 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1111 "mov{b}\t{$src, $dst|$dst, $src}",
1112 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1113 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1114 "mov{w}\t{$src, $dst|$dst, $src}",
1115 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1116 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1117 "mov{l}\t{$src, $dst|$dst, $src}",
1118 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
1119 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1120 "movabs{q}\t{$src, $dst|$dst, $src}",
1121 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1122 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1123 "mov{q}\t{$src, $dst|$dst, $src}",
1124 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1128 let SchedRW = [WriteStore] in {
1129 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1130 "mov{b}\t{$src, $dst|$dst, $src}",
1131 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1132 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1133 "mov{w}\t{$src, $dst|$dst, $src}",
1134 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1135 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1136 "mov{l}\t{$src, $dst|$dst, $src}",
1137 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1138 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1139 "mov{q}\t{$src, $dst|$dst, $src}",
1140 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1143 let hasSideEffects = 0 in {
1145 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1146 /// 32-bit offset from the segment base. These are only valid in x86-32 mode.
1147 let SchedRW = [WriteALU] in {
1148 let mayLoad = 1 in {
1149 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1150 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1151 Requires<[In32BitMode]>;
1152 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1153 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1154 Requires<[In32BitMode]>;
1155 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1156 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1157 OpSize16, Requires<[In32BitMode]>;
1159 def MOV8o8a_16 : Ii16 <0xA0, RawFrm, (outs), (ins offset8:$src),
1160 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1161 AdSize, Requires<[In16BitMode]>;
1162 def MOV16o16a_16 : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
1163 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1164 AdSize, Requires<[In16BitMode]>;
1165 def MOV32o32a_16 : Ii16 <0xA1, RawFrm, (outs), (ins offset32:$src),
1166 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1167 AdSize, OpSize16, Requires<[In16BitMode]>;
1169 let mayStore = 1 in {
1170 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1171 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1172 Requires<[In32BitMode]>;
1173 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1174 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1175 Requires<[In32BitMode]>;
1176 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1177 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1178 OpSize16, Requires<[In32BitMode]>;
1180 def MOV8ao8_16 : Ii16 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1181 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1182 AdSize, Requires<[In16BitMode]>;
1183 def MOV16ao16_16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1184 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1185 AdSize, Requires<[In16BitMode]>;
1186 def MOV32ao32_16 : Ii16 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1187 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1188 OpSize16, AdSize, Requires<[In16BitMode]>;
1192 // These forms all have full 64-bit absolute addresses in their instructions
1193 // and use the movabs mnemonic to indicate this specific form.
1194 let mayLoad = 1 in {
1195 def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset8:$src),
1196 "movabs{b}\t{$src, %al|al, $src}", []>,
1197 Requires<[In64BitMode]>;
1198 def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset16:$src),
1199 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
1200 Requires<[In64BitMode]>;
1201 def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset32:$src),
1202 "movabs{l}\t{$src, %eax|eax, $src}", []>,
1203 Requires<[In64BitMode]>;
1204 def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src),
1205 "movabs{q}\t{$src, %rax|rax, $src}", []>,
1206 Requires<[In64BitMode]>;
1209 let mayStore = 1 in {
1210 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset8:$dst), (ins),
1211 "movabs{b}\t{%al, $dst|$dst, al}", []>,
1212 Requires<[In64BitMode]>;
1213 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset16:$dst), (ins),
1214 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
1215 Requires<[In64BitMode]>;
1216 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset32:$dst), (ins),
1217 "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
1218 Requires<[In64BitMode]>;
1219 def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins),
1220 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1221 Requires<[In64BitMode]>;
1223 } // hasSideEffects = 0
1225 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1226 SchedRW = [WriteMove] in {
1227 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1228 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1229 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1230 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1231 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1232 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1233 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1234 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1237 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1238 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1239 "mov{b}\t{$src, $dst|$dst, $src}",
1240 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1241 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1242 "mov{w}\t{$src, $dst|$dst, $src}",
1243 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1244 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1245 "mov{l}\t{$src, $dst|$dst, $src}",
1246 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;
1247 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1248 "mov{q}\t{$src, $dst|$dst, $src}",
1249 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1252 let SchedRW = [WriteStore] in {
1253 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1254 "mov{b}\t{$src, $dst|$dst, $src}",
1255 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1256 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1257 "mov{w}\t{$src, $dst|$dst, $src}",
1258 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1259 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1260 "mov{l}\t{$src, $dst|$dst, $src}",
1261 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1262 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1263 "mov{q}\t{$src, $dst|$dst, $src}",
1264 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1267 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1268 // that they can be used for copying and storing h registers, which can't be
1269 // encoded when a REX prefix is present.
1270 let isCodeGenOnly = 1 in {
1271 let neverHasSideEffects = 1 in
1272 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1273 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1274 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1276 let mayStore = 1, neverHasSideEffects = 1 in
1277 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1278 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1279 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1280 IIC_MOV_MEM>, Sched<[WriteStore]>;
1281 let mayLoad = 1, neverHasSideEffects = 1,
1282 canFoldAsLoad = 1, isReMaterializable = 1 in
1283 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1284 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1285 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1286 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1290 // Condition code ops, incl. set if equal/not equal/...
1291 let SchedRW = [WriteALU] in {
1292 let Defs = [EFLAGS], Uses = [AH] in
1293 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1294 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1295 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1296 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1297 IIC_AHF>; // AH = flags
1300 //===----------------------------------------------------------------------===//
1301 // Bit tests instructions: BT, BTS, BTR, BTC.
1303 let Defs = [EFLAGS] in {
1304 let SchedRW = [WriteALU] in {
1305 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1306 "bt{w}\t{$src2, $src1|$src1, $src2}",
1307 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1309 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1310 "bt{l}\t{$src2, $src1|$src1, $src2}",
1311 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1313 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1314 "bt{q}\t{$src2, $src1|$src1, $src2}",
1315 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1318 // Unlike with the register+register form, the memory+register form of the
1319 // bt instruction does not ignore the high bits of the index. From ISel's
1320 // perspective, this is pretty bizarre. Make these instructions disassembly
1323 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1324 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1325 "bt{w}\t{$src2, $src1|$src1, $src2}",
1326 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1327 // (implicit EFLAGS)]
1329 >, OpSize, TB, Requires<[FastBTMem]>;
1330 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1331 "bt{l}\t{$src2, $src1|$src1, $src2}",
1332 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1333 // (implicit EFLAGS)]
1335 >, OpSize16, TB, Requires<[FastBTMem]>;
1336 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1337 "bt{q}\t{$src2, $src1|$src1, $src2}",
1338 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1339 // (implicit EFLAGS)]
1344 let SchedRW = [WriteALU] in {
1345 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1346 "bt{w}\t{$src2, $src1|$src1, $src2}",
1347 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1348 IIC_BT_RI>, OpSize, TB;
1349 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1350 "bt{l}\t{$src2, $src1|$src1, $src2}",
1351 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1352 IIC_BT_RI>, OpSize16, TB;
1353 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1354 "bt{q}\t{$src2, $src1|$src1, $src2}",
1355 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1359 // Note that these instructions don't need FastBTMem because that
1360 // only applies when the other operand is in a register. When it's
1361 // an immediate, bt is still fast.
1362 let SchedRW = [WriteALU] in {
1363 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1364 "bt{w}\t{$src2, $src1|$src1, $src2}",
1365 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1366 ], IIC_BT_MI>, OpSize, TB;
1367 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1368 "bt{l}\t{$src2, $src1|$src1, $src2}",
1369 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1370 ], IIC_BT_MI>, OpSize16, TB;
1371 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1372 "bt{q}\t{$src2, $src1|$src1, $src2}",
1373 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1374 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1377 let hasSideEffects = 0 in {
1378 let SchedRW = [WriteALU] in {
1379 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1380 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1382 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1383 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1385 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1386 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1389 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1390 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1391 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1393 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1394 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1396 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1397 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1400 let SchedRW = [WriteALU] in {
1401 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1402 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1404 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1405 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1407 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1408 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1411 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1412 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1413 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1415 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1416 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1418 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1419 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1422 let SchedRW = [WriteALU] in {
1423 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1424 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1426 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1427 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1429 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1430 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1433 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1434 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1435 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1437 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1438 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1440 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1441 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1444 let SchedRW = [WriteALU] in {
1445 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1446 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1448 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1449 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1451 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1452 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1455 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1456 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1457 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1459 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1460 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1462 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1463 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1466 let SchedRW = [WriteALU] in {
1467 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1468 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1470 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1471 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1473 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1474 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1477 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1478 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1479 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1481 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1482 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1484 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1485 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1488 let SchedRW = [WriteALU] in {
1489 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1490 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1492 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1493 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1495 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1496 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1499 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1500 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1501 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1503 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1504 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1506 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1507 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1509 } // hasSideEffects = 0
1510 } // Defs = [EFLAGS]
1513 //===----------------------------------------------------------------------===//
1517 // Atomic swap. These are just normal xchg instructions. But since a memory
1518 // operand is referenced, the atomicity is ensured.
1519 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1520 InstrItinClass itin> {
1521 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1522 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1523 (ins GR8:$val, i8mem:$ptr),
1524 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1527 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1529 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1530 (ins GR16:$val, i16mem:$ptr),
1531 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1534 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1536 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1537 (ins GR32:$val, i32mem:$ptr),
1538 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1541 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1543 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1544 (ins GR64:$val, i64mem:$ptr),
1545 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1548 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1553 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1555 // Swap between registers.
1556 let SchedRW = [WriteALU] in {
1557 let Constraints = "$val = $dst" in {
1558 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1559 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1560 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1561 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1562 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1563 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1565 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1566 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1569 // Swap between EAX and other registers.
1570 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1571 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
1572 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1573 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1574 OpSize16, Requires<[Not64BitMode]>;
1575 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1576 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1577 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1578 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1579 Requires<[In64BitMode]>;
1580 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1581 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1584 let SchedRW = [WriteALU] in {
1585 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1586 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1587 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1588 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1590 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1591 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1593 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1594 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1597 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1598 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1599 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1600 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1601 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1603 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1604 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1606 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1607 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1611 let SchedRW = [WriteALU] in {
1612 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1613 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1614 IIC_CMPXCHG_REG8>, TB;
1615 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1616 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1617 IIC_CMPXCHG_REG>, TB, OpSize;
1618 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1619 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1620 IIC_CMPXCHG_REG>, TB, OpSize16;
1621 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1622 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1623 IIC_CMPXCHG_REG>, TB;
1626 let SchedRW = [WriteALULd, WriteRMW] in {
1627 let mayLoad = 1, mayStore = 1 in {
1628 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1629 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1630 IIC_CMPXCHG_MEM8>, TB;
1631 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1632 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1633 IIC_CMPXCHG_MEM>, TB, OpSize;
1634 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1635 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1636 IIC_CMPXCHG_MEM>, TB, OpSize16;
1637 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1638 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1639 IIC_CMPXCHG_MEM>, TB;
1642 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1643 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1644 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1646 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1647 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1648 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1649 TB, Requires<[HasCmpxchg16b]>;
1653 // Lock instruction prefix
1654 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1656 // Rex64 instruction prefix
1657 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1658 Requires<[In64BitMode]>;
1660 // Data16 instruction prefix
1661 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1663 // Repeat string operation instruction prefixes
1664 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1665 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1666 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1667 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1668 // Repeat while not equal (used with CMPS and SCAS)
1669 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1673 // String manipulation instructions
1674 let SchedRW = [WriteMicrocoded] in {
1675 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1676 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1677 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>, OpSize16;
1678 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1681 let SchedRW = [WriteSystem] in {
1682 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1683 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1684 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>, OpSize16;
1687 // Flag instructions
1688 let SchedRW = [WriteALU] in {
1689 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1690 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1691 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1692 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1693 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1694 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1695 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1697 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1700 // Table lookup instructions
1701 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1704 let SchedRW = [WriteMicrocoded] in {
1705 // ASCII Adjust After Addition
1706 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1707 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1708 Requires<[Not64BitMode]>;
1710 // ASCII Adjust AX Before Division
1711 // sets AL, AH and EFLAGS and uses AL and AH
1712 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1713 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1715 // ASCII Adjust AX After Multiply
1716 // sets AL, AH and EFLAGS and uses AL
1717 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1718 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1720 // ASCII Adjust AL After Subtraction - sets
1721 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1722 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1723 Requires<[Not64BitMode]>;
1725 // Decimal Adjust AL after Addition
1726 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1727 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1728 Requires<[Not64BitMode]>;
1730 // Decimal Adjust AL after Subtraction
1731 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1732 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1733 Requires<[Not64BitMode]>;
1736 let SchedRW = [WriteSystem] in {
1737 // Check Array Index Against Bounds
1738 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1739 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1740 Requires<[Not64BitMode]>;
1741 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1742 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1743 Requires<[Not64BitMode]>;
1745 // Adjust RPL Field of Segment Selector
1746 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1747 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1748 Requires<[Not64BitMode]>;
1749 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1750 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1751 Requires<[Not64BitMode]>;
1754 //===----------------------------------------------------------------------===//
1755 // MOVBE Instructions
1757 let Predicates = [HasMOVBE] in {
1758 let SchedRW = [WriteALULd] in {
1759 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1760 "movbe{w}\t{$src, $dst|$dst, $src}",
1761 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1763 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1764 "movbe{l}\t{$src, $dst|$dst, $src}",
1765 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1767 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1768 "movbe{q}\t{$src, $dst|$dst, $src}",
1769 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1772 let SchedRW = [WriteStore] in {
1773 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1774 "movbe{w}\t{$src, $dst|$dst, $src}",
1775 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1777 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1778 "movbe{l}\t{$src, $dst|$dst, $src}",
1779 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1781 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1782 "movbe{q}\t{$src, $dst|$dst, $src}",
1783 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1788 //===----------------------------------------------------------------------===//
1789 // RDRAND Instruction
1791 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1792 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1794 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1795 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1797 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1798 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1800 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1803 //===----------------------------------------------------------------------===//
1804 // RDSEED Instruction
1806 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1807 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1809 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1810 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1812 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1813 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1815 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1818 //===----------------------------------------------------------------------===//
1819 // LZCNT Instruction
1821 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1822 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1823 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1824 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1826 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1827 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1828 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1829 (implicit EFLAGS)]>, XS, OpSize;
1831 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1832 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1833 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1835 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1836 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1837 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1838 (implicit EFLAGS)]>, XS, OpSize16;
1840 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1841 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1842 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1844 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1845 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1846 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1847 (implicit EFLAGS)]>, XS;
1850 //===----------------------------------------------------------------------===//
1853 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1854 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1855 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1856 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1858 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1859 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1860 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1861 (implicit EFLAGS)]>, XS, OpSize;
1863 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1864 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1865 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
1867 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1868 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1869 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1870 (implicit EFLAGS)]>, XS, OpSize16;
1872 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1873 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1874 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1876 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1877 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1878 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1879 (implicit EFLAGS)]>, XS;
1882 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1883 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1885 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1886 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1887 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1888 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1889 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1890 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1894 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1895 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1897 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1898 X86blsr, loadi64>, VEX_W;
1899 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1900 X86blsmsk, loadi32>;
1901 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1902 X86blsmsk, loadi64>, VEX_W;
1903 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1905 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1906 X86blsi, loadi64>, VEX_W;
1909 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1910 X86MemOperand x86memop, Intrinsic Int,
1912 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1913 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1914 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1916 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1917 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1918 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1919 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1922 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1923 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1924 int_x86_bmi_bextr_32, loadi32>;
1925 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1926 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1929 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1930 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1931 int_x86_bmi_bzhi_32, loadi32>;
1932 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1933 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1936 def : Pat<(X86bzhi GR32:$src1, GR8:$src2),
1937 (BZHI32rr GR32:$src1,
1938 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1939 def : Pat<(X86bzhi (loadi32 addr:$src1), GR8:$src2),
1940 (BZHI32rm addr:$src1,
1941 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1942 def : Pat<(X86bzhi GR64:$src1, GR8:$src2),
1943 (BZHI64rr GR64:$src1,
1944 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1945 def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),
1946 (BZHI64rm addr:$src1,
1947 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1949 let Predicates = [HasBMI] in {
1950 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
1951 (BEXTR32rr GR32:$src1, GR32:$src2)>;
1952 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
1953 (BEXTR32rm addr:$src1, GR32:$src2)>;
1954 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
1955 (BEXTR64rr GR64:$src1, GR64:$src2)>;
1956 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
1957 (BEXTR64rm addr:$src1, GR64:$src2)>;
1960 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1961 X86MemOperand x86memop, Intrinsic Int,
1963 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1964 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1965 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1967 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1968 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1969 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1972 let Predicates = [HasBMI2] in {
1973 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1974 int_x86_bmi_pdep_32, loadi32>, T8XD;
1975 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1976 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1977 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1978 int_x86_bmi_pext_32, loadi32>, T8XS;
1979 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1980 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1983 //===----------------------------------------------------------------------===//
1986 let Predicates = [HasTBM], Defs = [EFLAGS] in {
1988 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
1989 X86MemOperand x86memop, PatFrag ld_frag,
1990 Intrinsic Int, Operand immtype,
1991 SDPatternOperator immoperator> {
1992 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
1993 !strconcat(OpcodeStr,
1994 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
1995 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
1997 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
1998 (ins x86memop:$src1, immtype:$cntl),
1999 !strconcat(OpcodeStr,
2000 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2001 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2005 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2006 int_x86_tbm_bextri_u32, i32imm, imm>;
2007 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2008 int_x86_tbm_bextri_u64, i64i32imm,
2009 i64immSExt32>, VEX_W;
2011 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2012 RegisterClass RC, string OpcodeStr,
2013 X86MemOperand x86memop, PatFrag ld_frag> {
2014 let hasSideEffects = 0 in {
2015 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2016 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2017 []>, XOP, XOP9, VEX_4V;
2019 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2020 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2021 []>, XOP, XOP9, VEX_4V;
2025 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2026 Format FormReg, Format FormMem> {
2027 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2029 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2033 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2034 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2035 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2036 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2037 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2038 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2039 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2040 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2041 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2044 //===----------------------------------------------------------------------===//
2045 // Pattern fragments to auto generate TBM instructions.
2046 //===----------------------------------------------------------------------===//
2048 let Predicates = [HasTBM] in {
2049 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2050 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2051 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2052 (BEXTRI32mi addr:$src1, imm:$src2)>;
2053 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2054 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2055 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2056 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2058 // FIXME: patterns for the load versions are not implemented
2059 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2060 (BLCFILL32rr GR32:$src)>;
2061 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2062 (BLCFILL64rr GR64:$src)>;
2064 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2065 (BLCI32rr GR32:$src)>;
2066 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2067 (BLCI64rr GR64:$src)>;
2069 // Extra patterns because opt can optimize the above patterns to this.
2070 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2071 (BLCI32rr GR32:$src)>;
2072 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2073 (BLCI64rr GR64:$src)>;
2075 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2076 (BLCIC32rr GR32:$src)>;
2077 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2078 (BLCIC64rr GR64:$src)>;
2080 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2081 (BLCMSK32rr GR32:$src)>;
2082 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2083 (BLCMSK64rr GR64:$src)>;
2085 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2086 (BLCS32rr GR32:$src)>;
2087 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2088 (BLCS64rr GR64:$src)>;
2090 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2091 (BLSFILL32rr GR32:$src)>;
2092 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2093 (BLSFILL64rr GR64:$src)>;
2095 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2096 (BLSIC32rr GR32:$src)>;
2097 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2098 (BLSIC64rr GR64:$src)>;
2100 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2101 (T1MSKC32rr GR32:$src)>;
2102 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2103 (T1MSKC64rr GR64:$src)>;
2105 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2106 (TZMSK32rr GR32:$src)>;
2107 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2108 (TZMSK64rr GR64:$src)>;
2111 //===----------------------------------------------------------------------===//
2113 //===----------------------------------------------------------------------===//
2115 include "X86InstrArithmetic.td"
2116 include "X86InstrCMovSetCC.td"
2117 include "X86InstrExtension.td"
2118 include "X86InstrControl.td"
2119 include "X86InstrShiftRotate.td"
2121 // X87 Floating Point Stack.
2122 include "X86InstrFPStack.td"
2124 // SIMD support (SSE, MMX and AVX)
2125 include "X86InstrFragmentsSIMD.td"
2127 // FMA - Fused Multiply-Add support (requires FMA)
2128 include "X86InstrFMA.td"
2131 include "X86InstrXOP.td"
2133 // SSE, MMX and 3DNow! vector support.
2134 include "X86InstrSSE.td"
2135 include "X86InstrAVX512.td"
2136 include "X86InstrMMX.td"
2137 include "X86Instr3DNow.td"
2139 include "X86InstrVMX.td"
2140 include "X86InstrSVM.td"
2142 include "X86InstrTSX.td"
2144 // System instructions.
2145 include "X86InstrSystem.td"
2147 // Compiler Pseudo Instructions and Pat Patterns
2148 include "X86InstrCompiler.td"
2150 //===----------------------------------------------------------------------===//
2151 // Assembler Mnemonic Aliases
2152 //===----------------------------------------------------------------------===//
2154 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2155 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2156 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2158 def : MnemonicAlias<"cbw", "cbtw", "att">;
2159 def : MnemonicAlias<"cwde", "cwtl", "att">;
2160 def : MnemonicAlias<"cwd", "cwtd", "att">;
2161 def : MnemonicAlias<"cdq", "cltd", "att">;
2162 def : MnemonicAlias<"cdqe", "cltq", "att">;
2163 def : MnemonicAlias<"cqo", "cqto", "att">;
2165 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2166 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2167 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2169 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2170 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2172 def : MnemonicAlias<"loopz", "loope", "att">;
2173 def : MnemonicAlias<"loopnz", "loopne", "att">;
2175 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2176 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2177 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2178 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2179 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2180 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2181 def : MnemonicAlias<"popfd", "popfl", "att">;
2183 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2184 // all modes. However: "push (addr)" and "push $42" should default to
2185 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2186 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2187 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2188 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2189 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2190 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2191 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2192 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2194 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2195 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2196 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2197 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2198 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2199 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2201 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2202 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2203 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2204 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2206 def : MnemonicAlias<"repe", "rep", "att">;
2207 def : MnemonicAlias<"repz", "rep", "att">;
2208 def : MnemonicAlias<"repnz", "repne", "att">;
2210 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2211 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2212 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2214 def : MnemonicAlias<"salb", "shlb", "att">;
2215 def : MnemonicAlias<"salw", "shlw", "att">;
2216 def : MnemonicAlias<"sall", "shll", "att">;
2217 def : MnemonicAlias<"salq", "shlq", "att">;
2219 def : MnemonicAlias<"smovb", "movsb", "att">;
2220 def : MnemonicAlias<"smovw", "movsw", "att">;
2221 def : MnemonicAlias<"smovl", "movsl", "att">;
2222 def : MnemonicAlias<"smovq", "movsq", "att">;
2224 def : MnemonicAlias<"ud2a", "ud2", "att">;
2225 def : MnemonicAlias<"verrw", "verr", "att">;
2227 // System instruction aliases.
2228 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2229 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2230 def : MnemonicAlias<"sysret", "sysretl", "att">;
2231 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2233 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2234 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2235 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2236 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2237 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2238 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2239 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2240 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2241 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2242 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2243 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2244 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2247 // Floating point stack aliases.
2248 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2249 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2250 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2251 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2252 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2253 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2254 def : MnemonicAlias<"fildq", "fildll", "att">;
2255 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2256 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2257 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2258 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2259 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2260 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2261 def : MnemonicAlias<"fwait", "wait", "att">;
2264 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2266 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2267 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2269 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2270 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2271 /// example "setz" -> "sete".
2272 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2274 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2275 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2276 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2277 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2278 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2279 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2280 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2281 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2282 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2283 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2285 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2286 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2287 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2288 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2291 // Aliases for set<CC>
2292 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2293 // Aliases for j<CC>
2294 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2295 // Aliases for cmov<CC>{w,l,q}
2296 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2297 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2298 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2299 // No size suffix for intel-style asm.
2300 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2303 //===----------------------------------------------------------------------===//
2304 // Assembler Instruction Aliases
2305 //===----------------------------------------------------------------------===//
2307 // aad/aam default to base 10 if no operand is specified.
2308 def : InstAlias<"aad", (AAD8i8 10)>;
2309 def : InstAlias<"aam", (AAM8i8 10)>;
2311 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2312 // Likewise for btc/btr/bts.
2313 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2314 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2315 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2316 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2317 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2318 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2319 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2320 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2323 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2324 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2325 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2326 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2328 // div and idiv aliases for explicit A register.
2329 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2330 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2331 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2332 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2333 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2334 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2335 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2336 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2337 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2338 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2339 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2340 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2341 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2342 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2343 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2344 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2348 // Various unary fpstack operations default to operating on on ST1.
2349 // For example, "fxch" -> "fxch %st(1)"
2350 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2351 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2352 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2353 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2354 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2355 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2356 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2357 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2358 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2359 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2360 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2361 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2362 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2363 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2364 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2366 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2367 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2368 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2370 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2371 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2372 (Inst RST:$op), EmitAlias>;
2373 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2374 (Inst ST0), EmitAlias>;
2377 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2378 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2379 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2380 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2381 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2382 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2383 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2384 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2385 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2386 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2387 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2388 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2389 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2390 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2391 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2392 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2395 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2396 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2397 // solely because gas supports it.
2398 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2399 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2400 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2401 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2402 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2403 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2405 // We accept "fnstsw %eax" even though it only writes %ax.
2406 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2407 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2408 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2410 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2411 // this is compatible with what GAS does.
2412 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2413 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2414 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2415 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2416 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2417 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2418 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2419 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2421 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst)>, Requires<[In64BitMode]>;
2422 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst)>, Requires<[In64BitMode]>;
2423 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst)>, Requires<[In32BitMode]>;
2424 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst)>, Requires<[In32BitMode]>;
2425 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst)>, Requires<[In16BitMode]>;
2426 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst)>, Requires<[In16BitMode]>;
2429 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2430 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2431 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2432 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2433 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2434 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2435 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2437 // inb %dx -> inb %al, %dx
2438 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2439 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2440 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2441 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2442 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2443 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2446 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2447 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2448 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2449 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2450 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2451 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2452 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2453 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2454 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2456 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2457 // the move. All segment/mem forms are equivalent, this has the shortest
2459 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2460 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2462 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2463 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2465 // Match 'movq GR64, MMX' as an alias for movd.
2466 def : InstAlias<"movq $src, $dst",
2467 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2468 def : InstAlias<"movq $src, $dst",
2469 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2471 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2472 // alias for movsl. (as in rep; movsd)
2473 def : InstAlias<"movsd", (MOVSD), 0>;
2476 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2477 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2478 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2479 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2480 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2481 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2482 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2485 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2486 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2487 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2488 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2489 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2490 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2491 // Note: No GR32->GR64 movzx form.
2493 // outb %dx -> outb %al, %dx
2494 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2495 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2496 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2497 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2498 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2499 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2501 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2502 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2503 // errors, since its encoding is the most compact.
2504 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2506 // shld/shrd op,op -> shld op, op, CL
2507 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2508 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2509 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2510 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2511 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2512 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2514 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2515 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2516 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2517 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2518 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2519 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2521 /* FIXME: This is disabled because the asm matcher is currently incapable of
2522 * matching a fixed immediate like $1.
2523 // "shl X, $1" is an alias for "shl X".
2524 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2525 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2526 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2527 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2528 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2529 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2530 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2531 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2532 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2533 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2534 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2535 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2536 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2537 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2538 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2539 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2540 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2543 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2544 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2545 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2546 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2549 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2550 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", (TEST8rm GR8 :$val, i8mem :$mem)>;
2551 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", (TEST16rm GR16:$val, i16mem:$mem)>;
2552 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", (TEST32rm GR32:$val, i32mem:$mem)>;
2553 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", (TEST64rm GR64:$val, i64mem:$mem)>;
2555 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2556 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2557 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", (XCHG16rm GR16:$val, i16mem:$mem)>;
2558 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:$mem)>;
2559 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
2561 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2562 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
2563 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[Not64BitMode]>;
2564 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2565 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;