1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, FlagVT>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, FlagVT>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
35 [SDTCisVT<0, i8>, SDTCisVT<1, i8>,
36 SDTCisVT<2, FlagVT>]>;
38 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
40 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
41 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
44 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>;
47 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
49 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
50 SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
51 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
52 SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
53 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
54 SDTCisVT<2, OtherVT>]>;
56 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
58 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
60 def X86addflag : SDNode<"X86ISD::ADD_FLAG", SDTIntBinOp ,
61 [SDNPCommutative, SDNPAssociative, SDNPOutFlag]>;
62 def X86subflag : SDNode<"X86ISD::SUB_FLAG", SDTIntBinOp,
64 def X86adc : SDNode<"X86ISD::ADC" , SDTIntBinOp ,
65 [SDNPCommutative, SDNPAssociative]>;
66 def X86sbb : SDNode<"X86ISD::SBB" , SDTIntBinOp>;
68 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
69 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
71 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
72 def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
74 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
76 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
78 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
81 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
82 [SDNPHasChain, SDNPOptInFlag]>;
84 def X86callseq_start :
85 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
88 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
91 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
92 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
94 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
95 [SDNPHasChain, SDNPInFlag]>;
96 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
97 [SDNPHasChain, SDNPOutFlag]>;
99 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
101 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
103 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
106 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
107 [SDNPHasChain, SDNPInFlag]>;
108 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
109 [SDNPHasChain, SDNPInFlag]>;
111 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
112 [SDNPHasChain, SDNPOutFlag]>;
114 //===----------------------------------------------------------------------===//
115 // X86 Operand Definitions.
118 // *mem - Operand definitions for the funky X86 addressing mode operands.
120 class X86MemOperand<string printMethod> : Operand<i32> {
121 let PrintMethod = printMethod;
122 let NumMIOperands = 4;
123 let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
126 def i8mem : X86MemOperand<"printi8mem">;
127 def i16mem : X86MemOperand<"printi16mem">;
128 def i32mem : X86MemOperand<"printi32mem">;
129 def i64mem : X86MemOperand<"printi64mem">;
130 def f32mem : X86MemOperand<"printf32mem">;
131 def f64mem : X86MemOperand<"printf64mem">;
132 def f80mem : X86MemOperand<"printf80mem">;
134 def SSECC : Operand<i8> {
135 let PrintMethod = "printSSECC";
138 // A couple of more descriptive operand definitions.
139 // 16-bits but only 8 bits are significant.
140 def i16i8imm : Operand<i16>;
141 // 32-bits but only 8 bits are significant.
142 def i32i8imm : Operand<i32>;
144 // PCRelative calls need special operand formatting.
145 let PrintMethod = "printCallOperand" in
146 def calltarget : Operand<i32>;
148 // Branch targets have OtherVT type.
149 def brtarget : Operand<OtherVT>;
151 //===----------------------------------------------------------------------===//
152 // X86 Complex Pattern Definitions.
155 // Define X86 specific addressing mode.
156 def addr : ComplexPattern<i32, 4, "SelectAddr", []>;
157 def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr",
158 [add, frameindex, constpool]>;
160 //===----------------------------------------------------------------------===//
161 // X86 Instruction Format Definitions.
164 // Format specifies the encoding used by the instruction. This is part of the
165 // ad-hoc solution used to emit machine instruction encodings by our machine
167 class Format<bits<5> val> {
171 def Pseudo : Format<0>; def RawFrm : Format<1>;
172 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
173 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
174 def MRMSrcMem : Format<6>;
175 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
176 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
177 def MRM6r : Format<22>; def MRM7r : Format<23>;
178 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
179 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
180 def MRM6m : Format<30>; def MRM7m : Format<31>;
182 //===----------------------------------------------------------------------===//
183 // X86 Instruction Predicate Definitions.
184 def HasSSE1 : Predicate<"X86Vector >= SSE">;
185 def HasSSE2 : Predicate<"X86Vector >= SSE2">;
186 def HasSSE3 : Predicate<"X86Vector >= SSE3">;
187 def FPStack : Predicate<"X86Vector < SSE2">;
189 //===----------------------------------------------------------------------===//
190 // X86 specific pattern fragments.
193 // ImmType - This specifies the immediate type used by an instruction. This is
194 // part of the ad-hoc solution used to emit machine instruction encodings by our
195 // machine code emitter.
196 class ImmType<bits<2> val> {
199 def NoImm : ImmType<0>;
200 def Imm8 : ImmType<1>;
201 def Imm16 : ImmType<2>;
202 def Imm32 : ImmType<3>;
204 // FPFormat - This specifies what form this FP instruction has. This is used by
205 // the Floating-Point stackifier pass.
206 class FPFormat<bits<3> val> {
209 def NotFP : FPFormat<0>;
210 def ZeroArgFP : FPFormat<1>;
211 def OneArgFP : FPFormat<2>;
212 def OneArgFPRW : FPFormat<3>;
213 def TwoArgFP : FPFormat<4>;
214 def CompareFP : FPFormat<5>;
215 def CondMovFP : FPFormat<6>;
216 def SpecialFP : FPFormat<7>;
219 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
221 let Namespace = "X86";
223 bits<8> Opcode = opcod;
225 bits<5> FormBits = Form.Value;
227 bits<2> ImmTypeBits = ImmT.Value;
229 dag OperandList = ops;
230 string AsmString = AsmStr;
233 // Attributes specific to X86 instructions...
235 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
237 bits<4> Prefix = 0; // Which prefix byte does this inst have?
238 FPFormat FPForm; // What flavor of FP instruction is this?
239 bits<3> FPFormBits = 0;
242 class Imp<list<Register> uses, list<Register> defs> {
243 list<Register> Uses = uses;
244 list<Register> Defs = defs;
248 // Prefix byte classes which are used to indicate to the ad-hoc machine code
249 // emitter that various prefix bytes are required.
250 class OpSize { bit hasOpSizePrefix = 1; }
251 class TB { bits<4> Prefix = 1; }
252 class REP { bits<4> Prefix = 2; }
253 class D8 { bits<4> Prefix = 3; }
254 class D9 { bits<4> Prefix = 4; }
255 class DA { bits<4> Prefix = 5; }
256 class DB { bits<4> Prefix = 6; }
257 class DC { bits<4> Prefix = 7; }
258 class DD { bits<4> Prefix = 8; }
259 class DE { bits<4> Prefix = 9; }
260 class DF { bits<4> Prefix = 10; }
261 class XD { bits<4> Prefix = 11; }
262 class XS { bits<4> Prefix = 12; }
265 //===----------------------------------------------------------------------===//
266 // Pattern fragments...
269 // X86 specific condition code. These correspond to CondCode in
270 // X86ISelLowering.h. They must be kept in synch.
271 def X86_COND_A : PatLeaf<(i8 0)>;
272 def X86_COND_AE : PatLeaf<(i8 1)>;
273 def X86_COND_B : PatLeaf<(i8 2)>;
274 def X86_COND_BE : PatLeaf<(i8 3)>;
275 def X86_COND_E : PatLeaf<(i8 4)>;
276 def X86_COND_G : PatLeaf<(i8 5)>;
277 def X86_COND_GE : PatLeaf<(i8 6)>;
278 def X86_COND_L : PatLeaf<(i8 7)>;
279 def X86_COND_LE : PatLeaf<(i8 8)>;
280 def X86_COND_NE : PatLeaf<(i8 9)>;
281 def X86_COND_NO : PatLeaf<(i8 10)>;
282 def X86_COND_NP : PatLeaf<(i8 11)>;
283 def X86_COND_NS : PatLeaf<(i8 12)>;
284 def X86_COND_O : PatLeaf<(i8 13)>;
285 def X86_COND_P : PatLeaf<(i8 14)>;
286 def X86_COND_S : PatLeaf<(i8 15)>;
288 def i16immSExt8 : PatLeaf<(i16 imm), [{
289 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
290 // sign extended field.
291 return (int)N->getValue() == (signed char)N->getValue();
294 def i32immSExt8 : PatLeaf<(i32 imm), [{
295 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
296 // sign extended field.
297 return (int)N->getValue() == (signed char)N->getValue();
300 def i16immZExt8 : PatLeaf<(i16 imm), [{
301 // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero
303 return (unsigned)N->getValue() == (unsigned char)N->getValue();
306 def fp32imm0 : PatLeaf<(f32 fpimm), [{
307 return N->isExactlyValue(+0.0);
310 def fp64imm0 : PatLeaf<(f64 fpimm), [{
311 return N->isExactlyValue(+0.0);
314 def fp64immneg0 : PatLeaf<(f64 fpimm), [{
315 return N->isExactlyValue(-0.0);
318 def fp64imm1 : PatLeaf<(f64 fpimm), [{
319 return N->isExactlyValue(+1.0);
322 def fp64immneg1 : PatLeaf<(f64 fpimm), [{
323 return N->isExactlyValue(-1.0);
326 // Helper fragments for loads.
327 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
328 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
329 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
330 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
331 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
333 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
334 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
335 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
336 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>;
337 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>;
339 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>;
340 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>;
341 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>;
342 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>;
343 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
345 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
346 def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
348 //===----------------------------------------------------------------------===//
349 // Instruction templates...
351 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
352 : X86Inst<o, f, NoImm, ops, asm> {
353 let Pattern = pattern;
355 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
356 : X86Inst<o, f, Imm8 , ops, asm> {
357 let Pattern = pattern;
359 class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
360 : X86Inst<o, f, Imm16, ops, asm> {
361 let Pattern = pattern;
363 class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
364 : X86Inst<o, f, Imm32, ops, asm> {
365 let Pattern = pattern;
368 //===----------------------------------------------------------------------===//
369 // Instruction list...
372 // Pseudo-instructions:
373 def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node.
375 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
376 [(X86callseq_start imm:$amt)]>;
377 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
379 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
380 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
381 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
382 def IMPLICIT_DEF_R8 : I<0, Pseudo, (ops R8:$dst),
383 "#IMPLICIT_DEF $dst",
384 [(set R8:$dst, (undef))]>;
385 def IMPLICIT_DEF_R16 : I<0, Pseudo, (ops R16:$dst),
386 "#IMPLICIT_DEF $dst",
387 [(set R16:$dst, (undef))]>;
388 def IMPLICIT_DEF_R32 : I<0, Pseudo, (ops R32:$dst),
389 "#IMPLICIT_DEF $dst",
390 [(set R32:$dst, (undef))]>;
391 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
392 "#IMPLICIT_DEF $dst",
393 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
394 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
395 "#IMPLICIT_DEF $dst",
396 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
399 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
400 // scheduler into a branch sequence.
401 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
402 def CMOV_FR32 : I<0, Pseudo,
403 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
405 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
407 def CMOV_FR64 : I<0, Pseudo,
408 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
410 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
414 let isTerminator = 1 in
415 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
416 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
420 def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
422 //===----------------------------------------------------------------------===//
423 // Control Flow Instructions...
426 // Return instructions.
427 let isTerminator = 1, isReturn = 1, isBarrier = 1,
428 hasCtrlDep = 1, noResults = 1 in {
429 def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>;
430 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt",
431 [(X86retflag imm:$amt)]>;
434 // All branches are RawFrm, Void, Branch, and Terminators
435 let isBranch = 1, isTerminator = 1, noResults = 1 in
436 class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
437 I<opcode, RawFrm, ops, asm, pattern>;
439 // Conditional branches
441 def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
443 def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
444 [(X86brcond bb:$dst, X86_COND_E, STATUS)]>, Imp<[STATUS],[]>, TB;
445 def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
446 [(X86brcond bb:$dst, X86_COND_NE, STATUS)]>, Imp<[STATUS],[]>, TB;
447 def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
448 [(X86brcond bb:$dst, X86_COND_L, STATUS)]>, Imp<[STATUS],[]>, TB;
449 def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
450 [(X86brcond bb:$dst, X86_COND_LE, STATUS)]>, Imp<[STATUS],[]>, TB;
451 def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
452 [(X86brcond bb:$dst, X86_COND_G, STATUS)]>, Imp<[STATUS],[]>, TB;
453 def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
454 [(X86brcond bb:$dst, X86_COND_GE, STATUS)]>, Imp<[STATUS],[]>, TB;
456 def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
457 [(X86brcond bb:$dst, X86_COND_B, STATUS)]>, Imp<[STATUS],[]>, TB;
458 def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
459 [(X86brcond bb:$dst, X86_COND_BE, STATUS)]>, Imp<[STATUS],[]>, TB;
460 def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
461 [(X86brcond bb:$dst, X86_COND_A, STATUS)]>, Imp<[STATUS],[]>, TB;
462 def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
463 [(X86brcond bb:$dst, X86_COND_AE, STATUS)]>, Imp<[STATUS],[]>, TB;
465 def JS : IBr<0x88, (ops brtarget:$dst), "js $dst",
466 [(X86brcond bb:$dst, X86_COND_S, STATUS)]>, Imp<[STATUS],[]>, TB;
467 def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst",
468 [(X86brcond bb:$dst, X86_COND_NS, STATUS)]>, Imp<[STATUS],[]>, TB;
469 def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst",
470 [(X86brcond bb:$dst, X86_COND_P, STATUS)]>, Imp<[STATUS],[]>, TB;
471 def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst",
472 [(X86brcond bb:$dst, X86_COND_NP, STATUS)]>, Imp<[STATUS],[]>, TB;
473 def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst",
474 [(X86brcond bb:$dst, X86_COND_O, STATUS)]>, Imp<[STATUS],[]>, TB;
475 def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
476 [(X86brcond bb:$dst, X86_COND_NO, STATUS)]>, Imp<[STATUS],[]>, TB;
478 //===----------------------------------------------------------------------===//
479 // Call Instructions...
481 let isCall = 1, noResults = 1 in
482 // All calls clobber the non-callee saved registers...
483 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
484 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
485 def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst",
487 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst",
488 [(X86call R32:$dst)]>;
489 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst",
490 [(X86call (loadi32 addr:$dst))]>;
494 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
495 def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>;
496 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
497 def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>;
498 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
499 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
500 "jmp {*}$dst # TAIL CALL", []>;
502 // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
503 // way, except that it is marked as being a terminator. This causes the epilog
504 // inserter to insert reloads of callee saved registers BEFORE this. We need
505 // this until we have a more accurate way of tracking where the stack pointer is
506 // within a function.
507 let isTerminator = 1, isTwoAddress = 1 in
508 def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
509 "add{l} {$src2, $dst|$dst, $src2}", []>;
511 //===----------------------------------------------------------------------===//
512 // Miscellaneous Instructions...
514 def LEAVE : I<0xC9, RawFrm,
515 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
516 def POP32r : I<0x58, AddRegFrm,
517 (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
519 let isTwoAddress = 1 in // R32 = bswap R32
520 def BSWAP32r : I<0xC8, AddRegFrm,
521 (ops R32:$dst, R32:$src),
523 [(set R32:$dst, (bswap R32:$src))]>, TB;
525 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
526 (ops R8:$src1, R8:$src2),
527 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
528 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
529 (ops R16:$src1, R16:$src2),
530 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
531 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
532 (ops R32:$src1, R32:$src2),
533 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
535 def XCHG8mr : I<0x86, MRMDestMem,
536 (ops i8mem:$src1, R8:$src2),
537 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
538 def XCHG16mr : I<0x87, MRMDestMem,
539 (ops i16mem:$src1, R16:$src2),
540 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
541 def XCHG32mr : I<0x87, MRMDestMem,
542 (ops i32mem:$src1, R32:$src2),
543 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
544 def XCHG8rm : I<0x86, MRMSrcMem,
545 (ops R8:$src1, i8mem:$src2),
546 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
547 def XCHG16rm : I<0x87, MRMSrcMem,
548 (ops R16:$src1, i16mem:$src2),
549 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
550 def XCHG32rm : I<0x87, MRMSrcMem,
551 (ops R32:$src1, i32mem:$src2),
552 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
554 def LEA16r : I<0x8D, MRMSrcMem,
555 (ops R16:$dst, i32mem:$src),
556 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
557 def LEA32r : I<0x8D, MRMSrcMem,
558 (ops R32:$dst, i32mem:$src),
559 "lea{l} {$src|$dst}, {$dst|$src}",
560 [(set R32:$dst, leaaddr:$src)]>;
562 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
564 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
565 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}",
566 [(X86rep_movs i16)]>,
567 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
568 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}",
569 [(X86rep_movs i32)]>,
570 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
572 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}",
574 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
575 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}",
576 [(X86rep_stos i16)]>,
577 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
578 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}",
579 [(X86rep_stos i32)]>,
580 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
583 //===----------------------------------------------------------------------===//
584 // Input/Output Instructions...
586 def IN8rr : I<0xEC, RawFrm, (ops),
587 "in{b} {%dx, %al|%AL, %DX}",
588 [(set AL, (readport DX))]>, Imp<[DX], [AL]>;
589 def IN16rr : I<0xED, RawFrm, (ops),
590 "in{w} {%dx, %ax|%AX, %DX}",
591 [(set AX, (readport DX))]>, Imp<[DX], [AX]>, OpSize;
592 def IN32rr : I<0xED, RawFrm, (ops),
593 "in{l} {%dx, %eax|%EAX, %DX}",
594 [(set EAX, (readport DX))]>, Imp<[DX],[EAX]>;
596 def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
597 "in{b} {$port, %al|%AL, $port}",
598 [(set AL, (readport i16immZExt8:$port))]>,
600 def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
601 "in{w} {$port, %ax|%AX, $port}",
602 [(set AX, (readport i16immZExt8:$port))]>,
603 Imp<[], [AX]>, OpSize;
604 def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
605 "in{l} {$port, %eax|%EAX, $port}",
606 [(set EAX, (readport i16immZExt8:$port))]>,
609 def OUT8rr : I<0xEE, RawFrm, (ops),
610 "out{b} {%al, %dx|%DX, %AL}",
611 [(writeport AL, DX)]>, Imp<[DX, AL], []>;
612 def OUT16rr : I<0xEF, RawFrm, (ops),
613 "out{w} {%ax, %dx|%DX, %AX}",
614 [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
615 def OUT32rr : I<0xEF, RawFrm, (ops),
616 "out{l} {%eax, %dx|%DX, %EAX}",
617 [(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
619 def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
620 "out{b} {%al, $port|$port, %AL}",
621 [(writeport AL, i16immZExt8:$port)]>,
623 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
624 "out{w} {%ax, $port|$port, %AX}",
625 [(writeport AX, i16immZExt8:$port)]>,
626 Imp<[AX], []>, OpSize;
627 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
628 "out{l} {%eax, $port|$port, %EAX}",
629 [(writeport EAX, i16immZExt8:$port)]>,
632 //===----------------------------------------------------------------------===//
633 // Move Instructions...
635 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src),
636 "mov{b} {$src, $dst|$dst, $src}", []>;
637 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src),
638 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
639 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
640 "mov{l} {$src, $dst|$dst, $src}", []>;
641 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
642 "mov{b} {$src, $dst|$dst, $src}",
643 [(set R8:$dst, imm:$src)]>;
644 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
645 "mov{w} {$src, $dst|$dst, $src}",
646 [(set R16:$dst, imm:$src)]>, OpSize;
647 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
648 "mov{l} {$src, $dst|$dst, $src}",
649 [(set R32:$dst, imm:$src)]>;
650 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
651 "mov{b} {$src, $dst|$dst, $src}",
652 [(store (i8 imm:$src), addr:$dst)]>;
653 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
654 "mov{w} {$src, $dst|$dst, $src}",
655 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
656 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
657 "mov{l} {$src, $dst|$dst, $src}",
658 [(store (i32 imm:$src), addr:$dst)]>;
660 def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
661 "mov{b} {$src, $dst|$dst, $src}",
662 [(set R8:$dst, (load addr:$src))]>;
663 def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
664 "mov{w} {$src, $dst|$dst, $src}",
665 [(set R16:$dst, (load addr:$src))]>, OpSize;
666 def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
667 "mov{l} {$src, $dst|$dst, $src}",
668 [(set R32:$dst, (load addr:$src))]>;
670 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
671 "mov{b} {$src, $dst|$dst, $src}",
672 [(store R8:$src, addr:$dst)]>;
673 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
674 "mov{w} {$src, $dst|$dst, $src}",
675 [(store R16:$src, addr:$dst)]>, OpSize;
676 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
677 "mov{l} {$src, $dst|$dst, $src}",
678 [(store R32:$src, addr:$dst)]>;
680 //===----------------------------------------------------------------------===//
681 // Fixed-Register Multiplication and Division Instructions...
684 // Extra precision multiplication
685 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src",
686 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
687 // This probably ought to be moved to a def : Pat<> if the
688 // syntax can be accepted.
689 [(set AL, (mul AL, R8:$src))]>,
690 Imp<[AL],[AX]>; // AL,AH = AL*R8
691 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>,
692 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
693 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>,
694 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
695 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
697 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
698 // This probably ought to be moved to a def : Pat<> if the
699 // syntax can be accepted.
700 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
701 Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
702 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
703 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
704 OpSize; // AX,DX = AX*[mem16]
705 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
706 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
708 def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>,
709 Imp<[AL],[AX]>; // AL,AH = AL*R8
710 def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>,
711 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
712 def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>,
713 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
714 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
715 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
716 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
717 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
718 OpSize; // AX,DX = AX*[mem16]
719 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
721 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
723 // unsigned division/remainder
724 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH
725 "div{b} $src", []>, Imp<[AX],[AX]>;
726 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX
727 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
728 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
729 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
730 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
731 "div{b} $src", []>, Imp<[AX],[AX]>;
732 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
733 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
734 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
735 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
737 // Signed division/remainder.
738 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH
739 "idiv{b} $src", []>, Imp<[AX],[AX]>;
740 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX
741 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
742 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
743 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
744 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
745 "idiv{b} $src", []>, Imp<[AX],[AX]>;
746 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
747 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
748 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
749 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
751 // Sign-extenders for division.
752 def CBW : I<0x98, RawFrm, (ops),
753 "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL)
754 def CWD : I<0x99, RawFrm, (ops),
755 "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX)
756 def CDQ : I<0x99, RawFrm, (ops),
757 "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
760 //===----------------------------------------------------------------------===//
761 // Two address Instructions...
763 let isTwoAddress = 1 in {
766 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16
767 (ops R16:$dst, R16:$src1, R16:$src2),
768 "cmovb {$src2, $dst|$dst, $src2}",
769 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
770 X86_COND_B, STATUS))]>,
771 Imp<[STATUS],[]>, TB, OpSize;
772 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16]
773 (ops R16:$dst, R16:$src1, i16mem:$src2),
774 "cmovb {$src2, $dst|$dst, $src2}",
775 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
776 X86_COND_B, STATUS))]>,
777 Imp<[STATUS],[]>, TB, OpSize;
778 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32
779 (ops R32:$dst, R32:$src1, R32:$src2),
780 "cmovb {$src2, $dst|$dst, $src2}",
781 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
782 X86_COND_B, STATUS))]>,
783 Imp<[STATUS],[]>, TB;
784 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32]
785 (ops R32:$dst, R32:$src1, i32mem:$src2),
786 "cmovb {$src2, $dst|$dst, $src2}",
787 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
788 X86_COND_B, STATUS))]>,
789 Imp<[STATUS],[]>, TB;
791 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16
792 (ops R16:$dst, R16:$src1, R16:$src2),
793 "cmovae {$src2, $dst|$dst, $src2}",
794 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
795 X86_COND_AE, STATUS))]>,
796 Imp<[STATUS],[]>, TB, OpSize;
797 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16]
798 (ops R16:$dst, R16:$src1, i16mem:$src2),
799 "cmovae {$src2, $dst|$dst, $src2}",
800 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
801 X86_COND_AE, STATUS))]>,
802 Imp<[STATUS],[]>, TB, OpSize;
803 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32
804 (ops R32:$dst, R32:$src1, R32:$src2),
805 "cmovae {$src2, $dst|$dst, $src2}",
806 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
807 X86_COND_AE, STATUS))]>,
808 Imp<[STATUS],[]>, TB;
809 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32]
810 (ops R32:$dst, R32:$src1, i32mem:$src2),
811 "cmovae {$src2, $dst|$dst, $src2}",
812 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
813 X86_COND_AE, STATUS))]>,
814 Imp<[STATUS],[]>, TB;
816 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16
817 (ops R16:$dst, R16:$src1, R16:$src2),
818 "cmove {$src2, $dst|$dst, $src2}",
819 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
820 X86_COND_E, STATUS))]>,
821 Imp<[STATUS],[]>, TB, OpSize;
822 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16]
823 (ops R16:$dst, R16:$src1, i16mem:$src2),
824 "cmove {$src2, $dst|$dst, $src2}",
825 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
826 X86_COND_E, STATUS))]>,
827 Imp<[STATUS],[]>, TB, OpSize;
828 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32
829 (ops R32:$dst, R32:$src1, R32:$src2),
830 "cmove {$src2, $dst|$dst, $src2}",
831 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
832 X86_COND_E, STATUS))]>,
833 Imp<[STATUS],[]>, TB;
834 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32]
835 (ops R32:$dst, R32:$src1, i32mem:$src2),
836 "cmove {$src2, $dst|$dst, $src2}",
837 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
838 X86_COND_E, STATUS))]>,
839 Imp<[STATUS],[]>, TB;
841 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16
842 (ops R16:$dst, R16:$src1, R16:$src2),
843 "cmovne {$src2, $dst|$dst, $src2}",
844 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
845 X86_COND_NE, STATUS))]>,
846 Imp<[STATUS],[]>, TB, OpSize;
847 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16]
848 (ops R16:$dst, R16:$src1, i16mem:$src2),
849 "cmovne {$src2, $dst|$dst, $src2}",
850 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
851 X86_COND_NE, STATUS))]>,
852 Imp<[STATUS],[]>, TB, OpSize;
853 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32
854 (ops R32:$dst, R32:$src1, R32:$src2),
855 "cmovne {$src2, $dst|$dst, $src2}",
856 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
857 X86_COND_NE, STATUS))]>,
858 Imp<[STATUS],[]>, TB;
859 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32]
860 (ops R32:$dst, R32:$src1, i32mem:$src2),
861 "cmovne {$src2, $dst|$dst, $src2}",
862 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
863 X86_COND_NE, STATUS))]>,
864 Imp<[STATUS],[]>, TB;
866 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16
867 (ops R16:$dst, R16:$src1, R16:$src2),
868 "cmovbe {$src2, $dst|$dst, $src2}",
869 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
870 X86_COND_BE, STATUS))]>,
871 Imp<[STATUS],[]>, TB, OpSize;
872 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16]
873 (ops R16:$dst, R16:$src1, i16mem:$src2),
874 "cmovbe {$src2, $dst|$dst, $src2}",
875 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
876 X86_COND_BE, STATUS))]>,
877 Imp<[STATUS],[]>, TB, OpSize;
878 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32
879 (ops R32:$dst, R32:$src1, R32:$src2),
880 "cmovbe {$src2, $dst|$dst, $src2}",
881 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
882 X86_COND_BE, STATUS))]>,
883 Imp<[STATUS],[]>, TB;
884 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32]
885 (ops R32:$dst, R32:$src1, i32mem:$src2),
886 "cmovbe {$src2, $dst|$dst, $src2}",
887 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
888 X86_COND_BE, STATUS))]>,
889 Imp<[STATUS],[]>, TB;
891 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16
892 (ops R16:$dst, R16:$src1, R16:$src2),
893 "cmova {$src2, $dst|$dst, $src2}",
894 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
895 X86_COND_A, STATUS))]>,
896 Imp<[STATUS],[]>, TB, OpSize;
897 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16]
898 (ops R16:$dst, R16:$src1, i16mem:$src2),
899 "cmova {$src2, $dst|$dst, $src2}",
900 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
901 X86_COND_A, STATUS))]>,
902 Imp<[STATUS],[]>, TB, OpSize;
903 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32
904 (ops R32:$dst, R32:$src1, R32:$src2),
905 "cmova {$src2, $dst|$dst, $src2}",
906 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
907 X86_COND_A, STATUS))]>,
908 Imp<[STATUS],[]>, TB;
909 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32]
910 (ops R32:$dst, R32:$src1, i32mem:$src2),
911 "cmova {$src2, $dst|$dst, $src2}",
912 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
913 X86_COND_A, STATUS))]>,
914 Imp<[STATUS],[]>, TB;
916 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16
917 (ops R16:$dst, R16:$src1, R16:$src2),
918 "cmovl {$src2, $dst|$dst, $src2}",
919 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
920 X86_COND_L, STATUS))]>,
921 Imp<[STATUS],[]>, TB, OpSize;
922 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16]
923 (ops R16:$dst, R16:$src1, i16mem:$src2),
924 "cmovl {$src2, $dst|$dst, $src2}",
925 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
926 X86_COND_L, STATUS))]>,
927 Imp<[STATUS],[]>, TB, OpSize;
928 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32
929 (ops R32:$dst, R32:$src1, R32:$src2),
930 "cmovl {$src2, $dst|$dst, $src2}",
931 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
932 X86_COND_L, STATUS))]>,
933 Imp<[STATUS],[]>, TB;
934 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32]
935 (ops R32:$dst, R32:$src1, i32mem:$src2),
936 "cmovl {$src2, $dst|$dst, $src2}",
937 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
938 X86_COND_L, STATUS))]>,
939 Imp<[STATUS],[]>, TB;
941 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16
942 (ops R16:$dst, R16:$src1, R16:$src2),
943 "cmovge {$src2, $dst|$dst, $src2}",
944 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
945 X86_COND_GE, STATUS))]>,
946 Imp<[STATUS],[]>, TB, OpSize;
947 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16]
948 (ops R16:$dst, R16:$src1, i16mem:$src2),
949 "cmovge {$src2, $dst|$dst, $src2}",
950 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
951 X86_COND_GE, STATUS))]>,
952 Imp<[STATUS],[]>, TB, OpSize;
953 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32
954 (ops R32:$dst, R32:$src1, R32:$src2),
955 "cmovge {$src2, $dst|$dst, $src2}",
956 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
957 X86_COND_GE, STATUS))]>,
958 Imp<[STATUS],[]>, TB;
959 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32]
960 (ops R32:$dst, R32:$src1, i32mem:$src2),
961 "cmovge {$src2, $dst|$dst, $src2}",
962 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
963 X86_COND_GE, STATUS))]>,
964 Imp<[STATUS],[]>, TB;
966 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16
967 (ops R16:$dst, R16:$src1, R16:$src2),
968 "cmovle {$src2, $dst|$dst, $src2}",
969 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
970 X86_COND_LE, STATUS))]>,
971 Imp<[STATUS],[]>, TB, OpSize;
972 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16]
973 (ops R16:$dst, R16:$src1, i16mem:$src2),
974 "cmovle {$src2, $dst|$dst, $src2}",
975 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
976 X86_COND_LE, STATUS))]>,
977 Imp<[STATUS],[]>, TB, OpSize;
978 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32
979 (ops R32:$dst, R32:$src1, R32:$src2),
980 "cmovle {$src2, $dst|$dst, $src2}",
981 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
982 X86_COND_LE, STATUS))]>,
983 Imp<[STATUS],[]>, TB;
984 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32]
985 (ops R32:$dst, R32:$src1, i32mem:$src2),
986 "cmovle {$src2, $dst|$dst, $src2}",
987 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
988 X86_COND_LE, STATUS))]>,
989 Imp<[STATUS],[]>, TB;
991 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16
992 (ops R16:$dst, R16:$src1, R16:$src2),
993 "cmovg {$src2, $dst|$dst, $src2}",
994 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
995 X86_COND_G, STATUS))]>,
996 Imp<[STATUS],[]>, TB, OpSize;
997 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16]
998 (ops R16:$dst, R16:$src1, i16mem:$src2),
999 "cmovg {$src2, $dst|$dst, $src2}",
1000 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
1001 X86_COND_G, STATUS))]>,
1002 Imp<[STATUS],[]>, TB, OpSize;
1003 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32
1004 (ops R32:$dst, R32:$src1, R32:$src2),
1005 "cmovg {$src2, $dst|$dst, $src2}",
1006 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
1007 X86_COND_G, STATUS))]>,
1008 Imp<[STATUS],[]>, TB;
1009 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32]
1010 (ops R32:$dst, R32:$src1, i32mem:$src2),
1011 "cmovg {$src2, $dst|$dst, $src2}",
1012 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
1013 X86_COND_G, STATUS))]>,
1014 Imp<[STATUS],[]>, TB;
1016 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16
1017 (ops R16:$dst, R16:$src1, R16:$src2),
1018 "cmovs {$src2, $dst|$dst, $src2}",
1019 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
1020 X86_COND_S, STATUS))]>,
1021 Imp<[STATUS],[]>, TB, OpSize;
1022 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16]
1023 (ops R16:$dst, R16:$src1, i16mem:$src2),
1024 "cmovs {$src2, $dst|$dst, $src2}",
1025 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
1026 X86_COND_S, STATUS))]>,
1027 Imp<[STATUS],[]>, TB, OpSize;
1028 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32
1029 (ops R32:$dst, R32:$src1, R32:$src2),
1030 "cmovs {$src2, $dst|$dst, $src2}",
1031 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
1032 X86_COND_S, STATUS))]>,
1033 Imp<[STATUS],[]>, TB;
1034 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32]
1035 (ops R32:$dst, R32:$src1, i32mem:$src2),
1036 "cmovs {$src2, $dst|$dst, $src2}",
1037 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
1038 X86_COND_S, STATUS))]>,
1039 Imp<[STATUS],[]>, TB;
1041 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16
1042 (ops R16:$dst, R16:$src1, R16:$src2),
1043 "cmovns {$src2, $dst|$dst, $src2}",
1044 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
1045 X86_COND_NS, STATUS))]>,
1046 Imp<[STATUS],[]>, TB, OpSize;
1047 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16]
1048 (ops R16:$dst, R16:$src1, i16mem:$src2),
1049 "cmovns {$src2, $dst|$dst, $src2}",
1050 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
1051 X86_COND_NS, STATUS))]>,
1052 Imp<[STATUS],[]>, TB, OpSize;
1053 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32
1054 (ops R32:$dst, R32:$src1, R32:$src2),
1055 "cmovns {$src2, $dst|$dst, $src2}",
1056 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
1057 X86_COND_NS, STATUS))]>,
1058 Imp<[STATUS],[]>, TB;
1059 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32]
1060 (ops R32:$dst, R32:$src1, i32mem:$src2),
1061 "cmovns {$src2, $dst|$dst, $src2}",
1062 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
1063 X86_COND_NS, STATUS))]>,
1064 Imp<[STATUS],[]>, TB;
1066 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16
1067 (ops R16:$dst, R16:$src1, R16:$src2),
1068 "cmovp {$src2, $dst|$dst, $src2}",
1069 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
1070 X86_COND_P, STATUS))]>,
1071 Imp<[STATUS],[]>, TB, OpSize;
1072 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16]
1073 (ops R16:$dst, R16:$src1, i16mem:$src2),
1074 "cmovp {$src2, $dst|$dst, $src2}",
1075 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
1076 X86_COND_P, STATUS))]>,
1077 Imp<[STATUS],[]>, TB, OpSize;
1078 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32
1079 (ops R32:$dst, R32:$src1, R32:$src2),
1080 "cmovp {$src2, $dst|$dst, $src2}",
1081 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
1082 X86_COND_P, STATUS))]>,
1083 Imp<[STATUS],[]>, TB;
1084 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32]
1085 (ops R32:$dst, R32:$src1, i32mem:$src2),
1086 "cmovp {$src2, $dst|$dst, $src2}",
1087 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
1088 X86_COND_P, STATUS))]>,
1089 Imp<[STATUS],[]>, TB;
1091 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16
1092 (ops R16:$dst, R16:$src1, R16:$src2),
1093 "cmovnp {$src2, $dst|$dst, $src2}",
1094 [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
1095 X86_COND_NP, STATUS))]>,
1096 Imp<[STATUS],[]>, TB, OpSize;
1097 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16]
1098 (ops R16:$dst, R16:$src1, i16mem:$src2),
1099 "cmovnp {$src2, $dst|$dst, $src2}",
1100 [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
1101 X86_COND_NP, STATUS))]>,
1102 Imp<[STATUS],[]>, TB, OpSize;
1103 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32
1104 (ops R32:$dst, R32:$src1, R32:$src2),
1105 "cmovnp {$src2, $dst|$dst, $src2}",
1106 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
1107 X86_COND_NP, STATUS))]>,
1108 Imp<[STATUS],[]>, TB;
1109 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32]
1110 (ops R32:$dst, R32:$src1, i32mem:$src2),
1111 "cmovnp {$src2, $dst|$dst, $src2}",
1112 [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
1113 X86_COND_NP, STATUS))]>,
1114 Imp<[STATUS],[]>, TB;
1117 // unary instructions
1118 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst",
1119 [(set R8:$dst, (ineg R8:$src))]>;
1120 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst",
1121 [(set R16:$dst, (ineg R16:$src))]>, OpSize;
1122 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst",
1123 [(set R32:$dst, (ineg R32:$src))]>;
1124 let isTwoAddress = 0 in {
1125 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst",
1126 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1127 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst",
1128 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1129 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst",
1130 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1134 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst",
1135 [(set R8:$dst, (not R8:$src))]>;
1136 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst",
1137 [(set R16:$dst, (not R16:$src))]>, OpSize;
1138 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst",
1139 [(set R32:$dst, (not R32:$src))]>;
1140 let isTwoAddress = 0 in {
1141 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst",
1142 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1143 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst",
1144 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1145 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst",
1146 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1149 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1150 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst",
1151 [(set R8:$dst, (add R8:$src, 1))]>;
1152 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1153 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst",
1154 [(set R16:$dst, (add R16:$src, 1))]>, OpSize;
1155 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst",
1156 [(set R32:$dst, (add R32:$src, 1))]>;
1158 let isTwoAddress = 0 in {
1159 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
1160 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1161 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
1162 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1163 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
1164 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1167 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst",
1168 [(set R8:$dst, (add R8:$src, -1))]>;
1169 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1170 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst",
1171 [(set R16:$dst, (add R16:$src, -1))]>, OpSize;
1172 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst",
1173 [(set R32:$dst, (add R32:$src, -1))]>;
1176 let isTwoAddress = 0 in {
1177 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
1178 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1179 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
1180 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1181 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
1182 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1185 // Logical operators...
1186 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1187 def AND8rr : I<0x20, MRMDestReg,
1188 (ops R8 :$dst, R8 :$src1, R8 :$src2),
1189 "and{b} {$src2, $dst|$dst, $src2}",
1190 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
1191 def AND16rr : I<0x21, MRMDestReg,
1192 (ops R16:$dst, R16:$src1, R16:$src2),
1193 "and{w} {$src2, $dst|$dst, $src2}",
1194 [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize;
1195 def AND32rr : I<0x21, MRMDestReg,
1196 (ops R32:$dst, R32:$src1, R32:$src2),
1197 "and{l} {$src2, $dst|$dst, $src2}",
1198 [(set R32:$dst, (and R32:$src1, R32:$src2))]>;
1201 def AND8rm : I<0x22, MRMSrcMem,
1202 (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1203 "and{b} {$src2, $dst|$dst, $src2}",
1204 [(set R8:$dst, (and R8:$src1, (load addr:$src2)))]>;
1205 def AND16rm : I<0x23, MRMSrcMem,
1206 (ops R16:$dst, R16:$src1, i16mem:$src2),
1207 "and{w} {$src2, $dst|$dst, $src2}",
1208 [(set R16:$dst, (and R16:$src1, (load addr:$src2)))]>, OpSize;
1209 def AND32rm : I<0x23, MRMSrcMem,
1210 (ops R32:$dst, R32:$src1, i32mem:$src2),
1211 "and{l} {$src2, $dst|$dst, $src2}",
1212 [(set R32:$dst, (and R32:$src1, (load addr:$src2)))]>;
1214 def AND8ri : Ii8<0x80, MRM4r,
1215 (ops R8 :$dst, R8 :$src1, i8imm :$src2),
1216 "and{b} {$src2, $dst|$dst, $src2}",
1217 [(set R8:$dst, (and R8:$src1, imm:$src2))]>;
1218 def AND16ri : Ii16<0x81, MRM4r,
1219 (ops R16:$dst, R16:$src1, i16imm:$src2),
1220 "and{w} {$src2, $dst|$dst, $src2}",
1221 [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize;
1222 def AND32ri : Ii32<0x81, MRM4r,
1223 (ops R32:$dst, R32:$src1, i32imm:$src2),
1224 "and{l} {$src2, $dst|$dst, $src2}",
1225 [(set R32:$dst, (and R32:$src1, imm:$src2))]>;
1226 def AND16ri8 : Ii8<0x83, MRM4r,
1227 (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1228 "and{w} {$src2, $dst|$dst, $src2}",
1229 [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>,
1231 def AND32ri8 : Ii8<0x83, MRM4r,
1232 (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1233 "and{l} {$src2, $dst|$dst, $src2}",
1234 [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>;
1236 let isTwoAddress = 0 in {
1237 def AND8mr : I<0x20, MRMDestMem,
1238 (ops i8mem :$dst, R8 :$src),
1239 "and{b} {$src, $dst|$dst, $src}",
1240 [(store (and (load addr:$dst), R8:$src), addr:$dst)]>;
1241 def AND16mr : I<0x21, MRMDestMem,
1242 (ops i16mem:$dst, R16:$src),
1243 "and{w} {$src, $dst|$dst, $src}",
1244 [(store (and (load addr:$dst), R16:$src), addr:$dst)]>,
1246 def AND32mr : I<0x21, MRMDestMem,
1247 (ops i32mem:$dst, R32:$src),
1248 "and{l} {$src, $dst|$dst, $src}",
1249 [(store (and (load addr:$dst), R32:$src), addr:$dst)]>;
1250 def AND8mi : Ii8<0x80, MRM4m,
1251 (ops i8mem :$dst, i8imm :$src),
1252 "and{b} {$src, $dst|$dst, $src}",
1253 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1254 def AND16mi : Ii16<0x81, MRM4m,
1255 (ops i16mem:$dst, i16imm:$src),
1256 "and{w} {$src, $dst|$dst, $src}",
1257 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1259 def AND32mi : Ii32<0x81, MRM4m,
1260 (ops i32mem:$dst, i32imm:$src),
1261 "and{l} {$src, $dst|$dst, $src}",
1262 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1263 def AND16mi8 : Ii8<0x83, MRM4m,
1264 (ops i16mem:$dst, i16i8imm :$src),
1265 "and{w} {$src, $dst|$dst, $src}",
1266 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1268 def AND32mi8 : Ii8<0x83, MRM4m,
1269 (ops i32mem:$dst, i32i8imm :$src),
1270 "and{l} {$src, $dst|$dst, $src}",
1271 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1275 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1276 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1277 "or{b} {$src2, $dst|$dst, $src2}",
1278 [(set R8:$dst, (or R8:$src1, R8:$src2))]>;
1279 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1280 "or{w} {$src2, $dst|$dst, $src2}",
1281 [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize;
1282 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1283 "or{l} {$src2, $dst|$dst, $src2}",
1284 [(set R32:$dst, (or R32:$src1, R32:$src2))]>;
1286 def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1287 "or{b} {$src2, $dst|$dst, $src2}",
1288 [(set R8:$dst, (or R8:$src1, (load addr:$src2)))]>;
1289 def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
1290 "or{w} {$src2, $dst|$dst, $src2}",
1291 [(set R16:$dst, (or R16:$src1, (load addr:$src2)))]>, OpSize;
1292 def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
1293 "or{l} {$src2, $dst|$dst, $src2}",
1294 [(set R32:$dst, (or R32:$src1, (load addr:$src2)))]>;
1296 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
1297 "or{b} {$src2, $dst|$dst, $src2}",
1298 [(set R8:$dst, (or R8:$src1, imm:$src2))]>;
1299 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1300 "or{w} {$src2, $dst|$dst, $src2}",
1301 [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize;
1302 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1303 "or{l} {$src2, $dst|$dst, $src2}",
1304 [(set R32:$dst, (or R32:$src1, imm:$src2))]>;
1306 def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1307 "or{w} {$src2, $dst|$dst, $src2}",
1308 [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize;
1309 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1310 "or{l} {$src2, $dst|$dst, $src2}",
1311 [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>;
1312 let isTwoAddress = 0 in {
1313 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
1314 "or{b} {$src, $dst|$dst, $src}",
1315 [(store (or (load addr:$dst), R8:$src), addr:$dst)]>;
1316 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
1317 "or{w} {$src, $dst|$dst, $src}",
1318 [(store (or (load addr:$dst), R16:$src), addr:$dst)]>, OpSize;
1319 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
1320 "or{l} {$src, $dst|$dst, $src}",
1321 [(store (or (load addr:$dst), R32:$src), addr:$dst)]>;
1322 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
1323 "or{b} {$src, $dst|$dst, $src}",
1324 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1325 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
1326 "or{w} {$src, $dst|$dst, $src}",
1327 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1329 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
1330 "or{l} {$src, $dst|$dst, $src}",
1331 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1332 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src),
1333 "or{w} {$src, $dst|$dst, $src}",
1334 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1336 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src),
1337 "or{l} {$src, $dst|$dst, $src}",
1338 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1342 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1343 def XOR8rr : I<0x30, MRMDestReg,
1344 (ops R8 :$dst, R8 :$src1, R8 :$src2),
1345 "xor{b} {$src2, $dst|$dst, $src2}",
1346 [(set R8:$dst, (xor R8:$src1, R8:$src2))]>;
1347 def XOR16rr : I<0x31, MRMDestReg,
1348 (ops R16:$dst, R16:$src1, R16:$src2),
1349 "xor{w} {$src2, $dst|$dst, $src2}",
1350 [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize;
1351 def XOR32rr : I<0x31, MRMDestReg,
1352 (ops R32:$dst, R32:$src1, R32:$src2),
1353 "xor{l} {$src2, $dst|$dst, $src2}",
1354 [(set R32:$dst, (xor R32:$src1, R32:$src2))]>;
1357 def XOR8rm : I<0x32, MRMSrcMem ,
1358 (ops R8 :$dst, R8:$src1, i8mem :$src2),
1359 "xor{b} {$src2, $dst|$dst, $src2}",
1360 [(set R8:$dst, (xor R8:$src1, (load addr:$src2)))]>;
1361 def XOR16rm : I<0x33, MRMSrcMem ,
1362 (ops R16:$dst, R16:$src1, i16mem:$src2),
1363 "xor{w} {$src2, $dst|$dst, $src2}",
1364 [(set R16:$dst, (xor R16:$src1, (load addr:$src2)))]>, OpSize;
1365 def XOR32rm : I<0x33, MRMSrcMem ,
1366 (ops R32:$dst, R32:$src1, i32mem:$src2),
1367 "xor{l} {$src2, $dst|$dst, $src2}",
1368 [(set R32:$dst, (xor R32:$src1, (load addr:$src2)))]>;
1370 def XOR8ri : Ii8<0x80, MRM6r,
1371 (ops R8:$dst, R8:$src1, i8imm:$src2),
1372 "xor{b} {$src2, $dst|$dst, $src2}",
1373 [(set R8:$dst, (xor R8:$src1, imm:$src2))]>;
1374 def XOR16ri : Ii16<0x81, MRM6r,
1375 (ops R16:$dst, R16:$src1, i16imm:$src2),
1376 "xor{w} {$src2, $dst|$dst, $src2}",
1377 [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize;
1378 def XOR32ri : Ii32<0x81, MRM6r,
1379 (ops R32:$dst, R32:$src1, i32imm:$src2),
1380 "xor{l} {$src2, $dst|$dst, $src2}",
1381 [(set R32:$dst, (xor R32:$src1, imm:$src2))]>;
1382 def XOR16ri8 : Ii8<0x83, MRM6r,
1383 (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1384 "xor{w} {$src2, $dst|$dst, $src2}",
1385 [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>,
1387 def XOR32ri8 : Ii8<0x83, MRM6r,
1388 (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1389 "xor{l} {$src2, $dst|$dst, $src2}",
1390 [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>;
1391 let isTwoAddress = 0 in {
1392 def XOR8mr : I<0x30, MRMDestMem,
1393 (ops i8mem :$dst, R8 :$src),
1394 "xor{b} {$src, $dst|$dst, $src}",
1395 [(store (xor (load addr:$dst), R8:$src), addr:$dst)]>;
1396 def XOR16mr : I<0x31, MRMDestMem,
1397 (ops i16mem:$dst, R16:$src),
1398 "xor{w} {$src, $dst|$dst, $src}",
1399 [(store (xor (load addr:$dst), R16:$src), addr:$dst)]>,
1401 def XOR32mr : I<0x31, MRMDestMem,
1402 (ops i32mem:$dst, R32:$src),
1403 "xor{l} {$src, $dst|$dst, $src}",
1404 [(store (xor (load addr:$dst), R32:$src), addr:$dst)]>;
1405 def XOR8mi : Ii8<0x80, MRM6m,
1406 (ops i8mem :$dst, i8imm :$src),
1407 "xor{b} {$src, $dst|$dst, $src}",
1408 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1409 def XOR16mi : Ii16<0x81, MRM6m,
1410 (ops i16mem:$dst, i16imm:$src),
1411 "xor{w} {$src, $dst|$dst, $src}",
1412 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1414 def XOR32mi : Ii32<0x81, MRM6m,
1415 (ops i32mem:$dst, i32imm:$src),
1416 "xor{l} {$src, $dst|$dst, $src}",
1417 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1418 def XOR16mi8 : Ii8<0x83, MRM6m,
1419 (ops i16mem:$dst, i16i8imm :$src),
1420 "xor{w} {$src, $dst|$dst, $src}",
1421 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1423 def XOR32mi8 : Ii8<0x83, MRM6m,
1424 (ops i32mem:$dst, i32i8imm :$src),
1425 "xor{l} {$src, $dst|$dst, $src}",
1426 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1429 // Shift instructions
1430 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
1431 "shl{b} {%cl, $dst|$dst, %CL}",
1432 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
1433 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
1434 "shl{w} {%cl, $dst|$dst, %CL}",
1435 [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1436 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
1437 "shl{l} {%cl, $dst|$dst, %CL}",
1438 [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>;
1440 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
1441 "shl{b} {$src2, $dst|$dst, $src2}",
1442 [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>;
1443 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1444 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1445 "shl{w} {$src2, $dst|$dst, $src2}",
1446 [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize;
1447 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1448 "shl{l} {$src2, $dst|$dst, $src2}",
1449 [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>;
1452 let isTwoAddress = 0 in {
1453 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
1454 "shl{b} {%cl, $dst|$dst, %CL}",
1455 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1457 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
1458 "shl{w} {%cl, $dst|$dst, %CL}",
1459 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1460 Imp<[CL],[]>, OpSize;
1461 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
1462 "shl{l} {%cl, $dst|$dst, %CL}",
1463 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1465 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
1466 "shl{b} {$src, $dst|$dst, $src}",
1467 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1468 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
1469 "shl{w} {$src, $dst|$dst, $src}",
1470 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1472 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
1473 "shl{l} {$src, $dst|$dst, $src}",
1474 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1477 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
1478 "shr{b} {%cl, $dst|$dst, %CL}",
1479 [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>;
1480 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
1481 "shr{w} {%cl, $dst|$dst, %CL}",
1482 [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1483 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
1484 "shr{l} {%cl, $dst|$dst, %CL}",
1485 [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>;
1487 def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1488 "shr{b} {$src2, $dst|$dst, $src2}",
1489 [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>;
1490 def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1491 "shr{w} {$src2, $dst|$dst, $src2}",
1492 [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize;
1493 def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1494 "shr{l} {$src2, $dst|$dst, $src2}",
1495 [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>;
1497 let isTwoAddress = 0 in {
1498 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
1499 "shr{b} {%cl, $dst|$dst, %CL}",
1500 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1502 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
1503 "shr{w} {%cl, $dst|$dst, %CL}",
1504 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1505 Imp<[CL],[]>, OpSize;
1506 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
1507 "shr{l} {%cl, $dst|$dst, %CL}",
1508 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1510 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
1511 "shr{b} {$src, $dst|$dst, $src}",
1512 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1513 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
1514 "shr{w} {$src, $dst|$dst, $src}",
1515 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1517 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
1518 "shr{l} {$src, $dst|$dst, $src}",
1519 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1522 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
1523 "sar{b} {%cl, $dst|$dst, %CL}",
1524 [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>;
1525 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
1526 "sar{w} {%cl, $dst|$dst, %CL}",
1527 [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1528 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
1529 "sar{l} {%cl, $dst|$dst, %CL}",
1530 [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>;
1532 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
1533 "sar{b} {$src2, $dst|$dst, $src2}",
1534 [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>;
1535 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1536 "sar{w} {$src2, $dst|$dst, $src2}",
1537 [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>,
1539 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1540 "sar{l} {$src2, $dst|$dst, $src2}",
1541 [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>;
1542 let isTwoAddress = 0 in {
1543 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
1544 "sar{b} {%cl, $dst|$dst, %CL}",
1545 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1547 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
1548 "sar{w} {%cl, $dst|$dst, %CL}",
1549 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1550 Imp<[CL],[]>, OpSize;
1551 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
1552 "sar{l} {%cl, $dst|$dst, %CL}",
1553 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1555 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
1556 "sar{b} {$src, $dst|$dst, $src}",
1557 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1558 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
1559 "sar{w} {$src, $dst|$dst, $src}",
1560 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1562 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
1563 "sar{l} {$src, $dst|$dst, $src}",
1564 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1567 // Rotate instructions
1568 // FIXME: provide shorter instructions when imm8 == 1
1569 def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
1570 "rol{b} {%cl, $dst|$dst, %CL}",
1571 [(set R8:$dst, (rotl R8:$src, CL))]>, Imp<[CL],[]>;
1572 def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
1573 "rol{w} {%cl, $dst|$dst, %CL}",
1574 [(set R16:$dst, (rotl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1575 def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
1576 "rol{l} {%cl, $dst|$dst, %CL}",
1577 [(set R32:$dst, (rotl R32:$src, CL))]>, Imp<[CL],[]>;
1579 def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
1580 "rol{b} {$src2, $dst|$dst, $src2}",
1581 [(set R8:$dst, (rotl R8:$src1, (i8 imm:$src2)))]>;
1582 def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1583 "rol{w} {$src2, $dst|$dst, $src2}",
1584 [(set R16:$dst, (rotl R16:$src1, (i8 imm:$src2)))]>, OpSize;
1585 def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1586 "rol{l} {$src2, $dst|$dst, $src2}",
1587 [(set R32:$dst, (rotl R32:$src1, (i8 imm:$src2)))]>;
1589 let isTwoAddress = 0 in {
1590 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
1591 "rol{b} {%cl, $dst|$dst, %CL}",
1592 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1594 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
1595 "rol{w} {%cl, $dst|$dst, %CL}",
1596 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1597 Imp<[CL],[]>, OpSize;
1598 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
1599 "rol{l} {%cl, $dst|$dst, %CL}",
1600 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1602 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
1603 "rol{b} {$src, $dst|$dst, $src}",
1604 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1605 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
1606 "rol{w} {$src, $dst|$dst, $src}",
1607 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1609 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
1610 "rol{l} {$src, $dst|$dst, $src}",
1611 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1614 def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
1615 "ror{b} {%cl, $dst|$dst, %CL}",
1616 [(set R8:$dst, (rotr R8:$src, CL))]>, Imp<[CL],[]>;
1617 def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
1618 "ror{w} {%cl, $dst|$dst, %CL}",
1619 [(set R16:$dst, (rotr R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1620 def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
1621 "ror{l} {%cl, $dst|$dst, %CL}",
1622 [(set R32:$dst, (rotr R32:$src, CL))]>, Imp<[CL],[]>;
1624 def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
1625 "ror{b} {$src2, $dst|$dst, $src2}",
1626 [(set R8:$dst, (rotr R8:$src1, (i8 imm:$src2)))]>;
1627 def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2),
1628 "ror{w} {$src2, $dst|$dst, $src2}",
1629 [(set R16:$dst, (rotr R16:$src1, (i8 imm:$src2)))]>, OpSize;
1630 def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
1631 "ror{l} {$src2, $dst|$dst, $src2}",
1632 [(set R32:$dst, (rotr R32:$src1, (i8 imm:$src2)))]>;
1633 let isTwoAddress = 0 in {
1634 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
1635 "ror{b} {%cl, $dst|$dst, %CL}",
1636 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1638 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
1639 "ror{w} {%cl, $dst|$dst, %CL}",
1640 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1641 Imp<[CL],[]>, OpSize;
1642 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
1643 "ror{l} {%cl, $dst|$dst, %CL}",
1644 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1646 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
1647 "ror{b} {$src, $dst|$dst, $src}",
1648 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1649 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
1650 "ror{w} {$src, $dst|$dst, $src}",
1651 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1653 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
1654 "ror{l} {$src, $dst|$dst, $src}",
1655 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1660 // Double shift instructions (generalizations of rotate)
1662 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1663 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1664 [(set R32:$dst, (X86shld R32:$src1, R32:$src2, CL))]>,
1666 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1667 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1668 [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, CL))]>,
1670 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1671 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1672 [(set R16:$dst, (X86shld R16:$src1, R16:$src2, CL))]>,
1673 Imp<[CL],[]>, TB, OpSize;
1674 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1675 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1676 [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, CL))]>,
1677 Imp<[CL],[]>, TB, OpSize;
1679 let isCommutable = 1 in { // These instructions commute to each other.
1680 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1681 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
1682 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1683 [(set R32:$dst, (X86shld R32:$src1, R32:$src2,
1686 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1687 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
1688 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1689 [(set R32:$dst, (X86shrd R32:$src1, R32:$src2,
1692 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1693 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
1694 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1695 [(set R16:$dst, (X86shld R16:$src1, R16:$src2,
1698 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1699 (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
1700 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1701 [(set R16:$dst, (X86shrd R16:$src1, R16:$src2,
1706 let isTwoAddress = 0 in {
1707 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1708 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1709 [(store (X86shld (loadi32 addr:$dst), R32:$src2, CL),
1712 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1713 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1714 [(store (X86shrd (loadi32 addr:$dst), R32:$src2, CL),
1717 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1718 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1719 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1720 [(store (X86shld (loadi32 addr:$dst), R32:$src2,
1721 (i8 imm:$src3)), addr:$dst)]>,
1723 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1724 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
1725 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1726 [(store (X86shrd (loadi32 addr:$dst), R32:$src2,
1727 (i8 imm:$src3)), addr:$dst)]>,
1730 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1731 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1732 [(store (X86shld (loadi16 addr:$dst), R16:$src2, CL),
1734 Imp<[CL],[]>, TB, OpSize;
1735 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1736 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1737 [(store (X86shrd (loadi16 addr:$dst), R16:$src2, CL),
1739 Imp<[CL],[]>, TB, OpSize;
1740 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1741 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1742 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1743 [(store (X86shld (loadi16 addr:$dst), R16:$src2,
1744 (i8 imm:$src3)), addr:$dst)]>,
1746 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1747 (ops i16mem:$dst, R16:$src2, i8imm:$src3),
1748 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1749 [(store (X86shrd (loadi16 addr:$dst), R16:$src2,
1750 (i8 imm:$src3)), addr:$dst)]>,
1756 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1757 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1758 "add{b} {$src2, $dst|$dst, $src2}",
1759 [(set R8:$dst, (add R8:$src1, R8:$src2))]>;
1760 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1761 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1762 "add{w} {$src2, $dst|$dst, $src2}",
1763 [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize;
1764 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1765 "add{l} {$src2, $dst|$dst, $src2}",
1766 [(set R32:$dst, (add R32:$src1, R32:$src2))]>;
1767 } // end isConvertibleToThreeAddress
1768 } // end isCommutable
1769 def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1770 "add{b} {$src2, $dst|$dst, $src2}",
1771 [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>;
1772 def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1773 "add{w} {$src2, $dst|$dst, $src2}",
1774 [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize;
1775 def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1776 "add{l} {$src2, $dst|$dst, $src2}",
1777 [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>;
1779 def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1780 "add{b} {$src2, $dst|$dst, $src2}",
1781 [(set R8:$dst, (add R8:$src1, imm:$src2))]>;
1783 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1784 def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1785 "add{w} {$src2, $dst|$dst, $src2}",
1786 [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize;
1787 def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1788 "add{l} {$src2, $dst|$dst, $src2}",
1789 [(set R32:$dst, (add R32:$src1, imm:$src2))]>;
1792 // FIXME: move ADD16ri8 above ADD16ri to optimize for space.
1793 def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1794 "add{w} {$src2, $dst|$dst, $src2}",
1795 [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>,
1797 def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1798 "add{l} {$src2, $dst|$dst, $src2}",
1799 [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>;
1801 let isTwoAddress = 0 in {
1802 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1803 "add{b} {$src2, $dst|$dst, $src2}",
1804 [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>;
1805 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1806 "add{w} {$src2, $dst|$dst, $src2}",
1807 [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>,
1809 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1810 "add{l} {$src2, $dst|$dst, $src2}",
1811 [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>;
1812 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1813 "add{b} {$src2, $dst|$dst, $src2}",
1814 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1815 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1816 "add{w} {$src2, $dst|$dst, $src2}",
1817 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1819 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1820 "add{l} {$src2, $dst|$dst, $src2}",
1821 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1822 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
1823 "add{w} {$src2, $dst|$dst, $src2}",
1824 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1826 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
1827 "add{l} {$src2, $dst|$dst, $src2}",
1828 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1831 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1832 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1833 "adc{l} {$src2, $dst|$dst, $src2}",
1834 [(set R32:$dst, (X86adc R32:$src1, R32:$src2))]>;
1836 def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
1837 "adc{l} {$src2, $dst|$dst, $src2}",
1838 [(set R32:$dst, (X86adc R32:$src1, (load addr:$src2)))]>;
1839 def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1840 "adc{l} {$src2, $dst|$dst, $src2}",
1841 [(set R32:$dst, (X86adc R32:$src1, imm:$src2))]>;
1842 def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1843 "adc{l} {$src2, $dst|$dst, $src2}",
1844 [(set R32:$dst, (X86adc R32:$src1, i32immSExt8:$src2))]>;
1846 let isTwoAddress = 0 in {
1847 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1848 "adc{l} {$src2, $dst|$dst, $src2}",
1849 [(store (X86adc (load addr:$dst), R32:$src2), addr:$dst)]>;
1850 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1851 "adc{l} {$src2, $dst|$dst, $src2}",
1852 [(store (X86adc (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1853 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
1854 "adc{l} {$src2, $dst|$dst, $src2}",
1855 [(store (X86adc (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1858 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
1859 "sub{b} {$src2, $dst|$dst, $src2}",
1860 [(set R8:$dst, (sub R8:$src1, R8:$src2))]>;
1861 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
1862 "sub{w} {$src2, $dst|$dst, $src2}",
1863 [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize;
1864 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1865 "sub{l} {$src2, $dst|$dst, $src2}",
1866 [(set R32:$dst, (sub R32:$src1, R32:$src2))]>;
1867 def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
1868 "sub{b} {$src2, $dst|$dst, $src2}",
1869 [(set R8:$dst, (sub R8:$src1, (load addr:$src2)))]>;
1870 def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1871 "sub{w} {$src2, $dst|$dst, $src2}",
1872 [(set R16:$dst, (sub R16:$src1, (load addr:$src2)))]>, OpSize;
1873 def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1874 "sub{l} {$src2, $dst|$dst, $src2}",
1875 [(set R32:$dst, (sub R32:$src1, (load addr:$src2)))]>;
1877 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1878 "sub{b} {$src2, $dst|$dst, $src2}",
1879 [(set R8:$dst, (sub R8:$src1, imm:$src2))]>;
1880 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1881 "sub{w} {$src2, $dst|$dst, $src2}",
1882 [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize;
1883 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1884 "sub{l} {$src2, $dst|$dst, $src2}",
1885 [(set R32:$dst, (sub R32:$src1, imm:$src2))]>;
1886 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1887 "sub{w} {$src2, $dst|$dst, $src2}",
1888 [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>,
1890 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1891 "sub{l} {$src2, $dst|$dst, $src2}",
1892 [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>;
1893 let isTwoAddress = 0 in {
1894 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
1895 "sub{b} {$src2, $dst|$dst, $src2}",
1896 [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>;
1897 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
1898 "sub{w} {$src2, $dst|$dst, $src2}",
1899 [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>,
1901 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1902 "sub{l} {$src2, $dst|$dst, $src2}",
1903 [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>;
1904 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1905 "sub{b} {$src2, $dst|$dst, $src2}",
1906 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1907 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1908 "sub{w} {$src2, $dst|$dst, $src2}",
1909 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1911 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1912 "sub{l} {$src2, $dst|$dst, $src2}",
1913 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1914 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
1915 "sub{w} {$src2, $dst|$dst, $src2}",
1916 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1918 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
1919 "sub{l} {$src2, $dst|$dst, $src2}",
1920 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1923 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
1924 "sbb{l} {$src2, $dst|$dst, $src2}",
1925 [(set R32:$dst, (X86sbb R32:$src1, R32:$src2))]>;
1927 let isTwoAddress = 0 in {
1928 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
1929 "sbb{l} {$src2, $dst|$dst, $src2}",
1930 [(store (X86sbb (load addr:$dst), R32:$src2), addr:$dst)]>;
1931 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
1932 "sbb{b} {$src2, $dst|$dst, $src2}",
1933 [(store (X86sbb (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1934 def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
1935 "sbb{w} {$src2, $dst|$dst, $src2}",
1936 [(store (X86sbb (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1938 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
1939 "sbb{l} {$src2, $dst|$dst, $src2}",
1940 [(store (X86sbb (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1941 def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i16i8imm :$src2),
1942 "sbb{w} {$src2, $dst|$dst, $src2}",
1943 [(store (X86sbb (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1945 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
1946 "sbb{l} {$src2, $dst|$dst, $src2}",
1947 [(store (X86sbb (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1949 def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
1950 "sbb{b} {$src2, $dst|$dst, $src2}",
1951 [(set R8:$dst, (X86sbb R8:$src1, imm:$src2))]>;
1952 def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
1953 "sbb{w} {$src2, $dst|$dst, $src2}",
1954 [(set R16:$dst, (X86sbb R16:$src1, imm:$src2))]>, OpSize;
1956 def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1957 "sbb{l} {$src2, $dst|$dst, $src2}",
1958 [(set R32:$dst, (X86sbb R32:$src1, (load addr:$src2)))]>;
1959 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
1960 "sbb{l} {$src2, $dst|$dst, $src2}",
1961 [(set R32:$dst, (X86sbb R32:$src1, imm:$src2))]>;
1963 def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
1964 "sbb{w} {$src2, $dst|$dst, $src2}",
1965 [(set R16:$dst, (X86sbb R16:$src1, i16immSExt8:$src2))]>,
1967 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
1968 "sbb{l} {$src2, $dst|$dst, $src2}",
1969 [(set R32:$dst, (X86sbb R32:$src1, i32immSExt8:$src2))]>;
1971 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
1972 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
1973 "imul{w} {$src2, $dst|$dst, $src2}",
1974 [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize;
1975 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
1976 "imul{l} {$src2, $dst|$dst, $src2}",
1977 [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB;
1979 def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1980 "imul{w} {$src2, $dst|$dst, $src2}",
1981 [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>,
1983 def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1984 "imul{l} {$src2, $dst|$dst, $src2}",
1985 [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB;
1987 } // end Two Address instructions
1989 // Suprisingly enough, these are not two address instructions!
1990 def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16
1991 (ops R16:$dst, R16:$src1, i16imm:$src2),
1992 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
1993 [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize;
1994 def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
1995 (ops R32:$dst, R32:$src1, i32imm:$src2),
1996 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
1997 [(set R32:$dst, (mul R32:$src1, imm:$src2))]>;
1998 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
1999 (ops R16:$dst, R16:$src1, i16i8imm:$src2),
2000 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2001 [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>,
2003 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
2004 (ops R32:$dst, R32:$src1, i32i8imm:$src2),
2005 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2006 [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>;
2008 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
2009 (ops R16:$dst, i16mem:$src1, i16imm:$src2),
2010 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2011 [(set R16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2013 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
2014 (ops R32:$dst, i32mem:$src1, i32imm:$src2),
2015 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2016 [(set R32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2017 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
2018 (ops R16:$dst, i16mem:$src1, i16i8imm :$src2),
2019 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2020 [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2022 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
2023 (ops R32:$dst, i32mem:$src1, i32i8imm: $src2),
2024 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2025 [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2027 //===----------------------------------------------------------------------===//
2028 // Test instructions are just like AND, except they don't generate a result.
2030 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2031 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
2032 "test{b} {$src2, $src1|$src1, $src2}",
2033 [(set STATUS, (X86test R8:$src1, R8:$src2))]>,
2035 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
2036 "test{w} {$src2, $src1|$src1, $src2}",
2037 [(set STATUS, (X86test R16:$src1, R16:$src2))]>,
2038 Imp<[],[STATUS]>, OpSize;
2039 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
2040 "test{l} {$src2, $src1|$src1, $src2}",
2041 [(set STATUS, (X86test R32:$src1, R32:$src2))]>,
2044 def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
2045 "test{b} {$src2, $src1|$src1, $src2}",
2046 [(set STATUS, (X86test (loadi8 addr:$src1), R8:$src2))]>,
2048 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
2049 "test{w} {$src2, $src1|$src1, $src2}",
2050 [(set STATUS, (X86test (loadi16 addr:$src1), R16:$src2))]>,
2051 Imp<[],[STATUS]>, OpSize;
2052 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
2053 "test{l} {$src2, $src1|$src1, $src2}",
2054 [(set STATUS, (X86test (loadi32 addr:$src1), R32:$src2))]>,
2056 def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
2057 "test{b} {$src2, $src1|$src1, $src2}",
2058 [(set STATUS, (X86test R8:$src1, (loadi8 addr:$src2)))]>,
2060 def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
2061 "test{w} {$src2, $src1|$src1, $src2}",
2062 [(set STATUS, (X86test R16:$src1, (loadi16 addr:$src2)))]>,
2063 Imp<[],[STATUS]>, OpSize;
2064 def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
2065 "test{l} {$src2, $src1|$src1, $src2}",
2066 [(set STATUS, (X86test R32:$src1, (loadi32 addr:$src2)))]>,
2069 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
2070 (ops R8:$src1, i8imm:$src2),
2071 "test{b} {$src2, $src1|$src1, $src2}",
2072 [(set STATUS, (X86test R8:$src1, imm:$src2))]>,
2074 def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
2075 (ops R16:$src1, i16imm:$src2),
2076 "test{w} {$src2, $src1|$src1, $src2}",
2077 [(set STATUS, (X86test R16:$src1, imm:$src2))]>,
2078 Imp<[],[STATUS]>, OpSize;
2079 def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
2080 (ops R32:$src1, i32imm:$src2),
2081 "test{l} {$src2, $src1|$src1, $src2}",
2082 [(set STATUS, (X86test R32:$src1, imm:$src2))]>,
2084 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2085 (ops i8mem:$src1, i8imm:$src2),
2086 "test{b} {$src2, $src1|$src1, $src2}",
2087 [(set STATUS, (X86test (loadi8 addr:$src1), imm:$src2))]>,
2089 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2090 (ops i16mem:$src1, i16imm:$src2),
2091 "test{w} {$src2, $src1|$src1, $src2}",
2092 [(set STATUS, (X86test (loadi16 addr:$src1), imm:$src2))]>,
2093 Imp<[],[STATUS]>, OpSize;
2094 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2095 (ops i32mem:$src1, i32imm:$src2),
2096 "test{l} {$src2, $src1|$src1, $src2}",
2097 [(set STATUS, (X86test (loadi32 addr:$src1), imm:$src2))]>,
2101 // Condition code ops, incl. set if equal/not equal/...
2102 def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
2103 def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
2105 def SETEr : I<0x94, MRM0r,
2108 [(set R8:$dst, (X86setcc X86_COND_E, STATUS))]>,
2110 def SETEm : I<0x94, MRM0m,
2113 [(store (X86setcc X86_COND_E, STATUS), addr:$dst)]>,
2115 def SETNEr : I<0x95, MRM0r,
2118 [(set R8:$dst, (X86setcc X86_COND_NE, STATUS))]>,
2120 def SETNEm : I<0x95, MRM0m,
2123 [(store (X86setcc X86_COND_NE, STATUS), addr:$dst)]>,
2125 def SETLr : I<0x9C, MRM0r,
2128 [(set R8:$dst, (X86setcc X86_COND_L, STATUS))]>,
2129 TB; // R8 = < signed
2130 def SETLm : I<0x9C, MRM0m,
2133 [(store (X86setcc X86_COND_L, STATUS), addr:$dst)]>,
2134 TB; // [mem8] = < signed
2135 def SETGEr : I<0x9D, MRM0r,
2138 [(set R8:$dst, (X86setcc X86_COND_GE, STATUS))]>,
2139 TB; // R8 = >= signed
2140 def SETGEm : I<0x9D, MRM0m,
2143 [(store (X86setcc X86_COND_GE, STATUS), addr:$dst)]>,
2144 TB; // [mem8] = >= signed
2145 def SETLEr : I<0x9E, MRM0r,
2148 [(set R8:$dst, (X86setcc X86_COND_LE, STATUS))]>,
2149 TB; // R8 = <= signed
2150 def SETLEm : I<0x9E, MRM0m,
2153 [(store (X86setcc X86_COND_LE, STATUS), addr:$dst)]>,
2154 TB; // [mem8] = <= signed
2155 def SETGr : I<0x9F, MRM0r,
2158 [(set R8:$dst, (X86setcc X86_COND_G, STATUS))]>,
2159 TB; // R8 = > signed
2160 def SETGm : I<0x9F, MRM0m,
2163 [(store (X86setcc X86_COND_G, STATUS), addr:$dst)]>,
2164 TB; // [mem8] = > signed
2166 def SETBr : I<0x92, MRM0r,
2169 [(set R8:$dst, (X86setcc X86_COND_B, STATUS))]>,
2170 TB; // R8 = < unsign
2171 def SETBm : I<0x92, MRM0m,
2174 [(store (X86setcc X86_COND_B, STATUS), addr:$dst)]>,
2175 TB; // [mem8] = < unsign
2176 def SETAEr : I<0x93, MRM0r,
2179 [(set R8:$dst, (X86setcc X86_COND_AE, STATUS))]>,
2180 TB; // R8 = >= unsign
2181 def SETAEm : I<0x93, MRM0m,
2184 [(store (X86setcc X86_COND_AE, STATUS), addr:$dst)]>,
2185 TB; // [mem8] = >= unsign
2186 def SETBEr : I<0x96, MRM0r,
2189 [(set R8:$dst, (X86setcc X86_COND_BE, STATUS))]>,
2190 TB; // R8 = <= unsign
2191 def SETBEm : I<0x96, MRM0m,
2194 [(store (X86setcc X86_COND_BE, STATUS), addr:$dst)]>,
2195 TB; // [mem8] = <= unsign
2196 def SETAr : I<0x97, MRM0r,
2199 [(set R8:$dst, (X86setcc X86_COND_A, STATUS))]>,
2200 TB; // R8 = > signed
2201 def SETAm : I<0x97, MRM0m,
2204 [(store (X86setcc X86_COND_A, STATUS), addr:$dst)]>,
2205 TB; // [mem8] = > signed
2207 def SETSr : I<0x98, MRM0r,
2210 [(set R8:$dst, (X86setcc X86_COND_S, STATUS))]>,
2211 TB; // R8 = <sign bit>
2212 def SETSm : I<0x98, MRM0m,
2215 [(store (X86setcc X86_COND_S, STATUS), addr:$dst)]>,
2216 TB; // [mem8] = <sign bit>
2217 def SETNSr : I<0x99, MRM0r,
2220 [(set R8:$dst, (X86setcc X86_COND_NS, STATUS))]>,
2221 TB; // R8 = !<sign bit>
2222 def SETNSm : I<0x99, MRM0m,
2225 [(store (X86setcc X86_COND_NS, STATUS), addr:$dst)]>,
2226 TB; // [mem8] = !<sign bit>
2227 def SETPr : I<0x9A, MRM0r,
2230 [(set R8:$dst, (X86setcc X86_COND_P, STATUS))]>,
2232 def SETPm : I<0x9A, MRM0m,
2235 [(store (X86setcc X86_COND_P, STATUS), addr:$dst)]>,
2236 TB; // [mem8] = parity
2237 def SETNPr : I<0x9B, MRM0r,
2240 [(set R8:$dst, (X86setcc X86_COND_NP, STATUS))]>,
2241 TB; // R8 = not parity
2242 def SETNPm : I<0x9B, MRM0m,
2245 [(store (X86setcc X86_COND_NP, STATUS), addr:$dst)]>,
2246 TB; // [mem8] = not parity
2248 // Integer comparisons
2249 def CMP8rr : I<0x38, MRMDestReg,
2250 (ops R8 :$src1, R8 :$src2),
2251 "cmp{b} {$src2, $src1|$src1, $src2}",
2252 [(set STATUS, (X86cmp R8:$src1, R8:$src2))]>,
2254 def CMP16rr : I<0x39, MRMDestReg,
2255 (ops R16:$src1, R16:$src2),
2256 "cmp{w} {$src2, $src1|$src1, $src2}",
2257 [(set STATUS, (X86cmp R16:$src1, R16:$src2))]>,
2258 Imp<[],[STATUS]>, OpSize;
2259 def CMP32rr : I<0x39, MRMDestReg,
2260 (ops R32:$src1, R32:$src2),
2261 "cmp{l} {$src2, $src1|$src1, $src2}",
2262 [(set STATUS, (X86cmp R32:$src1, R32:$src2))]>,
2264 def CMP8mr : I<0x38, MRMDestMem,
2265 (ops i8mem :$src1, R8 :$src2),
2266 "cmp{b} {$src2, $src1|$src1, $src2}",
2267 [(set STATUS, (X86cmp (loadi8 addr:$src1), R8:$src2))]>,
2269 def CMP16mr : I<0x39, MRMDestMem,
2270 (ops i16mem:$src1, R16:$src2),
2271 "cmp{w} {$src2, $src1|$src1, $src2}",
2272 [(set STATUS, (X86cmp (loadi16 addr:$src1), R16:$src2))]>,
2273 Imp<[],[STATUS]>, OpSize;
2274 def CMP32mr : I<0x39, MRMDestMem,
2275 (ops i32mem:$src1, R32:$src2),
2276 "cmp{l} {$src2, $src1|$src1, $src2}",
2277 [(set STATUS, (X86cmp (loadi32 addr:$src1), R32:$src2))]>,
2279 def CMP8rm : I<0x3A, MRMSrcMem,
2280 (ops R8 :$src1, i8mem :$src2),
2281 "cmp{b} {$src2, $src1|$src1, $src2}",
2282 [(set STATUS, (X86cmp R8:$src1, (loadi8 addr:$src2)))]>,
2284 def CMP16rm : I<0x3B, MRMSrcMem,
2285 (ops R16:$src1, i16mem:$src2),
2286 "cmp{w} {$src2, $src1|$src1, $src2}",
2287 [(set STATUS, (X86cmp R16:$src1, (loadi16 addr:$src2)))]>,
2288 Imp<[],[STATUS]>, OpSize;
2289 def CMP32rm : I<0x3B, MRMSrcMem,
2290 (ops R32:$src1, i32mem:$src2),
2291 "cmp{l} {$src2, $src1|$src1, $src2}",
2292 [(set STATUS, (X86cmp R32:$src1, (loadi32 addr:$src2)))]>,
2294 def CMP8ri : Ii8<0x80, MRM7r,
2295 (ops R8:$src1, i8imm:$src2),
2296 "cmp{b} {$src2, $src1|$src1, $src2}",
2297 [(set STATUS, (X86cmp R8:$src1, imm:$src2))]>,
2299 def CMP16ri : Ii16<0x81, MRM7r,
2300 (ops R16:$src1, i16imm:$src2),
2301 "cmp{w} {$src2, $src1|$src1, $src2}",
2302 [(set STATUS, (X86cmp R16:$src1, imm:$src2))]>,
2303 Imp<[],[STATUS]>, OpSize;
2304 def CMP32ri : Ii32<0x81, MRM7r,
2305 (ops R32:$src1, i32imm:$src2),
2306 "cmp{l} {$src2, $src1|$src1, $src2}",
2307 [(set STATUS, (X86cmp R32:$src1, imm:$src2))]>,
2309 def CMP8mi : Ii8 <0x80, MRM7m,
2310 (ops i8mem :$src1, i8imm :$src2),
2311 "cmp{b} {$src2, $src1|$src1, $src2}",
2312 [(set STATUS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>,
2314 def CMP16mi : Ii16<0x81, MRM7m,
2315 (ops i16mem:$src1, i16imm:$src2),
2316 "cmp{w} {$src2, $src1|$src1, $src2}",
2317 [(set STATUS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
2318 Imp<[],[STATUS]>, OpSize;
2319 def CMP32mi : Ii32<0x81, MRM7m,
2320 (ops i32mem:$src1, i32imm:$src2),
2321 "cmp{l} {$src2, $src1|$src1, $src2}",
2322 [(set STATUS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>,
2325 // Sign/Zero extenders
2326 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
2327 "movs{bw|x} {$src, $dst|$dst, $src}",
2328 [(set R16:$dst, (sext R8:$src))]>, TB, OpSize;
2329 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src),
2330 "movs{bw|x} {$src, $dst|$dst, $src}",
2331 [(set R16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2332 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src),
2333 "movs{bl|x} {$src, $dst|$dst, $src}",
2334 [(set R32:$dst, (sext R8:$src))]>, TB;
2335 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src),
2336 "movs{bl|x} {$src, $dst|$dst, $src}",
2337 [(set R32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2338 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src),
2339 "movs{wl|x} {$src, $dst|$dst, $src}",
2340 [(set R32:$dst, (sext R16:$src))]>, TB;
2341 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src),
2342 "movs{wl|x} {$src, $dst|$dst, $src}",
2343 [(set R32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2345 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src),
2346 "movz{bw|x} {$src, $dst|$dst, $src}",
2347 [(set R16:$dst, (zext R8:$src))]>, TB, OpSize;
2348 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src),
2349 "movz{bw|x} {$src, $dst|$dst, $src}",
2350 [(set R16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2351 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src),
2352 "movz{bl|x} {$src, $dst|$dst, $src}",
2353 [(set R32:$dst, (zext R8:$src))]>, TB;
2354 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src),
2355 "movz{bl|x} {$src, $dst|$dst, $src}",
2356 [(set R32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2357 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src),
2358 "movz{wl|x} {$src, $dst|$dst, $src}",
2359 [(set R32:$dst, (zext R16:$src))]>, TB;
2360 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
2361 "movz{wl|x} {$src, $dst|$dst, $src}",
2362 [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2364 //===----------------------------------------------------------------------===//
2365 // XMM Floating point support (requires SSE / SSE2)
2366 //===----------------------------------------------------------------------===//
2368 def MOVSSrr : I<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
2369 "movss {$src, $dst|$dst, $src}", []>,
2370 Requires<[HasSSE1]>, XS;
2371 def MOVSDrr : I<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
2372 "movsd {$src, $dst|$dst, $src}", []>,
2373 Requires<[HasSSE2]>, XD;
2375 def MOVSSrm : I<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
2376 "movss {$src, $dst|$dst, $src}",
2377 [(set FR32:$dst, (loadf32 addr:$src))]>,
2378 Requires<[HasSSE1]>, XS;
2379 def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
2380 "movss {$src, $dst|$dst, $src}",
2381 [(store FR32:$src, addr:$dst)]>,
2382 Requires<[HasSSE1]>, XS;
2383 def MOVSDrm : I<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
2384 "movsd {$src, $dst|$dst, $src}",
2385 [(set FR64:$dst, (loadf64 addr:$src))]>,
2386 Requires<[HasSSE2]>, XD;
2387 def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
2388 "movsd {$src, $dst|$dst, $src}",
2389 [(store FR64:$src, addr:$dst)]>,
2390 Requires<[HasSSE2]>, XD;
2392 def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
2393 "cvttsd2si {$src, $dst|$dst, $src}",
2394 [(set R32:$dst, (fp_to_sint FR64:$src))]>,
2395 Requires<[HasSSE2]>, XD;
2396 def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
2397 "cvttsd2si {$src, $dst|$dst, $src}",
2398 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>,
2399 Requires<[HasSSE2]>, XD;
2400 def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
2401 "cvttss2si {$src, $dst|$dst, $src}",
2402 [(set R32:$dst, (fp_to_sint FR32:$src))]>,
2403 Requires<[HasSSE1]>, XS;
2404 def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
2405 "cvttss2si {$src, $dst|$dst, $src}",
2406 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>,
2407 Requires<[HasSSE1]>, XS;
2408 def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
2409 "cvtsd2ss {$src, $dst|$dst, $src}",
2410 [(set FR32:$dst, (fround FR64:$src))]>,
2411 Requires<[HasSSE2]>, XS;
2412 def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
2413 "cvtsd2ss {$src, $dst|$dst, $src}",
2414 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>,
2415 Requires<[HasSSE2]>, XS;
2416 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
2417 "cvtss2sd {$src, $dst|$dst, $src}",
2418 [(set FR64:$dst, (fextend FR32:$src))]>,
2419 Requires<[HasSSE2]>, XD;
2420 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
2421 "cvtss2sd {$src, $dst|$dst, $src}",
2422 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>,
2423 Requires<[HasSSE2]>, XD;
2424 def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
2425 "cvtsi2ss {$src, $dst|$dst, $src}",
2426 [(set FR32:$dst, (sint_to_fp R32:$src))]>,
2427 Requires<[HasSSE2]>, XS;
2428 def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
2429 "cvtsi2ss {$src, $dst|$dst, $src}",
2430 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>,
2431 Requires<[HasSSE2]>, XS;
2432 def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
2433 "cvtsi2sd {$src, $dst|$dst, $src}",
2434 [(set FR64:$dst, (sint_to_fp R32:$src))]>,
2435 Requires<[HasSSE2]>, XD;
2436 def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
2437 "cvtsi2sd {$src, $dst|$dst, $src}",
2438 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>,
2439 Requires<[HasSSE2]>, XD;
2441 def SQRTSSrm : I<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
2442 "sqrtss {$src, $dst|$dst, $src}",
2443 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>,
2444 Requires<[HasSSE1]>, XS;
2445 def SQRTSSrr : I<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
2446 "sqrtss {$src, $dst|$dst, $src}",
2447 [(set FR32:$dst, (fsqrt FR32:$src))]>,
2448 Requires<[HasSSE1]>, XS;
2449 def SQRTSDrm : I<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
2450 "sqrtsd {$src, $dst|$dst, $src}",
2451 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>,
2452 Requires<[HasSSE2]>, XD;
2453 def SQRTSDrr : I<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
2454 "sqrtsd {$src, $dst|$dst, $src}",
2455 [(set FR64:$dst, (fsqrt FR64:$src))]>,
2456 Requires<[HasSSE2]>, XD;
2458 def UCOMISDrr: I<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
2459 "ucomisd {$src2, $src1|$src1, $src2}",
2460 [(set STATUS, (X86cmp FR64:$src1, FR64:$src2))]>,
2461 Requires<[HasSSE2]>, TB, OpSize;
2462 def UCOMISDrm: I<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
2463 "ucomisd {$src2, $src1|$src1, $src2}",
2464 [(set STATUS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>,
2465 Imp<[],[STATUS]>, Requires<[HasSSE2]>, TB, OpSize;
2466 def UCOMISSrr: I<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
2467 "ucomiss {$src2, $src1|$src1, $src2}",
2468 [(set STATUS, (X86cmp FR32:$src1, FR32:$src2))]>,
2469 Imp<[],[STATUS]>, Requires<[HasSSE1]>, TB;
2470 def UCOMISSrm: I<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
2471 "ucomiss {$src2, $src1|$src1, $src2}",
2472 [(set STATUS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>,
2473 Imp<[],[STATUS]>, Requires<[HasSSE1]>, TB;
2475 // Pseudo-instructions that map fld0 to xorps/xorpd for sse.
2476 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2477 def FLD0SS : I<0x57, MRMSrcReg, (ops FR32:$dst),
2478 "xorps $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
2479 Requires<[HasSSE1]>, TB;
2480 def FLD0SD : I<0x57, MRMSrcReg, (ops FR64:$dst),
2481 "xorpd $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
2482 Requires<[HasSSE2]>, TB, OpSize;
2484 let isTwoAddress = 1 in {
2485 // SSE Scalar Arithmetic
2486 let isCommutable = 1 in {
2487 def ADDSSrr : I<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2488 "addss {$src2, $dst|$dst, $src2}",
2489 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>,
2490 Requires<[HasSSE1]>, XS;
2491 def ADDSDrr : I<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2492 "addsd {$src2, $dst|$dst, $src2}",
2493 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>,
2494 Requires<[HasSSE2]>, XD;
2495 def MULSSrr : I<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2496 "mulss {$src2, $dst|$dst, $src2}",
2497 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>,
2498 Requires<[HasSSE1]>, XS;
2499 def MULSDrr : I<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2500 "mulsd {$src2, $dst|$dst, $src2}",
2501 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>,
2502 Requires<[HasSSE2]>, XD;
2505 def ADDSSrm : I<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
2506 "addss {$src2, $dst|$dst, $src2}",
2507 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>,
2508 Requires<[HasSSE1]>, XS;
2509 def ADDSDrm : I<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
2510 "addsd {$src2, $dst|$dst, $src2}",
2511 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>,
2512 Requires<[HasSSE2]>, XD;
2513 def MULSSrm : I<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
2514 "mulss {$src2, $dst|$dst, $src2}",
2515 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>,
2516 Requires<[HasSSE1]>, XS;
2517 def MULSDrm : I<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
2518 "mulsd {$src2, $dst|$dst, $src2}",
2519 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>,
2520 Requires<[HasSSE2]>, XD;
2522 def DIVSSrr : I<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2523 "divss {$src2, $dst|$dst, $src2}",
2524 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>,
2525 Requires<[HasSSE1]>, XS;
2526 def DIVSSrm : I<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
2527 "divss {$src2, $dst|$dst, $src2}",
2528 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>,
2529 Requires<[HasSSE1]>, XS;
2530 def DIVSDrr : I<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2531 "divsd {$src2, $dst|$dst, $src2}",
2532 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>,
2533 Requires<[HasSSE2]>, XD;
2534 def DIVSDrm : I<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
2535 "divsd {$src2, $dst|$dst, $src2}",
2536 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>,
2537 Requires<[HasSSE2]>, XD;
2539 def SUBSSrr : I<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2540 "subss {$src2, $dst|$dst, $src2}",
2541 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>,
2542 Requires<[HasSSE1]>, XS;
2543 def SUBSSrm : I<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
2544 "subss {$src2, $dst|$dst, $src2}",
2545 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>,
2546 Requires<[HasSSE1]>, XS;
2547 def SUBSDrr : I<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2548 "subsd {$src2, $dst|$dst, $src2}",
2549 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>,
2550 Requires<[HasSSE2]>, XD;
2551 def SUBSDrm : I<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
2552 "subsd {$src2, $dst|$dst, $src2}",
2553 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>,
2554 Requires<[HasSSE2]>, XD;
2557 let isCommutable = 1 in {
2558 def ANDPSrr : I<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2559 "andps {$src2, $dst|$dst, $src2}", []>,
2560 Requires<[HasSSE1]>, TB;
2561 def ANDPDrr : I<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2562 "andpd {$src2, $dst|$dst, $src2}", []>,
2563 Requires<[HasSSE2]>, TB, OpSize;
2564 def ORPSrr : I<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2565 "orps {$src2, $dst|$dst, $src2}", []>,
2566 Requires<[HasSSE1]>, TB;
2567 def ORPDrr : I<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2568 "orpd {$src2, $dst|$dst, $src2}", []>,
2569 Requires<[HasSSE2]>, TB, OpSize;
2570 def XORPSrr : I<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2571 "xorps {$src2, $dst|$dst, $src2}", []>,
2572 Requires<[HasSSE1]>, TB;
2573 def XORPDrr : I<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2574 "xorpd {$src2, $dst|$dst, $src2}", []>,
2575 Requires<[HasSSE2]>, TB, OpSize;
2577 def ANDNPSrr : I<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
2578 "andnps {$src2, $dst|$dst, $src2}", []>,
2579 Requires<[HasSSE1]>, TB;
2580 def ANDNPDrr : I<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
2581 "andnpd {$src2, $dst|$dst, $src2}", []>,
2582 Requires<[HasSSE2]>, TB, OpSize;
2584 def CMPSSrr : I<0xC2, MRMSrcReg,
2585 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
2586 "cmp${cc}ss {$src, $dst|$dst, $src}", []>,
2587 Requires<[HasSSE1]>, XS;
2588 def CMPSSrm : I<0xC2, MRMSrcMem,
2589 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
2590 "cmp${cc}ss {$src, $dst|$dst, $src}", []>,
2591 Requires<[HasSSE1]>, XS;
2592 def CMPSDrr : I<0xC2, MRMSrcReg,
2593 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
2594 "cmp${cc}sd {$src, $dst|$dst, $src}", []>,
2595 Requires<[HasSSE1]>, XD;
2596 def CMPSDrm : I<0xC2, MRMSrcMem,
2597 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
2598 "cmp${cc}sd {$src, $dst|$dst, $src}", []>,
2599 Requires<[HasSSE2]>, XD;
2602 //===----------------------------------------------------------------------===//
2603 // Floating Point Stack Support
2604 //===----------------------------------------------------------------------===//
2606 // Floating point support. All FP Stack operations are represented with two
2607 // instructions here. The first instruction, generated by the instruction
2608 // selector, uses "RFP" registers: a traditional register file to reference
2609 // floating point values. These instructions are all psuedo instructions and
2610 // use the "Fp" prefix. The second instruction is defined with FPI, which is
2611 // the actual instruction emitted by the assembler. The FP stackifier pass
2612 // converts one to the other after register allocation occurs.
2614 // Note that the FpI instruction should have instruction selection info (e.g.
2615 // a pattern) and the FPI instruction should have emission info (e.g. opcode
2616 // encoding and asm printing info).
2618 // FPI - Floating Point Instruction template.
2619 class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {}
2621 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
2622 class FpI_<dag ops, FPFormat fp, list<dag> pattern>
2623 : X86Inst<0, Pseudo, NoImm, ops, ""> {
2624 let FPForm = fp; let FPFormBits = FPForm.Value;
2625 let Pattern = pattern;
2628 // Random Pseudo Instructions.
2629 def FpGETRESULT : FpI_<(ops RFP:$dst), SpecialFP,
2630 [(set RFP:$dst, X86fpget)]>; // FPR = ST(0)
2632 let noResults = 1 in
2633 def FpSETRESULT : FpI_<(ops RFP:$src), SpecialFP,
2634 [(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
2636 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
2637 class FpI<dag ops, FPFormat fp, list<dag> pattern> :
2638 FpI_<ops, fp, pattern>, Requires<[FPStack]>;
2641 def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
2644 // Add, Sub, Mul, Div.
2645 def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
2646 [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>;
2647 def FpSUB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
2648 [(set RFP:$dst, (fsub RFP:$src1, RFP:$src2))]>;
2649 def FpMUL : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
2650 [(set RFP:$dst, (fmul RFP:$src1, RFP:$src2))]>;
2651 def FpDIV : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
2652 [(set RFP:$dst, (fdiv RFP:$src1, RFP:$src2))]>;
2654 class FPST0rInst<bits<8> o, string asm>
2655 : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8;
2656 class FPrST0Inst<bits<8> o, string asm>
2657 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC;
2658 class FPrST0PInst<bits<8> o, string asm>
2659 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE;
2661 // Binary Ops with a memory source.
2662 def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2663 [(set RFP:$dst, (fadd RFP:$src1,
2664 (extloadf64f32 addr:$src2)))]>;
2665 // ST(0) = ST(0) + [mem32]
2666 def FpADD64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2667 [(set RFP:$dst, (fadd RFP:$src1, (loadf64 addr:$src2)))]>;
2668 // ST(0) = ST(0) + [mem64]
2669 def FpMUL32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2670 [(set RFP:$dst, (fmul RFP:$src1,
2671 (extloadf64f32 addr:$src2)))]>;
2672 // ST(0) = ST(0) * [mem32]
2673 def FpMUL64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2674 [(set RFP:$dst, (fmul RFP:$src1, (loadf64 addr:$src2)))]>;
2675 // ST(0) = ST(0) * [mem64]
2676 def FpSUB32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2677 [(set RFP:$dst, (fsub RFP:$src1,
2678 (extloadf64f32 addr:$src2)))]>;
2679 // ST(0) = ST(0) - [mem32]
2680 def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2681 [(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>;
2682 // ST(0) = ST(0) - [mem64]
2683 def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2684 [(set RFP:$dst, (fsub (extloadf64f32 addr:$src2),
2686 // ST(0) = [mem32] - ST(0)
2687 def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2688 [(set RFP:$dst, (fsub (loadf64 addr:$src2), RFP:$src1))]>;
2689 // ST(0) = [mem64] - ST(0)
2690 def FpDIV32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2691 [(set RFP:$dst, (fdiv RFP:$src1,
2692 (extloadf64f32 addr:$src2)))]>;
2693 // ST(0) = ST(0) / [mem32]
2694 def FpDIV64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2695 [(set RFP:$dst, (fdiv RFP:$src1, (loadf64 addr:$src2)))]>;
2696 // ST(0) = ST(0) / [mem64]
2697 def FpDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2698 [(set RFP:$dst, (fdiv (extloadf64f32 addr:$src2),
2700 // ST(0) = [mem32] / ST(0)
2701 def FpDIVR64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
2702 [(set RFP:$dst, (fdiv (loadf64 addr:$src2), RFP:$src1))]>;
2703 // ST(0) = [mem64] / ST(0)
2706 def FADD32m : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">;
2707 def FADD64m : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">;
2708 def FMUL32m : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">;
2709 def FMUL64m : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">;
2710 def FSUB32m : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">;
2711 def FSUB64m : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">;
2712 def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">;
2713 def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">;
2714 def FDIV32m : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">;
2715 def FDIV64m : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">;
2716 def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">;
2717 def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">;
2719 // FIXME: Implement these when we have a dag-dag isel!
2720 def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2721 [(set RFP:$dst, (fadd RFP:$src1,
2722 (X86fild addr:$src2, i16)))]>;
2723 // ST(0) = ST(0) + [mem16int]
2724 def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2725 [(set RFP:$dst, (fadd RFP:$src1,
2726 (X86fild addr:$src2, i32)))]>;
2727 // ST(0) = ST(0) + [mem32int]
2728 def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2729 [(set RFP:$dst, (fmul RFP:$src1,
2730 (X86fild addr:$src2, i16)))]>;
2731 // ST(0) = ST(0) * [mem16int]
2732 def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2733 [(set RFP:$dst, (fmul RFP:$src1,
2734 (X86fild addr:$src2, i32)))]>;
2735 // ST(0) = ST(0) * [mem32int]
2736 def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2737 [(set RFP:$dst, (fsub RFP:$src1,
2738 (X86fild addr:$src2, i16)))]>;
2739 // ST(0) = ST(0) - [mem16int]
2740 def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2741 [(set RFP:$dst, (fsub RFP:$src1,
2742 (X86fild addr:$src2, i32)))]>;
2743 // ST(0) = ST(0) - [mem32int]
2744 def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2745 [(set RFP:$dst, (fsub (X86fild addr:$src2, i16),
2747 // ST(0) = [mem16int] - ST(0)
2748 def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2749 [(set RFP:$dst, (fsub (X86fild addr:$src2, i32),
2751 // ST(0) = [mem32int] - ST(0)
2752 def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2753 [(set RFP:$dst, (fdiv RFP:$src1,
2754 (X86fild addr:$src2, i16)))]>;
2755 // ST(0) = ST(0) / [mem16int]
2756 def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2757 [(set RFP:$dst, (fdiv RFP:$src1,
2758 (X86fild addr:$src2, i32)))]>;
2759 // ST(0) = ST(0) / [mem32int]
2760 def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2761 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i16),
2763 // ST(0) = [mem16int] / ST(0)
2764 def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
2765 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i32),
2767 // ST(0) = [mem32int] / ST(0)
2769 def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">;
2770 def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">;
2771 def FIMUL16m : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">;
2772 def FIMUL32m : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">;
2773 def FISUB16m : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">;
2774 def FISUB32m : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">;
2775 def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">;
2776 def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">;
2777 def FIDIV16m : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">;
2778 def FIDIV32m : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{s} $src">;
2779 def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">;
2780 def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{s} $src">;
2782 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
2783 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
2784 // we have to put some 'r's in and take them out of weird places.
2785 def FADDST0r : FPST0rInst <0xC0, "fadd $op">;
2786 def FADDrST0 : FPrST0Inst <0xC0, "fadd {%ST(0), $op|$op, %ST(0)}">;
2787 def FADDPrST0 : FPrST0PInst<0xC0, "faddp $op">;
2788 def FSUBRST0r : FPST0rInst <0xE8, "fsubr $op">;
2789 def FSUBrST0 : FPrST0Inst <0xE8, "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
2790 def FSUBPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
2791 def FSUBST0r : FPST0rInst <0xE0, "fsub $op">;
2792 def FSUBRrST0 : FPrST0Inst <0xE0, "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
2793 def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
2794 def FMULST0r : FPST0rInst <0xC8, "fmul $op">;
2795 def FMULrST0 : FPrST0Inst <0xC8, "fmul {%ST(0), $op|$op, %ST(0)}">;
2796 def FMULPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
2797 def FDIVRST0r : FPST0rInst <0xF8, "fdivr $op">;
2798 def FDIVrST0 : FPrST0Inst <0xF8, "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
2799 def FDIVPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
2800 def FDIVST0r : FPST0rInst <0xF0, "fdiv $op">;
2801 def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
2802 def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
2805 // Unary operations.
2806 def FpCHS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
2807 [(set RFP:$dst, (fneg RFP:$src))]>;
2808 def FpABS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
2809 [(set RFP:$dst, (fabs RFP:$src))]>;
2810 def FpSQRT : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
2811 [(set RFP:$dst, (fsqrt RFP:$src))]>;
2812 def FpSIN : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
2813 [(set RFP:$dst, (fsin RFP:$src))]>;
2814 def FpCOS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
2815 [(set RFP:$dst, (fcos RFP:$src))]>;
2816 def FpTST : FpI<(ops RFP:$src), OneArgFP,
2819 def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9;
2820 def FABS : FPI<0xE1, RawFrm, (ops), "fabs">, D9;
2821 def FSQRT : FPI<0xFA, RawFrm, (ops), "fsqrt">, D9;
2822 def FSIN : FPI<0xFE, RawFrm, (ops), "fsin">, D9;
2823 def FCOS : FPI<0xFF, RawFrm, (ops), "fcos">, D9;
2824 def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9;
2827 // Floating point cmovs.
2828 let isTwoAddress = 1 in {
2829 def FpCMOVB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2830 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2831 X86_COND_B, STATUS))]>;
2832 def FpCMOVBE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2833 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2834 X86_COND_BE, STATUS))]>;
2835 def FpCMOVE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2836 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2837 X86_COND_E, STATUS))]>;
2838 def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2839 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2840 X86_COND_P, STATUS))]>;
2841 def FpCMOVAE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2842 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2843 X86_COND_AE, STATUS))]>;
2844 def FpCMOVA : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2845 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2846 X86_COND_A, STATUS))]>;
2847 def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2848 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2849 X86_COND_NE, STATUS))]>;
2850 def FpCMOVNP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
2851 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
2852 X86_COND_NP, STATUS))]>;
2855 def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op),
2856 "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
2857 def FCMOVBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
2858 "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
2859 def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op),
2860 "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
2861 def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op),
2862 "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
2863 def FCMOVAE : FPI<0xC0, AddRegFrm, (ops RST:$op),
2864 "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
2865 def FCMOVA : FPI<0xD0, AddRegFrm, (ops RST:$op),
2866 "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
2867 def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op),
2868 "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
2869 def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op),
2870 "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
2872 // Floating point loads & stores.
2873 def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP,
2874 [(set RFP:$dst, (extloadf64f32 addr:$src))]>;
2875 def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP,
2876 [(set RFP:$dst, (loadf64 addr:$src))]>;
2877 def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP,
2878 [(set RFP:$dst, (X86fild addr:$src, i16))]>;
2879 def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
2880 [(set RFP:$dst, (X86fild addr:$src, i32))]>;
2881 def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
2882 [(set RFP:$dst, (X86fild addr:$src, i64))]>;
2884 def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
2885 [(truncstore RFP:$src, addr:$op, f32)]>;
2886 def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP,
2887 [(store RFP:$src, addr:$op)]>;
2889 def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>;
2890 def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>;
2891 def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>;
2892 def FpIST32m : FpI<(ops i32mem:$op, RFP:$src), OneArgFP, []>;
2893 def FpIST64m : FpI<(ops i64mem:$op, RFP:$src), OneArgFP, []>;
2895 def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">;
2896 def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">;
2897 def FILD16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">;
2898 def FILD32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">;
2899 def FILD64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">;
2900 def FST32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">;
2901 def FST64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">;
2902 def FSTP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">;
2903 def FSTP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">;
2904 def FIST16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">;
2905 def FIST32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">;
2906 def FISTP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">;
2907 def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
2908 def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
2910 // FP Stack manipulation instructions.
2911 def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
2912 def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
2913 def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD;
2914 def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
2916 // Floating point constant loads.
2917 def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
2918 [(set RFP:$dst, fp64imm0)]>;
2919 def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
2920 [(set RFP:$dst, fp64imm1)]>;
2922 def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
2923 def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
2926 // Floating point compares.
2927 def FpUCOMr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
2928 []>; // FPSW = cmp ST(0) with ST(i)
2929 def FpUCOMIr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
2930 [(set STATUS, (X86cmp RFP:$lhs, RFP:$rhs))]>,
2931 Imp<[],[STATUS]>; // CC = cmp ST(0) with ST(i)
2933 def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
2935 "fucom $reg">, DD, Imp<[ST0],[]>;
2936 def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
2938 "fucomp $reg">, DD, Imp<[ST0],[]>;
2939 def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
2941 "fucompp">, DA, Imp<[ST0],[]>;
2943 def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
2945 "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
2946 def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
2948 "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
2951 // Floating point flag ops.
2952 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
2953 (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
2955 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
2956 (ops i16mem:$dst), "fnstcw $dst", []>;
2957 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
2958 (ops i16mem:$dst), "fldcw $dst", []>;
2961 //===----------------------------------------------------------------------===//
2962 // Miscellaneous Instructions
2963 //===----------------------------------------------------------------------===//
2965 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
2966 TB, Imp<[],[EAX,EDX]>;
2969 //===----------------------------------------------------------------------===//
2970 // Non-Instruction Patterns
2971 //===----------------------------------------------------------------------===//
2973 // GlobalAddress and ExternalSymbol
2974 def : Pat<(i32 globaladdr:$dst), (MOV32ri tglobaladdr:$dst)>;
2975 def : Pat<(i32 externalsym:$dst), (MOV32ri texternalsym:$dst)>;
2978 def : Pat<(X86call tglobaladdr:$dst),
2979 (CALLpcrel32 tglobaladdr:$dst)>;
2980 def : Pat<(X86call texternalsym:$dst),
2981 (CALLpcrel32 texternalsym:$dst)>;
2983 // X86 specific add which produces a flag.
2984 def : Pat<(X86addflag R32:$src1, R32:$src2),
2985 (ADD32rr R32:$src1, R32:$src2)>;
2986 def : Pat<(X86addflag R32:$src1, (load addr:$src2)),
2987 (ADD32rm R32:$src1, addr:$src2)>;
2988 def : Pat<(X86addflag R32:$src1, imm:$src2),
2989 (ADD32ri R32:$src1, imm:$src2)>;
2990 def : Pat<(X86addflag R32:$src1, i32immSExt8:$src2),
2991 (ADD32ri8 R32:$src1, i32immSExt8:$src2)>;
2993 def : Pat<(X86subflag R32:$src1, R32:$src2),
2994 (SUB32rr R32:$src1, R32:$src2)>;
2995 def : Pat<(X86subflag R32:$src1, (load addr:$src2)),
2996 (SUB32rm R32:$src1, addr:$src2)>;
2997 def : Pat<(X86subflag R32:$src1, imm:$src2),
2998 (SUB32ri R32:$src1, imm:$src2)>;
2999 def : Pat<(X86subflag R32:$src1, i32immSExt8:$src2),
3000 (SUB32ri8 R32:$src1, i32immSExt8:$src2)>;
3002 def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1),
3003 (MOV8mi addr:$dst, imm:$src)>;
3004 def : Pat<(truncstore R8:$src, addr:$dst, i1),
3005 (MOV8mr addr:$dst, R8:$src)>;
3007 // {s|z}extload bool -> {s|z}extload byte
3008 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
3009 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
3010 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3011 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3013 // extload bool -> extload byte
3014 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3017 def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>;
3018 def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src)>;
3019 def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>;
3021 // Required for RET of f32 / f64 values.
3022 def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
3023 def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
3025 // Required for CALL which return f32 / f64 values.
3026 def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
3027 def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
3029 // Floatin point constant -0.0 and -1.0
3030 def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
3031 def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
3034 def : Pat<(f64 (undef)), (FpLD0)>, Requires<[FPStack]>;
3037 //===----------------------------------------------------------------------===//
3039 //===----------------------------------------------------------------------===//
3041 // (shl x, 1) ==> (add x, x)
3042 def : Pat<(shl R8 :$src1, (i8 1)), (ADD8rr R8 :$src1, R8 :$src1)>;
3043 def : Pat<(shl R16:$src1, (i8 1)), (ADD16rr R16:$src1, R16:$src1)>;
3044 def : Pat<(shl R32:$src1, (i8 1)), (ADD32rr R32:$src1, R32:$src1)>;