1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
68 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
92 def SDTX86Void : SDTypeProfile<0, 0, []>;
94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
100 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
102 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
106 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
107 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
109 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
111 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
113 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
115 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
117 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
121 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
122 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
123 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
124 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
126 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
127 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
129 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
130 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
132 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
133 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
135 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
136 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
137 SDNPMayLoad, SDNPMemOperand]>;
138 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
139 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
140 SDNPMayLoad, SDNPMemOperand]>;
141 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
142 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
143 SDNPMayLoad, SDNPMemOperand]>;
145 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
146 [SDNPHasChain, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
149 [SDNPHasChain, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
152 [SDNPHasChain, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
155 [SDNPHasChain, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
157 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
158 [SDNPHasChain, SDNPMayStore,
159 SDNPMayLoad, SDNPMemOperand]>;
160 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
161 [SDNPHasChain, SDNPMayStore,
162 SDNPMayLoad, SDNPMemOperand]>;
163 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
164 [SDNPHasChain, SDNPMayStore,
165 SDNPMayLoad, SDNPMemOperand]>;
166 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
167 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
169 def X86vastart_save_xmm_regs :
170 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
171 SDT_X86VASTART_SAVE_XMM_REGS,
172 [SDNPHasChain, SDNPVariadic]>;
174 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
175 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
177 def X86callseq_start :
178 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
179 [SDNPHasChain, SDNPOutGlue]>;
181 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
184 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
185 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
188 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
189 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
190 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
191 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
194 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
195 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
197 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
198 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
200 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
201 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
203 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
206 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
207 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
209 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
211 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
212 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
214 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
216 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
217 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
219 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
220 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
221 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
223 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
225 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
228 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
230 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
231 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
233 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
236 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
237 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
239 //===----------------------------------------------------------------------===//
240 // X86 Operand Definitions.
243 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
244 // the index operand of an address, to conform to x86 encoding restrictions.
245 def ptr_rc_nosp : PointerLikeRegClass<1>;
247 // *mem - Operand definitions for the funky X86 addressing mode operands.
249 def X86MemAsmOperand : AsmOperandClass {
251 let SuperClasses = [];
253 def X86AbsMemAsmOperand : AsmOperandClass {
255 let SuperClasses = [X86MemAsmOperand];
257 class X86MemOperand<string printMethod> : Operand<iPTR> {
258 let PrintMethod = printMethod;
259 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
260 let ParserMatchClass = X86MemAsmOperand;
263 let OperandType = "OPERAND_MEMORY" in {
264 def opaque32mem : X86MemOperand<"printopaquemem">;
265 def opaque48mem : X86MemOperand<"printopaquemem">;
266 def opaque80mem : X86MemOperand<"printopaquemem">;
267 def opaque512mem : X86MemOperand<"printopaquemem">;
269 def i8mem : X86MemOperand<"printi8mem">;
270 def i16mem : X86MemOperand<"printi16mem">;
271 def i32mem : X86MemOperand<"printi32mem">;
272 def i64mem : X86MemOperand<"printi64mem">;
273 def i128mem : X86MemOperand<"printi128mem">;
274 def i256mem : X86MemOperand<"printi256mem">;
275 def f32mem : X86MemOperand<"printf32mem">;
276 def f64mem : X86MemOperand<"printf64mem">;
277 def f80mem : X86MemOperand<"printf80mem">;
278 def f128mem : X86MemOperand<"printf128mem">;
279 def f256mem : X86MemOperand<"printf256mem">;
282 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
283 // plain GR64, so that it doesn't potentially require a REX prefix.
284 def i8mem_NOREX : Operand<i64> {
285 let PrintMethod = "printi8mem";
286 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
287 let ParserMatchClass = X86MemAsmOperand;
288 let OperandType = "OPERAND_MEMORY";
291 // GPRs available for tailcall.
292 // It represents GR64_TC or GR64_TCW64.
293 def ptr_rc_tailcall : PointerLikeRegClass<2>;
295 // Special i32mem for addresses of load folding tail calls. These are not
296 // allowed to use callee-saved registers since they must be scheduled
297 // after callee-saved register are popped.
298 def i32mem_TC : Operand<i32> {
299 let PrintMethod = "printi32mem";
300 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
301 let ParserMatchClass = X86MemAsmOperand;
302 let OperandType = "OPERAND_MEMORY";
305 // Special i64mem for addresses of load folding tail calls. These are not
306 // allowed to use callee-saved registers since they must be scheduled
307 // after callee-saved register are popped.
308 def i64mem_TC : Operand<i64> {
309 let PrintMethod = "printi64mem";
310 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
311 ptr_rc_tailcall, i32imm, i8imm);
312 let ParserMatchClass = X86MemAsmOperand;
313 let OperandType = "OPERAND_MEMORY";
316 let OperandType = "OPERAND_PCREL",
317 ParserMatchClass = X86AbsMemAsmOperand,
318 PrintMethod = "print_pcrel_imm" in {
319 def i32imm_pcrel : Operand<i32>;
320 def i16imm_pcrel : Operand<i16>;
322 def offset8 : Operand<i64>;
323 def offset16 : Operand<i64>;
324 def offset32 : Operand<i64>;
325 def offset64 : Operand<i64>;
327 // Branch targets have OtherVT type and print as pc-relative values.
328 def brtarget : Operand<OtherVT>;
329 def brtarget8 : Operand<OtherVT>;
333 def SSECC : Operand<i8> {
334 let PrintMethod = "printSSECC";
335 let OperandType = "OPERAND_IMMEDIATE";
338 class ImmSExtAsmOperandClass : AsmOperandClass {
339 let SuperClasses = [ImmAsmOperand];
340 let RenderMethod = "addImmOperands";
343 class ImmZExtAsmOperandClass : AsmOperandClass {
344 let SuperClasses = [ImmAsmOperand];
345 let RenderMethod = "addImmOperands";
348 // Sign-extended immediate classes. We don't need to define the full lattice
349 // here because there is no instruction with an ambiguity between ImmSExti64i32
352 // The strange ranges come from the fact that the assembler always works with
353 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
354 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
357 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
358 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
359 let Name = "ImmSExti64i32";
362 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
363 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
364 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
365 let Name = "ImmSExti16i8";
366 let SuperClasses = [ImmSExti64i32AsmOperand];
369 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
370 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
371 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
372 let Name = "ImmSExti32i8";
376 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
377 let Name = "ImmZExtu32u8";
382 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
383 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
384 let Name = "ImmSExti64i8";
385 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
386 ImmSExti64i32AsmOperand];
389 // A couple of more descriptive operand definitions.
390 // 16-bits but only 8 bits are significant.
391 def i16i8imm : Operand<i16> {
392 let ParserMatchClass = ImmSExti16i8AsmOperand;
393 let OperandType = "OPERAND_IMMEDIATE";
395 // 32-bits but only 8 bits are significant.
396 def i32i8imm : Operand<i32> {
397 let ParserMatchClass = ImmSExti32i8AsmOperand;
398 let OperandType = "OPERAND_IMMEDIATE";
400 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
401 def u32u8imm : Operand<i32> {
402 let ParserMatchClass = ImmZExtu32u8AsmOperand;
403 let OperandType = "OPERAND_IMMEDIATE";
406 // 64-bits but only 32 bits are significant.
407 def i64i32imm : Operand<i64> {
408 let ParserMatchClass = ImmSExti64i32AsmOperand;
409 let OperandType = "OPERAND_IMMEDIATE";
412 // 64-bits but only 32 bits are significant, and those bits are treated as being
414 def i64i32imm_pcrel : Operand<i64> {
415 let PrintMethod = "print_pcrel_imm";
416 let ParserMatchClass = X86AbsMemAsmOperand;
417 let OperandType = "OPERAND_PCREL";
420 // 64-bits but only 8 bits are significant.
421 def i64i8imm : Operand<i64> {
422 let ParserMatchClass = ImmSExti64i8AsmOperand;
423 let OperandType = "OPERAND_IMMEDIATE";
426 def lea64_32mem : Operand<i32> {
427 let PrintMethod = "printi32mem";
428 let AsmOperandLowerMethod = "lower_lea64_32mem";
429 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
430 let ParserMatchClass = X86MemAsmOperand;
434 //===----------------------------------------------------------------------===//
435 // X86 Complex Pattern Definitions.
438 // Define X86 specific addressing mode.
439 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
440 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
441 [add, sub, mul, X86mul_imm, shl, or, frameindex],
443 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
444 [tglobaltlsaddr], []>;
446 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
447 [add, sub, mul, X86mul_imm, shl, or, frameindex,
450 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
451 [tglobaltlsaddr], []>;
453 //===----------------------------------------------------------------------===//
454 // X86 Instruction Predicate Definitions.
455 def HasCMov : Predicate<"Subtarget->hasCMov()">;
456 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
458 def HasMMX : Predicate<"Subtarget->hasMMX()">;
459 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
460 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
461 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
462 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
463 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
464 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
465 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
466 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
467 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
469 def HasAVX : Predicate<"Subtarget->hasAVX()">;
470 def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
472 def HasAES : Predicate<"Subtarget->hasAES()">;
473 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
474 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
475 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
476 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
477 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
478 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
479 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
480 AssemblerPredicate<"!Mode64Bit">;
481 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
482 AssemblerPredicate<"Mode64Bit">;
483 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
484 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
485 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">,
486 AssemblerPredicate<"ModeNaCl">;
487 def IsNaCl32 : Predicate<"Subtarget->isTargetNaCl32()">,
488 AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
489 def IsNaCl64 : Predicate<"Subtarget->isTargetNaCl64()">,
490 AssemblerPredicate<"ModeNaCl,Mode64Bit">;
491 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">,
492 AssemblerPredicate<"!ModeNaCl">;
493 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
494 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
495 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
496 "TM.getCodeModel() != CodeModel::Kernel">;
497 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
498 "TM.getCodeModel() == CodeModel::Kernel">;
499 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
500 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
501 def OptForSize : Predicate<"OptForSize">;
502 def OptForSpeed : Predicate<"!OptForSize">;
503 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
504 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
506 //===----------------------------------------------------------------------===//
507 // X86 Instruction Format Definitions.
510 include "X86InstrFormats.td"
512 //===----------------------------------------------------------------------===//
513 // Pattern fragments.
516 // X86 specific condition code. These correspond to CondCode in
517 // X86InstrInfo.h. They must be kept in synch.
518 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
519 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
520 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
521 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
522 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
523 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
524 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
525 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
526 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
527 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
528 def X86_COND_NO : PatLeaf<(i8 10)>;
529 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
530 def X86_COND_NS : PatLeaf<(i8 12)>;
531 def X86_COND_O : PatLeaf<(i8 13)>;
532 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
533 def X86_COND_S : PatLeaf<(i8 15)>;
535 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
536 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
537 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
538 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
541 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
544 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
546 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
548 def i64immZExt32SExt8 : ImmLeaf<i64, [{
549 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
552 // Helper fragments for loads.
553 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
554 // known to be 32-bit aligned or better. Ditto for i8 to i16.
555 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
556 LoadSDNode *LD = cast<LoadSDNode>(N);
557 ISD::LoadExtType ExtType = LD->getExtensionType();
558 if (ExtType == ISD::NON_EXTLOAD)
560 if (ExtType == ISD::EXTLOAD)
561 return LD->getAlignment() >= 2 && !LD->isVolatile();
565 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
566 LoadSDNode *LD = cast<LoadSDNode>(N);
567 ISD::LoadExtType ExtType = LD->getExtensionType();
568 if (ExtType == ISD::EXTLOAD)
569 return LD->getAlignment() >= 2 && !LD->isVolatile();
573 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
574 LoadSDNode *LD = cast<LoadSDNode>(N);
575 ISD::LoadExtType ExtType = LD->getExtensionType();
576 if (ExtType == ISD::NON_EXTLOAD)
578 if (ExtType == ISD::EXTLOAD)
579 return LD->getAlignment() >= 4 && !LD->isVolatile();
583 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
584 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
585 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
586 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
587 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
589 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
590 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
591 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
592 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
593 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
594 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
596 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
597 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
598 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
599 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
600 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
601 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
602 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
603 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
604 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
605 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
607 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
608 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
609 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
610 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
611 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
612 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
613 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
614 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
615 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
616 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
619 // An 'and' node with a single use.
620 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
621 return N->hasOneUse();
623 // An 'srl' node with a single use.
624 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
625 return N->hasOneUse();
627 // An 'trunc' node with a single use.
628 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
629 return N->hasOneUse();
632 //===----------------------------------------------------------------------===//
637 let neverHasSideEffects = 1 in {
638 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
639 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
640 "nop{w}\t$zero", []>, TB, OpSize;
641 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
642 "nop{l}\t$zero", []>, TB;
646 // Constructing a stack frame.
647 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
648 "enter\t$len, $lvl", []>;
650 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
651 def LEAVE : I<0xC9, RawFrm,
652 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
654 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
655 def LEAVE64 : I<0xC9, RawFrm,
656 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
658 //===----------------------------------------------------------------------===//
659 // Miscellaneous Instructions.
662 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
664 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
666 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
667 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
669 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
671 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
672 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
674 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
675 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
676 Requires<[In32BitMode]>;
679 let mayStore = 1 in {
680 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
682 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
683 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
685 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
687 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
688 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
690 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
691 "push{l}\t$imm", []>;
692 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
693 "push{w}\t$imm", []>, OpSize;
694 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
695 "push{l}\t$imm", []>;
697 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
698 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
699 Requires<[In32BitMode]>;
704 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
706 def POP64r : I<0x58, AddRegFrm,
707 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
708 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
709 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
711 let mayStore = 1 in {
712 def PUSH64r : I<0x50, AddRegFrm,
713 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
714 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
715 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
719 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
720 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
721 "push{q}\t$imm", []>;
722 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
723 "push{q}\t$imm", []>;
724 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
725 "push{q}\t$imm", []>;
728 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
729 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
730 Requires<[In64BitMode]>;
731 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
732 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
733 Requires<[In64BitMode]>;
737 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
738 mayLoad=1, neverHasSideEffects=1 in {
739 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
740 Requires<[In32BitMode]>;
742 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
743 mayStore=1, neverHasSideEffects=1 in {
744 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
745 Requires<[In32BitMode]>;
748 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
749 def BSWAP32r : I<0xC8, AddRegFrm,
750 (outs GR32:$dst), (ins GR32:$src),
752 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
754 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
756 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
757 } // Constraints = "$src = $dst"
759 // Bit scan instructions.
760 let Defs = [EFLAGS] in {
761 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
762 "bsf{w}\t{$src, $dst|$dst, $src}",
763 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
764 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
765 "bsf{w}\t{$src, $dst|$dst, $src}",
766 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
768 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
769 "bsf{l}\t{$src, $dst|$dst, $src}",
770 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
771 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
772 "bsf{l}\t{$src, $dst|$dst, $src}",
773 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
774 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
775 "bsf{q}\t{$src, $dst|$dst, $src}",
776 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
777 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
778 "bsf{q}\t{$src, $dst|$dst, $src}",
779 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
781 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
782 "bsr{w}\t{$src, $dst|$dst, $src}",
783 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
784 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
785 "bsr{w}\t{$src, $dst|$dst, $src}",
786 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
788 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
789 "bsr{l}\t{$src, $dst|$dst, $src}",
790 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
791 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
792 "bsr{l}\t{$src, $dst|$dst, $src}",
793 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
794 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
795 "bsr{q}\t{$src, $dst|$dst, $src}",
796 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
797 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
798 "bsr{q}\t{$src, $dst|$dst, $src}",
799 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
803 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
804 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
805 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
806 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
807 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
808 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
811 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
812 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
813 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
814 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
815 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
816 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
817 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
818 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
819 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
821 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
822 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
823 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
824 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
826 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
827 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
828 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
829 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
832 //===----------------------------------------------------------------------===//
833 // Move Instructions.
836 let neverHasSideEffects = 1 in {
837 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
838 "mov{b}\t{$src, $dst|$dst, $src}", []>;
839 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
840 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
841 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
842 "mov{l}\t{$src, $dst|$dst, $src}", []>;
843 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
844 "mov{q}\t{$src, $dst|$dst, $src}", []>;
846 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
847 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
848 "mov{b}\t{$src, $dst|$dst, $src}",
849 [(set GR8:$dst, imm:$src)]>;
850 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
851 "mov{w}\t{$src, $dst|$dst, $src}",
852 [(set GR16:$dst, imm:$src)]>, OpSize;
853 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
854 "mov{l}\t{$src, $dst|$dst, $src}",
855 [(set GR32:$dst, imm:$src)]>;
856 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
857 "movabs{q}\t{$src, $dst|$dst, $src}",
858 [(set GR64:$dst, imm:$src)]>;
859 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
860 "mov{q}\t{$src, $dst|$dst, $src}",
861 [(set GR64:$dst, i64immSExt32:$src)]>;
864 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
865 "mov{b}\t{$src, $dst|$dst, $src}",
866 [(store (i8 imm:$src), addr:$dst)]>;
867 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
868 "mov{w}\t{$src, $dst|$dst, $src}",
869 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
870 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
871 "mov{l}\t{$src, $dst|$dst, $src}",
872 [(store (i32 imm:$src), addr:$dst)]>;
873 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
874 "mov{q}\t{$src, $dst|$dst, $src}",
875 [(store i64immSExt32:$src, addr:$dst)]>;
877 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
878 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
879 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
880 "mov{b}\t{$src, %al|%al, $src}", []>,
881 Requires<[In32BitMode]>;
882 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
883 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
884 Requires<[In32BitMode]>;
885 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
886 "mov{l}\t{$src, %eax|%eax, $src}", []>,
887 Requires<[In32BitMode]>;
888 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
889 "mov{b}\t{%al, $dst|$dst, %al}", []>,
890 Requires<[In32BitMode]>;
891 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
892 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
893 Requires<[In32BitMode]>;
894 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
895 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
896 Requires<[In32BitMode]>;
898 // FIXME: These definitions are utterly broken
899 // Just leave them commented out for now because they're useless outside
900 // of the large code model, and most compilers won't generate the instructions
903 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
904 "mov{q}\t{$src, %rax|%rax, $src}", []>;
905 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
906 "mov{q}\t{$src, %rax|%rax, $src}", []>;
907 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
908 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
909 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
910 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
914 let isCodeGenOnly = 1 in {
915 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
916 "mov{b}\t{$src, $dst|$dst, $src}", []>;
917 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
918 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
919 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
920 "mov{l}\t{$src, $dst|$dst, $src}", []>;
921 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
922 "mov{q}\t{$src, $dst|$dst, $src}", []>;
925 let canFoldAsLoad = 1, isReMaterializable = 1 in {
926 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
927 "mov{b}\t{$src, $dst|$dst, $src}",
928 [(set GR8:$dst, (loadi8 addr:$src))]>;
929 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
930 "mov{w}\t{$src, $dst|$dst, $src}",
931 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
932 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
933 "mov{l}\t{$src, $dst|$dst, $src}",
934 [(set GR32:$dst, (loadi32 addr:$src))]>;
935 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
936 "mov{q}\t{$src, $dst|$dst, $src}",
937 [(set GR64:$dst, (load addr:$src))]>;
940 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
941 "mov{b}\t{$src, $dst|$dst, $src}",
942 [(store GR8:$src, addr:$dst)]>;
943 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
944 "mov{w}\t{$src, $dst|$dst, $src}",
945 [(store GR16:$src, addr:$dst)]>, OpSize;
946 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
947 "mov{l}\t{$src, $dst|$dst, $src}",
948 [(store GR32:$src, addr:$dst)]>;
949 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
950 "mov{q}\t{$src, $dst|$dst, $src}",
951 [(store GR64:$src, addr:$dst)]>;
953 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
954 // that they can be used for copying and storing h registers, which can't be
955 // encoded when a REX prefix is present.
956 let isCodeGenOnly = 1 in {
957 let neverHasSideEffects = 1 in
958 def MOV8rr_NOREX : I<0x88, MRMDestReg,
959 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
960 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
962 def MOV8mr_NOREX : I<0x88, MRMDestMem,
963 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
964 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
966 canFoldAsLoad = 1, isReMaterializable = 1 in
967 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
968 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
969 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
973 // Condition code ops, incl. set if equal/not equal/...
974 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
975 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
976 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
977 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
980 //===----------------------------------------------------------------------===//
981 // Bit tests instructions: BT, BTS, BTR, BTC.
983 let Defs = [EFLAGS] in {
984 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
985 "bt{w}\t{$src2, $src1|$src1, $src2}",
986 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
987 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
988 "bt{l}\t{$src2, $src1|$src1, $src2}",
989 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
990 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
991 "bt{q}\t{$src2, $src1|$src1, $src2}",
992 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
994 // Unlike with the register+register form, the memory+register form of the
995 // bt instruction does not ignore the high bits of the index. From ISel's
996 // perspective, this is pretty bizarre. Make these instructions disassembly
999 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1000 "bt{w}\t{$src2, $src1|$src1, $src2}",
1001 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1002 // (implicit EFLAGS)]
1004 >, OpSize, TB, Requires<[FastBTMem]>;
1005 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1006 "bt{l}\t{$src2, $src1|$src1, $src2}",
1007 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1008 // (implicit EFLAGS)]
1010 >, TB, Requires<[FastBTMem]>;
1011 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1012 "bt{q}\t{$src2, $src1|$src1, $src2}",
1013 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1014 // (implicit EFLAGS)]
1018 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1019 "bt{w}\t{$src2, $src1|$src1, $src2}",
1020 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
1022 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1023 "bt{l}\t{$src2, $src1|$src1, $src2}",
1024 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
1025 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1026 "bt{q}\t{$src2, $src1|$src1, $src2}",
1027 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1029 // Note that these instructions don't need FastBTMem because that
1030 // only applies when the other operand is in a register. When it's
1031 // an immediate, bt is still fast.
1032 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1033 "bt{w}\t{$src2, $src1|$src1, $src2}",
1034 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1036 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1037 "bt{l}\t{$src2, $src1|$src1, $src2}",
1038 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1040 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1041 "bt{q}\t{$src2, $src1|$src1, $src2}",
1042 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1043 i64immSExt8:$src2))]>, TB;
1046 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1047 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1048 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1049 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1050 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1051 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1052 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1053 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1054 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1055 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1056 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1057 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1058 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1059 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1060 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1061 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1062 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1063 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1064 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1065 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1066 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1067 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1068 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1069 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1071 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1072 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1073 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1074 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1075 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1076 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1077 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1078 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1079 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1080 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1081 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1082 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1083 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1084 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1085 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1086 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1087 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1088 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1089 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1090 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1091 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1092 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1093 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1094 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1096 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1097 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1098 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1099 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1100 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1101 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1102 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1103 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1104 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1105 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1106 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1107 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1108 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1109 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1110 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1111 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1112 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1113 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1114 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1115 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1116 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1117 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1118 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1119 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1120 } // Defs = [EFLAGS]
1123 //===----------------------------------------------------------------------===//
1128 // Atomic swap. These are just normal xchg instructions. But since a memory
1129 // operand is referenced, the atomicity is ensured.
1130 let Constraints = "$val = $dst" in {
1131 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1132 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1133 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1134 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1135 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1136 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1138 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1139 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1140 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1141 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1142 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1143 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1145 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1146 "xchg{b}\t{$val, $src|$src, $val}", []>;
1147 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1148 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1149 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1150 "xchg{l}\t{$val, $src|$src, $val}", []>;
1151 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1152 "xchg{q}\t{$val, $src|$src, $val}", []>;
1155 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1156 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1157 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1158 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
1159 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1160 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1164 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1165 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1166 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1167 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1168 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1169 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1170 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1171 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1173 let mayLoad = 1, mayStore = 1 in {
1174 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1175 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1176 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1177 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1178 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1179 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1180 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1181 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1185 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1186 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1187 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1188 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1189 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1190 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1191 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1192 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1194 let mayLoad = 1, mayStore = 1 in {
1195 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1196 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1197 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1198 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1199 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1200 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1201 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1202 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1205 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1206 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1207 "cmpxchg8b\t$dst", []>, TB;
1209 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1210 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1211 "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>;
1215 // Lock instruction prefix
1216 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1218 // Rex64 instruction prefix
1219 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1221 // Data16 instruction prefix
1222 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1224 // Repeat string operation instruction prefixes
1225 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1226 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1227 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1228 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1229 // Repeat while not equal (used with CMPS and SCAS)
1230 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1234 // String manipulation instructions
1235 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1236 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1237 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1238 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1240 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1241 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1242 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1245 // Flag instructions
1246 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1247 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1248 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1249 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1250 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1251 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1252 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1254 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1256 // Table lookup instructions
1257 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1259 // ASCII Adjust After Addition
1260 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1261 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1263 // ASCII Adjust AX Before Division
1264 // sets AL, AH and EFLAGS and uses AL and AH
1265 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1266 "aad\t$src", []>, Requires<[In32BitMode]>;
1268 // ASCII Adjust AX After Multiply
1269 // sets AL, AH and EFLAGS and uses AL
1270 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1271 "aam\t$src", []>, Requires<[In32BitMode]>;
1273 // ASCII Adjust AL After Subtraction - sets
1274 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1275 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1277 // Decimal Adjust AL after Addition
1278 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1279 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1281 // Decimal Adjust AL after Subtraction
1282 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1283 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1285 // Check Array Index Against Bounds
1286 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1287 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1288 Requires<[In32BitMode]>;
1289 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1290 "bound\t{$src, $dst|$dst, $src}", []>,
1291 Requires<[In32BitMode]>;
1293 // Adjust RPL Field of Segment Selector
1294 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1295 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1296 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1297 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1299 //===----------------------------------------------------------------------===//
1301 //===----------------------------------------------------------------------===//
1303 include "X86InstrArithmetic.td"
1304 include "X86InstrCMovSetCC.td"
1305 include "X86InstrExtension.td"
1306 include "X86InstrControl.td"
1307 include "X86InstrShiftRotate.td"
1309 // X87 Floating Point Stack.
1310 include "X86InstrFPStack.td"
1312 // SIMD support (SSE, MMX and AVX)
1313 include "X86InstrFragmentsSIMD.td"
1315 // FMA - Fused Multiply-Add support (requires FMA)
1316 include "X86InstrFMA.td"
1318 // SSE, MMX and 3DNow! vector support.
1319 include "X86InstrSSE.td"
1320 include "X86InstrMMX.td"
1321 include "X86Instr3DNow.td"
1323 include "X86InstrVMX.td"
1325 // System instructions.
1326 include "X86InstrSystem.td"
1328 // Compiler Pseudo Instructions and Pat Patterns
1329 include "X86InstrCompiler.td"
1331 //===----------------------------------------------------------------------===//
1332 // Assembler Mnemonic Aliases
1333 //===----------------------------------------------------------------------===//
1335 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1336 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1338 def : MnemonicAlias<"cbw", "cbtw">;
1339 def : MnemonicAlias<"cwd", "cwtd">;
1340 def : MnemonicAlias<"cdq", "cltd">;
1341 def : MnemonicAlias<"cwde", "cwtl">;
1342 def : MnemonicAlias<"cdqe", "cltq">;
1344 // lret maps to lretl, it is not ambiguous with lretq.
1345 def : MnemonicAlias<"lret", "lretl">;
1347 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1348 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1350 def : MnemonicAlias<"loopz", "loope">;
1351 def : MnemonicAlias<"loopnz", "loopne">;
1353 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1354 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1355 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1356 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1357 def : MnemonicAlias<"popfd", "popfl">;
1359 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1360 // all modes. However: "push (addr)" and "push $42" should default to
1361 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1362 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1363 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1364 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1365 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1366 def : MnemonicAlias<"pushfd", "pushfl">;
1368 def : MnemonicAlias<"repe", "rep">;
1369 def : MnemonicAlias<"repz", "rep">;
1370 def : MnemonicAlias<"repnz", "repne">;
1372 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1373 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1375 def : MnemonicAlias<"salb", "shlb">;
1376 def : MnemonicAlias<"salw", "shlw">;
1377 def : MnemonicAlias<"sall", "shll">;
1378 def : MnemonicAlias<"salq", "shlq">;
1380 def : MnemonicAlias<"smovb", "movsb">;
1381 def : MnemonicAlias<"smovw", "movsw">;
1382 def : MnemonicAlias<"smovl", "movsl">;
1383 def : MnemonicAlias<"smovq", "movsq">;
1385 def : MnemonicAlias<"ud2a", "ud2">;
1386 def : MnemonicAlias<"verrw", "verr">;
1388 // System instruction aliases.
1389 def : MnemonicAlias<"iret", "iretl">;
1390 def : MnemonicAlias<"sysret", "sysretl">;
1392 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1393 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1394 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1395 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1396 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1397 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1398 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1399 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1402 // Floating point stack aliases.
1403 def : MnemonicAlias<"fcmovz", "fcmove">;
1404 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1405 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1406 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1407 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1408 def : MnemonicAlias<"fcomip", "fcompi">;
1409 def : MnemonicAlias<"fildq", "fildll">;
1410 def : MnemonicAlias<"fldcww", "fldcw">;
1411 def : MnemonicAlias<"fnstcww", "fnstcw">;
1412 def : MnemonicAlias<"fnstsww", "fnstsw">;
1413 def : MnemonicAlias<"fucomip", "fucompi">;
1414 def : MnemonicAlias<"fwait", "wait">;
1417 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1418 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1419 !strconcat(Prefix, NewCond, Suffix)>;
1421 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1422 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1423 /// example "setz" -> "sete".
1424 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1425 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1426 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1427 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1428 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1429 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1430 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1431 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1432 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1433 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1434 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1436 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1437 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1438 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1439 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1442 // Aliases for set<CC>
1443 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1444 // Aliases for j<CC>
1445 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1446 // Aliases for cmov<CC>{w,l,q}
1447 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1448 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1449 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1452 //===----------------------------------------------------------------------===//
1453 // Assembler Instruction Aliases
1454 //===----------------------------------------------------------------------===//
1456 // aad/aam default to base 10 if no operand is specified.
1457 def : InstAlias<"aad", (AAD8i8 10)>;
1458 def : InstAlias<"aam", (AAM8i8 10)>;
1460 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1461 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1464 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1465 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1466 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1467 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1469 // div and idiv aliases for explicit A register.
1470 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1471 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1472 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1473 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1474 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1475 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1476 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1477 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1478 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1479 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1480 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1481 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1482 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1483 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1484 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1485 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1489 // Various unary fpstack operations default to operating on on ST1.
1490 // For example, "fxch" -> "fxch %st(1)"
1491 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1492 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1493 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1494 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1495 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1496 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1497 def : InstAlias<"fxch", (XCH_F ST1)>;
1498 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1499 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1500 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1501 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1502 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1503 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1505 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1506 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1507 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1509 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1510 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1511 (Inst RST:$op), EmitAlias>;
1512 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1513 (Inst ST0), EmitAlias>;
1516 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1517 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1518 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1519 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1520 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1521 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1522 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1523 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1524 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1525 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1526 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1527 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1528 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1529 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1530 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1531 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1534 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1535 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1536 // solely because gas supports it.
1537 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1538 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1539 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1540 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1541 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1542 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1544 // We accept "fnstsw %eax" even though it only writes %ax.
1545 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1546 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1547 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1549 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1550 // this is compatible with what GAS does.
1551 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1552 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1553 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1554 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1556 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1557 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1558 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1559 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1560 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1561 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1562 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1564 // inb %dx -> inb %al, %dx
1565 def : InstAlias<"inb %dx", (IN8rr)>;
1566 def : InstAlias<"inw %dx", (IN16rr)>;
1567 def : InstAlias<"inl %dx", (IN32rr)>;
1568 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1569 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1570 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1573 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1574 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1575 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1576 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1577 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1578 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1579 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1581 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1582 // the move. All segment/mem forms are equivalent, this has the shortest
1584 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1585 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1587 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1588 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1590 // Match 'movq GR64, MMX' as an alias for movd.
1591 def : InstAlias<"movq $src, $dst",
1592 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1593 def : InstAlias<"movq $src, $dst",
1594 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1596 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1597 // alias for movsl. (as in rep; movsd)
1598 def : InstAlias<"movsd", (MOVSD)>;
1601 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1602 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1603 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1604 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1605 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1606 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1607 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1610 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1611 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1612 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1613 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1614 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1615 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1616 // Note: No GR32->GR64 movzx form.
1618 // outb %dx -> outb %al, %dx
1619 def : InstAlias<"outb %dx", (OUT8rr)>;
1620 def : InstAlias<"outw %dx", (OUT16rr)>;
1621 def : InstAlias<"outl %dx", (OUT32rr)>;
1622 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1623 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1624 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1626 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1627 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1628 // errors, since its encoding is the most compact.
1629 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1631 // shld/shrd op,op -> shld op, op, 1
1632 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1633 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1634 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1635 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1636 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1637 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1639 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1640 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1641 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1642 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1643 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1644 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1646 /* FIXME: This is disabled because the asm matcher is currently incapable of
1647 * matching a fixed immediate like $1.
1648 // "shl X, $1" is an alias for "shl X".
1649 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1650 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1651 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1652 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1653 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1654 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1655 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1656 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1657 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1658 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1659 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1660 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1661 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1662 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1663 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1664 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1665 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1668 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1669 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1670 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1671 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1674 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1675 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1676 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1677 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1678 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1680 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1681 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1682 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1683 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1684 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;