1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
40 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
42 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
44 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
45 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
48 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
50 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
52 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
54 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
56 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
58 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
62 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
64 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
65 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
66 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
67 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
69 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
71 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
72 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
74 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
76 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
77 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
79 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
83 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
84 [SDNPHasChain, SDNPOptInFlag]>;
86 def X86callseq_start :
87 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
88 [SDNPHasChain, SDNPOutFlag]>;
90 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
91 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
93 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
94 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
96 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
97 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
99 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
100 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
101 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
102 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
105 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
106 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
108 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
109 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
111 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
112 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
113 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
115 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
118 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 //===----------------------------------------------------------------------===//
122 // X86 Operand Definitions.
125 // *mem - Operand definitions for the funky X86 addressing mode operands.
127 class X86MemOperand<string printMethod> : Operand<iPTR> {
128 let PrintMethod = printMethod;
129 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
132 def i8mem : X86MemOperand<"printi8mem">;
133 def i16mem : X86MemOperand<"printi16mem">;
134 def i32mem : X86MemOperand<"printi32mem">;
135 def i64mem : X86MemOperand<"printi64mem">;
136 def i128mem : X86MemOperand<"printi128mem">;
137 def f32mem : X86MemOperand<"printf32mem">;
138 def f64mem : X86MemOperand<"printf64mem">;
139 def f80mem : X86MemOperand<"printf80mem">;
140 def f128mem : X86MemOperand<"printf128mem">;
142 def lea32mem : Operand<i32> {
143 let PrintMethod = "printi32mem";
144 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
147 def SSECC : Operand<i8> {
148 let PrintMethod = "printSSECC";
151 def piclabel: Operand<i32> {
152 let PrintMethod = "printPICLabel";
155 // A couple of more descriptive operand definitions.
156 // 16-bits but only 8 bits are significant.
157 def i16i8imm : Operand<i16>;
158 // 32-bits but only 8 bits are significant.
159 def i32i8imm : Operand<i32>;
161 // Branch targets have OtherVT type.
162 def brtarget : Operand<OtherVT>;
164 //===----------------------------------------------------------------------===//
165 // X86 Complex Pattern Definitions.
168 // Define X86 specific addressing mode.
169 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
170 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
171 [add, mul, shl, or, frameindex], []>;
173 //===----------------------------------------------------------------------===//
174 // X86 Instruction Predicate Definitions.
175 def HasMMX : Predicate<"Subtarget->hasMMX()">;
176 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
177 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
178 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
179 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
180 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
181 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
182 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
183 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
184 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
185 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
186 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
187 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
188 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
190 //===----------------------------------------------------------------------===//
191 // X86 Instruction Format Definitions.
194 include "X86InstrFormats.td"
196 //===----------------------------------------------------------------------===//
197 // Pattern fragments...
200 // X86 specific condition code. These correspond to CondCode in
201 // X86InstrInfo.h. They must be kept in synch.
202 def X86_COND_A : PatLeaf<(i8 0)>;
203 def X86_COND_AE : PatLeaf<(i8 1)>;
204 def X86_COND_B : PatLeaf<(i8 2)>;
205 def X86_COND_BE : PatLeaf<(i8 3)>;
206 def X86_COND_E : PatLeaf<(i8 4)>;
207 def X86_COND_G : PatLeaf<(i8 5)>;
208 def X86_COND_GE : PatLeaf<(i8 6)>;
209 def X86_COND_L : PatLeaf<(i8 7)>;
210 def X86_COND_LE : PatLeaf<(i8 8)>;
211 def X86_COND_NE : PatLeaf<(i8 9)>;
212 def X86_COND_NO : PatLeaf<(i8 10)>;
213 def X86_COND_NP : PatLeaf<(i8 11)>;
214 def X86_COND_NS : PatLeaf<(i8 12)>;
215 def X86_COND_O : PatLeaf<(i8 13)>;
216 def X86_COND_P : PatLeaf<(i8 14)>;
217 def X86_COND_S : PatLeaf<(i8 15)>;
219 def i16immSExt8 : PatLeaf<(i16 imm), [{
220 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
221 // sign extended field.
222 return (int16_t)N->getValue() == (int8_t)N->getValue();
225 def i32immSExt8 : PatLeaf<(i32 imm), [{
226 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
227 // sign extended field.
228 return (int32_t)N->getValue() == (int8_t)N->getValue();
231 // Helper fragments for loads.
232 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
233 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
234 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
235 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
237 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
238 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
239 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
241 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
242 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
243 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
245 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
246 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
247 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
248 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
249 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
250 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
252 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
253 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
254 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
255 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
256 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
257 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
260 // An 'and' node with a single use.
261 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
262 return N->hasOneUse();
265 //===----------------------------------------------------------------------===//
266 // Instruction list...
269 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
270 // a stack adjustment and the codegen must know that they may modify the stack
271 // pointer before prolog-epilog rewriting occurs.
272 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
273 // which can clobber EFLAGS.
274 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
275 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
277 [(X86callseq_start imm:$amt)]>;
278 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
280 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
282 let isImplicitDef = 1 in {
283 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
284 "#IMPLICIT_DEF $dst",
285 [(set GR8:$dst, (undef))]>;
286 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
287 "#IMPLICIT_DEF $dst",
288 [(set GR16:$dst, (undef))]>;
289 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
290 "#IMPLICIT_DEF $dst",
291 [(set GR32:$dst, (undef))]>;
295 let neverHasSideEffects = 1 in
296 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
299 let neverHasSideEffects = 1, isNotDuplicable = 1 in
300 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
301 "call\t$label\n\tpop{l}\t$reg", []>;
303 //===----------------------------------------------------------------------===//
304 // Control Flow Instructions...
307 // Return instructions.
308 let isTerminator = 1, isReturn = 1, isBarrier = 1,
310 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
311 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
312 [(X86retflag imm:$amt)]>;
315 // All branches are RawFrm, Void, Branch, and Terminators
316 let isBranch = 1, isTerminator = 1 in
317 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
318 I<opcode, RawFrm, (outs), ins, asm, pattern>;
320 let isBranch = 1, isBarrier = 1 in
321 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
324 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
325 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
326 [(brind GR32:$dst)]>;
327 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
328 [(brind (loadi32 addr:$dst))]>;
331 // Conditional branches
332 let Uses = [EFLAGS] in {
333 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
334 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
335 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
336 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
337 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
338 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
339 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
340 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
341 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
342 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
343 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
344 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
346 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
347 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
348 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
349 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
350 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
351 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
352 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
353 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
355 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
356 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
357 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
358 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
359 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
360 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
361 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
362 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
363 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
364 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
365 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
366 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
369 //===----------------------------------------------------------------------===//
370 // Call Instructions...
373 // All calls clobber the non-callee saved registers...
374 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
375 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
376 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
377 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
378 "call\t${dst:call}", []>;
379 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
380 "call\t{*}$dst", [(X86call GR32:$dst)]>;
381 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
382 "call\t{*}$dst", []>;
387 def TAILCALL : I<0, Pseudo, (outs), (ins ),
391 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
392 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset),
393 "#TC_RETURN $dst $offset",
396 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
397 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset),
398 "#TC_RETURN $dst $offset",
401 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
402 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
404 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
405 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
407 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
408 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
409 "jmp\t{*}$dst # TAILCALL", []>;
411 //===----------------------------------------------------------------------===//
412 // Miscellaneous Instructions...
414 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
415 def LEAVE : I<0xC9, RawFrm,
416 (outs), (ins), "leave", []>;
418 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
420 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
423 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
426 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
427 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
428 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
429 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
431 let isTwoAddress = 1 in // GR32 = bswap GR32
432 def BSWAP32r : I<0xC8, AddRegFrm,
433 (outs GR32:$dst), (ins GR32:$src),
435 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
438 // Bit scan instructions.
439 let Defs = [EFLAGS] in {
440 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
441 "bsf{w}\t{$src, $dst|$dst, $src}",
442 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
443 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
444 "bsf{w}\t{$src, $dst|$dst, $src}",
445 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
446 (implicit EFLAGS)]>, TB;
447 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
448 "bsf{l}\t{$src, $dst|$dst, $src}",
449 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
450 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
451 "bsf{l}\t{$src, $dst|$dst, $src}",
452 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
453 (implicit EFLAGS)]>, TB;
455 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
456 "bsr{w}\t{$src, $dst|$dst, $src}",
457 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
458 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
459 "bsr{w}\t{$src, $dst|$dst, $src}",
460 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
461 (implicit EFLAGS)]>, TB;
462 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
463 "bsr{l}\t{$src, $dst|$dst, $src}",
464 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
465 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
466 "bsr{l}\t{$src, $dst|$dst, $src}",
467 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
468 (implicit EFLAGS)]>, TB;
471 let neverHasSideEffects = 1 in
472 def LEA16r : I<0x8D, MRMSrcMem,
473 (outs GR16:$dst), (ins i32mem:$src),
474 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
475 def LEA32r : I<0x8D, MRMSrcMem,
476 (outs GR32:$dst), (ins lea32mem:$src),
477 "lea{l}\t{$src|$dst}, {$dst|$src}",
478 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
480 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
481 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
482 [(X86rep_movs i8)]>, REP;
483 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
484 [(X86rep_movs i16)]>, REP, OpSize;
485 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
486 [(X86rep_movs i32)]>, REP;
489 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
490 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
491 [(X86rep_stos i8)]>, REP;
492 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
493 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
494 [(X86rep_stos i16)]>, REP, OpSize;
495 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
496 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
497 [(X86rep_stos i32)]>, REP;
499 let Defs = [RAX, RDX] in
500 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
503 let isBarrier = 1, hasCtrlDep = 1 in {
504 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
507 //===----------------------------------------------------------------------===//
508 // Input/Output Instructions...
510 let Defs = [AL], Uses = [DX] in
511 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
512 "in{b}\t{%dx, %al|%AL, %DX}", []>;
513 let Defs = [AX], Uses = [DX] in
514 def IN16rr : I<0xED, RawFrm, (outs), (ins),
515 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
516 let Defs = [EAX], Uses = [DX] in
517 def IN32rr : I<0xED, RawFrm, (outs), (ins),
518 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
521 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
522 "in{b}\t{$port, %al|%AL, $port}", []>;
524 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
525 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
527 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
528 "in{l}\t{$port, %eax|%EAX, $port}", []>;
530 let Uses = [DX, AL] in
531 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
532 "out{b}\t{%al, %dx|%DX, %AL}", []>;
533 let Uses = [DX, AX] in
534 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
535 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
536 let Uses = [DX, EAX] in
537 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
538 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
541 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
542 "out{b}\t{%al, $port|$port, %AL}", []>;
544 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
545 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
547 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
548 "out{l}\t{%eax, $port|$port, %EAX}", []>;
550 //===----------------------------------------------------------------------===//
551 // Move Instructions...
553 let neverHasSideEffects = 1 in {
554 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
555 "mov{b}\t{$src, $dst|$dst, $src}", []>;
556 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
557 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
558 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
559 "mov{l}\t{$src, $dst|$dst, $src}", []>;
561 let isReMaterializable = 1 in {
562 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
563 "mov{b}\t{$src, $dst|$dst, $src}",
564 [(set GR8:$dst, imm:$src)]>;
565 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
566 "mov{w}\t{$src, $dst|$dst, $src}",
567 [(set GR16:$dst, imm:$src)]>, OpSize;
568 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
569 "mov{l}\t{$src, $dst|$dst, $src}",
570 [(set GR32:$dst, imm:$src)]>;
572 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
573 "mov{b}\t{$src, $dst|$dst, $src}",
574 [(store (i8 imm:$src), addr:$dst)]>;
575 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
576 "mov{w}\t{$src, $dst|$dst, $src}",
577 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
578 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
579 "mov{l}\t{$src, $dst|$dst, $src}",
580 [(store (i32 imm:$src), addr:$dst)]>;
582 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
583 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
584 "mov{b}\t{$src, $dst|$dst, $src}",
585 [(set GR8:$dst, (load addr:$src))]>;
586 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
587 "mov{w}\t{$src, $dst|$dst, $src}",
588 [(set GR16:$dst, (load addr:$src))]>, OpSize;
589 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
590 "mov{l}\t{$src, $dst|$dst, $src}",
591 [(set GR32:$dst, (load addr:$src))]>;
594 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
595 "mov{b}\t{$src, $dst|$dst, $src}",
596 [(store GR8:$src, addr:$dst)]>;
597 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
598 "mov{w}\t{$src, $dst|$dst, $src}",
599 [(store GR16:$src, addr:$dst)]>, OpSize;
600 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
601 "mov{l}\t{$src, $dst|$dst, $src}",
602 [(store GR32:$src, addr:$dst)]>;
604 //===----------------------------------------------------------------------===//
605 // Fixed-Register Multiplication and Division Instructions...
608 // Extra precision multiplication
609 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
610 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
611 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
612 // This probably ought to be moved to a def : Pat<> if the
613 // syntax can be accepted.
614 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
615 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
616 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
617 OpSize; // AX,DX = AX*GR16
618 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
619 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
620 // EAX,EDX = EAX*GR32
621 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
622 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
624 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
625 // This probably ought to be moved to a def : Pat<> if the
626 // syntax can be accepted.
627 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
628 let mayLoad = 1, neverHasSideEffects = 1 in {
629 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
630 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
631 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
632 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
633 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
634 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
637 let neverHasSideEffects = 1 in {
638 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
639 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
641 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
642 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
643 OpSize; // AX,DX = AX*GR16
644 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
645 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
646 // EAX,EDX = EAX*GR32
648 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
649 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
650 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
651 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
652 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
653 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
654 let Defs = [EAX,EDX], Uses = [EAX] in
655 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
656 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
659 // unsigned division/remainder
660 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
661 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
663 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
664 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
665 "div{w}\t$src", []>, OpSize;
666 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
667 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
670 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
671 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
673 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
674 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
675 "div{w}\t$src", []>, OpSize;
676 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
677 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
681 // Signed division/remainder.
682 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
683 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
684 "idiv{b}\t$src", []>;
685 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
686 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
687 "idiv{w}\t$src", []>, OpSize;
688 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
689 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
690 "idiv{l}\t$src", []>;
691 let mayLoad = 1, mayLoad = 1 in {
692 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
693 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
694 "idiv{b}\t$src", []>;
695 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
696 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
697 "idiv{w}\t$src", []>, OpSize;
698 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
699 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
700 "idiv{l}\t$src", []>;
702 } // neverHasSideEffects
704 //===----------------------------------------------------------------------===//
705 // Two address Instructions.
707 let isTwoAddress = 1 in {
710 let Uses = [EFLAGS] in {
711 let isCommutable = 1 in {
712 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
713 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
714 "cmovb\t{$src2, $dst|$dst, $src2}",
715 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
716 X86_COND_B, EFLAGS))]>,
718 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
719 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
720 "cmovb\t{$src2, $dst|$dst, $src2}",
721 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
722 X86_COND_B, EFLAGS))]>,
725 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
726 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
727 "cmovae\t{$src2, $dst|$dst, $src2}",
728 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
729 X86_COND_AE, EFLAGS))]>,
731 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
732 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
733 "cmovae\t{$src2, $dst|$dst, $src2}",
734 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
735 X86_COND_AE, EFLAGS))]>,
737 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
738 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
739 "cmove\t{$src2, $dst|$dst, $src2}",
740 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
741 X86_COND_E, EFLAGS))]>,
743 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
744 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
745 "cmove\t{$src2, $dst|$dst, $src2}",
746 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
747 X86_COND_E, EFLAGS))]>,
749 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
750 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
751 "cmovne\t{$src2, $dst|$dst, $src2}",
752 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
753 X86_COND_NE, EFLAGS))]>,
755 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
756 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
757 "cmovne\t{$src2, $dst|$dst, $src2}",
758 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
759 X86_COND_NE, EFLAGS))]>,
761 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
762 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
763 "cmovbe\t{$src2, $dst|$dst, $src2}",
764 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
765 X86_COND_BE, EFLAGS))]>,
767 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
768 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
769 "cmovbe\t{$src2, $dst|$dst, $src2}",
770 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
771 X86_COND_BE, EFLAGS))]>,
773 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
774 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
775 "cmova\t{$src2, $dst|$dst, $src2}",
776 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
777 X86_COND_A, EFLAGS))]>,
779 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
780 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
781 "cmova\t{$src2, $dst|$dst, $src2}",
782 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
783 X86_COND_A, EFLAGS))]>,
785 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
786 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
787 "cmovl\t{$src2, $dst|$dst, $src2}",
788 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
789 X86_COND_L, EFLAGS))]>,
791 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
792 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
793 "cmovl\t{$src2, $dst|$dst, $src2}",
794 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
795 X86_COND_L, EFLAGS))]>,
797 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
798 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
799 "cmovge\t{$src2, $dst|$dst, $src2}",
800 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
801 X86_COND_GE, EFLAGS))]>,
803 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
804 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
805 "cmovge\t{$src2, $dst|$dst, $src2}",
806 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
807 X86_COND_GE, EFLAGS))]>,
809 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
810 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
811 "cmovle\t{$src2, $dst|$dst, $src2}",
812 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
813 X86_COND_LE, EFLAGS))]>,
815 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
816 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
817 "cmovle\t{$src2, $dst|$dst, $src2}",
818 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
819 X86_COND_LE, EFLAGS))]>,
821 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
822 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
823 "cmovg\t{$src2, $dst|$dst, $src2}",
824 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
825 X86_COND_G, EFLAGS))]>,
827 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
828 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
829 "cmovg\t{$src2, $dst|$dst, $src2}",
830 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
831 X86_COND_G, EFLAGS))]>,
833 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
834 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
835 "cmovs\t{$src2, $dst|$dst, $src2}",
836 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
837 X86_COND_S, EFLAGS))]>,
839 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
840 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
841 "cmovs\t{$src2, $dst|$dst, $src2}",
842 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
843 X86_COND_S, EFLAGS))]>,
845 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
846 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
847 "cmovns\t{$src2, $dst|$dst, $src2}",
848 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
849 X86_COND_NS, EFLAGS))]>,
851 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
852 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
853 "cmovns\t{$src2, $dst|$dst, $src2}",
854 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
855 X86_COND_NS, EFLAGS))]>,
857 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
858 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
859 "cmovp\t{$src2, $dst|$dst, $src2}",
860 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
861 X86_COND_P, EFLAGS))]>,
863 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
864 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
865 "cmovp\t{$src2, $dst|$dst, $src2}",
866 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
867 X86_COND_P, EFLAGS))]>,
869 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
870 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
871 "cmovnp\t{$src2, $dst|$dst, $src2}",
872 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
873 X86_COND_NP, EFLAGS))]>,
875 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
876 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
877 "cmovnp\t{$src2, $dst|$dst, $src2}",
878 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
879 X86_COND_NP, EFLAGS))]>,
881 } // isCommutable = 1
883 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
884 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
885 "cmovnp\t{$src2, $dst|$dst, $src2}",
886 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
887 X86_COND_NP, EFLAGS))]>,
890 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
891 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
892 "cmovb\t{$src2, $dst|$dst, $src2}",
893 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
894 X86_COND_B, EFLAGS))]>,
896 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
897 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
898 "cmovb\t{$src2, $dst|$dst, $src2}",
899 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
900 X86_COND_B, EFLAGS))]>,
902 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
903 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
904 "cmovae\t{$src2, $dst|$dst, $src2}",
905 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
906 X86_COND_AE, EFLAGS))]>,
908 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
909 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
910 "cmovae\t{$src2, $dst|$dst, $src2}",
911 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
912 X86_COND_AE, EFLAGS))]>,
914 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
915 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
916 "cmove\t{$src2, $dst|$dst, $src2}",
917 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
918 X86_COND_E, EFLAGS))]>,
920 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
921 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
922 "cmove\t{$src2, $dst|$dst, $src2}",
923 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
924 X86_COND_E, EFLAGS))]>,
926 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
927 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
928 "cmovne\t{$src2, $dst|$dst, $src2}",
929 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
930 X86_COND_NE, EFLAGS))]>,
932 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
933 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
934 "cmovne\t{$src2, $dst|$dst, $src2}",
935 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
936 X86_COND_NE, EFLAGS))]>,
938 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
939 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
940 "cmovbe\t{$src2, $dst|$dst, $src2}",
941 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
942 X86_COND_BE, EFLAGS))]>,
944 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
945 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
946 "cmovbe\t{$src2, $dst|$dst, $src2}",
947 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
948 X86_COND_BE, EFLAGS))]>,
950 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
951 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
952 "cmova\t{$src2, $dst|$dst, $src2}",
953 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
954 X86_COND_A, EFLAGS))]>,
956 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
957 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
958 "cmova\t{$src2, $dst|$dst, $src2}",
959 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
960 X86_COND_A, EFLAGS))]>,
962 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
963 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
964 "cmovl\t{$src2, $dst|$dst, $src2}",
965 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
966 X86_COND_L, EFLAGS))]>,
968 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
969 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
970 "cmovl\t{$src2, $dst|$dst, $src2}",
971 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
972 X86_COND_L, EFLAGS))]>,
974 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
975 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
976 "cmovge\t{$src2, $dst|$dst, $src2}",
977 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
978 X86_COND_GE, EFLAGS))]>,
980 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
981 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
982 "cmovge\t{$src2, $dst|$dst, $src2}",
983 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
984 X86_COND_GE, EFLAGS))]>,
986 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
987 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
988 "cmovle\t{$src2, $dst|$dst, $src2}",
989 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
990 X86_COND_LE, EFLAGS))]>,
992 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
993 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
994 "cmovle\t{$src2, $dst|$dst, $src2}",
995 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
996 X86_COND_LE, EFLAGS))]>,
998 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
999 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1000 "cmovg\t{$src2, $dst|$dst, $src2}",
1001 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1002 X86_COND_G, EFLAGS))]>,
1004 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1005 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1006 "cmovg\t{$src2, $dst|$dst, $src2}",
1007 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1008 X86_COND_G, EFLAGS))]>,
1010 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1011 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1012 "cmovs\t{$src2, $dst|$dst, $src2}",
1013 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1014 X86_COND_S, EFLAGS))]>,
1016 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1017 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1018 "cmovs\t{$src2, $dst|$dst, $src2}",
1019 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1020 X86_COND_S, EFLAGS))]>,
1022 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1023 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1024 "cmovns\t{$src2, $dst|$dst, $src2}",
1025 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1026 X86_COND_NS, EFLAGS))]>,
1028 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1029 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1030 "cmovns\t{$src2, $dst|$dst, $src2}",
1031 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1032 X86_COND_NS, EFLAGS))]>,
1034 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1035 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1036 "cmovp\t{$src2, $dst|$dst, $src2}",
1037 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1038 X86_COND_P, EFLAGS))]>,
1040 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1041 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1042 "cmovp\t{$src2, $dst|$dst, $src2}",
1043 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1044 X86_COND_P, EFLAGS))]>,
1046 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1047 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1048 "cmovnp\t{$src2, $dst|$dst, $src2}",
1049 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1050 X86_COND_NP, EFLAGS))]>,
1052 } // Uses = [EFLAGS]
1055 // unary instructions
1056 let CodeSize = 2 in {
1057 let Defs = [EFLAGS] in {
1058 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1059 [(set GR8:$dst, (ineg GR8:$src))]>;
1060 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1061 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1062 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1063 [(set GR32:$dst, (ineg GR32:$src))]>;
1064 let isTwoAddress = 0 in {
1065 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1066 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1067 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1068 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1069 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1070 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1073 } // Defs = [EFLAGS]
1075 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1076 [(set GR8:$dst, (not GR8:$src))]>;
1077 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1078 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1079 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1080 [(set GR32:$dst, (not GR32:$src))]>;
1081 let isTwoAddress = 0 in {
1082 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1083 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1084 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1085 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1086 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1087 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1091 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1092 let Defs = [EFLAGS] in {
1094 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1095 [(set GR8:$dst, (add GR8:$src, 1))]>;
1096 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1097 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1098 [(set GR16:$dst, (add GR16:$src, 1))]>,
1099 OpSize, Requires<[In32BitMode]>;
1100 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1101 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1103 let isTwoAddress = 0, CodeSize = 2 in {
1104 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1105 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1106 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1107 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1108 OpSize, Requires<[In32BitMode]>;
1109 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1110 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1111 Requires<[In32BitMode]>;
1115 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1116 [(set GR8:$dst, (add GR8:$src, -1))]>;
1117 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1118 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1119 [(set GR16:$dst, (add GR16:$src, -1))]>,
1120 OpSize, Requires<[In32BitMode]>;
1121 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1122 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1125 let isTwoAddress = 0, CodeSize = 2 in {
1126 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1127 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1128 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1129 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1130 OpSize, Requires<[In32BitMode]>;
1131 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1132 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1133 Requires<[In32BitMode]>;
1135 } // Defs = [EFLAGS]
1137 // Logical operators...
1138 let Defs = [EFLAGS] in {
1139 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1140 def AND8rr : I<0x20, MRMDestReg,
1141 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1142 "and{b}\t{$src2, $dst|$dst, $src2}",
1143 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1144 def AND16rr : I<0x21, MRMDestReg,
1145 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1146 "and{w}\t{$src2, $dst|$dst, $src2}",
1147 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1148 def AND32rr : I<0x21, MRMDestReg,
1149 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1150 "and{l}\t{$src2, $dst|$dst, $src2}",
1151 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1154 def AND8rm : I<0x22, MRMSrcMem,
1155 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1156 "and{b}\t{$src2, $dst|$dst, $src2}",
1157 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1158 def AND16rm : I<0x23, MRMSrcMem,
1159 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1160 "and{w}\t{$src2, $dst|$dst, $src2}",
1161 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1162 def AND32rm : I<0x23, MRMSrcMem,
1163 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1164 "and{l}\t{$src2, $dst|$dst, $src2}",
1165 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1167 def AND8ri : Ii8<0x80, MRM4r,
1168 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1169 "and{b}\t{$src2, $dst|$dst, $src2}",
1170 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1171 def AND16ri : Ii16<0x81, MRM4r,
1172 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1173 "and{w}\t{$src2, $dst|$dst, $src2}",
1174 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1175 def AND32ri : Ii32<0x81, MRM4r,
1176 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1177 "and{l}\t{$src2, $dst|$dst, $src2}",
1178 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1179 def AND16ri8 : Ii8<0x83, MRM4r,
1180 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1181 "and{w}\t{$src2, $dst|$dst, $src2}",
1182 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1184 def AND32ri8 : Ii8<0x83, MRM4r,
1185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1186 "and{l}\t{$src2, $dst|$dst, $src2}",
1187 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1189 let isTwoAddress = 0 in {
1190 def AND8mr : I<0x20, MRMDestMem,
1191 (outs), (ins i8mem :$dst, GR8 :$src),
1192 "and{b}\t{$src, $dst|$dst, $src}",
1193 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1194 def AND16mr : I<0x21, MRMDestMem,
1195 (outs), (ins i16mem:$dst, GR16:$src),
1196 "and{w}\t{$src, $dst|$dst, $src}",
1197 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1199 def AND32mr : I<0x21, MRMDestMem,
1200 (outs), (ins i32mem:$dst, GR32:$src),
1201 "and{l}\t{$src, $dst|$dst, $src}",
1202 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1203 def AND8mi : Ii8<0x80, MRM4m,
1204 (outs), (ins i8mem :$dst, i8imm :$src),
1205 "and{b}\t{$src, $dst|$dst, $src}",
1206 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1207 def AND16mi : Ii16<0x81, MRM4m,
1208 (outs), (ins i16mem:$dst, i16imm:$src),
1209 "and{w}\t{$src, $dst|$dst, $src}",
1210 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1212 def AND32mi : Ii32<0x81, MRM4m,
1213 (outs), (ins i32mem:$dst, i32imm:$src),
1214 "and{l}\t{$src, $dst|$dst, $src}",
1215 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1216 def AND16mi8 : Ii8<0x83, MRM4m,
1217 (outs), (ins i16mem:$dst, i16i8imm :$src),
1218 "and{w}\t{$src, $dst|$dst, $src}",
1219 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1221 def AND32mi8 : Ii8<0x83, MRM4m,
1222 (outs), (ins i32mem:$dst, i32i8imm :$src),
1223 "and{l}\t{$src, $dst|$dst, $src}",
1224 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1228 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1229 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1230 "or{b}\t{$src2, $dst|$dst, $src2}",
1231 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1232 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1233 "or{w}\t{$src2, $dst|$dst, $src2}",
1234 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1235 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1236 "or{l}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1239 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1240 "or{b}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1242 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1243 "or{w}\t{$src2, $dst|$dst, $src2}",
1244 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1245 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1246 "or{l}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1249 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1250 "or{b}\t{$src2, $dst|$dst, $src2}",
1251 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1252 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1253 "or{w}\t{$src2, $dst|$dst, $src2}",
1254 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1255 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1256 "or{l}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1259 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1260 "or{w}\t{$src2, $dst|$dst, $src2}",
1261 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1262 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1263 "or{l}\t{$src2, $dst|$dst, $src2}",
1264 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1265 let isTwoAddress = 0 in {
1266 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1267 "or{b}\t{$src, $dst|$dst, $src}",
1268 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1269 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1270 "or{w}\t{$src, $dst|$dst, $src}",
1271 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1272 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1273 "or{l}\t{$src, $dst|$dst, $src}",
1274 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1275 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1276 "or{b}\t{$src, $dst|$dst, $src}",
1277 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1278 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1279 "or{w}\t{$src, $dst|$dst, $src}",
1280 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1282 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1283 "or{l}\t{$src, $dst|$dst, $src}",
1284 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1285 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1286 "or{w}\t{$src, $dst|$dst, $src}",
1287 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1289 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1290 "or{l}\t{$src, $dst|$dst, $src}",
1291 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1295 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1296 def XOR8rr : I<0x30, MRMDestReg,
1297 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1298 "xor{b}\t{$src2, $dst|$dst, $src2}",
1299 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1300 def XOR16rr : I<0x31, MRMDestReg,
1301 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1302 "xor{w}\t{$src2, $dst|$dst, $src2}",
1303 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1304 def XOR32rr : I<0x31, MRMDestReg,
1305 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1306 "xor{l}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1310 def XOR8rm : I<0x32, MRMSrcMem ,
1311 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1312 "xor{b}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1314 def XOR16rm : I<0x33, MRMSrcMem ,
1315 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1316 "xor{w}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1318 def XOR32rm : I<0x33, MRMSrcMem ,
1319 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1320 "xor{l}\t{$src2, $dst|$dst, $src2}",
1321 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1323 def XOR8ri : Ii8<0x80, MRM6r,
1324 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1325 "xor{b}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1327 def XOR16ri : Ii16<0x81, MRM6r,
1328 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1329 "xor{w}\t{$src2, $dst|$dst, $src2}",
1330 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1331 def XOR32ri : Ii32<0x81, MRM6r,
1332 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1333 "xor{l}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1335 def XOR16ri8 : Ii8<0x83, MRM6r,
1336 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1337 "xor{w}\t{$src2, $dst|$dst, $src2}",
1338 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1340 def XOR32ri8 : Ii8<0x83, MRM6r,
1341 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1342 "xor{l}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1344 let isTwoAddress = 0 in {
1345 def XOR8mr : I<0x30, MRMDestMem,
1346 (outs), (ins i8mem :$dst, GR8 :$src),
1347 "xor{b}\t{$src, $dst|$dst, $src}",
1348 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1349 def XOR16mr : I<0x31, MRMDestMem,
1350 (outs), (ins i16mem:$dst, GR16:$src),
1351 "xor{w}\t{$src, $dst|$dst, $src}",
1352 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1354 def XOR32mr : I<0x31, MRMDestMem,
1355 (outs), (ins i32mem:$dst, GR32:$src),
1356 "xor{l}\t{$src, $dst|$dst, $src}",
1357 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1358 def XOR8mi : Ii8<0x80, MRM6m,
1359 (outs), (ins i8mem :$dst, i8imm :$src),
1360 "xor{b}\t{$src, $dst|$dst, $src}",
1361 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1362 def XOR16mi : Ii16<0x81, MRM6m,
1363 (outs), (ins i16mem:$dst, i16imm:$src),
1364 "xor{w}\t{$src, $dst|$dst, $src}",
1365 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1367 def XOR32mi : Ii32<0x81, MRM6m,
1368 (outs), (ins i32mem:$dst, i32imm:$src),
1369 "xor{l}\t{$src, $dst|$dst, $src}",
1370 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1371 def XOR16mi8 : Ii8<0x83, MRM6m,
1372 (outs), (ins i16mem:$dst, i16i8imm :$src),
1373 "xor{w}\t{$src, $dst|$dst, $src}",
1374 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1376 def XOR32mi8 : Ii8<0x83, MRM6m,
1377 (outs), (ins i32mem:$dst, i32i8imm :$src),
1378 "xor{l}\t{$src, $dst|$dst, $src}",
1379 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1381 } // Defs = [EFLAGS]
1383 // Shift instructions
1384 let Defs = [EFLAGS] in {
1385 let Uses = [CL] in {
1386 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1387 "shl{b}\t{%cl, $dst|$dst, %CL}",
1388 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1389 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1390 "shl{w}\t{%cl, $dst|$dst, %CL}",
1391 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1392 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1393 "shl{l}\t{%cl, $dst|$dst, %CL}",
1394 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1397 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1398 "shl{b}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1400 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1401 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1402 "shl{w}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1404 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1405 "shl{l}\t{$src2, $dst|$dst, $src2}",
1406 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1407 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1411 let isTwoAddress = 0 in {
1412 let Uses = [CL] in {
1413 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1414 "shl{b}\t{%cl, $dst|$dst, %CL}",
1415 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1416 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1417 "shl{w}\t{%cl, $dst|$dst, %CL}",
1418 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1419 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1420 "shl{l}\t{%cl, $dst|$dst, %CL}",
1421 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1423 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1424 "shl{b}\t{$src, $dst|$dst, $src}",
1425 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1426 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1427 "shl{w}\t{$src, $dst|$dst, $src}",
1428 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1430 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1431 "shl{l}\t{$src, $dst|$dst, $src}",
1432 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1435 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1437 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1438 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1440 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1442 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1444 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1447 let Uses = [CL] in {
1448 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1449 "shr{b}\t{%cl, $dst|$dst, %CL}",
1450 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1451 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1452 "shr{w}\t{%cl, $dst|$dst, %CL}",
1453 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1454 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1455 "shr{l}\t{%cl, $dst|$dst, %CL}",
1456 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1459 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1460 "shr{b}\t{$src2, $dst|$dst, $src2}",
1461 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1462 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1463 "shr{w}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1465 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1466 "shr{l}\t{$src2, $dst|$dst, $src2}",
1467 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1470 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1472 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1473 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1475 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1476 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1478 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1480 let isTwoAddress = 0 in {
1481 let Uses = [CL] in {
1482 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1483 "shr{b}\t{%cl, $dst|$dst, %CL}",
1484 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1485 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1486 "shr{w}\t{%cl, $dst|$dst, %CL}",
1487 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1489 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1490 "shr{l}\t{%cl, $dst|$dst, %CL}",
1491 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1493 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1494 "shr{b}\t{$src, $dst|$dst, $src}",
1495 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1496 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1497 "shr{w}\t{$src, $dst|$dst, $src}",
1498 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1500 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1501 "shr{l}\t{$src, $dst|$dst, $src}",
1502 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1505 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1507 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1508 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1510 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1511 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1513 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1516 let Uses = [CL] in {
1517 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1518 "sar{b}\t{%cl, $dst|$dst, %CL}",
1519 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1520 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1521 "sar{w}\t{%cl, $dst|$dst, %CL}",
1522 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1523 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1524 "sar{l}\t{%cl, $dst|$dst, %CL}",
1525 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1528 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1529 "sar{b}\t{$src2, $dst|$dst, $src2}",
1530 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1531 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1532 "sar{w}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1535 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1536 "sar{l}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1540 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1542 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1543 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1545 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1546 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1548 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1550 let isTwoAddress = 0 in {
1551 let Uses = [CL] in {
1552 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1553 "sar{b}\t{%cl, $dst|$dst, %CL}",
1554 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1555 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1556 "sar{w}\t{%cl, $dst|$dst, %CL}",
1557 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1558 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1559 "sar{l}\t{%cl, $dst|$dst, %CL}",
1560 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1562 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1563 "sar{b}\t{$src, $dst|$dst, $src}",
1564 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1565 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1566 "sar{w}\t{$src, $dst|$dst, $src}",
1567 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1569 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1570 "sar{l}\t{$src, $dst|$dst, $src}",
1571 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1574 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1576 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1577 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1579 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1581 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1583 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1586 // Rotate instructions
1587 // FIXME: provide shorter instructions when imm8 == 1
1588 let Uses = [CL] in {
1589 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1590 "rol{b}\t{%cl, $dst|$dst, %CL}",
1591 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1592 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1593 "rol{w}\t{%cl, $dst|$dst, %CL}",
1594 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1595 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1596 "rol{l}\t{%cl, $dst|$dst, %CL}",
1597 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1600 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1601 "rol{b}\t{$src2, $dst|$dst, $src2}",
1602 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1603 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1604 "rol{w}\t{$src2, $dst|$dst, $src2}",
1605 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1606 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1607 "rol{l}\t{$src2, $dst|$dst, $src2}",
1608 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1611 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1613 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1614 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1616 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1617 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1619 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1621 let isTwoAddress = 0 in {
1622 let Uses = [CL] in {
1623 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1624 "rol{b}\t{%cl, $dst|$dst, %CL}",
1625 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1626 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1627 "rol{w}\t{%cl, $dst|$dst, %CL}",
1628 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1629 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1630 "rol{l}\t{%cl, $dst|$dst, %CL}",
1631 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1633 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1634 "rol{b}\t{$src, $dst|$dst, $src}",
1635 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1636 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1637 "rol{w}\t{$src, $dst|$dst, $src}",
1638 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1640 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1641 "rol{l}\t{$src, $dst|$dst, $src}",
1642 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1645 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1647 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1648 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1650 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1652 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1654 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1657 let Uses = [CL] in {
1658 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1659 "ror{b}\t{%cl, $dst|$dst, %CL}",
1660 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1661 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1662 "ror{w}\t{%cl, $dst|$dst, %CL}",
1663 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1664 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1665 "ror{l}\t{%cl, $dst|$dst, %CL}",
1666 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1669 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1670 "ror{b}\t{$src2, $dst|$dst, $src2}",
1671 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1672 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1673 "ror{w}\t{$src2, $dst|$dst, $src2}",
1674 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1675 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1676 "ror{l}\t{$src2, $dst|$dst, $src2}",
1677 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1680 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1682 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1683 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1685 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1686 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1688 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1690 let isTwoAddress = 0 in {
1691 let Uses = [CL] in {
1692 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1693 "ror{b}\t{%cl, $dst|$dst, %CL}",
1694 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1695 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1696 "ror{w}\t{%cl, $dst|$dst, %CL}",
1697 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1698 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1699 "ror{l}\t{%cl, $dst|$dst, %CL}",
1700 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1702 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1703 "ror{b}\t{$src, $dst|$dst, $src}",
1704 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1705 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1706 "ror{w}\t{$src, $dst|$dst, $src}",
1707 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1709 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1710 "ror{l}\t{$src, $dst|$dst, $src}",
1711 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1714 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1716 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1717 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1719 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1721 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1723 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1728 // Double shift instructions (generalizations of rotate)
1729 let Uses = [CL] in {
1730 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1731 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1732 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1733 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1734 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1735 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1736 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1737 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1738 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1740 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1741 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1742 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1746 let isCommutable = 1 in { // These instructions commute to each other.
1747 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1748 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1749 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1750 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1753 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1754 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1755 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1756 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1759 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1760 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1761 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1762 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1765 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1766 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1767 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1768 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1773 let isTwoAddress = 0 in {
1774 let Uses = [CL] in {
1775 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1776 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1777 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1779 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1780 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1781 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1784 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1785 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1786 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1787 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1788 (i8 imm:$src3)), addr:$dst)]>,
1790 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1791 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1792 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1793 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1794 (i8 imm:$src3)), addr:$dst)]>,
1797 let Uses = [CL] in {
1798 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1799 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1800 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1801 addr:$dst)]>, TB, OpSize;
1802 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1803 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1804 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1805 addr:$dst)]>, TB, OpSize;
1807 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1808 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1809 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1810 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1811 (i8 imm:$src3)), addr:$dst)]>,
1813 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1814 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1815 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1816 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1817 (i8 imm:$src3)), addr:$dst)]>,
1820 } // Defs = [EFLAGS]
1824 let Defs = [EFLAGS] in {
1825 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1826 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1827 (ins GR8 :$src1, GR8 :$src2),
1828 "add{b}\t{$src2, $dst|$dst, $src2}",
1829 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1830 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1831 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1832 (ins GR16:$src1, GR16:$src2),
1833 "add{w}\t{$src2, $dst|$dst, $src2}",
1834 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1835 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1836 (ins GR32:$src1, GR32:$src2),
1837 "add{l}\t{$src2, $dst|$dst, $src2}",
1838 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1839 } // end isConvertibleToThreeAddress
1840 } // end isCommutable
1841 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1842 (ins GR8 :$src1, i8mem :$src2),
1843 "add{b}\t{$src2, $dst|$dst, $src2}",
1844 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1845 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1846 (ins GR16:$src1, i16mem:$src2),
1847 "add{w}\t{$src2, $dst|$dst, $src2}",
1848 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1849 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1850 (ins GR32:$src1, i32mem:$src2),
1851 "add{l}\t{$src2, $dst|$dst, $src2}",
1852 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1854 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1855 "add{b}\t{$src2, $dst|$dst, $src2}",
1856 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1858 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1859 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1860 (ins GR16:$src1, i16imm:$src2),
1861 "add{w}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1863 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1864 (ins GR32:$src1, i32imm:$src2),
1865 "add{l}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1867 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1868 (ins GR16:$src1, i16i8imm:$src2),
1869 "add{w}\t{$src2, $dst|$dst, $src2}",
1870 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1871 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1872 (ins GR32:$src1, i32i8imm:$src2),
1873 "add{l}\t{$src2, $dst|$dst, $src2}",
1874 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1877 let isTwoAddress = 0 in {
1878 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1879 "add{b}\t{$src2, $dst|$dst, $src2}",
1880 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1881 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1882 "add{w}\t{$src2, $dst|$dst, $src2}",
1883 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1885 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1886 "add{l}\t{$src2, $dst|$dst, $src2}",
1887 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1888 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1889 "add{b}\t{$src2, $dst|$dst, $src2}",
1890 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1891 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1892 "add{w}\t{$src2, $dst|$dst, $src2}",
1893 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1895 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1896 "add{l}\t{$src2, $dst|$dst, $src2}",
1897 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1898 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1899 "add{w}\t{$src2, $dst|$dst, $src2}",
1900 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1902 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1903 "add{l}\t{$src2, $dst|$dst, $src2}",
1904 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1907 let Uses = [EFLAGS] in {
1908 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1909 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1910 "adc{l}\t{$src2, $dst|$dst, $src2}",
1911 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1913 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1914 "adc{l}\t{$src2, $dst|$dst, $src2}",
1915 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1916 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1917 "adc{l}\t{$src2, $dst|$dst, $src2}",
1918 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1919 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1920 "adc{l}\t{$src2, $dst|$dst, $src2}",
1921 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1923 let isTwoAddress = 0 in {
1924 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1925 "adc{l}\t{$src2, $dst|$dst, $src2}",
1926 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1927 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1928 "adc{l}\t{$src2, $dst|$dst, $src2}",
1929 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1930 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1931 "adc{l}\t{$src2, $dst|$dst, $src2}",
1932 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1934 } // Uses = [EFLAGS]
1936 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1937 "sub{b}\t{$src2, $dst|$dst, $src2}",
1938 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1939 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1940 "sub{w}\t{$src2, $dst|$dst, $src2}",
1941 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1942 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1943 "sub{l}\t{$src2, $dst|$dst, $src2}",
1944 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1945 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1946 "sub{b}\t{$src2, $dst|$dst, $src2}",
1947 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1948 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1949 "sub{w}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1951 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1952 "sub{l}\t{$src2, $dst|$dst, $src2}",
1953 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1955 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1956 "sub{b}\t{$src2, $dst|$dst, $src2}",
1957 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1958 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1959 "sub{w}\t{$src2, $dst|$dst, $src2}",
1960 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1961 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1962 "sub{l}\t{$src2, $dst|$dst, $src2}",
1963 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1964 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1965 "sub{w}\t{$src2, $dst|$dst, $src2}",
1966 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1968 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1969 "sub{l}\t{$src2, $dst|$dst, $src2}",
1970 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1971 let isTwoAddress = 0 in {
1972 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1973 "sub{b}\t{$src2, $dst|$dst, $src2}",
1974 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1975 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1976 "sub{w}\t{$src2, $dst|$dst, $src2}",
1977 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1979 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1980 "sub{l}\t{$src2, $dst|$dst, $src2}",
1981 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1982 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1983 "sub{b}\t{$src2, $dst|$dst, $src2}",
1984 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1985 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1986 "sub{w}\t{$src2, $dst|$dst, $src2}",
1987 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1989 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1990 "sub{l}\t{$src2, $dst|$dst, $src2}",
1991 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1992 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1993 "sub{w}\t{$src2, $dst|$dst, $src2}",
1994 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1996 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1997 "sub{l}\t{$src2, $dst|$dst, $src2}",
1998 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2001 let Uses = [EFLAGS] in {
2002 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2003 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2004 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2006 let isTwoAddress = 0 in {
2007 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2008 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2009 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2010 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2011 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2012 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2013 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2014 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2015 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2016 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2017 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2018 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2020 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2021 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2023 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2024 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2026 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2027 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2028 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2029 } // Uses = [EFLAGS]
2030 } // Defs = [EFLAGS]
2032 let Defs = [EFLAGS] in {
2033 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2034 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2035 "imul{w}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2037 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2038 "imul{l}\t{$src2, $dst|$dst, $src2}",
2039 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2041 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2042 "imul{w}\t{$src2, $dst|$dst, $src2}",
2043 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2045 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2046 "imul{l}\t{$src2, $dst|$dst, $src2}",
2047 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2048 } // Defs = [EFLAGS]
2049 } // end Two Address instructions
2051 // Suprisingly enough, these are not two address instructions!
2052 let Defs = [EFLAGS] in {
2053 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2054 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2055 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2056 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2057 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2058 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2059 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2060 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2061 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2062 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2063 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2064 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2066 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2067 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2068 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2069 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2071 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2072 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2073 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2074 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2076 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2077 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2078 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2079 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2080 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2081 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2082 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2083 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2085 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2086 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2087 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2088 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2089 } // Defs = [EFLAGS]
2091 //===----------------------------------------------------------------------===//
2092 // Test instructions are just like AND, except they don't generate a result.
2094 let Defs = [EFLAGS] in {
2095 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2096 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2097 "test{b}\t{$src2, $src1|$src1, $src2}",
2098 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2099 (implicit EFLAGS)]>;
2100 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2101 "test{w}\t{$src2, $src1|$src1, $src2}",
2102 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2103 (implicit EFLAGS)]>,
2105 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2106 "test{l}\t{$src2, $src1|$src1, $src2}",
2107 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2108 (implicit EFLAGS)]>;
2111 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2112 "test{b}\t{$src2, $src1|$src1, $src2}",
2113 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2114 (implicit EFLAGS)]>;
2115 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2116 "test{w}\t{$src2, $src1|$src1, $src2}",
2117 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2118 (implicit EFLAGS)]>, OpSize;
2119 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2120 "test{l}\t{$src2, $src1|$src1, $src2}",
2121 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2122 (implicit EFLAGS)]>;
2124 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2125 (outs), (ins GR8:$src1, i8imm:$src2),
2126 "test{b}\t{$src2, $src1|$src1, $src2}",
2127 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2128 (implicit EFLAGS)]>;
2129 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2130 (outs), (ins GR16:$src1, i16imm:$src2),
2131 "test{w}\t{$src2, $src1|$src1, $src2}",
2132 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2133 (implicit EFLAGS)]>, OpSize;
2134 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2135 (outs), (ins GR32:$src1, i32imm:$src2),
2136 "test{l}\t{$src2, $src1|$src1, $src2}",
2137 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2138 (implicit EFLAGS)]>;
2140 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2141 (outs), (ins i8mem:$src1, i8imm:$src2),
2142 "test{b}\t{$src2, $src1|$src1, $src2}",
2143 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2144 (implicit EFLAGS)]>;
2145 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2146 (outs), (ins i16mem:$src1, i16imm:$src2),
2147 "test{w}\t{$src2, $src1|$src1, $src2}",
2148 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2149 (implicit EFLAGS)]>, OpSize;
2150 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2151 (outs), (ins i32mem:$src1, i32imm:$src2),
2152 "test{l}\t{$src2, $src1|$src1, $src2}",
2153 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2154 (implicit EFLAGS)]>;
2155 } // Defs = [EFLAGS]
2158 // Condition code ops, incl. set if equal/not equal/...
2159 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2160 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2161 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2162 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2164 let Uses = [EFLAGS] in {
2165 def SETEr : I<0x94, MRM0r,
2166 (outs GR8 :$dst), (ins),
2168 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2170 def SETEm : I<0x94, MRM0m,
2171 (outs), (ins i8mem:$dst),
2173 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2175 def SETNEr : I<0x95, MRM0r,
2176 (outs GR8 :$dst), (ins),
2178 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2180 def SETNEm : I<0x95, MRM0m,
2181 (outs), (ins i8mem:$dst),
2183 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2185 def SETLr : I<0x9C, MRM0r,
2186 (outs GR8 :$dst), (ins),
2188 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2189 TB; // GR8 = < signed
2190 def SETLm : I<0x9C, MRM0m,
2191 (outs), (ins i8mem:$dst),
2193 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2194 TB; // [mem8] = < signed
2195 def SETGEr : I<0x9D, MRM0r,
2196 (outs GR8 :$dst), (ins),
2198 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2199 TB; // GR8 = >= signed
2200 def SETGEm : I<0x9D, MRM0m,
2201 (outs), (ins i8mem:$dst),
2203 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2204 TB; // [mem8] = >= signed
2205 def SETLEr : I<0x9E, MRM0r,
2206 (outs GR8 :$dst), (ins),
2208 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2209 TB; // GR8 = <= signed
2210 def SETLEm : I<0x9E, MRM0m,
2211 (outs), (ins i8mem:$dst),
2213 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2214 TB; // [mem8] = <= signed
2215 def SETGr : I<0x9F, MRM0r,
2216 (outs GR8 :$dst), (ins),
2218 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2219 TB; // GR8 = > signed
2220 def SETGm : I<0x9F, MRM0m,
2221 (outs), (ins i8mem:$dst),
2223 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2224 TB; // [mem8] = > signed
2226 def SETBr : I<0x92, MRM0r,
2227 (outs GR8 :$dst), (ins),
2229 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2230 TB; // GR8 = < unsign
2231 def SETBm : I<0x92, MRM0m,
2232 (outs), (ins i8mem:$dst),
2234 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2235 TB; // [mem8] = < unsign
2236 def SETAEr : I<0x93, MRM0r,
2237 (outs GR8 :$dst), (ins),
2239 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2240 TB; // GR8 = >= unsign
2241 def SETAEm : I<0x93, MRM0m,
2242 (outs), (ins i8mem:$dst),
2244 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2245 TB; // [mem8] = >= unsign
2246 def SETBEr : I<0x96, MRM0r,
2247 (outs GR8 :$dst), (ins),
2249 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2250 TB; // GR8 = <= unsign
2251 def SETBEm : I<0x96, MRM0m,
2252 (outs), (ins i8mem:$dst),
2254 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2255 TB; // [mem8] = <= unsign
2256 def SETAr : I<0x97, MRM0r,
2257 (outs GR8 :$dst), (ins),
2259 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2260 TB; // GR8 = > signed
2261 def SETAm : I<0x97, MRM0m,
2262 (outs), (ins i8mem:$dst),
2264 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2265 TB; // [mem8] = > signed
2267 def SETSr : I<0x98, MRM0r,
2268 (outs GR8 :$dst), (ins),
2270 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2271 TB; // GR8 = <sign bit>
2272 def SETSm : I<0x98, MRM0m,
2273 (outs), (ins i8mem:$dst),
2275 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2276 TB; // [mem8] = <sign bit>
2277 def SETNSr : I<0x99, MRM0r,
2278 (outs GR8 :$dst), (ins),
2280 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2281 TB; // GR8 = !<sign bit>
2282 def SETNSm : I<0x99, MRM0m,
2283 (outs), (ins i8mem:$dst),
2285 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2286 TB; // [mem8] = !<sign bit>
2287 def SETPr : I<0x9A, MRM0r,
2288 (outs GR8 :$dst), (ins),
2290 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2292 def SETPm : I<0x9A, MRM0m,
2293 (outs), (ins i8mem:$dst),
2295 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2296 TB; // [mem8] = parity
2297 def SETNPr : I<0x9B, MRM0r,
2298 (outs GR8 :$dst), (ins),
2300 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2301 TB; // GR8 = not parity
2302 def SETNPm : I<0x9B, MRM0m,
2303 (outs), (ins i8mem:$dst),
2305 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2306 TB; // [mem8] = not parity
2307 } // Uses = [EFLAGS]
2310 // Integer comparisons
2311 let Defs = [EFLAGS] in {
2312 def CMP8rr : I<0x38, MRMDestReg,
2313 (outs), (ins GR8 :$src1, GR8 :$src2),
2314 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2315 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2316 def CMP16rr : I<0x39, MRMDestReg,
2317 (outs), (ins GR16:$src1, GR16:$src2),
2318 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2319 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2320 def CMP32rr : I<0x39, MRMDestReg,
2321 (outs), (ins GR32:$src1, GR32:$src2),
2322 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2323 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2324 def CMP8mr : I<0x38, MRMDestMem,
2325 (outs), (ins i8mem :$src1, GR8 :$src2),
2326 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2327 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2328 (implicit EFLAGS)]>;
2329 def CMP16mr : I<0x39, MRMDestMem,
2330 (outs), (ins i16mem:$src1, GR16:$src2),
2331 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2332 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2333 (implicit EFLAGS)]>, OpSize;
2334 def CMP32mr : I<0x39, MRMDestMem,
2335 (outs), (ins i32mem:$src1, GR32:$src2),
2336 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2337 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2338 (implicit EFLAGS)]>;
2339 def CMP8rm : I<0x3A, MRMSrcMem,
2340 (outs), (ins GR8 :$src1, i8mem :$src2),
2341 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2342 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2343 (implicit EFLAGS)]>;
2344 def CMP16rm : I<0x3B, MRMSrcMem,
2345 (outs), (ins GR16:$src1, i16mem:$src2),
2346 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2347 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2348 (implicit EFLAGS)]>, OpSize;
2349 def CMP32rm : I<0x3B, MRMSrcMem,
2350 (outs), (ins GR32:$src1, i32mem:$src2),
2351 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2352 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2353 (implicit EFLAGS)]>;
2354 def CMP8ri : Ii8<0x80, MRM7r,
2355 (outs), (ins GR8:$src1, i8imm:$src2),
2356 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2357 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2358 def CMP16ri : Ii16<0x81, MRM7r,
2359 (outs), (ins GR16:$src1, i16imm:$src2),
2360 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2361 [(X86cmp GR16:$src1, imm:$src2),
2362 (implicit EFLAGS)]>, OpSize;
2363 def CMP32ri : Ii32<0x81, MRM7r,
2364 (outs), (ins GR32:$src1, i32imm:$src2),
2365 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2366 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2367 def CMP8mi : Ii8 <0x80, MRM7m,
2368 (outs), (ins i8mem :$src1, i8imm :$src2),
2369 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2370 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2371 (implicit EFLAGS)]>;
2372 def CMP16mi : Ii16<0x81, MRM7m,
2373 (outs), (ins i16mem:$src1, i16imm:$src2),
2374 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2375 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2376 (implicit EFLAGS)]>, OpSize;
2377 def CMP32mi : Ii32<0x81, MRM7m,
2378 (outs), (ins i32mem:$src1, i32imm:$src2),
2379 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2380 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2381 (implicit EFLAGS)]>;
2382 def CMP16ri8 : Ii8<0x83, MRM7r,
2383 (outs), (ins GR16:$src1, i16i8imm:$src2),
2384 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2385 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2386 (implicit EFLAGS)]>, OpSize;
2387 def CMP16mi8 : Ii8<0x83, MRM7m,
2388 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2389 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2390 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2391 (implicit EFLAGS)]>, OpSize;
2392 def CMP32mi8 : Ii8<0x83, MRM7m,
2393 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2394 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2395 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2396 (implicit EFLAGS)]>;
2397 def CMP32ri8 : Ii8<0x83, MRM7r,
2398 (outs), (ins GR32:$src1, i32i8imm:$src2),
2399 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2400 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2401 (implicit EFLAGS)]>;
2402 } // Defs = [EFLAGS]
2404 // Sign/Zero extenders
2405 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2406 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2407 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2408 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2409 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2410 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2411 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2412 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2413 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2414 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2415 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2416 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2417 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2418 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2419 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2420 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2421 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2422 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2424 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2425 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2426 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2427 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2428 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2429 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2430 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2431 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2432 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2433 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2434 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2435 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2436 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2437 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2438 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2439 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2440 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2441 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2443 let neverHasSideEffects = 1 in {
2444 let Defs = [AX], Uses = [AL] in
2445 def CBW : I<0x98, RawFrm, (outs), (ins),
2446 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2447 let Defs = [EAX], Uses = [AX] in
2448 def CWDE : I<0x98, RawFrm, (outs), (ins),
2449 "{cwtl|cwde}", []>; // EAX = signext(AX)
2451 let Defs = [AX,DX], Uses = [AX] in
2452 def CWD : I<0x99, RawFrm, (outs), (ins),
2453 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2454 let Defs = [EAX,EDX], Uses = [EAX] in
2455 def CDQ : I<0x99, RawFrm, (outs), (ins),
2456 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2459 //===----------------------------------------------------------------------===//
2460 // Alias Instructions
2461 //===----------------------------------------------------------------------===//
2463 // Alias instructions that map movr0 to xor.
2464 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2465 let Defs = [EFLAGS], isReMaterializable = 1 in {
2466 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2467 "xor{b}\t$dst, $dst",
2468 [(set GR8:$dst, 0)]>;
2469 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2470 "xor{w}\t$dst, $dst",
2471 [(set GR16:$dst, 0)]>, OpSize;
2472 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2473 "xor{l}\t$dst, $dst",
2474 [(set GR32:$dst, 0)]>;
2477 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2478 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2479 let neverHasSideEffects = 1 in {
2480 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2481 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2482 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2483 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2485 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2486 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2487 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2488 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2489 } // neverHasSideEffects
2491 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2492 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2493 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2494 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2495 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2497 let mayStore = 1, neverHasSideEffects = 1 in {
2498 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2499 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2500 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2501 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2504 //===----------------------------------------------------------------------===//
2505 // Thread Local Storage Instructions
2509 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2510 "leal\t${sym:mem}(,%ebx,1), $dst",
2511 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2513 let AddedComplexity = 10 in
2514 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2515 "movl\t%gs:($src), $dst",
2516 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2518 let AddedComplexity = 15 in
2519 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2520 "movl\t%gs:${src:mem}, $dst",
2522 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2524 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2525 "movl\t%gs:0, $dst",
2526 [(set GR32:$dst, X86TLStp)]>;
2528 //===----------------------------------------------------------------------===//
2529 // DWARF Pseudo Instructions
2532 def DWARF_LOC : I<0, Pseudo, (outs),
2533 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2534 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2535 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2538 //===----------------------------------------------------------------------===//
2539 // EH Pseudo Instructions
2541 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2543 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2544 "ret\t#eh_return, addr: $addr",
2545 [(X86ehret GR32:$addr)]>;
2549 //===----------------------------------------------------------------------===//
2553 //FIXME: Please check the format Pseudo is certainly wrong, but the opcode and
2554 // prefixes should be correct
2556 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2557 def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
2558 "cmpxchgl $swap,$ptr", []>, TB;
2559 def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
2560 "lock cmpxchgl $swap,$ptr",
2561 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2563 let Defs = [EAX, EBX, ECX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2564 def CMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr),
2565 "cmpxchg8b $ptr", []>, TB;
2566 def LCMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr),
2567 "lock cmpxchg8b $ptr",
2568 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2571 let Defs = [AX, EFLAGS], Uses = [AX] in {
2572 def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
2573 "cmpxchgw $swap,($ptr)", []>, TB, OpSize;
2574 def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
2575 "lock cmpxchgw $swap,$ptr",
2576 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2578 let Defs = [AL, EFLAGS], Uses = [AL] in {
2579 def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
2580 "cmpxchgb $swap,($ptr)", []>, TB;
2581 def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
2582 "lock cmpxchgb $swap,$ptr",
2583 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2586 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2587 def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2588 "lock xadd $val, $ptr",
2589 [(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>,
2591 def LXADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2592 "lock xadd $val, $ptr",
2593 [(set GR16:$dst, (atomic_las_16 addr:$ptr, GR16:$val))]>,
2595 def LXADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2596 "lock xadd $val, $ptr",
2597 [(set GR8:$dst, (atomic_las_8 addr:$ptr, GR8:$val))]>,
2599 def XADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2600 "xadd $val, $ptr", []>, TB;
2601 def XADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2602 "xadd $val, $ptr", []>, TB, OpSize;
2603 def XADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2604 "xadd $val, $ptr", []>, TB;
2606 def LXCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2607 "lock xchg $val, $ptr",
2608 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>, LOCK;
2609 def LXCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2610 "lock xchg $val, $ptr",
2611 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2613 def LXCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2614 "lock xchg $val, $ptr",
2615 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>, LOCK;
2616 def XCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2617 "xchg $val, $ptr", []>;
2618 def XCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2619 "xchg $val, $ptr", []>, OpSize;
2620 def XCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2621 "xchg $val, $ptr", []>;
2624 //===----------------------------------------------------------------------===//
2625 // Non-Instruction Patterns
2626 //===----------------------------------------------------------------------===//
2628 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2629 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2630 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2631 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2632 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2633 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2635 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2636 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2637 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2638 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2639 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2640 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2641 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2642 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2644 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2645 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2646 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2647 (MOV32mi addr:$dst, texternalsym:$src)>;
2651 def : Pat<(X86tailcall GR32:$dst),
2654 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2656 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2659 def : Pat<(X86tcret GR32:$dst, imm:$off),
2660 (TCRETURNri GR32:$dst, imm:$off)>;
2662 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2663 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2665 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2666 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2668 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2669 (CALLpcrel32 tglobaladdr:$dst)>;
2670 def : Pat<(X86call (i32 texternalsym:$dst)),
2671 (CALLpcrel32 texternalsym:$dst)>;
2673 // X86 specific add which produces a flag.
2674 def : Pat<(addc GR32:$src1, GR32:$src2),
2675 (ADD32rr GR32:$src1, GR32:$src2)>;
2676 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2677 (ADD32rm GR32:$src1, addr:$src2)>;
2678 def : Pat<(addc GR32:$src1, imm:$src2),
2679 (ADD32ri GR32:$src1, imm:$src2)>;
2680 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2681 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2683 def : Pat<(subc GR32:$src1, GR32:$src2),
2684 (SUB32rr GR32:$src1, GR32:$src2)>;
2685 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2686 (SUB32rm GR32:$src1, addr:$src2)>;
2687 def : Pat<(subc GR32:$src1, imm:$src2),
2688 (SUB32ri GR32:$src1, imm:$src2)>;
2689 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2690 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2694 // TEST R,R is smaller than CMP R,0
2695 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2696 (TEST8rr GR8:$src1, GR8:$src1)>;
2697 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2698 (TEST16rr GR16:$src1, GR16:$src1)>;
2699 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2700 (TEST32rr GR32:$src1, GR32:$src1)>;
2702 // zextload bool -> zextload byte
2703 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2704 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2705 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2707 // extload bool -> extload byte
2708 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2709 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2710 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2711 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2712 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2713 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2716 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2717 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2718 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2719 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2720 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2721 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2723 // (and (i32 load), 255) -> (zextload i8)
2724 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2725 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2727 //===----------------------------------------------------------------------===//
2729 //===----------------------------------------------------------------------===//
2731 // (shl x, 1) ==> (add x, x)
2732 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2733 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2734 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2736 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2737 def : Pat<(or (srl GR32:$src1, CL:$amt),
2738 (shl GR32:$src2, (sub 32, CL:$amt))),
2739 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2741 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2742 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2743 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2745 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2746 def : Pat<(or (shl GR32:$src1, CL:$amt),
2747 (srl GR32:$src2, (sub 32, CL:$amt))),
2748 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2750 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2751 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2752 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2754 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2755 def : Pat<(or (srl GR16:$src1, CL:$amt),
2756 (shl GR16:$src2, (sub 16, CL:$amt))),
2757 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2759 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2760 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2761 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2763 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2764 def : Pat<(or (shl GR16:$src1, CL:$amt),
2765 (srl GR16:$src2, (sub 16, CL:$amt))),
2766 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2768 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2769 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2770 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2772 //===----------------------------------------------------------------------===//
2773 // Floating Point Stack Support
2774 //===----------------------------------------------------------------------===//
2776 include "X86InstrFPStack.td"
2778 //===----------------------------------------------------------------------===//
2780 //===----------------------------------------------------------------------===//
2782 include "X86Instr64bit.td"
2784 //===----------------------------------------------------------------------===//
2785 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2786 //===----------------------------------------------------------------------===//
2788 include "X86InstrMMX.td"
2790 //===----------------------------------------------------------------------===//
2791 // XMM Floating point support (requires SSE / SSE2)
2792 //===----------------------------------------------------------------------===//
2794 include "X86InstrSSE.td"