1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
82 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
83 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
84 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
86 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
128 [SDNPHasChain, SDNPVariadic]>;
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
141 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
142 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
143 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
147 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
148 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
150 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
151 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
153 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
154 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
155 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
156 SDT_X86SegmentBaseAddress, []>;
158 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
161 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
162 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
164 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
166 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
167 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
169 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
172 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
173 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
174 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
176 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
178 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
181 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
183 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
184 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
186 //===----------------------------------------------------------------------===//
187 // X86 Operand Definitions.
190 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
191 // the index operand of an address, to conform to x86 encoding restrictions.
192 def ptr_rc_nosp : PointerLikeRegClass<1>;
194 // *mem - Operand definitions for the funky X86 addressing mode operands.
196 def X86MemAsmOperand : AsmOperandClass {
200 def X86AbsMemAsmOperand : AsmOperandClass {
202 let SuperClass = X86MemAsmOperand;
204 def X86NoSegMemAsmOperand : AsmOperandClass {
205 let Name = "NoSegMem";
206 let SuperClass = X86MemAsmOperand;
208 class X86MemOperand<string printMethod> : Operand<iPTR> {
209 let PrintMethod = printMethod;
210 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
211 let ParserMatchClass = X86MemAsmOperand;
214 def opaque32mem : X86MemOperand<"printopaquemem">;
215 def opaque48mem : X86MemOperand<"printopaquemem">;
216 def opaque80mem : X86MemOperand<"printopaquemem">;
217 def opaque512mem : X86MemOperand<"printopaquemem">;
219 def i8mem : X86MemOperand<"printi8mem">;
220 def i16mem : X86MemOperand<"printi16mem">;
221 def i32mem : X86MemOperand<"printi32mem">;
222 def i64mem : X86MemOperand<"printi64mem">;
223 def i128mem : X86MemOperand<"printi128mem">;
224 //def i256mem : X86MemOperand<"printi256mem">;
225 def f32mem : X86MemOperand<"printf32mem">;
226 def f64mem : X86MemOperand<"printf64mem">;
227 def f80mem : X86MemOperand<"printf80mem">;
228 def f128mem : X86MemOperand<"printf128mem">;
229 //def f256mem : X86MemOperand<"printf256mem">;
231 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
232 // plain GR64, so that it doesn't potentially require a REX prefix.
233 def i8mem_NOREX : Operand<i64> {
234 let PrintMethod = "printi8mem";
235 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
236 let ParserMatchClass = X86MemAsmOperand;
239 // Special i32mem for addresses of load folding tail calls. These are not
240 // allowed to use callee-saved registers since they must be scheduled
241 // after callee-saved register are popped.
242 def i32mem_TC : Operand<i32> {
243 let PrintMethod = "printi32mem";
244 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
245 let ParserMatchClass = X86MemAsmOperand;
248 def lea32mem : Operand<i32> {
249 let PrintMethod = "printlea32mem";
250 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
251 let ParserMatchClass = X86NoSegMemAsmOperand;
254 let ParserMatchClass = X86AbsMemAsmOperand,
255 PrintMethod = "print_pcrel_imm" in {
256 def i32imm_pcrel : Operand<i32>;
258 def offset8 : Operand<i64>;
259 def offset16 : Operand<i64>;
260 def offset32 : Operand<i64>;
261 def offset64 : Operand<i64>;
263 // Branch targets have OtherVT type and print as pc-relative values.
264 def brtarget : Operand<OtherVT>;
265 def brtarget8 : Operand<OtherVT>;
269 def SSECC : Operand<i8> {
270 let PrintMethod = "printSSECC";
273 def ImmSExt8AsmOperand : AsmOperandClass {
274 let Name = "ImmSExt8";
275 let SuperClass = ImmAsmOperand;
278 // A couple of more descriptive operand definitions.
279 // 16-bits but only 8 bits are significant.
280 def i16i8imm : Operand<i16> {
281 let ParserMatchClass = ImmSExt8AsmOperand;
283 // 32-bits but only 8 bits are significant.
284 def i32i8imm : Operand<i32> {
285 let ParserMatchClass = ImmSExt8AsmOperand;
288 //===----------------------------------------------------------------------===//
289 // X86 Complex Pattern Definitions.
292 // Define X86 specific addressing mode.
293 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
294 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
295 [add, sub, mul, X86mul_imm, shl, or, frameindex],
297 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
298 [tglobaltlsaddr], []>;
300 //===----------------------------------------------------------------------===//
301 // X86 Instruction Predicate Definitions.
302 def HasCMov : Predicate<"Subtarget->hasCMov()">;
303 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
304 def HasMMX : Predicate<"Subtarget->hasMMX()">;
305 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
306 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
307 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
308 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
309 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
310 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
311 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
312 def HasAVX : Predicate<"Subtarget->hasAVX()">;
313 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
314 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
315 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
316 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
317 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
318 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
319 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
320 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
321 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
322 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
323 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
324 "TM.getCodeModel() != CodeModel::Kernel">;
325 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
326 "TM.getCodeModel() == CodeModel::Kernel">;
327 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
328 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
329 def OptForSize : Predicate<"OptForSize">;
330 def OptForSpeed : Predicate<"!OptForSize">;
331 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
332 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
333 def HasAES : Predicate<"Subtarget->hasAES()">;
334 def Promote16Bit : Predicate<"Subtarget->shouldPromote16Bit()">;
335 def NotPromote16Bit : Predicate<"!Subtarget->shouldPromote16Bit()">;
337 //===----------------------------------------------------------------------===//
338 // X86 Instruction Format Definitions.
341 include "X86InstrFormats.td"
343 //===----------------------------------------------------------------------===//
344 // Pattern fragments...
347 // X86 specific condition code. These correspond to CondCode in
348 // X86InstrInfo.h. They must be kept in synch.
349 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
350 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
351 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
352 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
353 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
354 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
355 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
356 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
357 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
358 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
359 def X86_COND_NO : PatLeaf<(i8 10)>;
360 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
361 def X86_COND_NS : PatLeaf<(i8 12)>;
362 def X86_COND_O : PatLeaf<(i8 13)>;
363 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
364 def X86_COND_S : PatLeaf<(i8 15)>;
366 def immSext8 : PatLeaf<(imm), [{
367 return N->getSExtValue() == (int8_t)N->getSExtValue();
370 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
371 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
373 /// Load patterns: these constraint the match to the right address space.
374 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
375 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
376 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
377 if (PT->getAddressSpace() > 255)
382 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
383 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
384 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
385 return PT->getAddressSpace() == 256;
389 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
390 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
391 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
392 return PT->getAddressSpace() == 257;
397 // Helper fragments for loads.
398 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
399 // known to be 32-bit aligned or better. Ditto for i8 to i16.
400 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
401 LoadSDNode *LD = cast<LoadSDNode>(N);
402 if (const Value *Src = LD->getSrcValue())
403 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
404 if (PT->getAddressSpace() > 255)
406 ISD::LoadExtType ExtType = LD->getExtensionType();
407 if (ExtType == ISD::NON_EXTLOAD)
409 if (ExtType == ISD::EXTLOAD)
410 return LD->getAlignment() >= 2 && !LD->isVolatile();
414 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
415 LoadSDNode *LD = cast<LoadSDNode>(N);
416 if (const Value *Src = LD->getSrcValue())
417 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
418 if (PT->getAddressSpace() > 255)
420 ISD::LoadExtType ExtType = LD->getExtensionType();
421 if (ExtType == ISD::EXTLOAD)
422 return LD->getAlignment() >= 2 && !LD->isVolatile();
426 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
427 LoadSDNode *LD = cast<LoadSDNode>(N);
428 if (const Value *Src = LD->getSrcValue())
429 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
430 if (PT->getAddressSpace() > 255)
432 ISD::LoadExtType ExtType = LD->getExtensionType();
433 if (ExtType == ISD::NON_EXTLOAD)
435 if (ExtType == ISD::EXTLOAD)
436 return LD->getAlignment() >= 4 && !LD->isVolatile();
440 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
441 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
442 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
443 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
444 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
446 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
447 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
448 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
450 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
451 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
452 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
453 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
454 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
455 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
457 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
458 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
459 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
460 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
461 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
462 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
465 // An 'and' node with a single use.
466 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
467 return N->hasOneUse();
469 // An 'srl' node with a single use.
470 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
471 return N->hasOneUse();
473 // An 'trunc' node with a single use.
474 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
475 return N->hasOneUse();
478 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
479 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
480 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
481 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
483 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
484 APInt Mask = APInt::getAllOnesValue(BitWidth);
485 APInt KnownZero0, KnownOne0;
486 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
487 APInt KnownZero1, KnownOne1;
488 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
489 return (~KnownZero0 & ~KnownZero1) == 0;
492 // 'shld' and 'shrd' instruction patterns. Note that even though these have
493 // the srl and shl in their patterns, the C++ code must still check for them,
494 // because predicates are tested before children nodes are explored.
496 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
497 (or (srl node:$src1, node:$amt1),
498 (shl node:$src2, node:$amt2)), [{
499 assert(N->getOpcode() == ISD::OR);
500 return N->getOperand(0).getOpcode() == ISD::SRL &&
501 N->getOperand(1).getOpcode() == ISD::SHL &&
502 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
503 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
504 N->getOperand(0).getConstantOperandVal(1) ==
505 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
508 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
509 (or (shl node:$src1, node:$amt1),
510 (srl node:$src2, node:$amt2)), [{
511 assert(N->getOpcode() == ISD::OR);
512 return N->getOperand(0).getOpcode() == ISD::SHL &&
513 N->getOperand(1).getOpcode() == ISD::SRL &&
514 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
515 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
516 N->getOperand(0).getConstantOperandVal(1) ==
517 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
520 //===----------------------------------------------------------------------===//
521 // Instruction list...
524 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
525 // a stack adjustment and the codegen must know that they may modify the stack
526 // pointer before prolog-epilog rewriting occurs.
527 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
528 // sub / add which can clobber EFLAGS.
529 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
530 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
532 [(X86callseq_start timm:$amt)]>,
533 Requires<[In32BitMode]>;
534 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
536 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
537 Requires<[In32BitMode]>;
540 // x86-64 va_start lowering magic.
541 let usesCustomInserter = 1 in {
542 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
545 i64imm:$regsavefi, i64imm:$offset,
547 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
548 [(X86vastart_save_xmm_regs GR8:$al,
552 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
553 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
554 // one go. Touching the stack at 4K increments is necessary to ensure that the
555 // guard pages used by the OS virtual memory manager are allocated in correct
557 // The main point of having separate instruction are extra unmodelled effects
558 // (compared to ordinary calls) like stack pointer change.
560 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
561 "# dynamic stack allocation",
566 let neverHasSideEffects = 1 in {
567 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
568 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
569 "nop{w}\t$zero", []>, TB, OpSize;
570 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
571 "nop{l}\t$zero", []>, TB;
575 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
576 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
577 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
578 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
580 // PIC base construction. This expands to code that looks like this:
583 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
584 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
587 //===----------------------------------------------------------------------===//
588 // Control Flow Instructions.
591 // Return instructions.
592 let isTerminator = 1, isReturn = 1, isBarrier = 1,
593 hasCtrlDep = 1, FPForm = SpecialFP in {
594 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
597 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
599 [(X86retflag timm:$amt)]>;
600 def LRET : I <0xCB, RawFrm, (outs), (ins),
602 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
606 // Unconditional branches.
607 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
608 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
609 "jmp\t$dst", [(br bb:$dst)]>;
610 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
614 // Conditional Branches.
615 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
616 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
617 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
618 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
619 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
623 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
624 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
625 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
626 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
627 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
628 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
629 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
630 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
631 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
632 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
633 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
634 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
635 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
636 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
637 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
638 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
640 // FIXME: What about the CX/RCX versions of this instruction?
641 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
642 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
647 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
648 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
649 [(brind GR32:$dst)]>;
650 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
651 [(brind (loadi32 addr:$dst))]>;
653 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
654 (ins i16imm:$seg, i16imm:$off),
655 "ljmp{w}\t$seg, $off", []>, OpSize;
656 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
657 (ins i16imm:$seg, i32imm:$off),
658 "ljmp{l}\t$seg, $off", []>;
660 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
661 "ljmp{w}\t{*}$dst", []>, OpSize;
662 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
663 "ljmp{l}\t{*}$dst", []>;
669 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
670 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
671 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
673 //===----------------------------------------------------------------------===//
674 // Call Instructions...
677 // All calls clobber the non-callee saved registers. ESP is marked as
678 // a use to prevent stack-pointer assignments that appear immediately
679 // before calls from potentially appearing dead. Uses for argument
680 // registers are added manually.
681 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
682 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
683 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
684 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
686 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
687 (outs), (ins i32imm_pcrel:$dst,variable_ops),
689 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
690 "call\t{*}$dst", [(X86call GR32:$dst)]>;
691 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
692 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
694 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
695 (ins i16imm:$seg, i16imm:$off),
696 "lcall{w}\t$seg, $off", []>, OpSize;
697 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
698 (ins i16imm:$seg, i32imm:$off),
699 "lcall{l}\t$seg, $off", []>;
701 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
702 "lcall{w}\t{*}$dst", []>, OpSize;
703 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
704 "lcall{l}\t{*}$dst", []>;
707 // Constructing a stack frame.
709 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
710 "enter\t$len, $lvl", []>;
714 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
715 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
716 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
717 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
718 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
720 def TCRETURNdi : I<0, Pseudo, (outs),
721 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
722 "#TC_RETURN $dst $offset", []>;
723 def TCRETURNri : I<0, Pseudo, (outs),
724 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
725 "#TC_RETURN $dst $offset", []>;
726 def TCRETURNmi : I<0, Pseudo, (outs),
727 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
728 "#TC_RETURN $dst $offset", []>;
730 // FIXME: The should be pseudo instructions that are lowered when going to
732 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
733 (ins i32imm_pcrel:$dst, variable_ops),
734 "jmp\t$dst # TAILCALL",
736 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
737 "jmp{l}\t{*}$dst # TAILCALL",
739 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
740 "jmp{l}\t{*}$dst # TAILCALL", []>;
743 //===----------------------------------------------------------------------===//
744 // Miscellaneous Instructions...
746 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
747 def LEAVE : I<0xC9, RawFrm,
748 (outs), (ins), "leave", []>;
750 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
751 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
752 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
753 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
754 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
755 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
756 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
757 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
759 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
761 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
763 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
764 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
766 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
768 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
769 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
772 let mayStore = 1 in {
773 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
775 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
776 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
778 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
780 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
781 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
785 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
786 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
787 "push{l}\t$imm", []>;
788 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
789 "push{l}\t$imm", []>;
790 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
791 "push{l}\t$imm", []>;
794 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
795 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
796 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
798 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
799 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
800 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
803 let isTwoAddress = 1 in // GR32 = bswap GR32
804 def BSWAP32r : I<0xC8, AddRegFrm,
805 (outs GR32:$dst), (ins GR32:$src),
807 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
810 // Bit scan instructions.
811 let Defs = [EFLAGS] in {
812 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
813 "bsf{w}\t{$src, $dst|$dst, $src}",
814 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB;
815 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
816 "bsf{w}\t{$src, $dst|$dst, $src}",
817 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB;
818 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
819 "bsf{l}\t{$src, $dst|$dst, $src}",
820 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
821 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
822 "bsf{l}\t{$src, $dst|$dst, $src}",
823 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
825 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
826 "bsr{w}\t{$src, $dst|$dst, $src}",
827 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB;
828 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
829 "bsr{w}\t{$src, $dst|$dst, $src}",
830 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB;
831 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
832 "bsr{l}\t{$src, $dst|$dst, $src}",
833 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
834 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
835 "bsr{l}\t{$src, $dst|$dst, $src}",
836 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
839 let neverHasSideEffects = 1 in
840 def LEA16r : I<0x8D, MRMSrcMem,
841 (outs GR16:$dst), (ins lea32mem:$src),
842 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
843 let isReMaterializable = 1 in
844 def LEA32r : I<0x8D, MRMSrcMem,
845 (outs GR32:$dst), (ins lea32mem:$src),
846 "lea{l}\t{$src|$dst}, {$dst|$src}",
847 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
849 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
850 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
851 [(X86rep_movs i8)]>, REP;
852 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
853 [(X86rep_movs i16)]>, REP, OpSize;
854 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
855 [(X86rep_movs i32)]>, REP;
858 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
859 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
860 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
861 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
862 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
865 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
866 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
867 [(X86rep_stos i8)]>, REP;
868 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
869 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
870 [(X86rep_stos i16)]>, REP, OpSize;
871 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
872 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
873 [(X86rep_stos i32)]>, REP;
875 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
876 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
877 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
878 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
879 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
880 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
881 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
883 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
884 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
885 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
887 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
888 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
889 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
891 let Defs = [RAX, RDX] in
892 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
895 let Defs = [RAX, RCX, RDX] in
896 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
898 let isBarrier = 1, hasCtrlDep = 1 in {
899 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
902 def SYSCALL : I<0x05, RawFrm,
903 (outs), (ins), "syscall", []>, TB;
904 def SYSRET : I<0x07, RawFrm,
905 (outs), (ins), "sysret", []>, TB;
906 def SYSENTER : I<0x34, RawFrm,
907 (outs), (ins), "sysenter", []>, TB;
908 def SYSEXIT : I<0x35, RawFrm,
909 (outs), (ins), "sysexit", []>, TB;
911 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
914 //===----------------------------------------------------------------------===//
915 // Input/Output Instructions...
917 let Defs = [AL], Uses = [DX] in
918 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
919 "in{b}\t{%dx, %al|%AL, %DX}", []>;
920 let Defs = [AX], Uses = [DX] in
921 def IN16rr : I<0xED, RawFrm, (outs), (ins),
922 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
923 let Defs = [EAX], Uses = [DX] in
924 def IN32rr : I<0xED, RawFrm, (outs), (ins),
925 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
928 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
929 "in{b}\t{$port, %al|%AL, $port}", []>;
931 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
932 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
934 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
935 "in{l}\t{$port, %eax|%EAX, $port}", []>;
937 let Uses = [DX, AL] in
938 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
939 "out{b}\t{%al, %dx|%DX, %AL}", []>;
940 let Uses = [DX, AX] in
941 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
942 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
943 let Uses = [DX, EAX] in
944 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
945 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
948 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
949 "out{b}\t{%al, $port|$port, %AL}", []>;
951 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
952 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
954 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
955 "out{l}\t{%eax, $port|$port, %EAX}", []>;
957 def IN8 : I<0x6C, RawFrm, (outs), (ins),
959 def IN16 : I<0x6D, RawFrm, (outs), (ins),
960 "ins{w}", []>, OpSize;
961 def IN32 : I<0x6D, RawFrm, (outs), (ins),
964 //===----------------------------------------------------------------------===//
965 // Move Instructions...
967 let neverHasSideEffects = 1 in {
968 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
969 "mov{b}\t{$src, $dst|$dst, $src}", []>;
970 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
971 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
972 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
973 "mov{l}\t{$src, $dst|$dst, $src}", []>;
975 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
976 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
977 "mov{b}\t{$src, $dst|$dst, $src}",
978 [(set GR8:$dst, imm:$src)]>;
979 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
980 "mov{w}\t{$src, $dst|$dst, $src}",
981 [(set GR16:$dst, imm:$src)]>, OpSize;
982 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
983 "mov{l}\t{$src, $dst|$dst, $src}",
984 [(set GR32:$dst, imm:$src)]>;
987 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
988 "mov{b}\t{$src, $dst|$dst, $src}",
989 [(store (i8 imm:$src), addr:$dst)]>;
990 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
991 "mov{w}\t{$src, $dst|$dst, $src}",
992 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
993 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
994 "mov{l}\t{$src, $dst|$dst, $src}",
995 [(store (i32 imm:$src), addr:$dst)]>;
997 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
998 "mov{b}\t{$src, %al|%al, $src}", []>;
999 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
1000 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1001 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1002 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1004 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1005 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1006 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1007 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1008 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1009 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1011 // Moves to and from segment registers
1012 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1013 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1014 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1015 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1016 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1017 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1018 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1019 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1021 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1022 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1023 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1024 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1025 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1026 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1028 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1029 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1030 "mov{b}\t{$src, $dst|$dst, $src}",
1031 [(set GR8:$dst, (loadi8 addr:$src))]>;
1032 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1033 "mov{w}\t{$src, $dst|$dst, $src}",
1034 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1035 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1036 "mov{l}\t{$src, $dst|$dst, $src}",
1037 [(set GR32:$dst, (loadi32 addr:$src))]>;
1040 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1041 "mov{b}\t{$src, $dst|$dst, $src}",
1042 [(store GR8:$src, addr:$dst)]>;
1043 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1044 "mov{w}\t{$src, $dst|$dst, $src}",
1045 [(store GR16:$src, addr:$dst)]>, OpSize;
1046 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1047 "mov{l}\t{$src, $dst|$dst, $src}",
1048 [(store GR32:$src, addr:$dst)]>;
1050 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1051 let neverHasSideEffects = 1 in
1052 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1053 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1056 canFoldAsLoad = 1, isReMaterializable = 1 in
1057 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1058 "mov{l}\t{$src, $dst|$dst, $src}",
1062 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1063 "mov{l}\t{$src, $dst|$dst, $src}",
1066 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1067 // that they can be used for copying and storing h registers, which can't be
1068 // encoded when a REX prefix is present.
1069 let neverHasSideEffects = 1 in
1070 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1071 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1072 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1074 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1075 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1076 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1078 canFoldAsLoad = 1, isReMaterializable = 1 in
1079 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1080 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1081 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1083 // Moves to and from debug registers
1084 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1085 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1086 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1087 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1089 // Moves to and from control registers
1090 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1091 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1092 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1093 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1095 //===----------------------------------------------------------------------===//
1096 // Fixed-Register Multiplication and Division Instructions...
1099 // Extra precision multiplication
1101 // AL is really implied by AX, by the registers in Defs must match the
1102 // SDNode results (i8, i32).
1103 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1104 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1105 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1106 // This probably ought to be moved to a def : Pat<> if the
1107 // syntax can be accepted.
1108 [(set AL, (mul AL, GR8:$src)),
1109 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1111 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1112 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1114 []>, OpSize; // AX,DX = AX*GR16
1116 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1117 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1119 []>; // EAX,EDX = EAX*GR32
1121 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1122 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1124 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1125 // This probably ought to be moved to a def : Pat<> if the
1126 // syntax can be accepted.
1127 [(set AL, (mul AL, (loadi8 addr:$src))),
1128 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1130 let mayLoad = 1, neverHasSideEffects = 1 in {
1131 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1132 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1134 []>, OpSize; // AX,DX = AX*[mem16]
1136 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1137 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1139 []>; // EAX,EDX = EAX*[mem32]
1142 let neverHasSideEffects = 1 in {
1143 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1144 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1146 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1147 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1148 OpSize; // AX,DX = AX*GR16
1149 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1150 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1151 // EAX,EDX = EAX*GR32
1152 let mayLoad = 1 in {
1153 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1154 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1155 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1156 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1157 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1158 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1159 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1160 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1161 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1163 } // neverHasSideEffects
1165 // unsigned division/remainder
1166 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1167 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1168 "div{b}\t$src", []>;
1169 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1170 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1171 "div{w}\t$src", []>, OpSize;
1172 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1173 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1174 "div{l}\t$src", []>;
1175 let mayLoad = 1 in {
1176 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1177 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1178 "div{b}\t$src", []>;
1179 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1180 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1181 "div{w}\t$src", []>, OpSize;
1182 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1183 // EDX:EAX/[mem32] = EAX,EDX
1184 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1185 "div{l}\t$src", []>;
1188 // Signed division/remainder.
1189 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1190 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1191 "idiv{b}\t$src", []>;
1192 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1193 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1194 "idiv{w}\t$src", []>, OpSize;
1195 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1196 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1197 "idiv{l}\t$src", []>;
1198 let mayLoad = 1, mayLoad = 1 in {
1199 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1200 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1201 "idiv{b}\t$src", []>;
1202 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1203 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1204 "idiv{w}\t$src", []>, OpSize;
1205 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1206 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1207 // EDX:EAX/[mem32] = EAX,EDX
1208 "idiv{l}\t$src", []>;
1211 //===----------------------------------------------------------------------===//
1212 // Two address Instructions.
1214 let isTwoAddress = 1 in {
1216 // Conditional moves
1217 let Uses = [EFLAGS] in {
1219 let Predicates = [HasCMov] in {
1220 let isCommutable = 1 in {
1221 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1222 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1223 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1224 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1225 X86_COND_B, EFLAGS))]>,
1227 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1228 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1229 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1230 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1231 X86_COND_B, EFLAGS))]>,
1233 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1234 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1235 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1236 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1237 X86_COND_AE, EFLAGS))]>,
1239 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1240 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1241 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1242 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1243 X86_COND_AE, EFLAGS))]>,
1245 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1246 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1247 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1248 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1249 X86_COND_E, EFLAGS))]>,
1251 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1252 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1253 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1254 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1255 X86_COND_E, EFLAGS))]>,
1257 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1258 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1259 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1260 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1261 X86_COND_NE, EFLAGS))]>,
1263 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1264 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1265 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1266 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1267 X86_COND_NE, EFLAGS))]>,
1269 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1270 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1271 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1272 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1273 X86_COND_BE, EFLAGS))]>,
1275 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1276 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1277 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1278 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1279 X86_COND_BE, EFLAGS))]>,
1281 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1282 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1283 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1284 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1285 X86_COND_A, EFLAGS))]>,
1287 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1288 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1289 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1290 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1291 X86_COND_A, EFLAGS))]>,
1293 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1294 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1295 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1296 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1297 X86_COND_L, EFLAGS))]>,
1299 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1300 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1301 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1302 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1303 X86_COND_L, EFLAGS))]>,
1305 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1306 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1307 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1308 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1309 X86_COND_GE, EFLAGS))]>,
1311 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1312 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1313 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1315 X86_COND_GE, EFLAGS))]>,
1317 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1318 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1319 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1321 X86_COND_LE, EFLAGS))]>,
1323 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1324 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1325 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1327 X86_COND_LE, EFLAGS))]>,
1329 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1330 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1331 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1332 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1333 X86_COND_G, EFLAGS))]>,
1335 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1336 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1337 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1338 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1339 X86_COND_G, EFLAGS))]>,
1341 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1342 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1343 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1344 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1345 X86_COND_S, EFLAGS))]>,
1347 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1348 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1349 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1350 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1351 X86_COND_S, EFLAGS))]>,
1353 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1354 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1355 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1356 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1357 X86_COND_NS, EFLAGS))]>,
1359 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1360 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1361 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1362 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1363 X86_COND_NS, EFLAGS))]>,
1365 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1366 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1367 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1368 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1369 X86_COND_P, EFLAGS))]>,
1371 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1372 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1373 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1374 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1375 X86_COND_P, EFLAGS))]>,
1377 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1378 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1379 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1380 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1381 X86_COND_NP, EFLAGS))]>,
1383 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1384 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1385 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1386 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1387 X86_COND_NP, EFLAGS))]>,
1389 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1390 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1391 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1393 X86_COND_O, EFLAGS))]>,
1395 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1396 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1397 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1398 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1399 X86_COND_O, EFLAGS))]>,
1401 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1402 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1403 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1404 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1405 X86_COND_NO, EFLAGS))]>,
1407 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1408 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1409 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1410 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1411 X86_COND_NO, EFLAGS))]>,
1413 } // isCommutable = 1
1415 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1416 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1417 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1418 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1419 X86_COND_B, EFLAGS))]>,
1421 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1422 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1423 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1424 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1425 X86_COND_B, EFLAGS))]>,
1427 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1428 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1429 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1430 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1431 X86_COND_AE, EFLAGS))]>,
1433 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1434 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1435 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1437 X86_COND_AE, EFLAGS))]>,
1439 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1440 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1441 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1443 X86_COND_E, EFLAGS))]>,
1445 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1446 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1447 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1449 X86_COND_E, EFLAGS))]>,
1451 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1452 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1453 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1455 X86_COND_NE, EFLAGS))]>,
1457 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1458 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1459 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1461 X86_COND_NE, EFLAGS))]>,
1463 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1464 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1465 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1467 X86_COND_BE, EFLAGS))]>,
1469 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1470 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1471 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1472 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1473 X86_COND_BE, EFLAGS))]>,
1475 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1476 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1477 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1478 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1479 X86_COND_A, EFLAGS))]>,
1481 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1482 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1483 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1484 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1485 X86_COND_A, EFLAGS))]>,
1487 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1488 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1489 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1490 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1491 X86_COND_L, EFLAGS))]>,
1493 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1494 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1495 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1496 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1497 X86_COND_L, EFLAGS))]>,
1499 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1500 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1501 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1503 X86_COND_GE, EFLAGS))]>,
1505 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1506 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1507 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1508 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1509 X86_COND_GE, EFLAGS))]>,
1511 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1512 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1513 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1514 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1515 X86_COND_LE, EFLAGS))]>,
1517 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1518 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1519 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1521 X86_COND_LE, EFLAGS))]>,
1523 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1524 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1525 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1526 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1527 X86_COND_G, EFLAGS))]>,
1529 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1530 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1531 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1532 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1533 X86_COND_G, EFLAGS))]>,
1535 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1536 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1537 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1538 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1539 X86_COND_S, EFLAGS))]>,
1541 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1542 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1543 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1544 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1545 X86_COND_S, EFLAGS))]>,
1547 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1548 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1549 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1550 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1551 X86_COND_NS, EFLAGS))]>,
1553 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1554 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1555 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1556 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1557 X86_COND_NS, EFLAGS))]>,
1559 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1560 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1561 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1562 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1563 X86_COND_P, EFLAGS))]>,
1565 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1566 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1567 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1568 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1569 X86_COND_P, EFLAGS))]>,
1571 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1572 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1573 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1574 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1575 X86_COND_NP, EFLAGS))]>,
1577 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1578 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1579 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1580 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1581 X86_COND_NP, EFLAGS))]>,
1583 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1584 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1585 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1586 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1587 X86_COND_O, EFLAGS))]>,
1589 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1590 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1591 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1592 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1593 X86_COND_O, EFLAGS))]>,
1595 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1596 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1597 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1598 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1599 X86_COND_NO, EFLAGS))]>,
1601 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1602 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1603 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1604 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1605 X86_COND_NO, EFLAGS))]>,
1607 } // Predicates = [HasCMov]
1609 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1610 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1611 // however that requires promoting the operands, and can induce additional
1612 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1613 // clobber EFLAGS, because if one of the operands is zero, the expansion
1614 // could involve an xor.
1615 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1616 def CMOV_GR8 : I<0, Pseudo,
1617 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1618 "#CMOV_GR8 PSEUDO!",
1619 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1620 imm:$cond, EFLAGS))]>;
1622 let Predicates = [NoCMov] in {
1623 def CMOV_GR32 : I<0, Pseudo,
1624 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1625 "#CMOV_GR32* PSEUDO!",
1627 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1628 def CMOV_GR16 : I<0, Pseudo,
1629 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1630 "#CMOV_GR16* PSEUDO!",
1632 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1633 def CMOV_RFP32 : I<0, Pseudo,
1634 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1635 "#CMOV_RFP32 PSEUDO!",
1636 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1638 def CMOV_RFP64 : I<0, Pseudo,
1639 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1640 "#CMOV_RFP64 PSEUDO!",
1641 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1643 def CMOV_RFP80 : I<0, Pseudo,
1644 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1645 "#CMOV_RFP80 PSEUDO!",
1646 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1648 } // Predicates = [NoCMov]
1649 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1650 } // Uses = [EFLAGS]
1653 // unary instructions
1654 let CodeSize = 2 in {
1655 let Defs = [EFLAGS] in {
1656 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1657 [(set GR8:$dst, (ineg GR8:$src)),
1658 (implicit EFLAGS)]>;
1659 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1660 [(set GR16:$dst, (ineg GR16:$src)),
1661 (implicit EFLAGS)]>, OpSize;
1662 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1663 [(set GR32:$dst, (ineg GR32:$src)),
1664 (implicit EFLAGS)]>;
1665 let isTwoAddress = 0 in {
1666 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1667 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1668 (implicit EFLAGS)]>;
1669 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1670 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1671 (implicit EFLAGS)]>, OpSize;
1672 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1673 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1674 (implicit EFLAGS)]>;
1676 } // Defs = [EFLAGS]
1678 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1679 let AddedComplexity = 15 in {
1680 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1681 [(set GR8:$dst, (not GR8:$src))]>;
1682 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1683 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1684 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1685 [(set GR32:$dst, (not GR32:$src))]>;
1687 let isTwoAddress = 0 in {
1688 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1689 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1690 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1691 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1692 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1693 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1697 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1698 let Defs = [EFLAGS] in {
1700 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1701 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
1703 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1704 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1706 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
1707 OpSize, Requires<[In32BitMode]>;
1708 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1710 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
1711 Requires<[In32BitMode]>;
1713 let isTwoAddress = 0, CodeSize = 2 in {
1714 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1715 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1716 (implicit EFLAGS)]>;
1717 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1718 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1719 (implicit EFLAGS)]>,
1720 OpSize, Requires<[In32BitMode]>;
1721 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1722 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1723 (implicit EFLAGS)]>,
1724 Requires<[In32BitMode]>;
1728 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1729 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
1730 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1731 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1733 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
1734 OpSize, Requires<[In32BitMode]>;
1735 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1737 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
1738 Requires<[In32BitMode]>;
1741 let isTwoAddress = 0, CodeSize = 2 in {
1742 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1743 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1744 (implicit EFLAGS)]>;
1745 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1746 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1747 (implicit EFLAGS)]>,
1748 OpSize, Requires<[In32BitMode]>;
1749 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1750 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1751 (implicit EFLAGS)]>,
1752 Requires<[In32BitMode]>;
1754 } // Defs = [EFLAGS]
1756 // Logical operators...
1757 let Defs = [EFLAGS] in {
1758 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1759 def AND8rr : I<0x20, MRMDestReg,
1760 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1761 "and{b}\t{$src2, $dst|$dst, $src2}",
1762 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1763 def AND16rr : I<0x21, MRMDestReg,
1764 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1765 "and{w}\t{$src2, $dst|$dst, $src2}",
1766 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1767 GR16:$src2))]>, OpSize;
1768 def AND32rr : I<0x21, MRMDestReg,
1769 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1770 "and{l}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1775 // AND instructions with the destination register in REG and the source register
1776 // in R/M. Included for the disassembler.
1777 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1778 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1779 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1780 (ins GR16:$src1, GR16:$src2),
1781 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1782 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1783 (ins GR32:$src1, GR32:$src2),
1784 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1786 def AND8rm : I<0x22, MRMSrcMem,
1787 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1788 "and{b}\t{$src2, $dst|$dst, $src2}",
1789 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1790 (loadi8 addr:$src2)))]>;
1791 def AND16rm : I<0x23, MRMSrcMem,
1792 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1793 "and{w}\t{$src2, $dst|$dst, $src2}",
1794 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1795 (loadi16 addr:$src2)))]>,
1797 def AND32rm : I<0x23, MRMSrcMem,
1798 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1799 "and{l}\t{$src2, $dst|$dst, $src2}",
1800 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1801 (loadi32 addr:$src2)))]>;
1803 def AND8ri : Ii8<0x80, MRM4r,
1804 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1805 "and{b}\t{$src2, $dst|$dst, $src2}",
1806 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1808 def AND16ri : Ii16<0x81, MRM4r,
1809 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1810 "and{w}\t{$src2, $dst|$dst, $src2}",
1811 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1812 imm:$src2))]>, OpSize;
1813 def AND32ri : Ii32<0x81, MRM4r,
1814 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1815 "and{l}\t{$src2, $dst|$dst, $src2}",
1816 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1818 def AND16ri8 : Ii8<0x83, MRM4r,
1819 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1820 "and{w}\t{$src2, $dst|$dst, $src2}",
1821 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1822 i16immSExt8:$src2))]>,
1824 def AND32ri8 : Ii8<0x83, MRM4r,
1825 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1826 "and{l}\t{$src2, $dst|$dst, $src2}",
1827 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1828 i32immSExt8:$src2))]>;
1830 let isTwoAddress = 0 in {
1831 def AND8mr : I<0x20, MRMDestMem,
1832 (outs), (ins i8mem :$dst, GR8 :$src),
1833 "and{b}\t{$src, $dst|$dst, $src}",
1834 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1835 (implicit EFLAGS)]>;
1836 def AND16mr : I<0x21, MRMDestMem,
1837 (outs), (ins i16mem:$dst, GR16:$src),
1838 "and{w}\t{$src, $dst|$dst, $src}",
1839 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1840 (implicit EFLAGS)]>,
1842 def AND32mr : I<0x21, MRMDestMem,
1843 (outs), (ins i32mem:$dst, GR32:$src),
1844 "and{l}\t{$src, $dst|$dst, $src}",
1845 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1846 (implicit EFLAGS)]>;
1847 def AND8mi : Ii8<0x80, MRM4m,
1848 (outs), (ins i8mem :$dst, i8imm :$src),
1849 "and{b}\t{$src, $dst|$dst, $src}",
1850 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1851 (implicit EFLAGS)]>;
1852 def AND16mi : Ii16<0x81, MRM4m,
1853 (outs), (ins i16mem:$dst, i16imm:$src),
1854 "and{w}\t{$src, $dst|$dst, $src}",
1855 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1856 (implicit EFLAGS)]>,
1858 def AND32mi : Ii32<0x81, MRM4m,
1859 (outs), (ins i32mem:$dst, i32imm:$src),
1860 "and{l}\t{$src, $dst|$dst, $src}",
1861 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1862 (implicit EFLAGS)]>;
1863 def AND16mi8 : Ii8<0x83, MRM4m,
1864 (outs), (ins i16mem:$dst, i16i8imm :$src),
1865 "and{w}\t{$src, $dst|$dst, $src}",
1866 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1867 (implicit EFLAGS)]>,
1869 def AND32mi8 : Ii8<0x83, MRM4m,
1870 (outs), (ins i32mem:$dst, i32i8imm :$src),
1871 "and{l}\t{$src, $dst|$dst, $src}",
1872 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1873 (implicit EFLAGS)]>;
1875 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1876 "and{b}\t{$src, %al|%al, $src}", []>;
1877 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1878 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1879 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1880 "and{l}\t{$src, %eax|%eax, $src}", []>;
1885 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1886 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1887 (ins GR8 :$src1, GR8 :$src2),
1888 "or{b}\t{$src2, $dst|$dst, $src2}",
1889 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1890 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1891 (ins GR16:$src1, GR16:$src2),
1892 "or{w}\t{$src2, $dst|$dst, $src2}",
1893 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1895 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1896 (ins GR32:$src1, GR32:$src2),
1897 "or{l}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1901 // OR instructions with the destination register in REG and the source register
1902 // in R/M. Included for the disassembler.
1903 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1904 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1905 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1906 (ins GR16:$src1, GR16:$src2),
1907 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1908 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1909 (ins GR32:$src1, GR32:$src2),
1910 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1912 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1913 (ins GR8 :$src1, i8mem :$src2),
1914 "or{b}\t{$src2, $dst|$dst, $src2}",
1915 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1916 (load addr:$src2)))]>;
1917 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1918 (ins GR16:$src1, i16mem:$src2),
1919 "or{w}\t{$src2, $dst|$dst, $src2}",
1920 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1921 (load addr:$src2)))]>,
1923 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1924 (ins GR32:$src1, i32mem:$src2),
1925 "or{l}\t{$src2, $dst|$dst, $src2}",
1926 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1927 (load addr:$src2)))]>;
1929 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1930 (ins GR8 :$src1, i8imm:$src2),
1931 "or{b}\t{$src2, $dst|$dst, $src2}",
1932 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1933 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1934 (ins GR16:$src1, i16imm:$src2),
1935 "or{w}\t{$src2, $dst|$dst, $src2}",
1936 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1937 imm:$src2))]>, OpSize;
1938 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1939 (ins GR32:$src1, i32imm:$src2),
1940 "or{l}\t{$src2, $dst|$dst, $src2}",
1941 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1944 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1945 (ins GR16:$src1, i16i8imm:$src2),
1946 "or{w}\t{$src2, $dst|$dst, $src2}",
1947 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1948 i16immSExt8:$src2))]>, OpSize;
1949 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1950 (ins GR32:$src1, i32i8imm:$src2),
1951 "or{l}\t{$src2, $dst|$dst, $src2}",
1952 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1953 i32immSExt8:$src2))]>;
1954 let isTwoAddress = 0 in {
1955 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1956 "or{b}\t{$src, $dst|$dst, $src}",
1957 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1958 (implicit EFLAGS)]>;
1959 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1960 "or{w}\t{$src, $dst|$dst, $src}",
1961 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1962 (implicit EFLAGS)]>, OpSize;
1963 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1964 "or{l}\t{$src, $dst|$dst, $src}",
1965 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1966 (implicit EFLAGS)]>;
1967 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1968 "or{b}\t{$src, $dst|$dst, $src}",
1969 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1970 (implicit EFLAGS)]>;
1971 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1972 "or{w}\t{$src, $dst|$dst, $src}",
1973 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1974 (implicit EFLAGS)]>,
1976 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1977 "or{l}\t{$src, $dst|$dst, $src}",
1978 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1979 (implicit EFLAGS)]>;
1980 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1981 "or{w}\t{$src, $dst|$dst, $src}",
1982 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1983 (implicit EFLAGS)]>,
1985 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1986 "or{l}\t{$src, $dst|$dst, $src}",
1987 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1988 (implicit EFLAGS)]>;
1990 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1991 "or{b}\t{$src, %al|%al, $src}", []>;
1992 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1993 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1994 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1995 "or{l}\t{$src, %eax|%eax, $src}", []>;
1996 } // isTwoAddress = 0
1999 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2000 def XOR8rr : I<0x30, MRMDestReg,
2001 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2002 "xor{b}\t{$src2, $dst|$dst, $src2}",
2003 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2005 def XOR16rr : I<0x31, MRMDestReg,
2006 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2007 "xor{w}\t{$src2, $dst|$dst, $src2}",
2008 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2009 GR16:$src2))]>, OpSize;
2010 def XOR32rr : I<0x31, MRMDestReg,
2011 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2012 "xor{l}\t{$src2, $dst|$dst, $src2}",
2013 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2015 } // isCommutable = 1
2017 // XOR instructions with the destination register in REG and the source register
2018 // in R/M. Included for the disassembler.
2019 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2020 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2021 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2022 (ins GR16:$src1, GR16:$src2),
2023 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2024 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2025 (ins GR32:$src1, GR32:$src2),
2026 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2028 def XOR8rm : I<0x32, MRMSrcMem,
2029 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2030 "xor{b}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2032 (load addr:$src2)))]>;
2033 def XOR16rm : I<0x33, MRMSrcMem,
2034 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2035 "xor{w}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2037 (load addr:$src2)))]>,
2039 def XOR32rm : I<0x33, MRMSrcMem,
2040 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2041 "xor{l}\t{$src2, $dst|$dst, $src2}",
2042 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2043 (load addr:$src2)))]>;
2045 def XOR8ri : Ii8<0x80, MRM6r,
2046 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2047 "xor{b}\t{$src2, $dst|$dst, $src2}",
2048 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2049 def XOR16ri : Ii16<0x81, MRM6r,
2050 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2051 "xor{w}\t{$src2, $dst|$dst, $src2}",
2052 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2053 imm:$src2))]>, OpSize;
2054 def XOR32ri : Ii32<0x81, MRM6r,
2055 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2056 "xor{l}\t{$src2, $dst|$dst, $src2}",
2057 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2059 def XOR16ri8 : Ii8<0x83, MRM6r,
2060 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2061 "xor{w}\t{$src2, $dst|$dst, $src2}",
2062 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2063 i16immSExt8:$src2))]>,
2065 def XOR32ri8 : Ii8<0x83, MRM6r,
2066 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2067 "xor{l}\t{$src2, $dst|$dst, $src2}",
2068 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2069 i32immSExt8:$src2))]>;
2071 let isTwoAddress = 0 in {
2072 def XOR8mr : I<0x30, MRMDestMem,
2073 (outs), (ins i8mem :$dst, GR8 :$src),
2074 "xor{b}\t{$src, $dst|$dst, $src}",
2075 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2076 (implicit EFLAGS)]>;
2077 def XOR16mr : I<0x31, MRMDestMem,
2078 (outs), (ins i16mem:$dst, GR16:$src),
2079 "xor{w}\t{$src, $dst|$dst, $src}",
2080 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2081 (implicit EFLAGS)]>,
2083 def XOR32mr : I<0x31, MRMDestMem,
2084 (outs), (ins i32mem:$dst, GR32:$src),
2085 "xor{l}\t{$src, $dst|$dst, $src}",
2086 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2087 (implicit EFLAGS)]>;
2088 def XOR8mi : Ii8<0x80, MRM6m,
2089 (outs), (ins i8mem :$dst, i8imm :$src),
2090 "xor{b}\t{$src, $dst|$dst, $src}",
2091 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2092 (implicit EFLAGS)]>;
2093 def XOR16mi : Ii16<0x81, MRM6m,
2094 (outs), (ins i16mem:$dst, i16imm:$src),
2095 "xor{w}\t{$src, $dst|$dst, $src}",
2096 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2097 (implicit EFLAGS)]>,
2099 def XOR32mi : Ii32<0x81, MRM6m,
2100 (outs), (ins i32mem:$dst, i32imm:$src),
2101 "xor{l}\t{$src, $dst|$dst, $src}",
2102 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2103 (implicit EFLAGS)]>;
2104 def XOR16mi8 : Ii8<0x83, MRM6m,
2105 (outs), (ins i16mem:$dst, i16i8imm :$src),
2106 "xor{w}\t{$src, $dst|$dst, $src}",
2107 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2108 (implicit EFLAGS)]>,
2110 def XOR32mi8 : Ii8<0x83, MRM6m,
2111 (outs), (ins i32mem:$dst, i32i8imm :$src),
2112 "xor{l}\t{$src, $dst|$dst, $src}",
2113 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2114 (implicit EFLAGS)]>;
2116 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2117 "xor{b}\t{$src, %al|%al, $src}", []>;
2118 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2119 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2120 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2121 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2122 } // isTwoAddress = 0
2123 } // Defs = [EFLAGS]
2125 // Shift instructions
2126 let Defs = [EFLAGS] in {
2127 let Uses = [CL] in {
2128 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2129 "shl{b}\t{%cl, $dst|$dst, CL}",
2130 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2131 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2132 "shl{w}\t{%cl, $dst|$dst, CL}",
2133 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2134 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2135 "shl{l}\t{%cl, $dst|$dst, CL}",
2136 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2139 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2140 "shl{b}\t{$src2, $dst|$dst, $src2}",
2141 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2142 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2143 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2144 "shl{w}\t{$src2, $dst|$dst, $src2}",
2145 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2146 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2147 "shl{l}\t{$src2, $dst|$dst, $src2}",
2148 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2150 // NOTE: We don't include patterns for shifts of a register by one, because
2151 // 'add reg,reg' is cheaper.
2153 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2154 "shl{b}\t$dst", []>;
2155 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2156 "shl{w}\t$dst", []>, OpSize;
2157 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2158 "shl{l}\t$dst", []>;
2160 } // isConvertibleToThreeAddress = 1
2162 let isTwoAddress = 0 in {
2163 let Uses = [CL] in {
2164 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2165 "shl{b}\t{%cl, $dst|$dst, CL}",
2166 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2167 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2168 "shl{w}\t{%cl, $dst|$dst, CL}",
2169 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2170 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2171 "shl{l}\t{%cl, $dst|$dst, CL}",
2172 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2174 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2175 "shl{b}\t{$src, $dst|$dst, $src}",
2176 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2177 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2178 "shl{w}\t{$src, $dst|$dst, $src}",
2179 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2181 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2182 "shl{l}\t{$src, $dst|$dst, $src}",
2183 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2186 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2188 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2189 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2191 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2193 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2195 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2198 let Uses = [CL] in {
2199 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2200 "shr{b}\t{%cl, $dst|$dst, CL}",
2201 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2202 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2203 "shr{w}\t{%cl, $dst|$dst, CL}",
2204 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2205 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2206 "shr{l}\t{%cl, $dst|$dst, CL}",
2207 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2210 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2211 "shr{b}\t{$src2, $dst|$dst, $src2}",
2212 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2213 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2214 "shr{w}\t{$src2, $dst|$dst, $src2}",
2215 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2216 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2217 "shr{l}\t{$src2, $dst|$dst, $src2}",
2218 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2221 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2223 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2224 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2226 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2227 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2229 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2231 let isTwoAddress = 0 in {
2232 let Uses = [CL] in {
2233 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2234 "shr{b}\t{%cl, $dst|$dst, CL}",
2235 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2236 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2237 "shr{w}\t{%cl, $dst|$dst, CL}",
2238 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2240 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2241 "shr{l}\t{%cl, $dst|$dst, CL}",
2242 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2244 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2245 "shr{b}\t{$src, $dst|$dst, $src}",
2246 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2247 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2248 "shr{w}\t{$src, $dst|$dst, $src}",
2249 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2251 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2252 "shr{l}\t{$src, $dst|$dst, $src}",
2253 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2256 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2258 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2259 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2261 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2262 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2264 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2267 let Uses = [CL] in {
2268 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2269 "sar{b}\t{%cl, $dst|$dst, CL}",
2270 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2271 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2272 "sar{w}\t{%cl, $dst|$dst, CL}",
2273 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2274 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2275 "sar{l}\t{%cl, $dst|$dst, CL}",
2276 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2279 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2280 "sar{b}\t{$src2, $dst|$dst, $src2}",
2281 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2282 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2283 "sar{w}\t{$src2, $dst|$dst, $src2}",
2284 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2286 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2287 "sar{l}\t{$src2, $dst|$dst, $src2}",
2288 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2291 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2293 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2294 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2296 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2297 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2299 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2301 let isTwoAddress = 0 in {
2302 let Uses = [CL] in {
2303 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2304 "sar{b}\t{%cl, $dst|$dst, CL}",
2305 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2306 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2307 "sar{w}\t{%cl, $dst|$dst, CL}",
2308 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2309 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2310 "sar{l}\t{%cl, $dst|$dst, CL}",
2311 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2313 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2314 "sar{b}\t{$src, $dst|$dst, $src}",
2315 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2316 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2317 "sar{w}\t{$src, $dst|$dst, $src}",
2318 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2320 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2321 "sar{l}\t{$src, $dst|$dst, $src}",
2322 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2325 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2327 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2328 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2330 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2332 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2334 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2337 // Rotate instructions
2339 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2340 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2341 let Uses = [CL] in {
2342 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2343 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2345 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2346 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2348 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2349 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2350 let Uses = [CL] in {
2351 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2352 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2354 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2355 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2357 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2358 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2359 let Uses = [CL] in {
2360 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2361 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2363 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2364 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2366 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2367 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2368 let Uses = [CL] in {
2369 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2370 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2372 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2373 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2375 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2376 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2377 let Uses = [CL] in {
2378 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2379 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2381 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2382 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2384 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2385 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2386 let Uses = [CL] in {
2387 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2388 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2390 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2391 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2393 let isTwoAddress = 0 in {
2394 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2395 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2396 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2397 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2398 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2399 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2400 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2401 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2402 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2403 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2404 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2405 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2406 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2407 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2408 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2409 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2410 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2411 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2412 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2413 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2414 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2415 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2416 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2417 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2419 let Uses = [CL] in {
2420 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2421 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2422 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2423 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2424 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2425 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2426 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2427 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2428 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2429 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2430 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2431 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2435 // FIXME: provide shorter instructions when imm8 == 1
2436 let Uses = [CL] in {
2437 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2438 "rol{b}\t{%cl, $dst|$dst, CL}",
2439 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2440 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2441 "rol{w}\t{%cl, $dst|$dst, CL}",
2442 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2443 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2444 "rol{l}\t{%cl, $dst|$dst, CL}",
2445 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2448 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2449 "rol{b}\t{$src2, $dst|$dst, $src2}",
2450 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2451 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2452 "rol{w}\t{$src2, $dst|$dst, $src2}",
2453 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2455 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2456 "rol{l}\t{$src2, $dst|$dst, $src2}",
2457 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2460 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2462 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2463 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2465 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2466 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2468 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2470 let isTwoAddress = 0 in {
2471 let Uses = [CL] in {
2472 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2473 "rol{b}\t{%cl, $dst|$dst, CL}",
2474 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2475 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2476 "rol{w}\t{%cl, $dst|$dst, CL}",
2477 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2478 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2479 "rol{l}\t{%cl, $dst|$dst, CL}",
2480 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2482 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2483 "rol{b}\t{$src, $dst|$dst, $src}",
2484 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2485 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2486 "rol{w}\t{$src, $dst|$dst, $src}",
2487 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2489 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2490 "rol{l}\t{$src, $dst|$dst, $src}",
2491 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2494 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2496 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2497 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2499 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2501 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2503 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2506 let Uses = [CL] in {
2507 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2508 "ror{b}\t{%cl, $dst|$dst, CL}",
2509 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2510 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2511 "ror{w}\t{%cl, $dst|$dst, CL}",
2512 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2513 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2514 "ror{l}\t{%cl, $dst|$dst, CL}",
2515 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2518 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2519 "ror{b}\t{$src2, $dst|$dst, $src2}",
2520 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2521 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2522 "ror{w}\t{$src2, $dst|$dst, $src2}",
2523 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2525 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2526 "ror{l}\t{$src2, $dst|$dst, $src2}",
2527 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2530 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2532 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2533 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2535 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2536 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2538 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2540 let isTwoAddress = 0 in {
2541 let Uses = [CL] in {
2542 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2543 "ror{b}\t{%cl, $dst|$dst, CL}",
2544 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2545 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2546 "ror{w}\t{%cl, $dst|$dst, CL}",
2547 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2548 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2549 "ror{l}\t{%cl, $dst|$dst, CL}",
2550 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2552 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2553 "ror{b}\t{$src, $dst|$dst, $src}",
2554 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2555 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2556 "ror{w}\t{$src, $dst|$dst, $src}",
2557 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2559 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2560 "ror{l}\t{$src, $dst|$dst, $src}",
2561 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2564 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2566 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2567 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2569 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2571 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2573 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2578 // Double shift instructions (generalizations of rotate)
2579 let Uses = [CL] in {
2580 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2581 (ins GR32:$src1, GR32:$src2),
2582 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2583 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2584 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2585 (ins GR32:$src1, GR32:$src2),
2586 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2587 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2588 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2589 (ins GR16:$src1, GR16:$src2),
2590 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2591 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2593 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2594 (ins GR16:$src1, GR16:$src2),
2595 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2596 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2600 let isCommutable = 1 in { // These instructions commute to each other.
2601 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2603 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2604 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2605 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2608 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2610 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2611 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2612 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2615 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2617 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2618 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2619 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2622 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2624 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2625 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2626 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2631 let isTwoAddress = 0 in {
2632 let Uses = [CL] in {
2633 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2634 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2635 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2637 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2638 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2639 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2642 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2643 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2644 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2645 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2646 (i8 imm:$src3)), addr:$dst)]>,
2648 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2649 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2650 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2651 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2652 (i8 imm:$src3)), addr:$dst)]>,
2655 let Uses = [CL] in {
2656 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2657 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2658 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2659 addr:$dst)]>, TB, OpSize;
2660 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2661 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2662 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2663 addr:$dst)]>, TB, OpSize;
2665 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2666 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2667 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2668 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2669 (i8 imm:$src3)), addr:$dst)]>,
2671 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2672 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2673 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2674 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2675 (i8 imm:$src3)), addr:$dst)]>,
2678 } // Defs = [EFLAGS]
2682 let Defs = [EFLAGS] in {
2683 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2684 // Register-Register Addition
2685 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2686 (ins GR8 :$src1, GR8 :$src2),
2687 "add{b}\t{$src2, $dst|$dst, $src2}",
2688 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2690 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2691 // Register-Register Addition
2692 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2693 (ins GR16:$src1, GR16:$src2),
2694 "add{w}\t{$src2, $dst|$dst, $src2}",
2695 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2696 GR16:$src2))]>, OpSize;
2697 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2698 (ins GR32:$src1, GR32:$src2),
2699 "add{l}\t{$src2, $dst|$dst, $src2}",
2700 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2702 } // end isConvertibleToThreeAddress
2703 } // end isCommutable
2705 // These are alternate spellings for use by the disassembler, we mark them as
2706 // code gen only to ensure they aren't matched by the assembler.
2707 let isCodeGenOnly = 1 in {
2708 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2709 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2710 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2711 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2712 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2713 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2716 // Register-Memory Addition
2717 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2718 (ins GR8 :$src1, i8mem :$src2),
2719 "add{b}\t{$src2, $dst|$dst, $src2}",
2720 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2721 (load addr:$src2)))]>;
2722 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2723 (ins GR16:$src1, i16mem:$src2),
2724 "add{w}\t{$src2, $dst|$dst, $src2}",
2725 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2726 (load addr:$src2)))]>, OpSize;
2727 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2728 (ins GR32:$src1, i32mem:$src2),
2729 "add{l}\t{$src2, $dst|$dst, $src2}",
2730 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2731 (load addr:$src2)))]>;
2733 // Register-Integer Addition
2734 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2735 "add{b}\t{$src2, $dst|$dst, $src2}",
2736 [(set GR8:$dst, EFLAGS,
2737 (X86add_flag GR8:$src1, imm:$src2))]>;
2739 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2740 // Register-Integer Addition
2741 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2742 (ins GR16:$src1, i16imm:$src2),
2743 "add{w}\t{$src2, $dst|$dst, $src2}",
2744 [(set GR16:$dst, EFLAGS,
2745 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2746 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2747 (ins GR32:$src1, i32imm:$src2),
2748 "add{l}\t{$src2, $dst|$dst, $src2}",
2749 [(set GR32:$dst, EFLAGS,
2750 (X86add_flag GR32:$src1, imm:$src2))]>;
2751 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2752 (ins GR16:$src1, i16i8imm:$src2),
2753 "add{w}\t{$src2, $dst|$dst, $src2}",
2754 [(set GR16:$dst, EFLAGS,
2755 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2756 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2757 (ins GR32:$src1, i32i8imm:$src2),
2758 "add{l}\t{$src2, $dst|$dst, $src2}",
2759 [(set GR32:$dst, EFLAGS,
2760 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2763 let isTwoAddress = 0 in {
2764 // Memory-Register Addition
2765 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2766 "add{b}\t{$src2, $dst|$dst, $src2}",
2767 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2768 (implicit EFLAGS)]>;
2769 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2770 "add{w}\t{$src2, $dst|$dst, $src2}",
2771 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2772 (implicit EFLAGS)]>, OpSize;
2773 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2774 "add{l}\t{$src2, $dst|$dst, $src2}",
2775 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2776 (implicit EFLAGS)]>;
2777 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2778 "add{b}\t{$src2, $dst|$dst, $src2}",
2779 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2780 (implicit EFLAGS)]>;
2781 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2782 "add{w}\t{$src2, $dst|$dst, $src2}",
2783 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2784 (implicit EFLAGS)]>, OpSize;
2785 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2786 "add{l}\t{$src2, $dst|$dst, $src2}",
2787 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2788 (implicit EFLAGS)]>;
2789 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2790 "add{w}\t{$src2, $dst|$dst, $src2}",
2791 [(store (add (load addr:$dst), i16immSExt8:$src2),
2793 (implicit EFLAGS)]>, OpSize;
2794 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2795 "add{l}\t{$src2, $dst|$dst, $src2}",
2796 [(store (add (load addr:$dst), i32immSExt8:$src2),
2798 (implicit EFLAGS)]>;
2801 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2802 "add{b}\t{$src, %al|%al, $src}", []>;
2803 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2804 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2805 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2806 "add{l}\t{$src, %eax|%eax, $src}", []>;
2809 let Uses = [EFLAGS] in {
2810 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2811 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2812 "adc{b}\t{$src2, $dst|$dst, $src2}",
2813 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2814 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2815 (ins GR16:$src1, GR16:$src2),
2816 "adc{w}\t{$src2, $dst|$dst, $src2}",
2817 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2818 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2819 (ins GR32:$src1, GR32:$src2),
2820 "adc{l}\t{$src2, $dst|$dst, $src2}",
2821 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2824 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2825 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2826 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2827 (ins GR16:$src1, GR16:$src2),
2828 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2829 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2830 (ins GR32:$src1, GR32:$src2),
2831 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2833 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2834 (ins GR8:$src1, i8mem:$src2),
2835 "adc{b}\t{$src2, $dst|$dst, $src2}",
2836 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2837 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2838 (ins GR16:$src1, i16mem:$src2),
2839 "adc{w}\t{$src2, $dst|$dst, $src2}",
2840 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2842 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2843 (ins GR32:$src1, i32mem:$src2),
2844 "adc{l}\t{$src2, $dst|$dst, $src2}",
2845 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2846 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2847 "adc{b}\t{$src2, $dst|$dst, $src2}",
2848 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2849 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2850 (ins GR16:$src1, i16imm:$src2),
2851 "adc{w}\t{$src2, $dst|$dst, $src2}",
2852 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2853 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2854 (ins GR16:$src1, i16i8imm:$src2),
2855 "adc{w}\t{$src2, $dst|$dst, $src2}",
2856 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2858 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2859 (ins GR32:$src1, i32imm:$src2),
2860 "adc{l}\t{$src2, $dst|$dst, $src2}",
2861 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2862 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2863 (ins GR32:$src1, i32i8imm:$src2),
2864 "adc{l}\t{$src2, $dst|$dst, $src2}",
2865 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2867 let isTwoAddress = 0 in {
2868 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2869 "adc{b}\t{$src2, $dst|$dst, $src2}",
2870 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2871 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2872 "adc{w}\t{$src2, $dst|$dst, $src2}",
2873 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2875 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2876 "adc{l}\t{$src2, $dst|$dst, $src2}",
2877 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2878 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2879 "adc{b}\t{$src2, $dst|$dst, $src2}",
2880 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2881 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2882 "adc{w}\t{$src2, $dst|$dst, $src2}",
2883 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2885 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2886 "adc{w}\t{$src2, $dst|$dst, $src2}",
2887 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2889 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2890 "adc{l}\t{$src2, $dst|$dst, $src2}",
2891 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2892 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2893 "adc{l}\t{$src2, $dst|$dst, $src2}",
2894 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2896 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2897 "adc{b}\t{$src, %al|%al, $src}", []>;
2898 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2899 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2900 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2901 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2903 } // Uses = [EFLAGS]
2905 // Register-Register Subtraction
2906 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2907 "sub{b}\t{$src2, $dst|$dst, $src2}",
2908 [(set GR8:$dst, EFLAGS,
2909 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2910 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2911 "sub{w}\t{$src2, $dst|$dst, $src2}",
2912 [(set GR16:$dst, EFLAGS,
2913 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2914 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2915 "sub{l}\t{$src2, $dst|$dst, $src2}",
2916 [(set GR32:$dst, EFLAGS,
2917 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2919 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2920 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2921 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2922 (ins GR16:$src1, GR16:$src2),
2923 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2924 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2925 (ins GR32:$src1, GR32:$src2),
2926 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2928 // Register-Memory Subtraction
2929 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2930 (ins GR8 :$src1, i8mem :$src2),
2931 "sub{b}\t{$src2, $dst|$dst, $src2}",
2932 [(set GR8:$dst, EFLAGS,
2933 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2934 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2935 (ins GR16:$src1, i16mem:$src2),
2936 "sub{w}\t{$src2, $dst|$dst, $src2}",
2937 [(set GR16:$dst, EFLAGS,
2938 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2939 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2940 (ins GR32:$src1, i32mem:$src2),
2941 "sub{l}\t{$src2, $dst|$dst, $src2}",
2942 [(set GR32:$dst, EFLAGS,
2943 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2945 // Register-Integer Subtraction
2946 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2947 (ins GR8:$src1, i8imm:$src2),
2948 "sub{b}\t{$src2, $dst|$dst, $src2}",
2949 [(set GR8:$dst, EFLAGS,
2950 (X86sub_flag GR8:$src1, imm:$src2))]>;
2951 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2952 (ins GR16:$src1, i16imm:$src2),
2953 "sub{w}\t{$src2, $dst|$dst, $src2}",
2954 [(set GR16:$dst, EFLAGS,
2955 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2956 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2957 (ins GR32:$src1, i32imm:$src2),
2958 "sub{l}\t{$src2, $dst|$dst, $src2}",
2959 [(set GR32:$dst, EFLAGS,
2960 (X86sub_flag GR32:$src1, imm:$src2))]>;
2961 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2962 (ins GR16:$src1, i16i8imm:$src2),
2963 "sub{w}\t{$src2, $dst|$dst, $src2}",
2964 [(set GR16:$dst, EFLAGS,
2965 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2966 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2967 (ins GR32:$src1, i32i8imm:$src2),
2968 "sub{l}\t{$src2, $dst|$dst, $src2}",
2969 [(set GR32:$dst, EFLAGS,
2970 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2972 let isTwoAddress = 0 in {
2973 // Memory-Register Subtraction
2974 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2975 "sub{b}\t{$src2, $dst|$dst, $src2}",
2976 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2977 (implicit EFLAGS)]>;
2978 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2979 "sub{w}\t{$src2, $dst|$dst, $src2}",
2980 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2981 (implicit EFLAGS)]>, OpSize;
2982 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2983 "sub{l}\t{$src2, $dst|$dst, $src2}",
2984 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2985 (implicit EFLAGS)]>;
2987 // Memory-Integer Subtraction
2988 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2989 "sub{b}\t{$src2, $dst|$dst, $src2}",
2990 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2991 (implicit EFLAGS)]>;
2992 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2993 "sub{w}\t{$src2, $dst|$dst, $src2}",
2994 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2995 (implicit EFLAGS)]>, OpSize;
2996 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2997 "sub{l}\t{$src2, $dst|$dst, $src2}",
2998 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2999 (implicit EFLAGS)]>;
3000 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3001 "sub{w}\t{$src2, $dst|$dst, $src2}",
3002 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3004 (implicit EFLAGS)]>, OpSize;
3005 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3006 "sub{l}\t{$src2, $dst|$dst, $src2}",
3007 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3009 (implicit EFLAGS)]>;
3011 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3012 "sub{b}\t{$src, %al|%al, $src}", []>;
3013 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3014 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3015 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3016 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3019 let Uses = [EFLAGS] in {
3020 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3021 (ins GR8:$src1, GR8:$src2),
3022 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3023 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3024 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3025 (ins GR16:$src1, GR16:$src2),
3026 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3027 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3028 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3029 (ins GR32:$src1, GR32:$src2),
3030 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3031 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3033 let isTwoAddress = 0 in {
3034 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3035 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3036 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3037 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3038 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3039 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3041 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3042 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3043 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3044 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3045 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3046 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3047 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3048 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3049 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3051 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3052 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3053 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3055 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3056 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3057 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3058 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3059 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3060 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3062 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3063 "sbb{b}\t{$src, %al|%al, $src}", []>;
3064 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3065 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3066 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3067 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3070 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3071 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3072 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3073 (ins GR16:$src1, GR16:$src2),
3074 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3075 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3076 (ins GR32:$src1, GR32:$src2),
3077 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3079 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3080 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3081 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3082 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3083 (ins GR16:$src1, i16mem:$src2),
3084 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3085 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3087 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3088 (ins GR32:$src1, i32mem:$src2),
3089 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3090 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3091 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3092 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3093 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3094 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3095 (ins GR16:$src1, i16imm:$src2),
3096 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3097 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3098 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3099 (ins GR16:$src1, i16i8imm:$src2),
3100 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3101 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3103 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3104 (ins GR32:$src1, i32imm:$src2),
3105 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3106 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3107 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3108 (ins GR32:$src1, i32i8imm:$src2),
3109 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3110 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3111 } // Uses = [EFLAGS]
3112 } // Defs = [EFLAGS]
3114 let Defs = [EFLAGS] in {
3115 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3116 // Register-Register Signed Integer Multiply
3117 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3118 "imul{w}\t{$src2, $dst|$dst, $src2}",
3119 [(set GR16:$dst, EFLAGS,
3120 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3121 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3122 "imul{l}\t{$src2, $dst|$dst, $src2}",
3123 [(set GR32:$dst, EFLAGS,
3124 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3127 // Register-Memory Signed Integer Multiply
3128 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3129 (ins GR16:$src1, i16mem:$src2),
3130 "imul{w}\t{$src2, $dst|$dst, $src2}",
3131 [(set GR16:$dst, EFLAGS,
3132 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3134 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3135 (ins GR32:$src1, i32mem:$src2),
3136 "imul{l}\t{$src2, $dst|$dst, $src2}",
3137 [(set GR32:$dst, EFLAGS,
3138 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3139 } // Defs = [EFLAGS]
3140 } // end Two Address instructions
3142 // Suprisingly enough, these are not two address instructions!
3143 let Defs = [EFLAGS] in {
3144 // Register-Integer Signed Integer Multiply
3145 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3146 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3147 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3148 [(set GR16:$dst, EFLAGS,
3149 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3150 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3151 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3152 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3153 [(set GR32:$dst, EFLAGS,
3154 (X86smul_flag GR32:$src1, imm:$src2))]>;
3155 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3156 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3157 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3158 [(set GR16:$dst, EFLAGS,
3159 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3161 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3162 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3163 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3164 [(set GR32:$dst, EFLAGS,
3165 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3167 // Memory-Integer Signed Integer Multiply
3168 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3169 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3171 [(set GR16:$dst, EFLAGS,
3172 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3174 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3175 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3176 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3177 [(set GR32:$dst, EFLAGS,
3178 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3179 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3180 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3181 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3182 [(set GR16:$dst, EFLAGS,
3183 (X86smul_flag (load addr:$src1),
3184 i16immSExt8:$src2))]>, OpSize;
3185 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3186 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3187 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3188 [(set GR32:$dst, EFLAGS,
3189 (X86smul_flag (load addr:$src1),
3190 i32immSExt8:$src2))]>;
3191 } // Defs = [EFLAGS]
3193 //===----------------------------------------------------------------------===//
3194 // Test instructions are just like AND, except they don't generate a result.
3196 let Defs = [EFLAGS] in {
3197 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3198 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3199 "test{b}\t{$src2, $src1|$src1, $src2}",
3200 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3201 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3202 "test{w}\t{$src2, $src1|$src1, $src2}",
3203 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3206 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3207 "test{l}\t{$src2, $src1|$src1, $src2}",
3208 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3212 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3213 "test{b}\t{$src, %al|%al, $src}", []>;
3214 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3215 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3216 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3217 "test{l}\t{$src, %eax|%eax, $src}", []>;
3219 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3220 "test{b}\t{$src2, $src1|$src1, $src2}",
3221 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3223 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3224 "test{w}\t{$src2, $src1|$src1, $src2}",
3225 [(set EFLAGS, (X86cmp (and GR16:$src1,
3226 (loadi16 addr:$src2)), 0))]>, OpSize;
3227 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3228 "test{l}\t{$src2, $src1|$src1, $src2}",
3229 [(set EFLAGS, (X86cmp (and GR32:$src1,
3230 (loadi32 addr:$src2)), 0))]>;
3232 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3233 (outs), (ins GR8:$src1, i8imm:$src2),
3234 "test{b}\t{$src2, $src1|$src1, $src2}",
3235 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3236 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3237 (outs), (ins GR16:$src1, i16imm:$src2),
3238 "test{w}\t{$src2, $src1|$src1, $src2}",
3239 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3241 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3242 (outs), (ins GR32:$src1, i32imm:$src2),
3243 "test{l}\t{$src2, $src1|$src1, $src2}",
3244 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3246 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3247 (outs), (ins i8mem:$src1, i8imm:$src2),
3248 "test{b}\t{$src2, $src1|$src1, $src2}",
3249 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3251 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3252 (outs), (ins i16mem:$src1, i16imm:$src2),
3253 "test{w}\t{$src2, $src1|$src1, $src2}",
3254 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3256 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3257 (outs), (ins i32mem:$src1, i32imm:$src2),
3258 "test{l}\t{$src2, $src1|$src1, $src2}",
3259 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3261 } // Defs = [EFLAGS]
3264 // Condition code ops, incl. set if equal/not equal/...
3265 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3266 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3267 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3268 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3270 let Uses = [EFLAGS] in {
3271 // Use sbb to materialize carry bit.
3272 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3273 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3274 // However, Pat<> can't replicate the destination reg into the inputs of the
3276 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3278 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3279 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3280 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3281 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3283 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3284 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3287 def SETEr : I<0x94, MRM0r,
3288 (outs GR8 :$dst), (ins),
3290 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3292 def SETEm : I<0x94, MRM0m,
3293 (outs), (ins i8mem:$dst),
3295 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3298 def SETNEr : I<0x95, MRM0r,
3299 (outs GR8 :$dst), (ins),
3301 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3303 def SETNEm : I<0x95, MRM0m,
3304 (outs), (ins i8mem:$dst),
3306 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3309 def SETLr : I<0x9C, MRM0r,
3310 (outs GR8 :$dst), (ins),
3312 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3313 TB; // GR8 = < signed
3314 def SETLm : I<0x9C, MRM0m,
3315 (outs), (ins i8mem:$dst),
3317 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3318 TB; // [mem8] = < signed
3320 def SETGEr : I<0x9D, MRM0r,
3321 (outs GR8 :$dst), (ins),
3323 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3324 TB; // GR8 = >= signed
3325 def SETGEm : I<0x9D, MRM0m,
3326 (outs), (ins i8mem:$dst),
3328 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3329 TB; // [mem8] = >= signed
3331 def SETLEr : I<0x9E, MRM0r,
3332 (outs GR8 :$dst), (ins),
3334 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3335 TB; // GR8 = <= signed
3336 def SETLEm : I<0x9E, MRM0m,
3337 (outs), (ins i8mem:$dst),
3339 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3340 TB; // [mem8] = <= signed
3342 def SETGr : I<0x9F, MRM0r,
3343 (outs GR8 :$dst), (ins),
3345 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3346 TB; // GR8 = > signed
3347 def SETGm : I<0x9F, MRM0m,
3348 (outs), (ins i8mem:$dst),
3350 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3351 TB; // [mem8] = > signed
3353 def SETBr : I<0x92, MRM0r,
3354 (outs GR8 :$dst), (ins),
3356 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3357 TB; // GR8 = < unsign
3358 def SETBm : I<0x92, MRM0m,
3359 (outs), (ins i8mem:$dst),
3361 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3362 TB; // [mem8] = < unsign
3364 def SETAEr : I<0x93, MRM0r,
3365 (outs GR8 :$dst), (ins),
3367 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3368 TB; // GR8 = >= unsign
3369 def SETAEm : I<0x93, MRM0m,
3370 (outs), (ins i8mem:$dst),
3372 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3373 TB; // [mem8] = >= unsign
3375 def SETBEr : I<0x96, MRM0r,
3376 (outs GR8 :$dst), (ins),
3378 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3379 TB; // GR8 = <= unsign
3380 def SETBEm : I<0x96, MRM0m,
3381 (outs), (ins i8mem:$dst),
3383 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3384 TB; // [mem8] = <= unsign
3386 def SETAr : I<0x97, MRM0r,
3387 (outs GR8 :$dst), (ins),
3389 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3390 TB; // GR8 = > signed
3391 def SETAm : I<0x97, MRM0m,
3392 (outs), (ins i8mem:$dst),
3394 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3395 TB; // [mem8] = > signed
3397 def SETSr : I<0x98, MRM0r,
3398 (outs GR8 :$dst), (ins),
3400 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3401 TB; // GR8 = <sign bit>
3402 def SETSm : I<0x98, MRM0m,
3403 (outs), (ins i8mem:$dst),
3405 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3406 TB; // [mem8] = <sign bit>
3407 def SETNSr : I<0x99, MRM0r,
3408 (outs GR8 :$dst), (ins),
3410 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3411 TB; // GR8 = !<sign bit>
3412 def SETNSm : I<0x99, MRM0m,
3413 (outs), (ins i8mem:$dst),
3415 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3416 TB; // [mem8] = !<sign bit>
3418 def SETPr : I<0x9A, MRM0r,
3419 (outs GR8 :$dst), (ins),
3421 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3423 def SETPm : I<0x9A, MRM0m,
3424 (outs), (ins i8mem:$dst),
3426 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3427 TB; // [mem8] = parity
3428 def SETNPr : I<0x9B, MRM0r,
3429 (outs GR8 :$dst), (ins),
3431 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3432 TB; // GR8 = not parity
3433 def SETNPm : I<0x9B, MRM0m,
3434 (outs), (ins i8mem:$dst),
3436 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3437 TB; // [mem8] = not parity
3439 def SETOr : I<0x90, MRM0r,
3440 (outs GR8 :$dst), (ins),
3442 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3443 TB; // GR8 = overflow
3444 def SETOm : I<0x90, MRM0m,
3445 (outs), (ins i8mem:$dst),
3447 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3448 TB; // [mem8] = overflow
3449 def SETNOr : I<0x91, MRM0r,
3450 (outs GR8 :$dst), (ins),
3452 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3453 TB; // GR8 = not overflow
3454 def SETNOm : I<0x91, MRM0m,
3455 (outs), (ins i8mem:$dst),
3457 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3458 TB; // [mem8] = not overflow
3459 } // Uses = [EFLAGS]
3462 // Integer comparisons
3463 let Defs = [EFLAGS] in {
3464 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3465 "cmp{b}\t{$src, %al|%al, $src}", []>;
3466 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3467 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3468 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3469 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3471 def CMP8rr : I<0x38, MRMDestReg,
3472 (outs), (ins GR8 :$src1, GR8 :$src2),
3473 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3474 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3475 def CMP16rr : I<0x39, MRMDestReg,
3476 (outs), (ins GR16:$src1, GR16:$src2),
3477 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3478 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3479 def CMP32rr : I<0x39, MRMDestReg,
3480 (outs), (ins GR32:$src1, GR32:$src2),
3481 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3482 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3483 def CMP8mr : I<0x38, MRMDestMem,
3484 (outs), (ins i8mem :$src1, GR8 :$src2),
3485 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3486 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3487 def CMP16mr : I<0x39, MRMDestMem,
3488 (outs), (ins i16mem:$src1, GR16:$src2),
3489 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3490 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3492 def CMP32mr : I<0x39, MRMDestMem,
3493 (outs), (ins i32mem:$src1, GR32:$src2),
3494 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3495 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3496 def CMP8rm : I<0x3A, MRMSrcMem,
3497 (outs), (ins GR8 :$src1, i8mem :$src2),
3498 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3499 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3500 def CMP16rm : I<0x3B, MRMSrcMem,
3501 (outs), (ins GR16:$src1, i16mem:$src2),
3502 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3503 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3505 def CMP32rm : I<0x3B, MRMSrcMem,
3506 (outs), (ins GR32:$src1, i32mem:$src2),
3507 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3508 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3510 // These are alternate spellings for use by the disassembler, we mark them as
3511 // code gen only to ensure they aren't matched by the assembler.
3512 let isCodeGenOnly = 1 in {
3513 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3514 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3515 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3516 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3517 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3518 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3521 def CMP8ri : Ii8<0x80, MRM7r,
3522 (outs), (ins GR8:$src1, i8imm:$src2),
3523 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3524 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3525 def CMP16ri : Ii16<0x81, MRM7r,
3526 (outs), (ins GR16:$src1, i16imm:$src2),
3527 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3528 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3529 def CMP32ri : Ii32<0x81, MRM7r,
3530 (outs), (ins GR32:$src1, i32imm:$src2),
3531 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3532 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3533 def CMP8mi : Ii8 <0x80, MRM7m,
3534 (outs), (ins i8mem :$src1, i8imm :$src2),
3535 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3536 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3537 def CMP16mi : Ii16<0x81, MRM7m,
3538 (outs), (ins i16mem:$src1, i16imm:$src2),
3539 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3540 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3542 def CMP32mi : Ii32<0x81, MRM7m,
3543 (outs), (ins i32mem:$src1, i32imm:$src2),
3544 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3545 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3546 def CMP16ri8 : Ii8<0x83, MRM7r,
3547 (outs), (ins GR16:$src1, i16i8imm:$src2),
3548 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3549 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3551 def CMP16mi8 : Ii8<0x83, MRM7m,
3552 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3553 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3554 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3555 i16immSExt8:$src2))]>, OpSize;
3556 def CMP32mi8 : Ii8<0x83, MRM7m,
3557 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3558 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3559 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3560 i32immSExt8:$src2))]>;
3561 def CMP32ri8 : Ii8<0x83, MRM7r,
3562 (outs), (ins GR32:$src1, i32i8imm:$src2),
3563 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3564 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3565 } // Defs = [EFLAGS]
3568 // TODO: BTC, BTR, and BTS
3569 let Defs = [EFLAGS] in {
3570 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3571 "bt{w}\t{$src2, $src1|$src1, $src2}",
3572 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3573 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3574 "bt{l}\t{$src2, $src1|$src1, $src2}",
3575 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3577 // Unlike with the register+register form, the memory+register form of the
3578 // bt instruction does not ignore the high bits of the index. From ISel's
3579 // perspective, this is pretty bizarre. Make these instructions disassembly
3582 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3583 "bt{w}\t{$src2, $src1|$src1, $src2}",
3584 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3585 // (implicit EFLAGS)]
3587 >, OpSize, TB, Requires<[FastBTMem]>;
3588 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3589 "bt{l}\t{$src2, $src1|$src1, $src2}",
3590 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3591 // (implicit EFLAGS)]
3593 >, TB, Requires<[FastBTMem]>;
3595 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3596 "bt{w}\t{$src2, $src1|$src1, $src2}",
3597 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3599 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3600 "bt{l}\t{$src2, $src1|$src1, $src2}",
3601 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3602 // Note that these instructions don't need FastBTMem because that
3603 // only applies when the other operand is in a register. When it's
3604 // an immediate, bt is still fast.
3605 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3606 "bt{w}\t{$src2, $src1|$src1, $src2}",
3607 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3609 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3610 "bt{l}\t{$src2, $src1|$src1, $src2}",
3611 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3614 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3615 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3616 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3617 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3618 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3619 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3620 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3621 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3622 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3623 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3624 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3625 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3626 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3627 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3628 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3629 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3631 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3632 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3633 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3634 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3635 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3636 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3637 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3638 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3639 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3640 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3641 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3642 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3643 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3644 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3645 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3646 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3648 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3649 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3650 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3651 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3652 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3653 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3654 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3655 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3656 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3657 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3658 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3659 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3660 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3661 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3662 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3663 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3664 } // Defs = [EFLAGS]
3666 // Sign/Zero extenders
3667 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3668 // of the register here. This has a smaller encoding and avoids a
3669 // partial-register update. Actual movsbw included for the disassembler.
3670 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3671 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3672 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3673 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3674 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3675 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3676 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3677 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3678 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3679 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3680 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3681 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3682 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3683 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3684 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3685 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3686 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3687 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3688 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3689 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3691 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3692 // of the register here. This has a smaller encoding and avoids a
3693 // partial-register update. Actual movzbw included for the disassembler.
3694 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3695 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3696 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3697 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3698 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3699 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3700 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3701 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3702 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3703 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3704 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3705 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3706 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3707 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3708 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3709 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3710 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3711 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3712 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3713 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3715 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3716 // except that they use GR32_NOREX for the output operand register class
3717 // instead of GR32. This allows them to operate on h registers on x86-64.
3718 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3719 (outs GR32_NOREX:$dst), (ins GR8:$src),
3720 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3723 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3724 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3725 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3728 let neverHasSideEffects = 1 in {
3729 let Defs = [AX], Uses = [AL] in
3730 def CBW : I<0x98, RawFrm, (outs), (ins),
3731 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3732 let Defs = [EAX], Uses = [AX] in
3733 def CWDE : I<0x98, RawFrm, (outs), (ins),
3734 "{cwtl|cwde}", []>; // EAX = signext(AX)
3736 let Defs = [AX,DX], Uses = [AX] in
3737 def CWD : I<0x99, RawFrm, (outs), (ins),
3738 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3739 let Defs = [EAX,EDX], Uses = [EAX] in
3740 def CDQ : I<0x99, RawFrm, (outs), (ins),
3741 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3744 //===----------------------------------------------------------------------===//
3745 // Alias Instructions
3746 //===----------------------------------------------------------------------===//
3748 // Alias instructions that map movr0 to xor.
3749 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3750 // FIXME: Set encoding to pseudo.
3751 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3752 isCodeGenOnly = 1 in {
3753 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3754 [(set GR8:$dst, 0)]>;
3756 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3757 // encoding and avoids a partial-register update sometimes, but doing so
3758 // at isel time interferes with rematerialization in the current register
3759 // allocator. For now, this is rewritten when the instruction is lowered
3761 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3763 [(set GR16:$dst, 0)]>, OpSize;
3765 // FIXME: Set encoding to pseudo.
3766 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3767 [(set GR32:$dst, 0)]>;
3770 //===----------------------------------------------------------------------===//
3771 // Thread Local Storage Instructions
3774 // All calls clobber the non-callee saved registers. ESP is marked as
3775 // a use to prevent stack-pointer assignments that appear immediately
3776 // before calls from potentially appearing dead.
3777 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3778 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3779 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3780 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3782 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3783 "leal\t$sym, %eax; "
3784 "call\t___tls_get_addr@PLT",
3785 [(X86tlsaddr tls32addr:$sym)]>,
3786 Requires<[In32BitMode]>;
3788 let AddedComplexity = 5, isCodeGenOnly = 1 in
3789 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3790 "movl\t%gs:$src, $dst",
3791 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3793 let AddedComplexity = 5, isCodeGenOnly = 1 in
3794 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3795 "movl\t%fs:$src, $dst",
3796 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3798 //===----------------------------------------------------------------------===//
3799 // EH Pseudo Instructions
3801 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3802 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3803 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3804 "ret\t#eh_return, addr: $addr",
3805 [(X86ehret GR32:$addr)]>;
3809 //===----------------------------------------------------------------------===//
3813 // Atomic swap. These are just normal xchg instructions. But since a memory
3814 // operand is referenced, the atomicity is ensured.
3815 let Constraints = "$val = $dst" in {
3816 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3817 (ins GR32:$val, i32mem:$ptr),
3818 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3819 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3820 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3821 (ins GR16:$val, i16mem:$ptr),
3822 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3823 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3825 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3826 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3827 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3829 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3830 "xchg{l}\t{$val, $src|$src, $val}", []>;
3831 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3832 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3833 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3834 "xchg{b}\t{$val, $src|$src, $val}", []>;
3837 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3838 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3839 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3840 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3842 // Atomic compare and swap.
3843 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3844 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3846 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3847 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3849 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3850 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3853 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3856 let Defs = [AX, EFLAGS], Uses = [AX] in {
3857 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3859 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3860 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3862 let Defs = [AL, EFLAGS], Uses = [AL] in {
3863 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3865 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3866 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3869 // Atomic exchange and add
3870 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3871 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3873 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3874 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3876 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3878 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3879 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3881 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3883 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3884 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3888 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3889 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3890 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3891 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3892 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3893 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3895 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3896 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3897 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3898 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3899 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3900 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3902 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3903 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3904 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3905 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3906 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3907 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3909 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3910 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3911 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3912 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3913 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3914 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3916 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3917 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3918 "cmpxchg8b\t$dst", []>, TB;
3920 // Optimized codegen when the non-memory output is not used.
3921 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3922 let Defs = [EFLAGS] in {
3923 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3925 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3926 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3928 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3929 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3931 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3932 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3934 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3935 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3937 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3938 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3940 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3941 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3943 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3944 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3946 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3948 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3950 "inc{b}\t$dst", []>, LOCK;
3951 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3953 "inc{w}\t$dst", []>, OpSize, LOCK;
3954 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3956 "inc{l}\t$dst", []>, LOCK;
3958 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3960 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3961 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3963 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3964 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3966 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3967 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3969 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3970 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3972 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3973 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3975 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3976 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3978 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3979 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3981 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3983 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3985 "dec{b}\t$dst", []>, LOCK;
3986 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3988 "dec{w}\t$dst", []>, OpSize, LOCK;
3989 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3991 "dec{l}\t$dst", []>, LOCK;
3994 // Atomic exchange, and, or, xor
3995 let Constraints = "$val = $dst", Defs = [EFLAGS],
3996 usesCustomInserter = 1 in {
3997 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3998 "#ATOMAND32 PSEUDO!",
3999 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4000 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4001 "#ATOMOR32 PSEUDO!",
4002 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4003 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4004 "#ATOMXOR32 PSEUDO!",
4005 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4006 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4007 "#ATOMNAND32 PSEUDO!",
4008 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4009 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4010 "#ATOMMIN32 PSEUDO!",
4011 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4012 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4013 "#ATOMMAX32 PSEUDO!",
4014 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4015 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4016 "#ATOMUMIN32 PSEUDO!",
4017 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4018 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4019 "#ATOMUMAX32 PSEUDO!",
4020 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4022 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4023 "#ATOMAND16 PSEUDO!",
4024 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4025 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4026 "#ATOMOR16 PSEUDO!",
4027 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4028 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4029 "#ATOMXOR16 PSEUDO!",
4030 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4031 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4032 "#ATOMNAND16 PSEUDO!",
4033 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4034 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4035 "#ATOMMIN16 PSEUDO!",
4036 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4037 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4038 "#ATOMMAX16 PSEUDO!",
4039 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4040 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4041 "#ATOMUMIN16 PSEUDO!",
4042 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4043 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4044 "#ATOMUMAX16 PSEUDO!",
4045 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4047 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4048 "#ATOMAND8 PSEUDO!",
4049 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4050 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4052 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4053 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4054 "#ATOMXOR8 PSEUDO!",
4055 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4056 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4057 "#ATOMNAND8 PSEUDO!",
4058 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4061 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4062 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4063 Uses = [EAX, EBX, ECX, EDX],
4064 mayLoad = 1, mayStore = 1,
4065 usesCustomInserter = 1 in {
4066 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4067 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4068 "#ATOMAND6432 PSEUDO!", []>;
4069 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4070 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4071 "#ATOMOR6432 PSEUDO!", []>;
4072 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4073 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4074 "#ATOMXOR6432 PSEUDO!", []>;
4075 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4076 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4077 "#ATOMNAND6432 PSEUDO!", []>;
4078 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4079 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4080 "#ATOMADD6432 PSEUDO!", []>;
4081 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4082 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4083 "#ATOMSUB6432 PSEUDO!", []>;
4084 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4085 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4086 "#ATOMSWAP6432 PSEUDO!", []>;
4089 // Segmentation support instructions.
4091 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4092 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4093 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4094 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4096 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4097 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4098 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4099 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4100 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4102 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4103 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4104 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4105 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4106 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4107 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4108 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4109 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4111 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4113 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4114 "str{w}\t{$dst}", []>, TB;
4115 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4116 "str{w}\t{$dst}", []>, TB;
4117 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4118 "ltr{w}\t{$src}", []>, TB;
4119 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4120 "ltr{w}\t{$src}", []>, TB;
4122 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4123 "push{w}\t%fs", []>, OpSize, TB;
4124 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4125 "push{l}\t%fs", []>, TB;
4126 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4127 "push{w}\t%gs", []>, OpSize, TB;
4128 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4129 "push{l}\t%gs", []>, TB;
4131 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4132 "pop{w}\t%fs", []>, OpSize, TB;
4133 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4134 "pop{l}\t%fs", []>, TB;
4135 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4136 "pop{w}\t%gs", []>, OpSize, TB;
4137 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4138 "pop{l}\t%gs", []>, TB;
4140 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4141 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4142 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4143 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4144 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4145 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4146 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4147 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4148 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4149 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4150 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4151 "les{l}\t{$src, $dst|$dst, $src}", []>;
4152 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4153 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4154 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4155 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4156 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4157 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4158 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4159 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4161 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4162 "verr\t$seg", []>, TB;
4163 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4164 "verr\t$seg", []>, TB;
4165 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4166 "verw\t$seg", []>, TB;
4167 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4168 "verw\t$seg", []>, TB;
4170 // Descriptor-table support instructions
4172 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4173 "sgdt\t$dst", []>, TB;
4174 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4175 "sidt\t$dst", []>, TB;
4176 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4177 "sldt{w}\t$dst", []>, TB;
4178 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4179 "sldt{w}\t$dst", []>, TB;
4180 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4181 "lgdt\t$src", []>, TB;
4182 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4183 "lidt\t$src", []>, TB;
4184 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4185 "lldt{w}\t$src", []>, TB;
4186 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4187 "lldt{w}\t$src", []>, TB;
4189 // Lock instruction prefix
4190 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4192 // Repeat string operation instruction prefixes
4193 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4194 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4195 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4196 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4197 // Repeat while not equal (used with CMPS and SCAS)
4198 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4201 // Segment override instruction prefixes
4202 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4203 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4204 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4205 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4206 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4207 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4209 // String manipulation instructions
4211 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4212 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4213 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4215 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4216 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4217 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4219 // CPU flow control instructions
4221 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4222 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4224 // FPU control instructions
4226 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4228 // Flag instructions
4230 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4231 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4232 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4233 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4234 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4235 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4236 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4238 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4240 // Table lookup instructions
4242 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4244 // Specialized register support
4246 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4247 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4248 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4250 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4251 "smsw{w}\t$dst", []>, OpSize, TB;
4252 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4253 "smsw{l}\t$dst", []>, TB;
4254 // For memory operands, there is only a 16-bit form
4255 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4256 "smsw{w}\t$dst", []>, TB;
4258 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4259 "lmsw{w}\t$src", []>, TB;
4260 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4261 "lmsw{w}\t$src", []>, TB;
4263 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4265 // Cache instructions
4267 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4268 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4273 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4275 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4277 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4278 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4279 "vmclear\t$vmcs", []>, OpSize, TB;
4281 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4283 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4284 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4285 "vmptrld\t$vmcs", []>, TB;
4286 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4287 "vmptrst\t$vmcs", []>, TB;
4288 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4289 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4290 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4291 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4292 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4293 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4294 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4295 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4296 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4297 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4298 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4299 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4300 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4301 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4302 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4303 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4305 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4306 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4307 "vmxon\t{$vmxon}", []>, XS;
4309 //===----------------------------------------------------------------------===//
4310 // Non-Instruction Patterns
4311 //===----------------------------------------------------------------------===//
4313 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4314 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4315 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4316 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4317 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4318 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4319 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4321 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4322 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4323 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4324 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4325 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4326 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4327 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4328 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4329 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4330 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4332 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4333 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4334 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4335 (MOV32mi addr:$dst, texternalsym:$src)>;
4336 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4337 (MOV32mi addr:$dst, tblockaddress:$src)>;
4341 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4342 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4343 Requires<[In32BitMode]>;
4345 // FIXME: This is disabled for 32-bit PIC mode because the global base
4346 // register which is part of the address mode may be assigned a
4347 // callee-saved register.
4348 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4349 (TCRETURNmi addr:$dst, imm:$off)>,
4350 Requires<[In32BitMode, IsNotPIC]>;
4352 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4353 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4354 Requires<[In32BitMode]>;
4356 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4357 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4358 Requires<[In32BitMode]>;
4360 // Normal calls, with various flavors of addresses.
4361 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4362 (CALLpcrel32 tglobaladdr:$dst)>;
4363 def : Pat<(X86call (i32 texternalsym:$dst)),
4364 (CALLpcrel32 texternalsym:$dst)>;
4365 def : Pat<(X86call (i32 imm:$dst)),
4366 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4368 // X86 specific add which produces a flag.
4369 def : Pat<(addc GR32:$src1, GR32:$src2),
4370 (ADD32rr GR32:$src1, GR32:$src2)>;
4371 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4372 (ADD32rm GR32:$src1, addr:$src2)>;
4373 def : Pat<(addc GR32:$src1, imm:$src2),
4374 (ADD32ri GR32:$src1, imm:$src2)>;
4375 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4376 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4378 def : Pat<(subc GR32:$src1, GR32:$src2),
4379 (SUB32rr GR32:$src1, GR32:$src2)>;
4380 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4381 (SUB32rm GR32:$src1, addr:$src2)>;
4382 def : Pat<(subc GR32:$src1, imm:$src2),
4383 (SUB32ri GR32:$src1, imm:$src2)>;
4384 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4385 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4389 // TEST R,R is smaller than CMP R,0
4390 def : Pat<(X86cmp GR8:$src1, 0),
4391 (TEST8rr GR8:$src1, GR8:$src1)>;
4392 def : Pat<(X86cmp GR16:$src1, 0),
4393 (TEST16rr GR16:$src1, GR16:$src1)>;
4394 def : Pat<(X86cmp GR32:$src1, 0),
4395 (TEST32rr GR32:$src1, GR32:$src1)>;
4397 // Conditional moves with folded loads with operands swapped and conditions
4399 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4400 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4401 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4402 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4403 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4404 (CMOVB16rm GR16:$src2, addr:$src1)>;
4405 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4406 (CMOVB32rm GR32:$src2, addr:$src1)>;
4407 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4408 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4409 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4410 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4411 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4412 (CMOVE16rm GR16:$src2, addr:$src1)>;
4413 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4414 (CMOVE32rm GR32:$src2, addr:$src1)>;
4415 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4416 (CMOVA16rm GR16:$src2, addr:$src1)>;
4417 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4418 (CMOVA32rm GR32:$src2, addr:$src1)>;
4419 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4420 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4421 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4422 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4423 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4424 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4425 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4426 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4427 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4428 (CMOVL16rm GR16:$src2, addr:$src1)>;
4429 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4430 (CMOVL32rm GR32:$src2, addr:$src1)>;
4431 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4432 (CMOVG16rm GR16:$src2, addr:$src1)>;
4433 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4434 (CMOVG32rm GR32:$src2, addr:$src1)>;
4435 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4436 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4437 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4438 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4439 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4440 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4441 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4442 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4443 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4444 (CMOVP16rm GR16:$src2, addr:$src1)>;
4445 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4446 (CMOVP32rm GR32:$src2, addr:$src1)>;
4447 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4448 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4449 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4450 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4451 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4452 (CMOVS16rm GR16:$src2, addr:$src1)>;
4453 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4454 (CMOVS32rm GR32:$src2, addr:$src1)>;
4455 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4456 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4457 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4458 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4459 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4460 (CMOVO16rm GR16:$src2, addr:$src1)>;
4461 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4462 (CMOVO32rm GR32:$src2, addr:$src1)>;
4464 // zextload bool -> zextload byte
4465 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4466 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4467 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4469 // extload bool -> extload byte
4470 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4471 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4472 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4473 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4474 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4475 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4477 // anyext. Define these to do an explicit zero-extend to
4478 // avoid partial-register updates.
4479 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4480 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4481 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>,
4482 Requires<[NotPromote16Bit]>;
4484 def : Pat<(i32 (anyext GR16:$src)),
4485 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>,
4486 Requires<[Promote16Bit]>;
4489 //===----------------------------------------------------------------------===//
4491 //===----------------------------------------------------------------------===//
4493 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4494 // +128 doesn't, so in this special case use a sub instead of an add.
4495 def : Pat<(add GR16:$src1, 128),
4496 (SUB16ri8 GR16:$src1, -128)>;
4497 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4498 (SUB16mi8 addr:$dst, -128)>;
4499 def : Pat<(add GR32:$src1, 128),
4500 (SUB32ri8 GR32:$src1, -128)>;
4501 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4502 (SUB32mi8 addr:$dst, -128)>;
4504 // r & (2^16-1) ==> movz
4505 def : Pat<(and GR32:$src1, 0xffff),
4506 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4507 // r & (2^8-1) ==> movz
4508 def : Pat<(and GR32:$src1, 0xff),
4509 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4512 Requires<[In32BitMode]>;
4513 // r & (2^8-1) ==> movz
4514 def : Pat<(and GR16:$src1, 0xff),
4515 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4518 Requires<[In32BitMode]>;
4520 // sext_inreg patterns
4521 def : Pat<(sext_inreg GR32:$src, i16),
4522 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4523 def : Pat<(sext_inreg GR32:$src, i8),
4524 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4527 Requires<[In32BitMode]>;
4528 def : Pat<(sext_inreg GR16:$src, i8),
4529 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4532 Requires<[In32BitMode]>;
4535 def : Pat<(i16 (trunc GR32:$src)),
4536 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4537 def : Pat<(i8 (trunc GR32:$src)),
4538 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4540 Requires<[In32BitMode]>;
4541 def : Pat<(i8 (trunc GR16:$src)),
4542 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4544 Requires<[In32BitMode]>;
4546 // h-register tricks
4547 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4548 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4549 x86_subreg_8bit_hi)>,
4550 Requires<[In32BitMode]>;
4551 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4552 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4553 x86_subreg_8bit_hi)>,
4554 Requires<[In32BitMode]>;
4555 def : Pat<(srl GR16:$src, (i8 8)),
4558 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4559 x86_subreg_8bit_hi)),
4561 Requires<[In32BitMode]>;
4562 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4563 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4565 x86_subreg_8bit_hi))>,
4566 Requires<[In32BitMode]>;
4567 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4568 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4570 x86_subreg_8bit_hi))>,
4571 Requires<[In32BitMode]>;
4572 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4573 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4575 x86_subreg_8bit_hi))>,
4576 Requires<[In32BitMode]>;
4578 // (shl x, 1) ==> (add x, x)
4579 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4580 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4581 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4583 // (shl x (and y, 31)) ==> (shl x, y)
4584 def : Pat<(shl GR8:$src1, (and CL, 31)),
4585 (SHL8rCL GR8:$src1)>;
4586 def : Pat<(shl GR16:$src1, (and CL, 31)),
4587 (SHL16rCL GR16:$src1)>;
4588 def : Pat<(shl GR32:$src1, (and CL, 31)),
4589 (SHL32rCL GR32:$src1)>;
4590 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4591 (SHL8mCL addr:$dst)>;
4592 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4593 (SHL16mCL addr:$dst)>;
4594 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4595 (SHL32mCL addr:$dst)>;
4597 def : Pat<(srl GR8:$src1, (and CL, 31)),
4598 (SHR8rCL GR8:$src1)>;
4599 def : Pat<(srl GR16:$src1, (and CL, 31)),
4600 (SHR16rCL GR16:$src1)>;
4601 def : Pat<(srl GR32:$src1, (and CL, 31)),
4602 (SHR32rCL GR32:$src1)>;
4603 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4604 (SHR8mCL addr:$dst)>;
4605 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4606 (SHR16mCL addr:$dst)>;
4607 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4608 (SHR32mCL addr:$dst)>;
4610 def : Pat<(sra GR8:$src1, (and CL, 31)),
4611 (SAR8rCL GR8:$src1)>;
4612 def : Pat<(sra GR16:$src1, (and CL, 31)),
4613 (SAR16rCL GR16:$src1)>;
4614 def : Pat<(sra GR32:$src1, (and CL, 31)),
4615 (SAR32rCL GR32:$src1)>;
4616 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4617 (SAR8mCL addr:$dst)>;
4618 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4619 (SAR16mCL addr:$dst)>;
4620 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4621 (SAR32mCL addr:$dst)>;
4623 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4624 def : Pat<(or (srl GR32:$src1, CL:$amt),
4625 (shl GR32:$src2, (sub 32, CL:$amt))),
4626 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4628 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4629 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4630 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4632 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4633 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4634 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4636 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4637 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4639 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4641 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4642 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4644 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4645 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4646 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4648 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4649 def : Pat<(or (shl GR32:$src1, CL:$amt),
4650 (srl GR32:$src2, (sub 32, CL:$amt))),
4651 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4653 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4654 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4655 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4657 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4658 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4659 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4661 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4662 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4664 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4666 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4667 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4669 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4670 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4671 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4673 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4674 def : Pat<(or (srl GR16:$src1, CL:$amt),
4675 (shl GR16:$src2, (sub 16, CL:$amt))),
4676 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4678 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4679 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4680 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4682 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4683 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4684 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4686 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4687 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4689 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4691 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4692 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4694 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4695 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4696 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4698 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4699 def : Pat<(or (shl GR16:$src1, CL:$amt),
4700 (srl GR16:$src2, (sub 16, CL:$amt))),
4701 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4703 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4704 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4705 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4707 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4708 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4709 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4711 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4712 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4714 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4716 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4717 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4719 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4720 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4721 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4723 // (anyext (setcc_carry)) -> (setcc_carry)
4724 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4726 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4728 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4731 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4732 let AddedComplexity = 5 in { // Try this before the selecting to OR
4733 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4734 (ADD16ri GR16:$src1, imm:$src2)>;
4735 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4736 (ADD32ri GR32:$src1, imm:$src2)>;
4737 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4738 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4739 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4740 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4741 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4742 (ADD16rr GR16:$src1, GR16:$src2)>;
4743 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4744 (ADD32rr GR32:$src1, GR32:$src2)>;
4745 } // AddedComplexity
4747 //===----------------------------------------------------------------------===//
4748 // EFLAGS-defining Patterns
4749 //===----------------------------------------------------------------------===//
4752 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4753 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4754 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4757 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4758 (ADD8rm GR8:$src1, addr:$src2)>;
4759 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4760 (ADD16rm GR16:$src1, addr:$src2)>;
4761 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4762 (ADD32rm GR32:$src1, addr:$src2)>;
4765 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4766 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4767 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4768 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4769 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4770 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4771 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4774 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4775 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4776 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4779 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4780 (SUB8rm GR8:$src1, addr:$src2)>;
4781 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4782 (SUB16rm GR16:$src1, addr:$src2)>;
4783 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4784 (SUB32rm GR32:$src1, addr:$src2)>;
4787 def : Pat<(sub GR8:$src1, imm:$src2),
4788 (SUB8ri GR8:$src1, imm:$src2)>;
4789 def : Pat<(sub GR16:$src1, imm:$src2),
4790 (SUB16ri GR16:$src1, imm:$src2)>;
4791 def : Pat<(sub GR32:$src1, imm:$src2),
4792 (SUB32ri GR32:$src1, imm:$src2)>;
4793 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4794 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4795 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4796 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4799 def : Pat<(mul GR16:$src1, GR16:$src2),
4800 (IMUL16rr GR16:$src1, GR16:$src2)>;
4801 def : Pat<(mul GR32:$src1, GR32:$src2),
4802 (IMUL32rr GR32:$src1, GR32:$src2)>;
4805 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4806 (IMUL16rm GR16:$src1, addr:$src2)>;
4807 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4808 (IMUL32rm GR32:$src1, addr:$src2)>;
4811 def : Pat<(mul GR16:$src1, imm:$src2),
4812 (IMUL16rri GR16:$src1, imm:$src2)>;
4813 def : Pat<(mul GR32:$src1, imm:$src2),
4814 (IMUL32rri GR32:$src1, imm:$src2)>;
4815 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4816 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4817 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4818 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4820 // reg = mul mem, imm
4821 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4822 (IMUL16rmi addr:$src1, imm:$src2)>;
4823 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4824 (IMUL32rmi addr:$src1, imm:$src2)>;
4825 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4826 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4827 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4828 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4830 // Optimize multiply by 2 with EFLAGS result.
4831 let AddedComplexity = 2 in {
4832 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4833 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4836 // Patterns for nodes that do not produce flags, for instructions that do.
4839 def : Pat<(add GR8:$src , 1), (INC8r GR8:$src)>;
4840 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4841 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4844 def : Pat<(add GR8:$src , -1), (DEC8r GR8:$src)>;
4845 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4846 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4849 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4850 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4851 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4854 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4855 (OR8rm GR8:$src1, addr:$src2)>;
4856 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4857 (OR16rm GR16:$src1, addr:$src2)>;
4858 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4859 (OR32rm GR32:$src1, addr:$src2)>;
4862 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4863 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4864 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4865 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4866 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4867 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4868 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4871 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4872 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4873 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4876 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4877 (XOR8rm GR8:$src1, addr:$src2)>;
4878 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4879 (XOR16rm GR16:$src1, addr:$src2)>;
4880 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4881 (XOR32rm GR32:$src1, addr:$src2)>;
4884 def : Pat<(xor GR8:$src1, imm:$src2),
4885 (XOR8ri GR8:$src1, imm:$src2)>;
4886 def : Pat<(xor GR16:$src1, imm:$src2),
4887 (XOR16ri GR16:$src1, imm:$src2)>;
4888 def : Pat<(xor GR32:$src1, imm:$src2),
4889 (XOR32ri GR32:$src1, imm:$src2)>;
4890 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4891 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4892 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4893 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4896 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4897 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4898 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4901 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4902 (AND8rm GR8:$src1, addr:$src2)>;
4903 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4904 (AND16rm GR16:$src1, addr:$src2)>;
4905 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4906 (AND32rm GR32:$src1, addr:$src2)>;
4909 def : Pat<(and GR8:$src1, imm:$src2),
4910 (AND8ri GR8:$src1, imm:$src2)>;
4911 def : Pat<(and GR16:$src1, imm:$src2),
4912 (AND16ri GR16:$src1, imm:$src2)>;
4913 def : Pat<(and GR32:$src1, imm:$src2),
4914 (AND32ri GR32:$src1, imm:$src2)>;
4915 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4916 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4917 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4918 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4920 // -disable-16bit support.
4921 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
4922 (MOV16mi addr:$dst, imm:$src)>;
4923 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
4924 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4925 def : Pat<(i32 (sextloadi16 addr:$dst)),
4926 (MOVSX32rm16 addr:$dst)>;
4927 def : Pat<(i32 (zextloadi16 addr:$dst)),
4928 (MOVZX32rm16 addr:$dst)>;
4929 def : Pat<(i32 (extloadi16 addr:$dst)),
4930 (MOVZX32rm16 addr:$dst)>;
4932 //===----------------------------------------------------------------------===//
4933 // Floating Point Stack Support
4934 //===----------------------------------------------------------------------===//
4936 include "X86InstrFPStack.td"
4938 //===----------------------------------------------------------------------===//
4940 //===----------------------------------------------------------------------===//
4942 include "X86Instr64bit.td"
4944 //===----------------------------------------------------------------------===//
4945 // SIMD support (SSE, MMX and AVX)
4946 //===----------------------------------------------------------------------===//
4948 include "X86InstrFragmentsSIMD.td"
4950 //===----------------------------------------------------------------------===//
4951 // XMM Floating point support (requires SSE / SSE2)
4952 //===----------------------------------------------------------------------===//
4954 include "X86InstrSSE.td"
4956 //===----------------------------------------------------------------------===//
4957 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4958 //===----------------------------------------------------------------------===//
4960 include "X86InstrMMX.td"