1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
146 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
155 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
156 [SDNPHasChain, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
179 def X86vastart_save_xmm_regs :
180 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
181 SDT_X86VASTART_SAVE_XMM_REGS,
182 [SDNPHasChain, SDNPVariadic]>;
184 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
185 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
187 def X86callseq_start :
188 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
189 [SDNPHasChain, SDNPOutGlue]>;
191 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
194 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
195 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
198 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
199 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
200 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
201 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
204 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
205 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
207 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
208 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
210 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
211 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
213 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
219 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
220 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
222 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
224 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
225 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
227 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
229 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
230 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
232 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
233 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
234 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
236 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
238 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
242 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>;
243 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>;
244 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>;
246 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
248 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
249 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
251 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
254 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
255 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
257 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
258 [SDNPHasChain, SDNPOutGlue]>;
260 //===----------------------------------------------------------------------===//
261 // X86 Operand Definitions.
264 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
265 // the index operand of an address, to conform to x86 encoding restrictions.
266 def ptr_rc_nosp : PointerLikeRegClass<1>;
268 // *mem - Operand definitions for the funky X86 addressing mode operands.
270 def X86MemAsmOperand : AsmOperandClass {
271 let Name = "Mem"; let PredicateMethod = "isMem";
273 def X86Mem8AsmOperand : AsmOperandClass {
274 let Name = "Mem8"; let PredicateMethod = "isMem8";
276 def X86Mem16AsmOperand : AsmOperandClass {
277 let Name = "Mem16"; let PredicateMethod = "isMem16";
279 def X86Mem32AsmOperand : AsmOperandClass {
280 let Name = "Mem32"; let PredicateMethod = "isMem32";
282 def X86Mem64AsmOperand : AsmOperandClass {
283 let Name = "Mem64"; let PredicateMethod = "isMem64";
285 def X86Mem80AsmOperand : AsmOperandClass {
286 let Name = "Mem80"; let PredicateMethod = "isMem80";
288 def X86Mem128AsmOperand : AsmOperandClass {
289 let Name = "Mem128"; let PredicateMethod = "isMem128";
291 def X86Mem256AsmOperand : AsmOperandClass {
292 let Name = "Mem256"; let PredicateMethod = "isMem256";
295 def X86AbsMemAsmOperand : AsmOperandClass {
297 let SuperClasses = [X86MemAsmOperand];
299 class X86MemOperand<string printMethod> : Operand<iPTR> {
300 let PrintMethod = printMethod;
301 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
302 let ParserMatchClass = X86MemAsmOperand;
305 let OperandType = "OPERAND_MEMORY" in {
306 def opaque32mem : X86MemOperand<"printopaquemem">;
307 def opaque48mem : X86MemOperand<"printopaquemem">;
308 def opaque80mem : X86MemOperand<"printopaquemem">;
309 def opaque512mem : X86MemOperand<"printopaquemem">;
311 def i8mem : X86MemOperand<"printi8mem"> {
312 let ParserMatchClass = X86Mem8AsmOperand; }
313 def i16mem : X86MemOperand<"printi16mem"> {
314 let ParserMatchClass = X86Mem16AsmOperand; }
315 def i32mem : X86MemOperand<"printi32mem"> {
316 let ParserMatchClass = X86Mem32AsmOperand; }
317 def i64mem : X86MemOperand<"printi64mem"> {
318 let ParserMatchClass = X86Mem64AsmOperand; }
319 def i128mem : X86MemOperand<"printi128mem"> {
320 let ParserMatchClass = X86Mem128AsmOperand; }
321 def i256mem : X86MemOperand<"printi256mem"> {
322 let ParserMatchClass = X86Mem256AsmOperand; }
323 def f32mem : X86MemOperand<"printf32mem"> {
324 let ParserMatchClass = X86Mem32AsmOperand; }
325 def f64mem : X86MemOperand<"printf64mem"> {
326 let ParserMatchClass = X86Mem64AsmOperand; }
327 def f80mem : X86MemOperand<"printf80mem"> {
328 let ParserMatchClass = X86Mem80AsmOperand; }
329 def f128mem : X86MemOperand<"printf128mem"> {
330 let ParserMatchClass = X86Mem128AsmOperand; }
331 def f256mem : X86MemOperand<"printf256mem">{
332 let ParserMatchClass = X86Mem256AsmOperand; }
333 def v128mem : X86MemOperand<"printf128mem"> {
334 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
335 let ParserMatchClass = X86Mem128AsmOperand; }
336 def v256mem : X86MemOperand<"printf256mem"> {
337 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
338 let ParserMatchClass = X86Mem256AsmOperand; }
341 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
342 // plain GR64, so that it doesn't potentially require a REX prefix.
343 def i8mem_NOREX : Operand<i64> {
344 let PrintMethod = "printi8mem";
345 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
346 let ParserMatchClass = X86Mem8AsmOperand;
347 let OperandType = "OPERAND_MEMORY";
350 // GPRs available for tailcall.
351 // It represents GR32_TC, GR64_TC or GR64_TCW64.
352 def ptr_rc_tailcall : PointerLikeRegClass<2>;
354 // Special i32mem for addresses of load folding tail calls. These are not
355 // allowed to use callee-saved registers since they must be scheduled
356 // after callee-saved register are popped.
357 def i32mem_TC : Operand<i32> {
358 let PrintMethod = "printi32mem";
359 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
361 let ParserMatchClass = X86Mem32AsmOperand;
362 let OperandType = "OPERAND_MEMORY";
365 // Special i64mem for addresses of load folding tail calls. These are not
366 // allowed to use callee-saved registers since they must be scheduled
367 // after callee-saved register are popped.
368 def i64mem_TC : Operand<i64> {
369 let PrintMethod = "printi64mem";
370 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
371 ptr_rc_tailcall, i32imm, i8imm);
372 let ParserMatchClass = X86Mem64AsmOperand;
373 let OperandType = "OPERAND_MEMORY";
376 let OperandType = "OPERAND_PCREL",
377 ParserMatchClass = X86AbsMemAsmOperand,
378 PrintMethod = "print_pcrel_imm" in {
379 def i32imm_pcrel : Operand<i32>;
380 def i16imm_pcrel : Operand<i16>;
382 def offset8 : Operand<i64>;
383 def offset16 : Operand<i64>;
384 def offset32 : Operand<i64>;
385 def offset64 : Operand<i64>;
387 // Branch targets have OtherVT type and print as pc-relative values.
388 def brtarget : Operand<OtherVT>;
389 def brtarget8 : Operand<OtherVT>;
393 def SSECC : Operand<i8> {
394 let PrintMethod = "printSSECC";
395 let OperandType = "OPERAND_IMMEDIATE";
398 def AVXCC : Operand<i8> {
399 let PrintMethod = "printSSECC";
400 let OperandType = "OPERAND_IMMEDIATE";
403 class ImmSExtAsmOperandClass : AsmOperandClass {
404 let SuperClasses = [ImmAsmOperand];
405 let RenderMethod = "addImmOperands";
408 class ImmZExtAsmOperandClass : AsmOperandClass {
409 let SuperClasses = [ImmAsmOperand];
410 let RenderMethod = "addImmOperands";
413 // Sign-extended immediate classes. We don't need to define the full lattice
414 // here because there is no instruction with an ambiguity between ImmSExti64i32
417 // The strange ranges come from the fact that the assembler always works with
418 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
419 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
422 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
423 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
424 let Name = "ImmSExti64i32";
427 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
428 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
429 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
430 let Name = "ImmSExti16i8";
431 let SuperClasses = [ImmSExti64i32AsmOperand];
434 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
435 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
436 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
437 let Name = "ImmSExti32i8";
441 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
442 let Name = "ImmZExtu32u8";
447 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
448 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
449 let Name = "ImmSExti64i8";
450 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
451 ImmSExti64i32AsmOperand];
454 // A couple of more descriptive operand definitions.
455 // 16-bits but only 8 bits are significant.
456 def i16i8imm : Operand<i16> {
457 let ParserMatchClass = ImmSExti16i8AsmOperand;
458 let OperandType = "OPERAND_IMMEDIATE";
460 // 32-bits but only 8 bits are significant.
461 def i32i8imm : Operand<i32> {
462 let ParserMatchClass = ImmSExti32i8AsmOperand;
463 let OperandType = "OPERAND_IMMEDIATE";
465 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
466 def u32u8imm : Operand<i32> {
467 let ParserMatchClass = ImmZExtu32u8AsmOperand;
468 let OperandType = "OPERAND_IMMEDIATE";
471 // 64-bits but only 32 bits are significant.
472 def i64i32imm : Operand<i64> {
473 let ParserMatchClass = ImmSExti64i32AsmOperand;
474 let OperandType = "OPERAND_IMMEDIATE";
477 // 64-bits but only 32 bits are significant, and those bits are treated as being
479 def i64i32imm_pcrel : Operand<i64> {
480 let PrintMethod = "print_pcrel_imm";
481 let ParserMatchClass = X86AbsMemAsmOperand;
482 let OperandType = "OPERAND_PCREL";
485 // 64-bits but only 8 bits are significant.
486 def i64i8imm : Operand<i64> {
487 let ParserMatchClass = ImmSExti64i8AsmOperand;
488 let OperandType = "OPERAND_IMMEDIATE";
491 def lea64_32mem : Operand<i32> {
492 let PrintMethod = "printi32mem";
493 let AsmOperandLowerMethod = "lower_lea64_32mem";
494 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
495 let ParserMatchClass = X86MemAsmOperand;
499 //===----------------------------------------------------------------------===//
500 // X86 Complex Pattern Definitions.
503 // Define X86 specific addressing mode.
504 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
505 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
506 [add, sub, mul, X86mul_imm, shl, or, frameindex],
508 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
509 [tglobaltlsaddr], []>;
511 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
512 [tglobaltlsaddr], []>;
514 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
515 [add, sub, mul, X86mul_imm, shl, or, frameindex,
518 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
519 [tglobaltlsaddr], []>;
521 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
522 [tglobaltlsaddr], []>;
524 //===----------------------------------------------------------------------===//
525 // X86 Instruction Predicate Definitions.
526 def HasCMov : Predicate<"Subtarget->hasCMov()">;
527 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
529 def HasMMX : Predicate<"Subtarget->hasMMX()">;
530 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
531 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
532 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
533 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
534 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
535 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
536 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
537 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
538 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
539 def HasAVX : Predicate<"Subtarget->hasAVX()">;
540 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
542 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
543 def HasAES : Predicate<"Subtarget->hasAES()">;
544 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
545 def HasFMA : Predicate<"Subtarget->hasFMA()">;
546 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
547 def HasXOP : Predicate<"Subtarget->hasXOP()">;
548 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
549 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
550 def HasF16C : Predicate<"Subtarget->hasF16C()">;
551 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
552 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
553 def HasBMI : Predicate<"Subtarget->hasBMI()">;
554 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
555 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
556 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
557 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
558 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
559 AssemblerPredicate<"!Mode64Bit">;
560 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
561 AssemblerPredicate<"Mode64Bit">;
562 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
563 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
564 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
565 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
566 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
567 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
568 "TM.getCodeModel() != CodeModel::Kernel">;
569 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
570 "TM.getCodeModel() == CodeModel::Kernel">;
571 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
572 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
573 def OptForSize : Predicate<"OptForSize">;
574 def OptForSpeed : Predicate<"!OptForSize">;
575 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
576 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
578 //===----------------------------------------------------------------------===//
579 // X86 Instruction Format Definitions.
582 include "X86InstrFormats.td"
584 //===----------------------------------------------------------------------===//
585 // Pattern fragments.
588 // X86 specific condition code. These correspond to CondCode in
589 // X86InstrInfo.h. They must be kept in synch.
590 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
591 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
592 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
593 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
594 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
595 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
596 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
597 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
598 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
599 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
600 def X86_COND_NO : PatLeaf<(i8 10)>;
601 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
602 def X86_COND_NS : PatLeaf<(i8 12)>;
603 def X86_COND_O : PatLeaf<(i8 13)>;
604 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
605 def X86_COND_S : PatLeaf<(i8 15)>;
607 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
608 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
609 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
610 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
613 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
616 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
618 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
620 def i64immZExt32SExt8 : ImmLeaf<i64, [{
621 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
624 // Helper fragments for loads.
625 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
626 // known to be 32-bit aligned or better. Ditto for i8 to i16.
627 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
628 LoadSDNode *LD = cast<LoadSDNode>(N);
629 ISD::LoadExtType ExtType = LD->getExtensionType();
630 if (ExtType == ISD::NON_EXTLOAD)
632 if (ExtType == ISD::EXTLOAD)
633 return LD->getAlignment() >= 2 && !LD->isVolatile();
637 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
638 LoadSDNode *LD = cast<LoadSDNode>(N);
639 ISD::LoadExtType ExtType = LD->getExtensionType();
640 if (ExtType == ISD::EXTLOAD)
641 return LD->getAlignment() >= 2 && !LD->isVolatile();
645 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
646 LoadSDNode *LD = cast<LoadSDNode>(N);
647 ISD::LoadExtType ExtType = LD->getExtensionType();
648 if (ExtType == ISD::NON_EXTLOAD)
650 if (ExtType == ISD::EXTLOAD)
651 return LD->getAlignment() >= 4 && !LD->isVolatile();
655 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
656 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
657 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
658 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
659 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
661 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
662 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
663 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
664 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
665 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
666 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
668 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
669 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
670 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
671 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
672 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
673 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
674 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
675 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
676 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
677 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
679 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
680 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
681 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
682 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
683 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
684 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
685 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
686 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
687 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
688 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
691 // An 'and' node with a single use.
692 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
693 return N->hasOneUse();
695 // An 'srl' node with a single use.
696 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
697 return N->hasOneUse();
699 // An 'trunc' node with a single use.
700 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
701 return N->hasOneUse();
704 //===----------------------------------------------------------------------===//
709 let neverHasSideEffects = 1 in {
710 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
711 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
712 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
713 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
714 "nop{l}\t$zero", [], IIC_NOP>, TB;
718 // Constructing a stack frame.
719 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
720 "enter\t$len, $lvl", [], IIC_ENTER>;
722 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
723 def LEAVE : I<0xC9, RawFrm,
724 (outs), (ins), "leave", [], IIC_LEAVE>,
725 Requires<[In32BitMode]>;
727 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
728 def LEAVE64 : I<0xC9, RawFrm,
729 (outs), (ins), "leave", [], IIC_LEAVE>,
730 Requires<[In64BitMode]>;
732 //===----------------------------------------------------------------------===//
733 // Miscellaneous Instructions.
736 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
738 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
739 IIC_POP_REG16>, OpSize;
740 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
742 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
743 IIC_POP_REG>, OpSize;
744 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [],
745 IIC_POP_MEM>, OpSize;
746 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
748 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
751 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
752 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
753 Requires<[In32BitMode]>;
756 let mayStore = 1 in {
757 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
758 IIC_PUSH_REG>, OpSize;
759 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
761 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
762 IIC_PUSH_REG>, OpSize;
763 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
766 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
768 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
771 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
772 "push{l}\t$imm", [], IIC_PUSH_IMM>;
773 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
774 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
775 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
776 "push{l}\t$imm", [], IIC_PUSH_IMM>;
778 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
780 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
781 Requires<[In32BitMode]>;
786 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
788 def POP64r : I<0x58, AddRegFrm,
789 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
790 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
792 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
795 let mayStore = 1 in {
796 def PUSH64r : I<0x50, AddRegFrm,
797 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
798 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
800 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
805 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
806 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
807 "push{q}\t$imm", [], IIC_PUSH_IMM>;
808 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
809 "push{q}\t$imm", [], IIC_PUSH_IMM>;
810 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
811 "push{q}\t$imm", [], IIC_PUSH_IMM>;
814 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
815 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
816 Requires<[In64BitMode]>;
817 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
818 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
819 Requires<[In64BitMode]>;
823 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
824 mayLoad=1, neverHasSideEffects=1 in {
825 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
826 Requires<[In32BitMode]>;
828 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
829 mayStore=1, neverHasSideEffects=1 in {
830 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
831 Requires<[In32BitMode]>;
834 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
835 def BSWAP32r : I<0xC8, AddRegFrm,
836 (outs GR32:$dst), (ins GR32:$src),
838 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
840 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
842 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
843 } // Constraints = "$src = $dst"
845 // Bit scan instructions.
846 let Defs = [EFLAGS] in {
847 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
848 "bsf{w}\t{$src, $dst|$dst, $src}",
849 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
850 IIC_BSF>, TB, OpSize;
851 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
852 "bsf{w}\t{$src, $dst|$dst, $src}",
853 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
854 IIC_BSF>, TB, OpSize;
855 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
856 "bsf{l}\t{$src, $dst|$dst, $src}",
857 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB;
858 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
859 "bsf{l}\t{$src, $dst|$dst, $src}",
860 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
862 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
863 "bsf{q}\t{$src, $dst|$dst, $src}",
864 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
866 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
867 "bsf{q}\t{$src, $dst|$dst, $src}",
868 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
871 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
872 "bsr{w}\t{$src, $dst|$dst, $src}",
873 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
875 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
876 "bsr{w}\t{$src, $dst|$dst, $src}",
877 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
880 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
881 "bsr{l}\t{$src, $dst|$dst, $src}",
882 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB;
883 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
884 "bsr{l}\t{$src, $dst|$dst, $src}",
885 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
887 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
888 "bsr{q}\t{$src, $dst|$dst, $src}",
889 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB;
890 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
891 "bsr{q}\t{$src, $dst|$dst, $src}",
892 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
897 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
898 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
899 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
900 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
901 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
902 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
905 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
906 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
907 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
908 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
909 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
910 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
911 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
912 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
913 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
915 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
916 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
917 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
918 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
920 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
921 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
922 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
923 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
926 //===----------------------------------------------------------------------===//
927 // Move Instructions.
930 let neverHasSideEffects = 1 in {
931 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
932 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
933 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
934 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
935 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
936 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
937 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
938 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
940 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
941 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
942 "mov{b}\t{$src, $dst|$dst, $src}",
943 [(set GR8:$dst, imm:$src)], IIC_MOV>;
944 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
945 "mov{w}\t{$src, $dst|$dst, $src}",
946 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
947 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
948 "mov{l}\t{$src, $dst|$dst, $src}",
949 [(set GR32:$dst, imm:$src)], IIC_MOV>;
950 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
951 "movabs{q}\t{$src, $dst|$dst, $src}",
952 [(set GR64:$dst, imm:$src)], IIC_MOV>;
953 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
954 "mov{q}\t{$src, $dst|$dst, $src}",
955 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
958 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
959 "mov{b}\t{$src, $dst|$dst, $src}",
960 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
961 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
962 "mov{w}\t{$src, $dst|$dst, $src}",
963 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
964 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
965 "mov{l}\t{$src, $dst|$dst, $src}",
966 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
967 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
968 "mov{q}\t{$src, $dst|$dst, $src}",
969 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
971 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
972 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
973 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
974 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
975 Requires<[In32BitMode]>;
976 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
977 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
978 Requires<[In32BitMode]>;
979 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
980 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
981 Requires<[In32BitMode]>;
982 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
983 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
984 Requires<[In32BitMode]>;
985 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
986 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
987 Requires<[In32BitMode]>;
988 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
989 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
990 Requires<[In32BitMode]>;
992 // FIXME: These definitions are utterly broken
993 // Just leave them commented out for now because they're useless outside
994 // of the large code model, and most compilers won't generate the instructions
997 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
998 "mov{q}\t{$src, %rax|RAX, $src}", []>;
999 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
1000 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1001 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
1002 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1003 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
1004 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1008 let isCodeGenOnly = 1 in {
1009 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1010 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1011 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1012 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1013 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1014 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1015 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1016 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1019 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1020 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1021 "mov{b}\t{$src, $dst|$dst, $src}",
1022 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1023 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1024 "mov{w}\t{$src, $dst|$dst, $src}",
1025 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1026 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1027 "mov{l}\t{$src, $dst|$dst, $src}",
1028 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1029 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1030 "mov{q}\t{$src, $dst|$dst, $src}",
1031 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1034 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1035 "mov{b}\t{$src, $dst|$dst, $src}",
1036 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1037 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1038 "mov{w}\t{$src, $dst|$dst, $src}",
1039 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1040 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1041 "mov{l}\t{$src, $dst|$dst, $src}",
1042 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1043 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1044 "mov{q}\t{$src, $dst|$dst, $src}",
1045 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1047 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1048 // that they can be used for copying and storing h registers, which can't be
1049 // encoded when a REX prefix is present.
1050 let isCodeGenOnly = 1 in {
1051 let neverHasSideEffects = 1 in
1052 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1053 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1054 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>;
1056 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1057 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1058 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1060 let mayLoad = 1, neverHasSideEffects = 1,
1061 canFoldAsLoad = 1, isReMaterializable = 1 in
1062 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1063 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1064 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1069 // Condition code ops, incl. set if equal/not equal/...
1070 let Defs = [EFLAGS], Uses = [AH] in
1071 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1072 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1073 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1074 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1075 IIC_AHF>; // AH = flags
1078 //===----------------------------------------------------------------------===//
1079 // Bit tests instructions: BT, BTS, BTR, BTC.
1081 let Defs = [EFLAGS] in {
1082 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1083 "bt{w}\t{$src2, $src1|$src1, $src2}",
1084 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1086 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1087 "bt{l}\t{$src2, $src1|$src1, $src2}",
1088 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1089 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1090 "bt{q}\t{$src2, $src1|$src1, $src2}",
1091 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1093 // Unlike with the register+register form, the memory+register form of the
1094 // bt instruction does not ignore the high bits of the index. From ISel's
1095 // perspective, this is pretty bizarre. Make these instructions disassembly
1098 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1099 "bt{w}\t{$src2, $src1|$src1, $src2}",
1100 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1101 // (implicit EFLAGS)]
1103 >, OpSize, TB, Requires<[FastBTMem]>;
1104 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1105 "bt{l}\t{$src2, $src1|$src1, $src2}",
1106 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1107 // (implicit EFLAGS)]
1109 >, TB, Requires<[FastBTMem]>;
1110 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1111 "bt{q}\t{$src2, $src1|$src1, $src2}",
1112 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1113 // (implicit EFLAGS)]
1117 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1118 "bt{w}\t{$src2, $src1|$src1, $src2}",
1119 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1120 IIC_BT_RI>, OpSize, TB;
1121 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1122 "bt{l}\t{$src2, $src1|$src1, $src2}",
1123 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1125 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1126 "bt{q}\t{$src2, $src1|$src1, $src2}",
1127 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1130 // Note that these instructions don't need FastBTMem because that
1131 // only applies when the other operand is in a register. When it's
1132 // an immediate, bt is still fast.
1133 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1134 "bt{w}\t{$src2, $src1|$src1, $src2}",
1135 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1136 ], IIC_BT_MI>, OpSize, TB;
1137 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1138 "bt{l}\t{$src2, $src1|$src1, $src2}",
1139 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1141 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1142 "bt{q}\t{$src2, $src1|$src1, $src2}",
1143 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1144 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1147 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1148 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1150 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1151 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1152 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1153 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1154 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1155 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1157 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1158 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1159 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1160 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1161 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1162 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1164 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1165 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1166 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1167 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1168 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1169 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1171 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1172 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1173 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1174 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1176 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1177 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1179 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1180 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1181 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1182 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1183 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1184 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1186 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1187 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1188 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1189 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1190 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1191 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1193 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1194 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1195 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1196 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1197 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1198 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1200 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1201 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1202 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1203 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1205 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1206 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1208 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1209 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1210 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1211 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1212 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1213 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1215 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1216 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1217 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1218 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1219 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1220 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1222 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1223 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1224 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1225 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1226 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1227 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1229 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1230 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1231 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1232 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1233 } // Defs = [EFLAGS]
1236 //===----------------------------------------------------------------------===//
1241 // Atomic swap. These are just normal xchg instructions. But since a memory
1242 // operand is referenced, the atomicity is ensured.
1243 let Constraints = "$val = $dst" in {
1244 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1245 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1246 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))],
1248 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1249 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1250 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))],
1253 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1254 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1255 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))],
1257 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1258 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1259 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))],
1262 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1263 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1264 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1265 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1266 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1267 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1268 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1269 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1272 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1273 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1274 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1275 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1276 Requires<[In32BitMode]>;
1277 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1278 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1279 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1280 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1281 Requires<[In64BitMode]>;
1282 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1283 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1287 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1288 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1289 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1290 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1292 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1293 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1294 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1295 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1297 let mayLoad = 1, mayStore = 1 in {
1298 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1299 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1300 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1301 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1303 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1304 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1305 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1306 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1310 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1311 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1312 IIC_CMPXCHG_REG8>, TB;
1313 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1314 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1315 IIC_CMPXCHG_REG>, TB, OpSize;
1316 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1317 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1318 IIC_CMPXCHG_REG>, TB;
1319 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1320 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1321 IIC_CMPXCHG_REG>, TB;
1323 let mayLoad = 1, mayStore = 1 in {
1324 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1325 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1326 IIC_CMPXCHG_MEM8>, TB;
1327 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1328 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1329 IIC_CMPXCHG_MEM>, TB, OpSize;
1330 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1331 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1332 IIC_CMPXCHG_MEM>, TB;
1333 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1334 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1335 IIC_CMPXCHG_MEM>, TB;
1338 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1339 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1340 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1342 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1343 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1344 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1345 TB, Requires<[HasCmpxchg16b]>;
1349 // Lock instruction prefix
1350 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1352 // Rex64 instruction prefix
1353 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1355 // Data16 instruction prefix
1356 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1358 // Repeat string operation instruction prefixes
1359 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1360 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1361 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1362 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1363 // Repeat while not equal (used with CMPS and SCAS)
1364 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1368 // String manipulation instructions
1369 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1370 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1371 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1372 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1374 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1375 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1376 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1379 // Flag instructions
1380 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1381 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1382 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1383 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1384 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1385 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1386 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1388 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1390 // Table lookup instructions
1391 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>;
1393 // ASCII Adjust After Addition
1394 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1395 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1396 Requires<[In32BitMode]>;
1398 // ASCII Adjust AX Before Division
1399 // sets AL, AH and EFLAGS and uses AL and AH
1400 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1401 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1403 // ASCII Adjust AX After Multiply
1404 // sets AL, AH and EFLAGS and uses AL
1405 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1406 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1408 // ASCII Adjust AL After Subtraction - sets
1409 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1410 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1411 Requires<[In32BitMode]>;
1413 // Decimal Adjust AL after Addition
1414 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1415 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1416 Requires<[In32BitMode]>;
1418 // Decimal Adjust AL after Subtraction
1419 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1420 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1421 Requires<[In32BitMode]>;
1423 // Check Array Index Against Bounds
1424 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1425 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1426 Requires<[In32BitMode]>;
1427 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1428 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1429 Requires<[In32BitMode]>;
1431 // Adjust RPL Field of Segment Selector
1432 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1433 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1434 Requires<[In32BitMode]>;
1435 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1436 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1437 Requires<[In32BitMode]>;
1439 //===----------------------------------------------------------------------===//
1440 // MOVBE Instructions
1442 let Predicates = [HasMOVBE] in {
1443 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1444 "movbe{w}\t{$src, $dst|$dst, $src}",
1445 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1447 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1448 "movbe{l}\t{$src, $dst|$dst, $src}",
1449 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1451 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1452 "movbe{q}\t{$src, $dst|$dst, $src}",
1453 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1455 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1456 "movbe{w}\t{$src, $dst|$dst, $src}",
1457 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1459 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1460 "movbe{l}\t{$src, $dst|$dst, $src}",
1461 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1463 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1464 "movbe{q}\t{$src, $dst|$dst, $src}",
1465 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1469 //===----------------------------------------------------------------------===//
1470 // RDRAND Instruction
1472 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1473 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1475 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1476 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1478 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1479 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1481 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1484 //===----------------------------------------------------------------------===//
1485 // LZCNT Instruction
1487 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1488 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1489 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1490 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1492 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1493 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1494 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1495 (implicit EFLAGS)]>, XS, OpSize;
1497 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1498 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1499 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1500 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1501 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1502 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1503 (implicit EFLAGS)]>, XS;
1505 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1506 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1507 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1509 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1510 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1511 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1512 (implicit EFLAGS)]>, XS;
1515 //===----------------------------------------------------------------------===//
1518 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1519 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1520 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1521 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1523 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1524 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1525 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1526 (implicit EFLAGS)]>, XS, OpSize;
1528 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1529 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1530 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1531 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1532 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1533 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1534 (implicit EFLAGS)]>, XS;
1536 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1537 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1538 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1540 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1541 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1542 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1543 (implicit EFLAGS)]>, XS;
1546 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1547 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1549 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1550 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1551 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V;
1552 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1553 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1554 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>,
1558 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1559 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1560 X86blsr_flag, loadi32>;
1561 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1562 X86blsr_flag, loadi64>, VEX_W;
1563 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1564 X86blsmsk_flag, loadi32>;
1565 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1566 X86blsmsk_flag, loadi64>, VEX_W;
1567 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1568 X86blsi_flag, loadi32>;
1569 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1570 X86blsi_flag, loadi64>, VEX_W;
1573 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1574 X86MemOperand x86memop, Intrinsic Int,
1576 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1577 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1578 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1580 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1581 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1582 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1583 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1586 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1587 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1588 int_x86_bmi_bextr_32, loadi32>;
1589 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1590 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1593 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1594 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1595 int_x86_bmi_bzhi_32, loadi32>;
1596 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1597 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1600 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1601 X86MemOperand x86memop, Intrinsic Int,
1603 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1604 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1605 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1607 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1608 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1609 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1612 let Predicates = [HasBMI2] in {
1613 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1614 int_x86_bmi_pdep_32, loadi32>, T8XD;
1615 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1616 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1617 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1618 int_x86_bmi_pext_32, loadi32>, T8XS;
1619 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1620 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1623 //===----------------------------------------------------------------------===//
1625 //===----------------------------------------------------------------------===//
1627 include "X86InstrArithmetic.td"
1628 include "X86InstrCMovSetCC.td"
1629 include "X86InstrExtension.td"
1630 include "X86InstrControl.td"
1631 include "X86InstrShiftRotate.td"
1633 // X87 Floating Point Stack.
1634 include "X86InstrFPStack.td"
1636 // SIMD support (SSE, MMX and AVX)
1637 include "X86InstrFragmentsSIMD.td"
1639 // FMA - Fused Multiply-Add support (requires FMA)
1640 include "X86InstrFMA.td"
1643 include "X86InstrXOP.td"
1645 // SSE, MMX and 3DNow! vector support.
1646 include "X86InstrSSE.td"
1647 include "X86InstrMMX.td"
1648 include "X86Instr3DNow.td"
1650 include "X86InstrVMX.td"
1651 include "X86InstrSVM.td"
1653 // System instructions.
1654 include "X86InstrSystem.td"
1656 // Compiler Pseudo Instructions and Pat Patterns
1657 include "X86InstrCompiler.td"
1659 //===----------------------------------------------------------------------===//
1660 // Assembler Mnemonic Aliases
1661 //===----------------------------------------------------------------------===//
1663 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1664 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1666 def : MnemonicAlias<"cbw", "cbtw">;
1667 def : MnemonicAlias<"cwde", "cwtl">;
1668 def : MnemonicAlias<"cwd", "cwtd">;
1669 def : MnemonicAlias<"cdq", "cltd">;
1670 def : MnemonicAlias<"cdqe", "cltq">;
1671 def : MnemonicAlias<"cqo", "cqto">;
1673 // lret maps to lretl, it is not ambiguous with lretq.
1674 def : MnemonicAlias<"lret", "lretl">;
1676 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1677 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1679 def : MnemonicAlias<"loopz", "loope">;
1680 def : MnemonicAlias<"loopnz", "loopne">;
1682 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1683 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1684 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1685 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1686 def : MnemonicAlias<"popfd", "popfl">;
1688 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1689 // all modes. However: "push (addr)" and "push $42" should default to
1690 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1691 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1692 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1693 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1694 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1695 def : MnemonicAlias<"pushfd", "pushfl">;
1697 def : MnemonicAlias<"repe", "rep">;
1698 def : MnemonicAlias<"repz", "rep">;
1699 def : MnemonicAlias<"repnz", "repne">;
1701 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1702 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1704 def : MnemonicAlias<"salb", "shlb">;
1705 def : MnemonicAlias<"salw", "shlw">;
1706 def : MnemonicAlias<"sall", "shll">;
1707 def : MnemonicAlias<"salq", "shlq">;
1709 def : MnemonicAlias<"smovb", "movsb">;
1710 def : MnemonicAlias<"smovw", "movsw">;
1711 def : MnemonicAlias<"smovl", "movsl">;
1712 def : MnemonicAlias<"smovq", "movsq">;
1714 def : MnemonicAlias<"ud2a", "ud2">;
1715 def : MnemonicAlias<"verrw", "verr">;
1717 // System instruction aliases.
1718 def : MnemonicAlias<"iret", "iretl">;
1719 def : MnemonicAlias<"sysret", "sysretl">;
1720 def : MnemonicAlias<"sysexit", "sysexitl">;
1722 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1723 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1724 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1725 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1726 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1727 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1728 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1729 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1732 // Floating point stack aliases.
1733 def : MnemonicAlias<"fcmovz", "fcmove">;
1734 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1735 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1736 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1737 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1738 def : MnemonicAlias<"fcomip", "fcompi">;
1739 def : MnemonicAlias<"fildq", "fildll">;
1740 def : MnemonicAlias<"fistpq", "fistpll">;
1741 def : MnemonicAlias<"fisttpq", "fisttpll">;
1742 def : MnemonicAlias<"fldcww", "fldcw">;
1743 def : MnemonicAlias<"fnstcww", "fnstcw">;
1744 def : MnemonicAlias<"fnstsww", "fnstsw">;
1745 def : MnemonicAlias<"fucomip", "fucompi">;
1746 def : MnemonicAlias<"fwait", "wait">;
1749 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1750 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1751 !strconcat(Prefix, NewCond, Suffix)>;
1753 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1754 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1755 /// example "setz" -> "sete".
1756 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1757 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1758 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1759 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1760 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1761 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1762 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1763 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1764 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1765 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1766 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1768 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1769 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1770 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1771 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1774 // Aliases for set<CC>
1775 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1776 // Aliases for j<CC>
1777 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1778 // Aliases for cmov<CC>{w,l,q}
1779 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1780 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1781 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1784 //===----------------------------------------------------------------------===//
1785 // Assembler Instruction Aliases
1786 //===----------------------------------------------------------------------===//
1788 // aad/aam default to base 10 if no operand is specified.
1789 def : InstAlias<"aad", (AAD8i8 10)>;
1790 def : InstAlias<"aam", (AAM8i8 10)>;
1792 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1793 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1796 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1797 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1798 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1799 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1801 // div and idiv aliases for explicit A register.
1802 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1803 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1804 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1805 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1806 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1807 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1808 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1809 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1810 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1811 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1812 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1813 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1814 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1815 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1816 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1817 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1821 // Various unary fpstack operations default to operating on on ST1.
1822 // For example, "fxch" -> "fxch %st(1)"
1823 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1824 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1825 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1826 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1827 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1828 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1829 def : InstAlias<"fxch", (XCH_F ST1)>;
1830 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1831 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1832 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1833 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1834 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1835 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1837 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1838 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1839 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1841 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1842 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1843 (Inst RST:$op), EmitAlias>;
1844 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1845 (Inst ST0), EmitAlias>;
1848 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1849 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1850 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1851 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1852 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1853 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1854 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1855 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1856 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1857 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1858 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1859 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1860 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1861 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1862 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1863 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1866 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1867 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1868 // solely because gas supports it.
1869 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1870 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1871 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1872 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1873 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1874 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1876 // We accept "fnstsw %eax" even though it only writes %ax.
1877 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
1878 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
1879 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
1881 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1882 // this is compatible with what GAS does.
1883 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1884 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1885 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1886 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1888 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1889 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1890 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1891 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1892 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1893 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1894 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1896 // inb %dx -> inb %al, %dx
1897 def : InstAlias<"inb %dx", (IN8rr)>;
1898 def : InstAlias<"inw %dx", (IN16rr)>;
1899 def : InstAlias<"inl %dx", (IN32rr)>;
1900 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1901 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1902 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1905 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1906 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1907 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1908 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1909 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1910 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1911 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1913 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1914 // the move. All segment/mem forms are equivalent, this has the shortest
1916 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1917 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1919 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1920 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1922 // Match 'movq GR64, MMX' as an alias for movd.
1923 def : InstAlias<"movq $src, $dst",
1924 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1925 def : InstAlias<"movq $src, $dst",
1926 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1928 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1929 // alias for movsl. (as in rep; movsd)
1930 def : InstAlias<"movsd", (MOVSD)>;
1933 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1934 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1935 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1936 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1937 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1938 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1939 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1942 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1943 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1944 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1945 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1946 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1947 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1948 // Note: No GR32->GR64 movzx form.
1950 // outb %dx -> outb %al, %dx
1951 def : InstAlias<"outb %dx", (OUT8rr)>;
1952 def : InstAlias<"outw %dx", (OUT16rr)>;
1953 def : InstAlias<"outl %dx", (OUT32rr)>;
1954 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1955 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1956 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1958 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1959 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1960 // errors, since its encoding is the most compact.
1961 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1963 // shld/shrd op,op -> shld op, op, CL
1964 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
1965 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
1966 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
1967 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
1968 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
1969 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
1971 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
1972 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
1973 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
1974 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
1975 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
1976 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
1978 /* FIXME: This is disabled because the asm matcher is currently incapable of
1979 * matching a fixed immediate like $1.
1980 // "shl X, $1" is an alias for "shl X".
1981 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1982 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1983 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1984 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1985 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1986 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1987 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1988 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1989 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1990 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1991 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1992 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1993 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1994 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1995 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1996 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1997 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2000 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2001 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2002 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2003 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2006 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2007 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
2008 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
2009 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
2010 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
2012 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2013 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2014 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2015 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2016 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2018 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2019 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2020 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2021 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2022 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;