1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
30 def SDTX86BrCond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
33 def SDTX86SetCC : SDTypeProfile<1, 1,
34 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
36 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
38 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
39 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
42 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
44 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
46 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
48 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
52 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
54 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
55 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
57 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
58 [SDNPHasChain, SDNPOutFlag]>;
60 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
61 [SDNPInFlag, SDNPOutFlag]>;
62 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
63 [SDNPHasChain, SDNPInFlag]>;
64 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
65 [SDNPInFlag, SDNPOutFlag]>;
67 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
68 [SDNPHasChain, SDNPOptInFlag]>;
70 def X86callseq_start :
71 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
72 [SDNPHasChain, SDNPOutFlag]>;
74 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
75 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
77 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
78 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
80 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
81 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
83 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
84 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
85 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
86 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
88 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
89 [SDNPHasChain, SDNPOutFlag]>;
91 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
92 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
94 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
96 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
99 //===----------------------------------------------------------------------===//
100 // X86 Operand Definitions.
103 // *mem - Operand definitions for the funky X86 addressing mode operands.
105 class X86MemOperand<string printMethod> : Operand<iPTR> {
106 let PrintMethod = printMethod;
107 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
110 def i8mem : X86MemOperand<"printi8mem">;
111 def i16mem : X86MemOperand<"printi16mem">;
112 def i32mem : X86MemOperand<"printi32mem">;
113 def i64mem : X86MemOperand<"printi64mem">;
114 def i128mem : X86MemOperand<"printi128mem">;
115 def f32mem : X86MemOperand<"printf32mem">;
116 def f64mem : X86MemOperand<"printf64mem">;
117 def f128mem : X86MemOperand<"printf128mem">;
119 def lea32mem : Operand<i32> {
120 let PrintMethod = "printi32mem";
121 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
124 def SSECC : Operand<i8> {
125 let PrintMethod = "printSSECC";
128 def piclabel: Operand<i32> {
129 let PrintMethod = "printPICLabel";
132 // A couple of more descriptive operand definitions.
133 // 16-bits but only 8 bits are significant.
134 def i16i8imm : Operand<i16>;
135 // 32-bits but only 8 bits are significant.
136 def i32i8imm : Operand<i32>;
138 // Branch targets have OtherVT type.
139 def brtarget : Operand<OtherVT>;
141 //===----------------------------------------------------------------------===//
142 // X86 Complex Pattern Definitions.
145 // Define X86 specific addressing mode.
146 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
147 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
148 [add, mul, shl, or, frameindex], []>;
150 //===----------------------------------------------------------------------===//
151 // X86 Instruction Format Definitions.
154 // Format specifies the encoding used by the instruction. This is part of the
155 // ad-hoc solution used to emit machine instruction encodings by our machine
157 class Format<bits<6> val> {
161 def Pseudo : Format<0>; def RawFrm : Format<1>;
162 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
163 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
164 def MRMSrcMem : Format<6>;
165 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
166 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
167 def MRM6r : Format<22>; def MRM7r : Format<23>;
168 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
169 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
170 def MRM6m : Format<30>; def MRM7m : Format<31>;
171 def MRMInitReg : Format<32>;
173 //===----------------------------------------------------------------------===//
174 // X86 Instruction Predicate Definitions.
175 def HasMMX : Predicate<"Subtarget->hasMMX()">;
176 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
177 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
178 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
179 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
180 def FPStack : Predicate<"!Subtarget->hasSSE2()">;
181 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
182 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
183 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
184 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
185 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
187 //===----------------------------------------------------------------------===//
188 // X86 specific pattern fragments.
191 // ImmType - This specifies the immediate type used by an instruction. This is
192 // part of the ad-hoc solution used to emit machine instruction encodings by our
193 // machine code emitter.
194 class ImmType<bits<3> val> {
197 def NoImm : ImmType<0>;
198 def Imm8 : ImmType<1>;
199 def Imm16 : ImmType<2>;
200 def Imm32 : ImmType<3>;
201 def Imm64 : ImmType<4>;
203 // FPFormat - This specifies what form this FP instruction has. This is used by
204 // the Floating-Point stackifier pass.
205 class FPFormat<bits<3> val> {
208 def NotFP : FPFormat<0>;
209 def ZeroArgFP : FPFormat<1>;
210 def OneArgFP : FPFormat<2>;
211 def OneArgFPRW : FPFormat<3>;
212 def TwoArgFP : FPFormat<4>;
213 def CompareFP : FPFormat<5>;
214 def CondMovFP : FPFormat<6>;
215 def SpecialFP : FPFormat<7>;
218 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
220 let Namespace = "X86";
222 bits<8> Opcode = opcod;
224 bits<6> FormBits = Form.Value;
226 bits<3> ImmTypeBits = ImmT.Value;
228 dag OperandList = ops;
229 string AsmString = AsmStr;
232 // Attributes specific to X86 instructions...
234 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
235 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
237 bits<4> Prefix = 0; // Which prefix byte does this inst have?
238 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
239 FPFormat FPForm; // What flavor of FP instruction is this?
240 bits<3> FPFormBits = 0;
244 // Prefix byte classes which are used to indicate to the ad-hoc machine code
245 // emitter that various prefix bytes are required.
246 class OpSize { bit hasOpSizePrefix = 1; }
247 class AdSize { bit hasAdSizePrefix = 1; }
248 class REX_W { bit hasREX_WPrefix = 1; }
249 class TB { bits<4> Prefix = 1; }
250 class REP { bits<4> Prefix = 2; }
251 class D8 { bits<4> Prefix = 3; }
252 class D9 { bits<4> Prefix = 4; }
253 class DA { bits<4> Prefix = 5; }
254 class DB { bits<4> Prefix = 6; }
255 class DC { bits<4> Prefix = 7; }
256 class DD { bits<4> Prefix = 8; }
257 class DE { bits<4> Prefix = 9; }
258 class DF { bits<4> Prefix = 10; }
259 class XD { bits<4> Prefix = 11; }
260 class XS { bits<4> Prefix = 12; }
261 class T8 { bits<4> Prefix = 13; }
262 class TA { bits<4> Prefix = 14; }
265 //===----------------------------------------------------------------------===//
266 // Pattern fragments...
269 // X86 specific condition code. These correspond to CondCode in
270 // X86ISelLowering.h. They must be kept in synch.
271 def X86_COND_A : PatLeaf<(i8 0)>;
272 def X86_COND_AE : PatLeaf<(i8 1)>;
273 def X86_COND_B : PatLeaf<(i8 2)>;
274 def X86_COND_BE : PatLeaf<(i8 3)>;
275 def X86_COND_E : PatLeaf<(i8 4)>;
276 def X86_COND_G : PatLeaf<(i8 5)>;
277 def X86_COND_GE : PatLeaf<(i8 6)>;
278 def X86_COND_L : PatLeaf<(i8 7)>;
279 def X86_COND_LE : PatLeaf<(i8 8)>;
280 def X86_COND_NE : PatLeaf<(i8 9)>;
281 def X86_COND_NO : PatLeaf<(i8 10)>;
282 def X86_COND_NP : PatLeaf<(i8 11)>;
283 def X86_COND_NS : PatLeaf<(i8 12)>;
284 def X86_COND_O : PatLeaf<(i8 13)>;
285 def X86_COND_P : PatLeaf<(i8 14)>;
286 def X86_COND_S : PatLeaf<(i8 15)>;
288 def i16immSExt8 : PatLeaf<(i16 imm), [{
289 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
290 // sign extended field.
291 return (int16_t)N->getValue() == (int8_t)N->getValue();
294 def i32immSExt8 : PatLeaf<(i32 imm), [{
295 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
296 // sign extended field.
297 return (int32_t)N->getValue() == (int8_t)N->getValue();
300 // Helper fragments for loads.
301 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
302 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
303 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
304 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
306 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
307 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
309 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
310 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
311 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
312 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
313 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
315 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
316 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
317 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
318 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
319 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
320 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
322 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
323 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
324 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
325 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
326 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
327 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
329 //===----------------------------------------------------------------------===//
330 // Instruction templates...
333 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
334 : X86Inst<o, f, NoImm, ops, asm> {
335 let Pattern = pattern;
338 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
339 : X86Inst<o, f, Imm8 , ops, asm> {
340 let Pattern = pattern;
343 class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
344 : X86Inst<o, f, Imm16, ops, asm> {
345 let Pattern = pattern;
348 class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
349 : X86Inst<o, f, Imm32, ops, asm> {
350 let Pattern = pattern;
354 //===----------------------------------------------------------------------===//
355 // Instruction list...
358 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
359 // a stack adjustment and the codegen must know that they may modify the stack
360 // pointer before prolog-epilog rewriting occurs.
361 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
362 [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>;
363 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
365 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
367 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
368 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
369 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst),
370 "#IMPLICIT_DEF $dst",
371 [(set GR8:$dst, (undef))]>;
372 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst),
373 "#IMPLICIT_DEF $dst",
374 [(set GR16:$dst, (undef))]>;
375 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst),
376 "#IMPLICIT_DEF $dst",
377 [(set GR32:$dst, (undef))]>;
380 def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
383 def TRUNC_32_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src),
384 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>;
385 def TRUNC_16_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src),
386 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>;
387 def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src),
388 "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
389 [(set GR16:$dst, (trunc GR32:$src))]>;
391 //===----------------------------------------------------------------------===//
392 // Control Flow Instructions...
395 // Return instructions.
396 let isTerminator = 1, isReturn = 1, isBarrier = 1,
397 hasCtrlDep = 1, noResults = 1 in {
398 def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>;
399 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt",
400 [(X86retflag imm:$amt)]>;
403 // All branches are RawFrm, Void, Branch, and Terminators
404 let isBranch = 1, isTerminator = 1, noResults = 1 in
405 class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
406 I<opcode, RawFrm, ops, asm, pattern>;
409 let isBranch = 1, isBarrier = 1 in
410 def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
412 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
413 def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst",
414 [(brind GR32:$dst)]>;
415 def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst",
416 [(brind (loadi32 addr:$dst))]>;
419 // Conditional branches
420 def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
421 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
422 def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
423 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
424 def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
425 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
426 def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
427 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
428 def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
429 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
430 def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
431 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
433 def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
434 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
435 def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
436 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
437 def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
438 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
439 def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
440 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
442 def JS : IBr<0x88, (ops brtarget:$dst), "js $dst",
443 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
444 def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst",
445 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
446 def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst",
447 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
448 def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst",
449 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
450 def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst",
451 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
452 def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
453 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
455 //===----------------------------------------------------------------------===//
456 // Call Instructions...
458 let isCall = 1, noResults = 1 in
459 // All calls clobber the non-callee saved registers...
460 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
461 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
462 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
463 def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops),
464 "call ${dst:call}", []>;
465 def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
466 "call {*}$dst", [(X86call GR32:$dst)]>;
467 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst, variable_ops),
472 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
473 def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
475 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
476 def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL",
478 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
479 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
480 "jmp {*}$dst # TAIL CALL", []>;
482 //===----------------------------------------------------------------------===//
483 // Miscellaneous Instructions...
485 def LEAVE : I<0xC9, RawFrm,
486 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
487 def POP32r : I<0x58, AddRegFrm,
488 (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
490 def PUSH32r : I<0x50, AddRegFrm,
491 (ops GR32:$reg), "push{l} $reg", []>, Imp<[ESP],[ESP]>;
493 def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label),
496 let isTwoAddress = 1 in // GR32 = bswap GR32
497 def BSWAP32r : I<0xC8, AddRegFrm,
498 (ops GR32:$dst, GR32:$src),
500 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
502 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
503 (ops GR8:$src1, GR8:$src2),
504 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
505 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
506 (ops GR16:$src1, GR16:$src2),
507 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
508 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
509 (ops GR32:$src1, GR32:$src2),
510 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
512 def XCHG8mr : I<0x86, MRMDestMem,
513 (ops i8mem:$src1, GR8:$src2),
514 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
515 def XCHG16mr : I<0x87, MRMDestMem,
516 (ops i16mem:$src1, GR16:$src2),
517 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
518 def XCHG32mr : I<0x87, MRMDestMem,
519 (ops i32mem:$src1, GR32:$src2),
520 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
521 def XCHG8rm : I<0x86, MRMSrcMem,
522 (ops GR8:$src1, i8mem:$src2),
523 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
524 def XCHG16rm : I<0x87, MRMSrcMem,
525 (ops GR16:$src1, i16mem:$src2),
526 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
527 def XCHG32rm : I<0x87, MRMSrcMem,
528 (ops GR32:$src1, i32mem:$src2),
529 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
531 def LEA16r : I<0x8D, MRMSrcMem,
532 (ops GR16:$dst, i32mem:$src),
533 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
534 def LEA32r : I<0x8D, MRMSrcMem,
535 (ops GR32:$dst, lea32mem:$src),
536 "lea{l} {$src|$dst}, {$dst|$src}",
537 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
539 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
541 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
542 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}",
543 [(X86rep_movs i16)]>,
544 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
545 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsl|rep movsd}",
546 [(X86rep_movs i32)]>,
547 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
549 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}",
551 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
552 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}",
553 [(X86rep_stos i16)]>,
554 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
555 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}",
556 [(X86rep_stos i32)]>,
557 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
559 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
560 TB, Imp<[],[RAX,RDX]>;
562 //===----------------------------------------------------------------------===//
563 // Input/Output Instructions...
565 def IN8rr : I<0xEC, RawFrm, (ops),
566 "in{b} {%dx, %al|%AL, %DX}",
567 []>, Imp<[DX], [AL]>;
568 def IN16rr : I<0xED, RawFrm, (ops),
569 "in{w} {%dx, %ax|%AX, %DX}",
570 []>, Imp<[DX], [AX]>, OpSize;
571 def IN32rr : I<0xED, RawFrm, (ops),
572 "in{l} {%dx, %eax|%EAX, %DX}",
573 []>, Imp<[DX],[EAX]>;
575 def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
576 "in{b} {$port, %al|%AL, $port}",
579 def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
580 "in{w} {$port, %ax|%AX, $port}",
582 Imp<[], [AX]>, OpSize;
583 def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
584 "in{l} {$port, %eax|%EAX, $port}",
588 def OUT8rr : I<0xEE, RawFrm, (ops),
589 "out{b} {%al, %dx|%DX, %AL}",
590 []>, Imp<[DX, AL], []>;
591 def OUT16rr : I<0xEF, RawFrm, (ops),
592 "out{w} {%ax, %dx|%DX, %AX}",
593 []>, Imp<[DX, AX], []>, OpSize;
594 def OUT32rr : I<0xEF, RawFrm, (ops),
595 "out{l} {%eax, %dx|%DX, %EAX}",
596 []>, Imp<[DX, EAX], []>;
598 def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
599 "out{b} {%al, $port|$port, %AL}",
602 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
603 "out{w} {%ax, $port|$port, %AX}",
605 Imp<[AX], []>, OpSize;
606 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
607 "out{l} {%eax, $port|$port, %EAX}",
611 //===----------------------------------------------------------------------===//
612 // Move Instructions...
614 def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src),
615 "mov{b} {$src, $dst|$dst, $src}", []>;
616 def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src),
617 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
618 def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
619 "mov{l} {$src, $dst|$dst, $src}", []>;
620 let isReMaterializable = 1 in {
621 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
622 "mov{b} {$src, $dst|$dst, $src}",
623 [(set GR8:$dst, imm:$src)]>;
624 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src),
625 "mov{w} {$src, $dst|$dst, $src}",
626 [(set GR16:$dst, imm:$src)]>, OpSize;
627 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
628 "mov{l} {$src, $dst|$dst, $src}",
629 [(set GR32:$dst, imm:$src)]>;
631 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
632 "mov{b} {$src, $dst|$dst, $src}",
633 [(store (i8 imm:$src), addr:$dst)]>;
634 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
635 "mov{w} {$src, $dst|$dst, $src}",
636 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
637 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
638 "mov{l} {$src, $dst|$dst, $src}",
639 [(store (i32 imm:$src), addr:$dst)]>;
641 def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
642 "mov{b} {$src, $dst|$dst, $src}",
643 [(set GR8:$dst, (load addr:$src))]>;
644 def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
645 "mov{w} {$src, $dst|$dst, $src}",
646 [(set GR16:$dst, (load addr:$src))]>, OpSize;
647 def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
648 "mov{l} {$src, $dst|$dst, $src}",
649 [(set GR32:$dst, (load addr:$src))]>;
651 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src),
652 "mov{b} {$src, $dst|$dst, $src}",
653 [(store GR8:$src, addr:$dst)]>;
654 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src),
655 "mov{w} {$src, $dst|$dst, $src}",
656 [(store GR16:$src, addr:$dst)]>, OpSize;
657 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src),
658 "mov{l} {$src, $dst|$dst, $src}",
659 [(store GR32:$src, addr:$dst)]>;
661 //===----------------------------------------------------------------------===//
662 // Fixed-Register Multiplication and Division Instructions...
665 // Extra precision multiplication
666 def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src",
667 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
668 // This probably ought to be moved to a def : Pat<> if the
669 // syntax can be accepted.
670 [(set AL, (mul AL, GR8:$src))]>,
671 Imp<[AL],[AX]>; // AL,AH = AL*GR8
672 def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>,
673 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
674 def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>,
675 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
676 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
678 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
679 // This probably ought to be moved to a def : Pat<> if the
680 // syntax can be accepted.
681 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
682 Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
683 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
684 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
685 OpSize; // AX,DX = AX*[mem16]
686 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
687 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
689 def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>,
690 Imp<[AL],[AX]>; // AL,AH = AL*GR8
691 def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>,
692 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
693 def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>,
694 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
695 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
696 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
697 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
698 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
699 OpSize; // AX,DX = AX*[mem16]
700 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
702 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
704 // unsigned division/remainder
705 def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH
706 "div{b} $src", []>, Imp<[AX],[AX]>;
707 def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX
708 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
709 def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
710 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
711 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
712 "div{b} $src", []>, Imp<[AX],[AX]>;
713 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
714 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
715 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
716 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
718 // Signed division/remainder.
719 def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH
720 "idiv{b} $src", []>, Imp<[AX],[AX]>;
721 def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX
722 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
723 def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
724 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
725 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
726 "idiv{b} $src", []>, Imp<[AX],[AX]>;
727 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
728 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
729 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
730 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
733 //===----------------------------------------------------------------------===//
734 // Two address Instructions...
736 let isTwoAddress = 1 in {
739 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
740 (ops GR16:$dst, GR16:$src1, GR16:$src2),
741 "cmovb {$src2, $dst|$dst, $src2}",
742 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
745 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
746 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
747 "cmovb {$src2, $dst|$dst, $src2}",
748 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
751 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
752 (ops GR32:$dst, GR32:$src1, GR32:$src2),
753 "cmovb {$src2, $dst|$dst, $src2}",
754 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
757 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
758 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
759 "cmovb {$src2, $dst|$dst, $src2}",
760 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
764 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
765 (ops GR16:$dst, GR16:$src1, GR16:$src2),
766 "cmovae {$src2, $dst|$dst, $src2}",
767 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
770 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
771 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
772 "cmovae {$src2, $dst|$dst, $src2}",
773 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
776 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
777 (ops GR32:$dst, GR32:$src1, GR32:$src2),
778 "cmovae {$src2, $dst|$dst, $src2}",
779 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
782 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
783 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
784 "cmovae {$src2, $dst|$dst, $src2}",
785 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
789 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
790 (ops GR16:$dst, GR16:$src1, GR16:$src2),
791 "cmove {$src2, $dst|$dst, $src2}",
792 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
795 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
796 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
797 "cmove {$src2, $dst|$dst, $src2}",
798 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
801 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
802 (ops GR32:$dst, GR32:$src1, GR32:$src2),
803 "cmove {$src2, $dst|$dst, $src2}",
804 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
807 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
808 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
809 "cmove {$src2, $dst|$dst, $src2}",
810 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
814 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
815 (ops GR16:$dst, GR16:$src1, GR16:$src2),
816 "cmovne {$src2, $dst|$dst, $src2}",
817 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
820 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
821 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
822 "cmovne {$src2, $dst|$dst, $src2}",
823 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
826 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
827 (ops GR32:$dst, GR32:$src1, GR32:$src2),
828 "cmovne {$src2, $dst|$dst, $src2}",
829 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
832 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
833 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
834 "cmovne {$src2, $dst|$dst, $src2}",
835 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
839 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
840 (ops GR16:$dst, GR16:$src1, GR16:$src2),
841 "cmovbe {$src2, $dst|$dst, $src2}",
842 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
845 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
846 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
847 "cmovbe {$src2, $dst|$dst, $src2}",
848 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
851 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
852 (ops GR32:$dst, GR32:$src1, GR32:$src2),
853 "cmovbe {$src2, $dst|$dst, $src2}",
854 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
857 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
858 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
859 "cmovbe {$src2, $dst|$dst, $src2}",
860 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
864 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
865 (ops GR16:$dst, GR16:$src1, GR16:$src2),
866 "cmova {$src2, $dst|$dst, $src2}",
867 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
870 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
871 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
872 "cmova {$src2, $dst|$dst, $src2}",
873 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
876 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
877 (ops GR32:$dst, GR32:$src1, GR32:$src2),
878 "cmova {$src2, $dst|$dst, $src2}",
879 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
882 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
883 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
884 "cmova {$src2, $dst|$dst, $src2}",
885 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
889 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
890 (ops GR16:$dst, GR16:$src1, GR16:$src2),
891 "cmovl {$src2, $dst|$dst, $src2}",
892 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
895 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
896 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
897 "cmovl {$src2, $dst|$dst, $src2}",
898 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
901 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
902 (ops GR32:$dst, GR32:$src1, GR32:$src2),
903 "cmovl {$src2, $dst|$dst, $src2}",
904 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
907 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
908 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
909 "cmovl {$src2, $dst|$dst, $src2}",
910 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
914 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
915 (ops GR16:$dst, GR16:$src1, GR16:$src2),
916 "cmovge {$src2, $dst|$dst, $src2}",
917 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
920 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
921 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
922 "cmovge {$src2, $dst|$dst, $src2}",
923 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
926 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
927 (ops GR32:$dst, GR32:$src1, GR32:$src2),
928 "cmovge {$src2, $dst|$dst, $src2}",
929 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
932 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
933 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
934 "cmovge {$src2, $dst|$dst, $src2}",
935 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
939 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
940 (ops GR16:$dst, GR16:$src1, GR16:$src2),
941 "cmovle {$src2, $dst|$dst, $src2}",
942 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
945 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
946 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
947 "cmovle {$src2, $dst|$dst, $src2}",
948 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
951 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
952 (ops GR32:$dst, GR32:$src1, GR32:$src2),
953 "cmovle {$src2, $dst|$dst, $src2}",
954 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
957 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
958 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
959 "cmovle {$src2, $dst|$dst, $src2}",
960 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
964 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
965 (ops GR16:$dst, GR16:$src1, GR16:$src2),
966 "cmovg {$src2, $dst|$dst, $src2}",
967 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
970 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
971 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
972 "cmovg {$src2, $dst|$dst, $src2}",
973 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
976 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
977 (ops GR32:$dst, GR32:$src1, GR32:$src2),
978 "cmovg {$src2, $dst|$dst, $src2}",
979 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
982 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
983 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
984 "cmovg {$src2, $dst|$dst, $src2}",
985 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
989 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
990 (ops GR16:$dst, GR16:$src1, GR16:$src2),
991 "cmovs {$src2, $dst|$dst, $src2}",
992 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
995 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
996 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
997 "cmovs {$src2, $dst|$dst, $src2}",
998 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1001 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1002 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1003 "cmovs {$src2, $dst|$dst, $src2}",
1004 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1007 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1008 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1009 "cmovs {$src2, $dst|$dst, $src2}",
1010 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1014 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1015 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1016 "cmovns {$src2, $dst|$dst, $src2}",
1017 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1020 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1021 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1022 "cmovns {$src2, $dst|$dst, $src2}",
1023 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1026 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1027 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1028 "cmovns {$src2, $dst|$dst, $src2}",
1029 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1032 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1033 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1034 "cmovns {$src2, $dst|$dst, $src2}",
1035 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1039 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1040 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1041 "cmovp {$src2, $dst|$dst, $src2}",
1042 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1045 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1046 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1047 "cmovp {$src2, $dst|$dst, $src2}",
1048 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1051 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1052 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1053 "cmovp {$src2, $dst|$dst, $src2}",
1054 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1057 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1058 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1059 "cmovp {$src2, $dst|$dst, $src2}",
1060 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1064 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1065 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1066 "cmovnp {$src2, $dst|$dst, $src2}",
1067 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1070 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1071 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1072 "cmovnp {$src2, $dst|$dst, $src2}",
1073 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1076 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1077 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1078 "cmovnp {$src2, $dst|$dst, $src2}",
1079 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1082 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1083 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1084 "cmovnp {$src2, $dst|$dst, $src2}",
1085 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1090 // unary instructions
1091 let CodeSize = 2 in {
1092 def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst",
1093 [(set GR8:$dst, (ineg GR8:$src))]>;
1094 def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst",
1095 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1096 def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst",
1097 [(set GR32:$dst, (ineg GR32:$src))]>;
1098 let isTwoAddress = 0 in {
1099 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst",
1100 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1101 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst",
1102 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1103 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst",
1104 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1108 def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst",
1109 [(set GR8:$dst, (not GR8:$src))]>;
1110 def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst",
1111 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1112 def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst",
1113 [(set GR32:$dst, (not GR32:$src))]>;
1114 let isTwoAddress = 0 in {
1115 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst",
1116 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1117 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst",
1118 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1119 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst",
1120 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1124 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1126 def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
1127 [(set GR8:$dst, (add GR8:$src, 1))]>;
1128 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1129 def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
1130 [(set GR16:$dst, (add GR16:$src, 1))]>,
1131 OpSize, Requires<[In32BitMode]>;
1132 def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
1133 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1135 let isTwoAddress = 0, CodeSize = 2 in {
1136 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
1137 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1138 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
1139 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1140 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
1141 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1145 def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst",
1146 [(set GR8:$dst, (add GR8:$src, -1))]>;
1147 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1148 def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
1149 [(set GR16:$dst, (add GR16:$src, -1))]>,
1150 OpSize, Requires<[In32BitMode]>;
1151 def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
1152 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1155 let isTwoAddress = 0, CodeSize = 2 in {
1156 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
1157 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1158 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
1159 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1160 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
1161 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1164 // Logical operators...
1165 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1166 def AND8rr : I<0x20, MRMDestReg,
1167 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1168 "and{b} {$src2, $dst|$dst, $src2}",
1169 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1170 def AND16rr : I<0x21, MRMDestReg,
1171 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1172 "and{w} {$src2, $dst|$dst, $src2}",
1173 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1174 def AND32rr : I<0x21, MRMDestReg,
1175 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1176 "and{l} {$src2, $dst|$dst, $src2}",
1177 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1180 def AND8rm : I<0x22, MRMSrcMem,
1181 (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1182 "and{b} {$src2, $dst|$dst, $src2}",
1183 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1184 def AND16rm : I<0x23, MRMSrcMem,
1185 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1186 "and{w} {$src2, $dst|$dst, $src2}",
1187 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1188 def AND32rm : I<0x23, MRMSrcMem,
1189 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1190 "and{l} {$src2, $dst|$dst, $src2}",
1191 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1193 def AND8ri : Ii8<0x80, MRM4r,
1194 (ops GR8 :$dst, GR8 :$src1, i8imm :$src2),
1195 "and{b} {$src2, $dst|$dst, $src2}",
1196 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1197 def AND16ri : Ii16<0x81, MRM4r,
1198 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1199 "and{w} {$src2, $dst|$dst, $src2}",
1200 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1201 def AND32ri : Ii32<0x81, MRM4r,
1202 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1203 "and{l} {$src2, $dst|$dst, $src2}",
1204 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1205 def AND16ri8 : Ii8<0x83, MRM4r,
1206 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1207 "and{w} {$src2, $dst|$dst, $src2}",
1208 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1210 def AND32ri8 : Ii8<0x83, MRM4r,
1211 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1212 "and{l} {$src2, $dst|$dst, $src2}",
1213 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1215 let isTwoAddress = 0 in {
1216 def AND8mr : I<0x20, MRMDestMem,
1217 (ops i8mem :$dst, GR8 :$src),
1218 "and{b} {$src, $dst|$dst, $src}",
1219 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1220 def AND16mr : I<0x21, MRMDestMem,
1221 (ops i16mem:$dst, GR16:$src),
1222 "and{w} {$src, $dst|$dst, $src}",
1223 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1225 def AND32mr : I<0x21, MRMDestMem,
1226 (ops i32mem:$dst, GR32:$src),
1227 "and{l} {$src, $dst|$dst, $src}",
1228 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1229 def AND8mi : Ii8<0x80, MRM4m,
1230 (ops i8mem :$dst, i8imm :$src),
1231 "and{b} {$src, $dst|$dst, $src}",
1232 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1233 def AND16mi : Ii16<0x81, MRM4m,
1234 (ops i16mem:$dst, i16imm:$src),
1235 "and{w} {$src, $dst|$dst, $src}",
1236 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1238 def AND32mi : Ii32<0x81, MRM4m,
1239 (ops i32mem:$dst, i32imm:$src),
1240 "and{l} {$src, $dst|$dst, $src}",
1241 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1242 def AND16mi8 : Ii8<0x83, MRM4m,
1243 (ops i16mem:$dst, i16i8imm :$src),
1244 "and{w} {$src, $dst|$dst, $src}",
1245 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1247 def AND32mi8 : Ii8<0x83, MRM4m,
1248 (ops i32mem:$dst, i32i8imm :$src),
1249 "and{l} {$src, $dst|$dst, $src}",
1250 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1254 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1255 def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1256 "or{b} {$src2, $dst|$dst, $src2}",
1257 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1258 def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1259 "or{w} {$src2, $dst|$dst, $src2}",
1260 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1261 def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1262 "or{l} {$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1265 def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1266 "or{b} {$src2, $dst|$dst, $src2}",
1267 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1268 def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1269 "or{w} {$src2, $dst|$dst, $src2}",
1270 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1271 def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1272 "or{l} {$src2, $dst|$dst, $src2}",
1273 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1275 def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1276 "or{b} {$src2, $dst|$dst, $src2}",
1277 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1278 def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1279 "or{w} {$src2, $dst|$dst, $src2}",
1280 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1281 def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1282 "or{l} {$src2, $dst|$dst, $src2}",
1283 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1285 def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1286 "or{w} {$src2, $dst|$dst, $src2}",
1287 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1288 def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1289 "or{l} {$src2, $dst|$dst, $src2}",
1290 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1291 let isTwoAddress = 0 in {
1292 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src),
1293 "or{b} {$src, $dst|$dst, $src}",
1294 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1295 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src),
1296 "or{w} {$src, $dst|$dst, $src}",
1297 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1298 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1299 "or{l} {$src, $dst|$dst, $src}",
1300 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1301 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
1302 "or{b} {$src, $dst|$dst, $src}",
1303 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1304 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
1305 "or{w} {$src, $dst|$dst, $src}",
1306 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1308 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
1309 "or{l} {$src, $dst|$dst, $src}",
1310 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1311 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src),
1312 "or{w} {$src, $dst|$dst, $src}",
1313 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1315 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src),
1316 "or{l} {$src, $dst|$dst, $src}",
1317 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1321 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1322 def XOR8rr : I<0x30, MRMDestReg,
1323 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1324 "xor{b} {$src2, $dst|$dst, $src2}",
1325 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1326 def XOR16rr : I<0x31, MRMDestReg,
1327 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1328 "xor{w} {$src2, $dst|$dst, $src2}",
1329 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1330 def XOR32rr : I<0x31, MRMDestReg,
1331 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1332 "xor{l} {$src2, $dst|$dst, $src2}",
1333 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1336 def XOR8rm : I<0x32, MRMSrcMem ,
1337 (ops GR8 :$dst, GR8:$src1, i8mem :$src2),
1338 "xor{b} {$src2, $dst|$dst, $src2}",
1339 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1340 def XOR16rm : I<0x33, MRMSrcMem ,
1341 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1342 "xor{w} {$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1344 def XOR32rm : I<0x33, MRMSrcMem ,
1345 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1346 "xor{l} {$src2, $dst|$dst, $src2}",
1347 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1349 def XOR8ri : Ii8<0x80, MRM6r,
1350 (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1351 "xor{b} {$src2, $dst|$dst, $src2}",
1352 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1353 def XOR16ri : Ii16<0x81, MRM6r,
1354 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1355 "xor{w} {$src2, $dst|$dst, $src2}",
1356 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1357 def XOR32ri : Ii32<0x81, MRM6r,
1358 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1359 "xor{l} {$src2, $dst|$dst, $src2}",
1360 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1361 def XOR16ri8 : Ii8<0x83, MRM6r,
1362 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1363 "xor{w} {$src2, $dst|$dst, $src2}",
1364 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1366 def XOR32ri8 : Ii8<0x83, MRM6r,
1367 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1368 "xor{l} {$src2, $dst|$dst, $src2}",
1369 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1370 let isTwoAddress = 0 in {
1371 def XOR8mr : I<0x30, MRMDestMem,
1372 (ops i8mem :$dst, GR8 :$src),
1373 "xor{b} {$src, $dst|$dst, $src}",
1374 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1375 def XOR16mr : I<0x31, MRMDestMem,
1376 (ops i16mem:$dst, GR16:$src),
1377 "xor{w} {$src, $dst|$dst, $src}",
1378 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1380 def XOR32mr : I<0x31, MRMDestMem,
1381 (ops i32mem:$dst, GR32:$src),
1382 "xor{l} {$src, $dst|$dst, $src}",
1383 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1384 def XOR8mi : Ii8<0x80, MRM6m,
1385 (ops i8mem :$dst, i8imm :$src),
1386 "xor{b} {$src, $dst|$dst, $src}",
1387 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1388 def XOR16mi : Ii16<0x81, MRM6m,
1389 (ops i16mem:$dst, i16imm:$src),
1390 "xor{w} {$src, $dst|$dst, $src}",
1391 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1393 def XOR32mi : Ii32<0x81, MRM6m,
1394 (ops i32mem:$dst, i32imm:$src),
1395 "xor{l} {$src, $dst|$dst, $src}",
1396 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1397 def XOR16mi8 : Ii8<0x83, MRM6m,
1398 (ops i16mem:$dst, i16i8imm :$src),
1399 "xor{w} {$src, $dst|$dst, $src}",
1400 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1402 def XOR32mi8 : Ii8<0x83, MRM6m,
1403 (ops i32mem:$dst, i32i8imm :$src),
1404 "xor{l} {$src, $dst|$dst, $src}",
1405 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1408 // Shift instructions
1409 def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src),
1410 "shl{b} {%cl, $dst|$dst, %CL}",
1411 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
1412 def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src),
1413 "shl{w} {%cl, $dst|$dst, %CL}",
1414 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1415 def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src),
1416 "shl{l} {%cl, $dst|$dst, %CL}",
1417 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
1419 def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1420 "shl{b} {$src2, $dst|$dst, $src2}",
1421 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1422 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1423 def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1424 "shl{w} {$src2, $dst|$dst, $src2}",
1425 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1426 def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1427 "shl{l} {$src2, $dst|$dst, $src2}",
1428 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1431 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1432 def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
1434 def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
1435 "shl{w} $dst", []>, OpSize;
1436 def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
1439 let isTwoAddress = 0 in {
1440 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
1441 "shl{b} {%cl, $dst|$dst, %CL}",
1442 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1444 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
1445 "shl{w} {%cl, $dst|$dst, %CL}",
1446 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1447 Imp<[CL],[]>, OpSize;
1448 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
1449 "shl{l} {%cl, $dst|$dst, %CL}",
1450 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1452 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
1453 "shl{b} {$src, $dst|$dst, $src}",
1454 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1455 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
1456 "shl{w} {$src, $dst|$dst, $src}",
1457 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1459 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
1460 "shl{l} {$src, $dst|$dst, $src}",
1461 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1464 def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
1466 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1467 def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
1469 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1471 def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
1473 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1476 def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
1477 "shr{b} {%cl, $dst|$dst, %CL}",
1478 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
1479 def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src),
1480 "shr{w} {%cl, $dst|$dst, %CL}",
1481 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1482 def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src),
1483 "shr{l} {%cl, $dst|$dst, %CL}",
1484 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
1486 def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1487 "shr{b} {$src2, $dst|$dst, $src2}",
1488 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1489 def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1490 "shr{w} {$src2, $dst|$dst, $src2}",
1491 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1492 def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1493 "shr{l} {$src2, $dst|$dst, $src2}",
1494 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1497 def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
1499 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1500 def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
1502 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1503 def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
1505 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1507 let isTwoAddress = 0 in {
1508 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
1509 "shr{b} {%cl, $dst|$dst, %CL}",
1510 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1512 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
1513 "shr{w} {%cl, $dst|$dst, %CL}",
1514 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1515 Imp<[CL],[]>, OpSize;
1516 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
1517 "shr{l} {%cl, $dst|$dst, %CL}",
1518 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1520 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
1521 "shr{b} {$src, $dst|$dst, $src}",
1522 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1523 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
1524 "shr{w} {$src, $dst|$dst, $src}",
1525 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1527 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
1528 "shr{l} {$src, $dst|$dst, $src}",
1529 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1532 def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
1534 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1535 def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
1537 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1538 def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
1540 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1543 def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
1544 "sar{b} {%cl, $dst|$dst, %CL}",
1545 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
1546 def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src),
1547 "sar{w} {%cl, $dst|$dst, %CL}",
1548 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1549 def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src),
1550 "sar{l} {%cl, $dst|$dst, %CL}",
1551 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
1553 def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1554 "sar{b} {$src2, $dst|$dst, $src2}",
1555 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1556 def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1557 "sar{w} {$src2, $dst|$dst, $src2}",
1558 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1560 def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1561 "sar{l} {$src2, $dst|$dst, $src2}",
1562 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1565 def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
1567 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1568 def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
1570 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1571 def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
1573 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1575 let isTwoAddress = 0 in {
1576 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
1577 "sar{b} {%cl, $dst|$dst, %CL}",
1578 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1580 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
1581 "sar{w} {%cl, $dst|$dst, %CL}",
1582 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1583 Imp<[CL],[]>, OpSize;
1584 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
1585 "sar{l} {%cl, $dst|$dst, %CL}",
1586 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1588 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
1589 "sar{b} {$src, $dst|$dst, $src}",
1590 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1591 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
1592 "sar{w} {$src, $dst|$dst, $src}",
1593 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1595 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
1596 "sar{l} {$src, $dst|$dst, $src}",
1597 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1600 def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
1602 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1603 def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst),
1605 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1607 def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst),
1609 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1612 // Rotate instructions
1613 // FIXME: provide shorter instructions when imm8 == 1
1614 def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src),
1615 "rol{b} {%cl, $dst|$dst, %CL}",
1616 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
1617 def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src),
1618 "rol{w} {%cl, $dst|$dst, %CL}",
1619 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1620 def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src),
1621 "rol{l} {%cl, $dst|$dst, %CL}",
1622 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
1624 def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1625 "rol{b} {$src2, $dst|$dst, $src2}",
1626 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1627 def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1628 "rol{w} {$src2, $dst|$dst, $src2}",
1629 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1630 def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1631 "rol{l} {$src2, $dst|$dst, $src2}",
1632 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1635 def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1),
1637 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1638 def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1),
1640 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1641 def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1),
1643 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1645 let isTwoAddress = 0 in {
1646 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
1647 "rol{b} {%cl, $dst|$dst, %CL}",
1648 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1650 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
1651 "rol{w} {%cl, $dst|$dst, %CL}",
1652 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1653 Imp<[CL],[]>, OpSize;
1654 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
1655 "rol{l} {%cl, $dst|$dst, %CL}",
1656 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1658 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
1659 "rol{b} {$src, $dst|$dst, $src}",
1660 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1661 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
1662 "rol{w} {$src, $dst|$dst, $src}",
1663 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1665 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
1666 "rol{l} {$src, $dst|$dst, $src}",
1667 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1670 def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst),
1672 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1673 def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst),
1675 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1677 def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst),
1679 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1682 def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src),
1683 "ror{b} {%cl, $dst|$dst, %CL}",
1684 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
1685 def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src),
1686 "ror{w} {%cl, $dst|$dst, %CL}",
1687 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1688 def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src),
1689 "ror{l} {%cl, $dst|$dst, %CL}",
1690 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
1692 def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1693 "ror{b} {$src2, $dst|$dst, $src2}",
1694 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1695 def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1696 "ror{w} {$src2, $dst|$dst, $src2}",
1697 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1698 def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1699 "ror{l} {$src2, $dst|$dst, $src2}",
1700 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1703 def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1),
1705 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1706 def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1),
1708 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1709 def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1),
1711 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1713 let isTwoAddress = 0 in {
1714 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
1715 "ror{b} {%cl, $dst|$dst, %CL}",
1716 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1718 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
1719 "ror{w} {%cl, $dst|$dst, %CL}",
1720 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1721 Imp<[CL],[]>, OpSize;
1722 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
1723 "ror{l} {%cl, $dst|$dst, %CL}",
1724 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1726 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
1727 "ror{b} {$src, $dst|$dst, $src}",
1728 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1729 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
1730 "ror{w} {$src, $dst|$dst, $src}",
1731 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1733 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
1734 "ror{l} {$src, $dst|$dst, $src}",
1735 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1738 def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst),
1740 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1741 def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst),
1743 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1745 def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst),
1747 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1752 // Double shift instructions (generalizations of rotate)
1753 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1754 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1755 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
1757 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1758 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1759 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
1761 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1762 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1763 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1764 Imp<[CL],[]>, TB, OpSize;
1765 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1766 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1767 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1768 Imp<[CL],[]>, TB, OpSize;
1770 let isCommutable = 1 in { // These instructions commute to each other.
1771 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1772 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1773 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1774 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1777 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1778 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1779 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1780 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1783 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1784 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1785 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1786 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1789 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1790 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1791 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1792 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1797 let isTwoAddress = 0 in {
1798 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1799 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1800 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1803 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1804 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1805 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1808 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1809 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1810 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1811 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1812 (i8 imm:$src3)), addr:$dst)]>,
1814 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1815 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1816 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1817 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1818 (i8 imm:$src3)), addr:$dst)]>,
1821 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1822 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1823 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1825 Imp<[CL],[]>, TB, OpSize;
1826 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1827 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1828 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1830 Imp<[CL],[]>, TB, OpSize;
1831 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1832 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1833 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1834 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1835 (i8 imm:$src3)), addr:$dst)]>,
1837 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1838 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1839 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1840 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1841 (i8 imm:$src3)), addr:$dst)]>,
1847 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1848 def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1849 "add{b} {$src2, $dst|$dst, $src2}",
1850 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1851 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1852 def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1853 "add{w} {$src2, $dst|$dst, $src2}",
1854 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1855 def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1856 "add{l} {$src2, $dst|$dst, $src2}",
1857 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1858 } // end isConvertibleToThreeAddress
1859 } // end isCommutable
1860 def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1861 "add{b} {$src2, $dst|$dst, $src2}",
1862 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1863 def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1864 "add{w} {$src2, $dst|$dst, $src2}",
1865 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
1866 def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1867 "add{l} {$src2, $dst|$dst, $src2}",
1868 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1870 def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1871 "add{b} {$src2, $dst|$dst, $src2}",
1872 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1874 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1875 def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1876 "add{w} {$src2, $dst|$dst, $src2}",
1877 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1878 def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1879 "add{l} {$src2, $dst|$dst, $src2}",
1880 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1881 def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1882 "add{w} {$src2, $dst|$dst, $src2}",
1883 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
1885 def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1886 "add{l} {$src2, $dst|$dst, $src2}",
1887 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1890 let isTwoAddress = 0 in {
1891 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1892 "add{b} {$src2, $dst|$dst, $src2}",
1893 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1894 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1895 "add{w} {$src2, $dst|$dst, $src2}",
1896 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1898 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1899 "add{l} {$src2, $dst|$dst, $src2}",
1900 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1901 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1902 "add{b} {$src2, $dst|$dst, $src2}",
1903 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1904 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1905 "add{w} {$src2, $dst|$dst, $src2}",
1906 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1908 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1909 "add{l} {$src2, $dst|$dst, $src2}",
1910 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1911 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
1912 "add{w} {$src2, $dst|$dst, $src2}",
1913 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1915 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
1916 "add{l} {$src2, $dst|$dst, $src2}",
1917 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1920 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1921 def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1922 "adc{l} {$src2, $dst|$dst, $src2}",
1923 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1925 def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1926 "adc{l} {$src2, $dst|$dst, $src2}",
1927 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1928 def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1929 "adc{l} {$src2, $dst|$dst, $src2}",
1930 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1931 def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1932 "adc{l} {$src2, $dst|$dst, $src2}",
1933 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1935 let isTwoAddress = 0 in {
1936 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1937 "adc{l} {$src2, $dst|$dst, $src2}",
1938 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1939 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1940 "adc{l} {$src2, $dst|$dst, $src2}",
1941 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1942 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
1943 "adc{l} {$src2, $dst|$dst, $src2}",
1944 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1947 def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1948 "sub{b} {$src2, $dst|$dst, $src2}",
1949 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1950 def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1951 "sub{w} {$src2, $dst|$dst, $src2}",
1952 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1953 def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1954 "sub{l} {$src2, $dst|$dst, $src2}",
1955 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1956 def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1957 "sub{b} {$src2, $dst|$dst, $src2}",
1958 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1959 def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1960 "sub{w} {$src2, $dst|$dst, $src2}",
1961 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1962 def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1963 "sub{l} {$src2, $dst|$dst, $src2}",
1964 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1966 def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1967 "sub{b} {$src2, $dst|$dst, $src2}",
1968 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1969 def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1970 "sub{w} {$src2, $dst|$dst, $src2}",
1971 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1972 def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1973 "sub{l} {$src2, $dst|$dst, $src2}",
1974 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1975 def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1976 "sub{w} {$src2, $dst|$dst, $src2}",
1977 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1979 def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1980 "sub{l} {$src2, $dst|$dst, $src2}",
1981 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1982 let isTwoAddress = 0 in {
1983 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1984 "sub{b} {$src2, $dst|$dst, $src2}",
1985 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1986 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1987 "sub{w} {$src2, $dst|$dst, $src2}",
1988 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1990 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1991 "sub{l} {$src2, $dst|$dst, $src2}",
1992 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1993 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1994 "sub{b} {$src2, $dst|$dst, $src2}",
1995 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1996 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1997 "sub{w} {$src2, $dst|$dst, $src2}",
1998 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2000 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
2001 "sub{l} {$src2, $dst|$dst, $src2}",
2002 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2003 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
2004 "sub{w} {$src2, $dst|$dst, $src2}",
2005 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2007 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
2008 "sub{l} {$src2, $dst|$dst, $src2}",
2009 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2012 def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
2013 "sbb{l} {$src2, $dst|$dst, $src2}",
2014 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2016 let isTwoAddress = 0 in {
2017 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
2018 "sbb{l} {$src2, $dst|$dst, $src2}",
2019 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2020 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
2021 "sbb{b} {$src2, $dst|$dst, $src2}",
2022 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2023 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
2024 "sbb{l} {$src2, $dst|$dst, $src2}",
2025 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2026 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
2027 "sbb{l} {$src2, $dst|$dst, $src2}",
2028 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2030 def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2031 "sbb{l} {$src2, $dst|$dst, $src2}",
2032 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2033 def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2034 "sbb{l} {$src2, $dst|$dst, $src2}",
2035 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2036 def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2037 "sbb{l} {$src2, $dst|$dst, $src2}",
2038 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2040 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2041 def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
2042 "imul{w} {$src2, $dst|$dst, $src2}",
2043 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2044 def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
2045 "imul{l} {$src2, $dst|$dst, $src2}",
2046 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2048 def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
2049 "imul{w} {$src2, $dst|$dst, $src2}",
2050 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2052 def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2053 "imul{l} {$src2, $dst|$dst, $src2}",
2054 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2056 } // end Two Address instructions
2058 // Suprisingly enough, these are not two address instructions!
2059 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2060 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
2061 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2063 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2064 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2065 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2066 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2067 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2068 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
2069 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2070 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2072 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2073 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2074 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2075 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2077 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2078 (ops GR16:$dst, i16mem:$src1, i16imm:$src2),
2079 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2080 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2082 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2083 (ops GR32:$dst, i32mem:$src1, i32imm:$src2),
2084 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2085 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2086 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2087 (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2),
2088 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2089 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2091 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2092 (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2),
2093 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2094 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2096 //===----------------------------------------------------------------------===//
2097 // Test instructions are just like AND, except they don't generate a result.
2099 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2100 def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2),
2101 "test{b} {$src2, $src1|$src1, $src2}",
2102 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
2103 def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2),
2104 "test{w} {$src2, $src1|$src1, $src2}",
2105 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
2106 def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
2107 "test{l} {$src2, $src1|$src1, $src2}",
2108 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
2111 def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
2112 "test{b} {$src2, $src1|$src1, $src2}",
2113 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
2114 def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
2115 "test{w} {$src2, $src1|$src1, $src2}",
2116 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
2118 def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
2119 "test{l} {$src2, $src1|$src1, $src2}",
2120 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
2122 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2123 (ops GR8:$src1, i8imm:$src2),
2124 "test{b} {$src2, $src1|$src1, $src2}",
2125 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
2126 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2127 (ops GR16:$src1, i16imm:$src2),
2128 "test{w} {$src2, $src1|$src1, $src2}",
2129 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
2130 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2131 (ops GR32:$src1, i32imm:$src2),
2132 "test{l} {$src2, $src1|$src1, $src2}",
2133 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
2135 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2136 (ops i8mem:$src1, i8imm:$src2),
2137 "test{b} {$src2, $src1|$src1, $src2}",
2138 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
2139 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2140 (ops i16mem:$src1, i16imm:$src2),
2141 "test{w} {$src2, $src1|$src1, $src2}",
2142 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
2144 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2145 (ops i32mem:$src1, i32imm:$src2),
2146 "test{l} {$src2, $src1|$src1, $src2}",
2147 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
2150 // Condition code ops, incl. set if equal/not equal/...
2151 def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
2152 def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
2154 def SETEr : I<0x94, MRM0r,
2157 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2159 def SETEm : I<0x94, MRM0m,
2162 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2164 def SETNEr : I<0x95, MRM0r,
2167 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2169 def SETNEm : I<0x95, MRM0m,
2172 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2174 def SETLr : I<0x9C, MRM0r,
2177 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2178 TB; // GR8 = < signed
2179 def SETLm : I<0x9C, MRM0m,
2182 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2183 TB; // [mem8] = < signed
2184 def SETGEr : I<0x9D, MRM0r,
2187 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2188 TB; // GR8 = >= signed
2189 def SETGEm : I<0x9D, MRM0m,
2192 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2193 TB; // [mem8] = >= signed
2194 def SETLEr : I<0x9E, MRM0r,
2197 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2198 TB; // GR8 = <= signed
2199 def SETLEm : I<0x9E, MRM0m,
2202 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2203 TB; // [mem8] = <= signed
2204 def SETGr : I<0x9F, MRM0r,
2207 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2208 TB; // GR8 = > signed
2209 def SETGm : I<0x9F, MRM0m,
2212 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2213 TB; // [mem8] = > signed
2215 def SETBr : I<0x92, MRM0r,
2218 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2219 TB; // GR8 = < unsign
2220 def SETBm : I<0x92, MRM0m,
2223 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2224 TB; // [mem8] = < unsign
2225 def SETAEr : I<0x93, MRM0r,
2228 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2229 TB; // GR8 = >= unsign
2230 def SETAEm : I<0x93, MRM0m,
2233 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2234 TB; // [mem8] = >= unsign
2235 def SETBEr : I<0x96, MRM0r,
2238 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2239 TB; // GR8 = <= unsign
2240 def SETBEm : I<0x96, MRM0m,
2243 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2244 TB; // [mem8] = <= unsign
2245 def SETAr : I<0x97, MRM0r,
2248 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2249 TB; // GR8 = > signed
2250 def SETAm : I<0x97, MRM0m,
2253 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2254 TB; // [mem8] = > signed
2256 def SETSr : I<0x98, MRM0r,
2259 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2260 TB; // GR8 = <sign bit>
2261 def SETSm : I<0x98, MRM0m,
2264 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2265 TB; // [mem8] = <sign bit>
2266 def SETNSr : I<0x99, MRM0r,
2269 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2270 TB; // GR8 = !<sign bit>
2271 def SETNSm : I<0x99, MRM0m,
2274 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2275 TB; // [mem8] = !<sign bit>
2276 def SETPr : I<0x9A, MRM0r,
2279 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2281 def SETPm : I<0x9A, MRM0m,
2284 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2285 TB; // [mem8] = parity
2286 def SETNPr : I<0x9B, MRM0r,
2289 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2290 TB; // GR8 = not parity
2291 def SETNPm : I<0x9B, MRM0m,
2294 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2295 TB; // [mem8] = not parity
2297 // Integer comparisons
2298 def CMP8rr : I<0x38, MRMDestReg,
2299 (ops GR8 :$src1, GR8 :$src2),
2300 "cmp{b} {$src2, $src1|$src1, $src2}",
2301 [(X86cmp GR8:$src1, GR8:$src2)]>;
2302 def CMP16rr : I<0x39, MRMDestReg,
2303 (ops GR16:$src1, GR16:$src2),
2304 "cmp{w} {$src2, $src1|$src1, $src2}",
2305 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2306 def CMP32rr : I<0x39, MRMDestReg,
2307 (ops GR32:$src1, GR32:$src2),
2308 "cmp{l} {$src2, $src1|$src1, $src2}",
2309 [(X86cmp GR32:$src1, GR32:$src2)]>;
2310 def CMP8mr : I<0x38, MRMDestMem,
2311 (ops i8mem :$src1, GR8 :$src2),
2312 "cmp{b} {$src2, $src1|$src1, $src2}",
2313 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2314 def CMP16mr : I<0x39, MRMDestMem,
2315 (ops i16mem:$src1, GR16:$src2),
2316 "cmp{w} {$src2, $src1|$src1, $src2}",
2317 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2318 def CMP32mr : I<0x39, MRMDestMem,
2319 (ops i32mem:$src1, GR32:$src2),
2320 "cmp{l} {$src2, $src1|$src1, $src2}",
2321 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2322 def CMP8rm : I<0x3A, MRMSrcMem,
2323 (ops GR8 :$src1, i8mem :$src2),
2324 "cmp{b} {$src2, $src1|$src1, $src2}",
2325 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2326 def CMP16rm : I<0x3B, MRMSrcMem,
2327 (ops GR16:$src1, i16mem:$src2),
2328 "cmp{w} {$src2, $src1|$src1, $src2}",
2329 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2330 def CMP32rm : I<0x3B, MRMSrcMem,
2331 (ops GR32:$src1, i32mem:$src2),
2332 "cmp{l} {$src2, $src1|$src1, $src2}",
2333 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2334 def CMP8ri : Ii8<0x80, MRM7r,
2335 (ops GR8:$src1, i8imm:$src2),
2336 "cmp{b} {$src2, $src1|$src1, $src2}",
2337 [(X86cmp GR8:$src1, imm:$src2)]>;
2338 def CMP16ri : Ii16<0x81, MRM7r,
2339 (ops GR16:$src1, i16imm:$src2),
2340 "cmp{w} {$src2, $src1|$src1, $src2}",
2341 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2342 def CMP32ri : Ii32<0x81, MRM7r,
2343 (ops GR32:$src1, i32imm:$src2),
2344 "cmp{l} {$src2, $src1|$src1, $src2}",
2345 [(X86cmp GR32:$src1, imm:$src2)]>;
2346 def CMP8mi : Ii8 <0x80, MRM7m,
2347 (ops i8mem :$src1, i8imm :$src2),
2348 "cmp{b} {$src2, $src1|$src1, $src2}",
2349 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2350 def CMP16mi : Ii16<0x81, MRM7m,
2351 (ops i16mem:$src1, i16imm:$src2),
2352 "cmp{w} {$src2, $src1|$src1, $src2}",
2353 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2354 def CMP32mi : Ii32<0x81, MRM7m,
2355 (ops i32mem:$src1, i32imm:$src2),
2356 "cmp{l} {$src2, $src1|$src1, $src2}",
2357 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2358 def CMP16ri8 : Ii8<0x83, MRM7r,
2359 (ops GR16:$src1, i16i8imm:$src2),
2360 "cmp{w} {$src2, $src1|$src1, $src2}",
2361 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2362 def CMP16mi8 : Ii8<0x83, MRM7m,
2363 (ops i16mem:$src1, i16i8imm:$src2),
2364 "cmp{w} {$src2, $src1|$src1, $src2}",
2365 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2366 def CMP32mi8 : Ii8<0x83, MRM7m,
2367 (ops i32mem:$src1, i32i8imm:$src2),
2368 "cmp{l} {$src2, $src1|$src1, $src2}",
2369 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2370 def CMP32ri8 : Ii8<0x83, MRM7r,
2371 (ops GR32:$src1, i32i8imm:$src2),
2372 "cmp{l} {$src2, $src1|$src1, $src2}",
2373 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2375 // Sign/Zero extenders
2376 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2377 "movs{bw|x} {$src, $dst|$dst, $src}",
2378 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2379 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2380 "movs{bw|x} {$src, $dst|$dst, $src}",
2381 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2382 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2383 "movs{bl|x} {$src, $dst|$dst, $src}",
2384 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2385 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2386 "movs{bl|x} {$src, $dst|$dst, $src}",
2387 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2388 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2389 "movs{wl|x} {$src, $dst|$dst, $src}",
2390 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2391 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2392 "movs{wl|x} {$src, $dst|$dst, $src}",
2393 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2395 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2396 "movz{bw|x} {$src, $dst|$dst, $src}",
2397 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2398 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2399 "movz{bw|x} {$src, $dst|$dst, $src}",
2400 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2401 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2402 "movz{bl|x} {$src, $dst|$dst, $src}",
2403 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2404 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2405 "movz{bl|x} {$src, $dst|$dst, $src}",
2406 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2407 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2408 "movz{wl|x} {$src, $dst|$dst, $src}",
2409 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2410 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2411 "movz{wl|x} {$src, $dst|$dst, $src}",
2412 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2414 def CBW : I<0x98, RawFrm, (ops),
2415 "{cbtw|cbw}", []>, Imp<[AL],[AX]>, OpSize; // AX = signext(AL)
2416 def CWDE : I<0x98, RawFrm, (ops),
2417 "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX)
2419 def CWD : I<0x99, RawFrm, (ops),
2420 "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>, OpSize; // DX:AX = signext(AX)
2421 def CDQ : I<0x99, RawFrm, (ops),
2422 "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
2425 //===----------------------------------------------------------------------===//
2426 // Alias Instructions
2427 //===----------------------------------------------------------------------===//
2429 // Alias instructions that map movr0 to xor.
2430 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2431 def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst),
2432 "xor{b} $dst, $dst",
2433 [(set GR8:$dst, 0)]>;
2434 def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst),
2435 "xor{w} $dst, $dst",
2436 [(set GR16:$dst, 0)]>, OpSize;
2437 def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst),
2438 "xor{l} $dst, $dst",
2439 [(set GR32:$dst, 0)]>;
2441 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2442 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2443 def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src),
2444 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2445 def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src),
2446 "mov{l} {$src, $dst|$dst, $src}", []>;
2448 def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src),
2449 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2450 def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src),
2451 "mov{l} {$src, $dst|$dst, $src}", []>;
2452 def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src),
2453 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2454 def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src),
2455 "mov{l} {$src, $dst|$dst, $src}", []>;
2456 def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src),
2457 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2458 def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src),
2459 "mov{l} {$src, $dst|$dst, $src}", []>;
2461 //===----------------------------------------------------------------------===//
2462 // Thread Local Storage Instructions
2465 def TLS_addr : I<0, Pseudo, (ops GR32:$dst, i32imm:$sym),
2466 "leal ${sym:mem}(,%ebx,1), $dst",
2467 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>,
2470 let AddedComplexity = 10 in
2471 def TLS_gs_rr : I<0, Pseudo, (ops GR32:$dst, GR32:$src),
2472 "movl %gs:($src), $dst",
2473 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2475 let AddedComplexity = 15 in
2476 def TLS_gs_ri : I<0, Pseudo, (ops GR32:$dst, i32imm:$src),
2477 "movl %gs:${src:mem}, $dst",
2479 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2481 def TLS_tp : I<0, Pseudo, (ops GR32:$dst),
2483 [(set GR32:$dst, X86TLStp)]>;
2485 //===----------------------------------------------------------------------===//
2486 // DWARF Pseudo Instructions
2489 def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
2490 "; .loc $file, $line, $col",
2491 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2494 //===----------------------------------------------------------------------===//
2495 // Non-Instruction Patterns
2496 //===----------------------------------------------------------------------===//
2498 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2499 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2500 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2501 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2502 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2503 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2505 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2506 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2507 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2508 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2509 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2510 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2511 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2512 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2514 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2515 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2516 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2517 (MOV32mi addr:$dst, texternalsym:$src)>;
2520 def : Pat<(X86tailcall GR32:$dst),
2521 (CALL32r GR32:$dst)>;
2523 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2524 (CALLpcrel32 tglobaladdr:$dst)>;
2525 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2526 (CALLpcrel32 texternalsym:$dst)>;
2528 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2529 (CALLpcrel32 tglobaladdr:$dst)>;
2530 def : Pat<(X86call (i32 texternalsym:$dst)),
2531 (CALLpcrel32 texternalsym:$dst)>;
2533 // X86 specific add which produces a flag.
2534 def : Pat<(addc GR32:$src1, GR32:$src2),
2535 (ADD32rr GR32:$src1, GR32:$src2)>;
2536 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2537 (ADD32rm GR32:$src1, addr:$src2)>;
2538 def : Pat<(addc GR32:$src1, imm:$src2),
2539 (ADD32ri GR32:$src1, imm:$src2)>;
2540 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2541 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2543 def : Pat<(subc GR32:$src1, GR32:$src2),
2544 (SUB32rr GR32:$src1, GR32:$src2)>;
2545 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2546 (SUB32rm GR32:$src1, addr:$src2)>;
2547 def : Pat<(subc GR32:$src1, imm:$src2),
2548 (SUB32ri GR32:$src1, imm:$src2)>;
2549 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2550 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2552 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
2553 (MOV8mi addr:$dst, imm:$src)>;
2554 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
2555 (MOV8mr addr:$dst, GR8:$src)>;
2559 // TEST R,R is smaller than CMP R,0
2560 def : Pat<(X86cmp GR8:$src1, 0),
2561 (TEST8rr GR8:$src1, GR8:$src1)>;
2562 def : Pat<(X86cmp GR16:$src1, 0),
2563 (TEST16rr GR16:$src1, GR16:$src1)>;
2564 def : Pat<(X86cmp GR32:$src1, 0),
2565 (TEST32rr GR32:$src1, GR32:$src1)>;
2567 // {s|z}extload bool -> {s|z}extload byte
2568 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
2569 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
2570 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2571 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2572 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2574 // extload bool -> extload byte
2575 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2576 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2577 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2578 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2579 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2580 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2583 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2584 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2585 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2586 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2587 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2588 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2590 //===----------------------------------------------------------------------===//
2592 //===----------------------------------------------------------------------===//
2594 // (shl x, 1) ==> (add x, x)
2595 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2596 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2597 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2599 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2600 def : Pat<(or (srl GR32:$src1, CL:$amt),
2601 (shl GR32:$src2, (sub 32, CL:$amt))),
2602 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2604 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2605 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2606 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2608 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2609 def : Pat<(or (shl GR32:$src1, CL:$amt),
2610 (srl GR32:$src2, (sub 32, CL:$amt))),
2611 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2613 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2614 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2615 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2617 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2618 def : Pat<(or (srl GR16:$src1, CL:$amt),
2619 (shl GR16:$src2, (sub 16, CL:$amt))),
2620 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2622 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2623 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2624 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2626 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2627 def : Pat<(or (shl GR16:$src1, CL:$amt),
2628 (srl GR16:$src2, (sub 16, CL:$amt))),
2629 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2631 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2632 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2633 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2636 //===----------------------------------------------------------------------===//
2637 // Floating Point Stack Support
2638 //===----------------------------------------------------------------------===//
2640 include "X86InstrFPStack.td"
2642 //===----------------------------------------------------------------------===//
2643 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2644 //===----------------------------------------------------------------------===//
2646 include "X86InstrMMX.td"
2648 //===----------------------------------------------------------------------===//
2649 // XMM Floating point support (requires SSE / SSE2)
2650 //===----------------------------------------------------------------------===//
2652 include "X86InstrSSE.td"
2654 //===----------------------------------------------------------------------===//
2656 //===----------------------------------------------------------------------===//
2658 include "X86InstrX86-64.td"