1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
79 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
83 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
84 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
86 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
88 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
90 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
92 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
94 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
98 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
99 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
100 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
101 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
103 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
104 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
106 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
107 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
109 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
110 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
112 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
113 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
115 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
116 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
118 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
119 [SDNPHasChain, SDNPMayStore,
120 SDNPMayLoad, SDNPMemOperand]>;
121 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
122 [SDNPHasChain, SDNPMayStore,
123 SDNPMayLoad, SDNPMemOperand]>;
124 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
125 [SDNPHasChain, SDNPMayStore,
126 SDNPMayLoad, SDNPMemOperand]>;
127 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
128 [SDNPHasChain, SDNPMayStore,
129 SDNPMayLoad, SDNPMemOperand]>;
130 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
131 [SDNPHasChain, SDNPMayStore,
132 SDNPMayLoad, SDNPMemOperand]>;
133 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
134 [SDNPHasChain, SDNPMayStore,
135 SDNPMayLoad, SDNPMemOperand]>;
136 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
137 [SDNPHasChain, SDNPMayStore,
138 SDNPMayLoad, SDNPMemOperand]>;
139 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
140 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def X86vastart_save_xmm_regs :
143 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
144 SDT_X86VASTART_SAVE_XMM_REGS,
145 [SDNPHasChain, SDNPVariadic]>;
147 def X86callseq_start :
148 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
149 [SDNPHasChain, SDNPOutFlag]>;
151 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
152 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
155 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
158 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
159 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
160 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
161 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
164 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
165 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
167 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
168 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
170 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
171 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
172 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
173 SDT_X86SegmentBaseAddress, []>;
175 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
178 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
179 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
181 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
183 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
184 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
186 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
189 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
190 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
191 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
193 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
195 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
198 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
200 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
201 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
203 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
206 //===----------------------------------------------------------------------===//
207 // X86 Operand Definitions.
210 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
211 // the index operand of an address, to conform to x86 encoding restrictions.
212 def ptr_rc_nosp : PointerLikeRegClass<1>;
214 // *mem - Operand definitions for the funky X86 addressing mode operands.
216 def X86MemAsmOperand : AsmOperandClass {
218 let SuperClasses = [];
220 def X86AbsMemAsmOperand : AsmOperandClass {
222 let SuperClasses = [X86MemAsmOperand];
224 class X86MemOperand<string printMethod> : Operand<iPTR> {
225 let PrintMethod = printMethod;
226 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
227 let ParserMatchClass = X86MemAsmOperand;
230 def opaque32mem : X86MemOperand<"printopaquemem">;
231 def opaque48mem : X86MemOperand<"printopaquemem">;
232 def opaque80mem : X86MemOperand<"printopaquemem">;
233 def opaque512mem : X86MemOperand<"printopaquemem">;
235 def i8mem : X86MemOperand<"printi8mem">;
236 def i16mem : X86MemOperand<"printi16mem">;
237 def i32mem : X86MemOperand<"printi32mem">;
238 def i64mem : X86MemOperand<"printi64mem">;
239 def i128mem : X86MemOperand<"printi128mem">;
240 def i256mem : X86MemOperand<"printi256mem">;
241 def f32mem : X86MemOperand<"printf32mem">;
242 def f64mem : X86MemOperand<"printf64mem">;
243 def f80mem : X86MemOperand<"printf80mem">;
244 def f128mem : X86MemOperand<"printf128mem">;
245 def f256mem : X86MemOperand<"printf256mem">;
247 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
248 // plain GR64, so that it doesn't potentially require a REX prefix.
249 def i8mem_NOREX : Operand<i64> {
250 let PrintMethod = "printi8mem";
251 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
252 let ParserMatchClass = X86MemAsmOperand;
255 // Special i32mem for addresses of load folding tail calls. These are not
256 // allowed to use callee-saved registers since they must be scheduled
257 // after callee-saved register are popped.
258 def i32mem_TC : Operand<i32> {
259 let PrintMethod = "printi32mem";
260 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
261 let ParserMatchClass = X86MemAsmOperand;
265 let ParserMatchClass = X86AbsMemAsmOperand,
266 PrintMethod = "print_pcrel_imm" in {
267 def i32imm_pcrel : Operand<i32>;
268 def i16imm_pcrel : Operand<i16>;
270 def offset8 : Operand<i64>;
271 def offset16 : Operand<i64>;
272 def offset32 : Operand<i64>;
273 def offset64 : Operand<i64>;
275 // Branch targets have OtherVT type and print as pc-relative values.
276 def brtarget : Operand<OtherVT>;
277 def brtarget8 : Operand<OtherVT>;
281 def SSECC : Operand<i8> {
282 let PrintMethod = "printSSECC";
285 class ImmSExtAsmOperandClass : AsmOperandClass {
286 let SuperClasses = [ImmAsmOperand];
287 let RenderMethod = "addImmOperands";
290 // Sign-extended immediate classes. We don't need to define the full lattice
291 // here because there is no instruction with an ambiguity between ImmSExti64i32
294 // The strange ranges come from the fact that the assembler always works with
295 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
296 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
299 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
300 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
301 let Name = "ImmSExti64i32";
304 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
305 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
306 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
307 let Name = "ImmSExti16i8";
308 let SuperClasses = [ImmSExti64i32AsmOperand];
311 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
312 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
313 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
314 let Name = "ImmSExti32i8";
318 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
319 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
320 let Name = "ImmSExti64i8";
321 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
322 ImmSExti64i32AsmOperand];
325 // A couple of more descriptive operand definitions.
326 // 16-bits but only 8 bits are significant.
327 def i16i8imm : Operand<i16> {
328 let ParserMatchClass = ImmSExti16i8AsmOperand;
330 // 32-bits but only 8 bits are significant.
331 def i32i8imm : Operand<i32> {
332 let ParserMatchClass = ImmSExti32i8AsmOperand;
335 //===----------------------------------------------------------------------===//
336 // X86 Complex Pattern Definitions.
339 // Define X86 specific addressing mode.
340 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
341 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
342 [add, sub, mul, X86mul_imm, shl, or, frameindex],
344 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
345 [tglobaltlsaddr], []>;
347 //===----------------------------------------------------------------------===//
348 // X86 Instruction Predicate Definitions.
349 def HasCMov : Predicate<"Subtarget->hasCMov()">;
350 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
352 // FIXME: temporary hack to let codegen assert or generate poor code in case
353 // no AVX version of the desired intructions is present, this is better for
354 // incremental dev (without fallbacks it's easier to spot what's missing)
355 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
356 def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
357 def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
358 def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
359 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
360 def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
361 def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
362 def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
364 def HasAVX : Predicate<"Subtarget->hasAVX()">;
365 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
366 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
367 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
368 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
369 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
370 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
371 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
372 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
373 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
374 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
375 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
376 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
377 "TM.getCodeModel() != CodeModel::Kernel">;
378 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
379 "TM.getCodeModel() == CodeModel::Kernel">;
380 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
381 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
382 def OptForSize : Predicate<"OptForSize">;
383 def OptForSpeed : Predicate<"!OptForSize">;
384 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
385 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
386 def HasAES : Predicate<"Subtarget->hasAES()">;
388 //===----------------------------------------------------------------------===//
389 // X86 Instruction Format Definitions.
392 include "X86InstrFormats.td"
394 //===----------------------------------------------------------------------===//
395 // Pattern fragments...
398 // X86 specific condition code. These correspond to CondCode in
399 // X86InstrInfo.h. They must be kept in synch.
400 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
401 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
402 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
403 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
404 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
405 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
406 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
407 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
408 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
409 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
410 def X86_COND_NO : PatLeaf<(i8 10)>;
411 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
412 def X86_COND_NS : PatLeaf<(i8 12)>;
413 def X86_COND_O : PatLeaf<(i8 13)>;
414 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
415 def X86_COND_S : PatLeaf<(i8 15)>;
417 def immSext8 : PatLeaf<(imm), [{
418 return N->getSExtValue() == (int8_t)N->getSExtValue();
421 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
422 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
424 /// Load patterns: these constraint the match to the right address space.
425 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
426 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 if (PT->getAddressSpace() > 255)
433 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
434 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
435 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
436 return PT->getAddressSpace() == 256;
440 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
441 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
442 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
443 return PT->getAddressSpace() == 257;
448 // Helper fragments for loads.
449 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
450 // known to be 32-bit aligned or better. Ditto for i8 to i16.
451 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
452 LoadSDNode *LD = cast<LoadSDNode>(N);
453 if (const Value *Src = LD->getSrcValue())
454 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
455 if (PT->getAddressSpace() > 255)
457 ISD::LoadExtType ExtType = LD->getExtensionType();
458 if (ExtType == ISD::NON_EXTLOAD)
460 if (ExtType == ISD::EXTLOAD)
461 return LD->getAlignment() >= 2 && !LD->isVolatile();
465 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
466 LoadSDNode *LD = cast<LoadSDNode>(N);
467 if (const Value *Src = LD->getSrcValue())
468 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
469 if (PT->getAddressSpace() > 255)
471 ISD::LoadExtType ExtType = LD->getExtensionType();
472 if (ExtType == ISD::EXTLOAD)
473 return LD->getAlignment() >= 2 && !LD->isVolatile();
477 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
478 LoadSDNode *LD = cast<LoadSDNode>(N);
479 if (const Value *Src = LD->getSrcValue())
480 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
481 if (PT->getAddressSpace() > 255)
483 ISD::LoadExtType ExtType = LD->getExtensionType();
484 if (ExtType == ISD::NON_EXTLOAD)
486 if (ExtType == ISD::EXTLOAD)
487 return LD->getAlignment() >= 4 && !LD->isVolatile();
491 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
492 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
493 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
494 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
495 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
497 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
498 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
499 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
501 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
502 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
503 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
504 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
505 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
506 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
508 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
509 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
510 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
511 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
512 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
513 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
516 // An 'and' node with a single use.
517 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
518 return N->hasOneUse();
520 // An 'srl' node with a single use.
521 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
522 return N->hasOneUse();
524 // An 'trunc' node with a single use.
525 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
526 return N->hasOneUse();
529 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
530 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
531 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
532 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
534 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
535 APInt Mask = APInt::getAllOnesValue(BitWidth);
536 APInt KnownZero0, KnownOne0;
537 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
538 APInt KnownZero1, KnownOne1;
539 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
540 return (~KnownZero0 & ~KnownZero1) == 0;
543 //===----------------------------------------------------------------------===//
544 // Instruction list...
547 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
548 // a stack adjustment and the codegen must know that they may modify the stack
549 // pointer before prolog-epilog rewriting occurs.
550 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
551 // sub / add which can clobber EFLAGS.
552 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
553 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
555 [(X86callseq_start timm:$amt)]>,
556 Requires<[In32BitMode]>;
557 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
559 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
560 Requires<[In32BitMode]>;
563 // x86-64 va_start lowering magic.
564 let usesCustomInserter = 1 in {
565 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
568 i64imm:$regsavefi, i64imm:$offset,
570 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
571 [(X86vastart_save_xmm_regs GR8:$al,
575 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
576 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
577 // one go. Touching the stack at 4K increments is necessary to ensure that the
578 // guard pages used by the OS virtual memory manager are allocated in correct
580 // The main point of having separate instruction are extra unmodelled effects
581 // (compared to ordinary calls) like stack pointer change.
583 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
584 "# dynamic stack allocation",
589 let neverHasSideEffects = 1 in {
590 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
591 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
592 "nop{w}\t$zero", []>, TB, OpSize;
593 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
594 "nop{l}\t$zero", []>, TB;
598 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
599 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", []>;
600 // FIXME: need to make sure that "int $3" matches int3
601 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
602 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
603 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
605 // PIC base construction. This expands to code that looks like this:
608 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
609 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
612 //===----------------------------------------------------------------------===//
613 // Control Flow Instructions.
616 // Return instructions.
617 let isTerminator = 1, isReturn = 1, isBarrier = 1,
618 hasCtrlDep = 1, FPForm = SpecialFP in {
619 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
622 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
624 [(X86retflag timm:$amt)]>;
625 def LRET : I <0xCB, RawFrm, (outs), (ins),
627 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
631 // Unconditional branches.
632 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
633 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
634 "jmp\t$dst", [(br bb:$dst)]>;
635 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
639 // Conditional Branches.
640 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
641 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
642 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
643 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
644 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
648 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
649 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
650 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
651 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
652 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
653 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
654 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
655 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
656 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
657 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
658 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
659 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
660 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
661 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
662 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
663 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
665 // FIXME: What about the CX/RCX versions of this instruction?
666 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
667 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
672 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
673 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
674 [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
675 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
676 [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
678 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
679 (ins i16imm:$seg, i16imm:$off),
680 "ljmp{w}\t$seg, $off", []>, OpSize;
681 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
682 (ins i16imm:$seg, i32imm:$off),
683 "ljmp{l}\t$seg, $off", []>;
685 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
686 "ljmp{w}\t{*}$dst", []>, OpSize;
687 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
688 "ljmp{l}\t{*}$dst", []>;
694 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
695 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
696 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
698 //===----------------------------------------------------------------------===//
699 // Call Instructions...
702 // All calls clobber the non-callee saved registers. ESP is marked as
703 // a use to prevent stack-pointer assignments that appear immediately
704 // before calls from potentially appearing dead. Uses for argument
705 // registers are added manually.
706 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
707 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
708 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
709 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
711 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
712 (outs), (ins i32imm_pcrel:$dst,variable_ops),
714 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
715 "call\t{*}$dst", [(X86call GR32:$dst)]>;
716 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
717 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
719 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
720 (ins i16imm:$seg, i16imm:$off),
721 "lcall{w}\t$seg, $off", []>, OpSize;
722 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
723 (ins i16imm:$seg, i32imm:$off),
724 "lcall{l}\t$seg, $off", []>;
726 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
727 "lcall{w}\t{*}$dst", []>, OpSize;
728 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
729 "lcall{l}\t{*}$dst", []>;
731 // callw for 16 bit code for the assembler.
732 let isAsmParserOnly = 1 in
733 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
734 (outs), (ins i16imm_pcrel:$dst, variable_ops),
735 "callw\t$dst", []>, OpSize;
738 // Constructing a stack frame.
740 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
741 "enter\t$len, $lvl", []>;
745 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
747 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
748 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
749 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
750 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
752 def TCRETURNdi : I<0, Pseudo, (outs),
753 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
754 "#TC_RETURN $dst $offset", []>;
755 def TCRETURNri : I<0, Pseudo, (outs),
756 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
757 "#TC_RETURN $dst $offset", []>;
759 def TCRETURNmi : I<0, Pseudo, (outs),
760 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
761 "#TC_RETURN $dst $offset", []>;
763 // FIXME: The should be pseudo instructions that are lowered when going to
765 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
766 (ins i32imm_pcrel:$dst, variable_ops),
767 "jmp\t$dst # TAILCALL",
769 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
770 "", []>; // FIXME: Remove encoding when JIT is dead.
772 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
773 "jmp{l}\t{*}$dst # TAILCALL", []>;
776 //===----------------------------------------------------------------------===//
777 // Miscellaneous Instructions...
779 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
780 def LEAVE : I<0xC9, RawFrm,
781 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
783 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
784 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
786 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
787 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
788 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
789 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
791 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
792 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
794 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
796 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
798 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
799 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
801 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
803 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
804 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
807 let mayStore = 1 in {
808 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
810 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
811 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
813 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
815 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
816 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
820 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
821 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
822 "push{l}\t$imm", []>;
823 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
824 "push{w}\t$imm", []>, OpSize;
825 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
826 "push{l}\t$imm", []>;
829 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
830 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
831 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
832 Requires<[In32BitMode]>;
834 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
835 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
836 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
837 Requires<[In32BitMode]>;
840 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
841 mayLoad=1, neverHasSideEffects=1 in {
842 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
843 Requires<[In32BitMode]>;
845 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
846 mayStore=1, neverHasSideEffects=1 in {
847 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
848 Requires<[In32BitMode]>;
851 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
852 def BSWAP32r : I<0xC8, AddRegFrm,
853 (outs GR32:$dst), (ins GR32:$src),
855 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
858 // Bit scan instructions.
859 let Defs = [EFLAGS] in {
860 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
861 "bsf{w}\t{$src, $dst|$dst, $src}",
862 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
863 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
864 "bsf{w}\t{$src, $dst|$dst, $src}",
865 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
867 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
868 "bsf{l}\t{$src, $dst|$dst, $src}",
869 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
870 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
871 "bsf{l}\t{$src, $dst|$dst, $src}",
872 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
874 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
875 "bsr{w}\t{$src, $dst|$dst, $src}",
876 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
877 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
878 "bsr{w}\t{$src, $dst|$dst, $src}",
879 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
881 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
882 "bsr{l}\t{$src, $dst|$dst, $src}",
883 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
884 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
885 "bsr{l}\t{$src, $dst|$dst, $src}",
886 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
889 let neverHasSideEffects = 1 in
890 def LEA16r : I<0x8D, MRMSrcMem,
891 (outs GR16:$dst), (ins i32mem:$src),
892 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
893 let isReMaterializable = 1 in
894 def LEA32r : I<0x8D, MRMSrcMem,
895 (outs GR32:$dst), (ins i32mem:$src),
896 "lea{l}\t{$src|$dst}, {$dst|$src}",
897 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
899 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
900 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
901 [(X86rep_movs i8)]>, REP;
902 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
903 [(X86rep_movs i16)]>, REP, OpSize;
904 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
905 [(X86rep_movs i32)]>, REP;
908 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
909 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
910 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
911 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
912 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
915 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
916 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
917 [(X86rep_stos i8)]>, REP;
918 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
919 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
920 [(X86rep_stos i16)]>, REP, OpSize;
921 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
922 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
923 [(X86rep_stos i32)]>, REP;
925 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
926 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
927 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
928 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
929 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
930 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
931 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
933 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
934 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
935 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
937 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
938 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
939 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
941 let Defs = [RAX, RDX] in
942 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
945 let Defs = [RAX, RCX, RDX] in
946 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
948 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
949 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
952 def SYSCALL : I<0x05, RawFrm,
953 (outs), (ins), "syscall", []>, TB;
954 def SYSRET : I<0x07, RawFrm,
955 (outs), (ins), "sysret", []>, TB;
956 def SYSENTER : I<0x34, RawFrm,
957 (outs), (ins), "sysenter", []>, TB;
958 def SYSEXIT : I<0x35, RawFrm,
959 (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
961 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
964 //===----------------------------------------------------------------------===//
965 // Input/Output Instructions...
967 let Defs = [AL], Uses = [DX] in
968 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
969 "in{b}\t{%dx, %al|%AL, %DX}", []>;
970 let Defs = [AX], Uses = [DX] in
971 def IN16rr : I<0xED, RawFrm, (outs), (ins),
972 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
973 let Defs = [EAX], Uses = [DX] in
974 def IN32rr : I<0xED, RawFrm, (outs), (ins),
975 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
978 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
979 "in{b}\t{$port, %al|%AL, $port}", []>;
981 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
982 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
984 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
985 "in{l}\t{$port, %eax|%EAX, $port}", []>;
987 let Uses = [DX, AL] in
988 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
989 "out{b}\t{%al, %dx|%DX, %AL}", []>;
990 let Uses = [DX, AX] in
991 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
992 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
993 let Uses = [DX, EAX] in
994 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
995 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
998 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
999 "out{b}\t{%al, $port|$port, %AL}", []>;
1001 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
1002 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
1004 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
1005 "out{l}\t{%eax, $port|$port, %EAX}", []>;
1007 def IN8 : I<0x6C, RawFrm, (outs), (ins),
1009 def IN16 : I<0x6D, RawFrm, (outs), (ins),
1010 "ins{w}", []>, OpSize;
1011 def IN32 : I<0x6D, RawFrm, (outs), (ins),
1014 //===----------------------------------------------------------------------===//
1015 // Move Instructions...
1017 let neverHasSideEffects = 1 in {
1018 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1019 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1020 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1021 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1022 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1023 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1025 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1026 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1027 "mov{b}\t{$src, $dst|$dst, $src}",
1028 [(set GR8:$dst, imm:$src)]>;
1029 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1030 "mov{w}\t{$src, $dst|$dst, $src}",
1031 [(set GR16:$dst, imm:$src)]>, OpSize;
1032 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1033 "mov{l}\t{$src, $dst|$dst, $src}",
1034 [(set GR32:$dst, imm:$src)]>;
1037 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1038 "mov{b}\t{$src, $dst|$dst, $src}",
1039 [(store (i8 imm:$src), addr:$dst)]>;
1040 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1041 "mov{w}\t{$src, $dst|$dst, $src}",
1042 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1043 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1044 "mov{l}\t{$src, $dst|$dst, $src}",
1045 [(store (i32 imm:$src), addr:$dst)]>;
1047 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1048 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1049 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1050 "mov{b}\t{$src, %al|%al, $src}", []>,
1051 Requires<[In32BitMode]>;
1052 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1053 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
1054 Requires<[In32BitMode]>;
1055 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1056 "mov{l}\t{$src, %eax|%eax, $src}", []>,
1057 Requires<[In32BitMode]>;
1058 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1059 "mov{b}\t{%al, $dst|$dst, %al}", []>,
1060 Requires<[In32BitMode]>;
1061 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1062 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
1063 Requires<[In32BitMode]>;
1064 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1065 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
1066 Requires<[In32BitMode]>;
1068 // Moves to and from segment registers
1069 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1070 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1071 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
1072 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1073 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1074 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1075 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
1076 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1077 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1078 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1079 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
1080 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1081 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1082 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1083 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
1084 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1086 let isCodeGenOnly = 1 in {
1087 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1088 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1089 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1090 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1091 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1092 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1095 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1096 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1097 "mov{b}\t{$src, $dst|$dst, $src}",
1098 [(set GR8:$dst, (loadi8 addr:$src))]>;
1099 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1100 "mov{w}\t{$src, $dst|$dst, $src}",
1101 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1102 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1103 "mov{l}\t{$src, $dst|$dst, $src}",
1104 [(set GR32:$dst, (loadi32 addr:$src))]>;
1107 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1108 "mov{b}\t{$src, $dst|$dst, $src}",
1109 [(store GR8:$src, addr:$dst)]>;
1110 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1111 "mov{w}\t{$src, $dst|$dst, $src}",
1112 [(store GR16:$src, addr:$dst)]>, OpSize;
1113 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1114 "mov{l}\t{$src, $dst|$dst, $src}",
1115 [(store GR32:$src, addr:$dst)]>;
1117 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1118 let isCodeGenOnly = 1 in {
1119 let neverHasSideEffects = 1 in
1120 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1121 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1124 canFoldAsLoad = 1, isReMaterializable = 1 in
1125 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1126 "mov{l}\t{$src, $dst|$dst, $src}",
1130 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1131 "mov{l}\t{$src, $dst|$dst, $src}",
1135 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1136 // that they can be used for copying and storing h registers, which can't be
1137 // encoded when a REX prefix is present.
1138 let isCodeGenOnly = 1 in {
1139 let neverHasSideEffects = 1 in
1140 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1141 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1142 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1144 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1145 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1146 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1148 canFoldAsLoad = 1, isReMaterializable = 1 in
1149 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1150 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1151 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1154 // Moves to and from debug registers
1155 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1156 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1157 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1158 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1160 // Moves to and from control registers
1161 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1162 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1163 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1164 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1166 //===----------------------------------------------------------------------===//
1167 // Fixed-Register Multiplication and Division Instructions...
1170 // Extra precision multiplication
1172 // AL is really implied by AX, by the registers in Defs must match the
1173 // SDNode results (i8, i32).
1174 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1175 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1176 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1177 // This probably ought to be moved to a def : Pat<> if the
1178 // syntax can be accepted.
1179 [(set AL, (mul AL, GR8:$src)),
1180 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1182 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1183 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1185 []>, OpSize; // AX,DX = AX*GR16
1187 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1188 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1190 []>; // EAX,EDX = EAX*GR32
1192 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1193 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1195 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1196 // This probably ought to be moved to a def : Pat<> if the
1197 // syntax can be accepted.
1198 [(set AL, (mul AL, (loadi8 addr:$src))),
1199 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1201 let mayLoad = 1, neverHasSideEffects = 1 in {
1202 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1203 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1205 []>, OpSize; // AX,DX = AX*[mem16]
1207 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1208 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1210 []>; // EAX,EDX = EAX*[mem32]
1213 let neverHasSideEffects = 1 in {
1214 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1215 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1217 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1218 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1219 OpSize; // AX,DX = AX*GR16
1220 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1221 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1222 // EAX,EDX = EAX*GR32
1223 let mayLoad = 1 in {
1224 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1225 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1226 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1227 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1228 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1229 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1230 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1231 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1232 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1234 } // neverHasSideEffects
1236 // unsigned division/remainder
1237 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1238 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1239 "div{b}\t$src", []>;
1240 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1241 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1242 "div{w}\t$src", []>, OpSize;
1243 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1244 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1245 "div{l}\t$src", []>;
1246 let mayLoad = 1 in {
1247 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1248 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1249 "div{b}\t$src", []>;
1250 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1251 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1252 "div{w}\t$src", []>, OpSize;
1253 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1254 // EDX:EAX/[mem32] = EAX,EDX
1255 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1256 "div{l}\t$src", []>;
1259 // Signed division/remainder.
1260 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1261 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1262 "idiv{b}\t$src", []>;
1263 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1264 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1265 "idiv{w}\t$src", []>, OpSize;
1266 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1267 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1268 "idiv{l}\t$src", []>;
1269 let mayLoad = 1, mayLoad = 1 in {
1270 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1271 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1272 "idiv{b}\t$src", []>;
1273 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1274 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1275 "idiv{w}\t$src", []>, OpSize;
1276 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1277 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1278 // EDX:EAX/[mem32] = EAX,EDX
1279 "idiv{l}\t$src", []>;
1282 //===----------------------------------------------------------------------===//
1283 // Two address Instructions.
1285 let Constraints = "$src1 = $dst" in {
1287 // Conditional moves
1288 let Uses = [EFLAGS] in {
1290 let Predicates = [HasCMov] in {
1291 let isCommutable = 1 in {
1292 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1293 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1294 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1296 X86_COND_B, EFLAGS))]>,
1298 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1299 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1300 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1302 X86_COND_B, EFLAGS))]>,
1304 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1305 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1306 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1308 X86_COND_AE, EFLAGS))]>,
1310 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1311 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1312 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1314 X86_COND_AE, EFLAGS))]>,
1316 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1317 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1318 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1320 X86_COND_E, EFLAGS))]>,
1322 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1323 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1324 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1326 X86_COND_E, EFLAGS))]>,
1328 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1329 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1330 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1332 X86_COND_NE, EFLAGS))]>,
1334 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1335 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1336 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1338 X86_COND_NE, EFLAGS))]>,
1340 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1341 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1342 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1344 X86_COND_BE, EFLAGS))]>,
1346 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1347 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1348 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1350 X86_COND_BE, EFLAGS))]>,
1352 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1353 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1354 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1356 X86_COND_A, EFLAGS))]>,
1358 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1359 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1360 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1362 X86_COND_A, EFLAGS))]>,
1364 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1365 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1366 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1368 X86_COND_L, EFLAGS))]>,
1370 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1371 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1372 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1374 X86_COND_L, EFLAGS))]>,
1376 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1377 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1378 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1380 X86_COND_GE, EFLAGS))]>,
1382 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1383 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1384 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1386 X86_COND_GE, EFLAGS))]>,
1388 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1389 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1390 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1392 X86_COND_LE, EFLAGS))]>,
1394 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1395 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1396 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1398 X86_COND_LE, EFLAGS))]>,
1400 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1401 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1402 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1404 X86_COND_G, EFLAGS))]>,
1406 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1407 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1408 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1410 X86_COND_G, EFLAGS))]>,
1412 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1413 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1414 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1416 X86_COND_S, EFLAGS))]>,
1418 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1419 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1420 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1422 X86_COND_S, EFLAGS))]>,
1424 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1425 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1426 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1428 X86_COND_NS, EFLAGS))]>,
1430 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1431 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1432 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1434 X86_COND_NS, EFLAGS))]>,
1436 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1437 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1438 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1439 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1440 X86_COND_P, EFLAGS))]>,
1442 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1443 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1444 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1446 X86_COND_P, EFLAGS))]>,
1448 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1449 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1450 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1452 X86_COND_NP, EFLAGS))]>,
1454 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1455 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1456 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1458 X86_COND_NP, EFLAGS))]>,
1460 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1461 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1462 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1464 X86_COND_O, EFLAGS))]>,
1466 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1467 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1468 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1470 X86_COND_O, EFLAGS))]>,
1472 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1473 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1474 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1476 X86_COND_NO, EFLAGS))]>,
1478 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1479 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1480 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1481 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1482 X86_COND_NO, EFLAGS))]>,
1484 } // isCommutable = 1
1486 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1487 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1488 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1490 X86_COND_B, EFLAGS))]>,
1492 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1493 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1494 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1496 X86_COND_B, EFLAGS))]>,
1498 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1499 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1500 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1501 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1502 X86_COND_AE, EFLAGS))]>,
1504 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1505 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1506 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1508 X86_COND_AE, EFLAGS))]>,
1510 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1511 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1512 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1514 X86_COND_E, EFLAGS))]>,
1516 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1517 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1518 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1520 X86_COND_E, EFLAGS))]>,
1522 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1523 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1524 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1526 X86_COND_NE, EFLAGS))]>,
1528 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1529 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1530 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1532 X86_COND_NE, EFLAGS))]>,
1534 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1535 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1536 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1538 X86_COND_BE, EFLAGS))]>,
1540 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1541 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1542 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1544 X86_COND_BE, EFLAGS))]>,
1546 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1547 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1548 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1550 X86_COND_A, EFLAGS))]>,
1552 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1553 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1554 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1556 X86_COND_A, EFLAGS))]>,
1558 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1559 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1560 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1562 X86_COND_L, EFLAGS))]>,
1564 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1565 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1566 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1568 X86_COND_L, EFLAGS))]>,
1570 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1571 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1572 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1574 X86_COND_GE, EFLAGS))]>,
1576 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1577 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1578 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1580 X86_COND_GE, EFLAGS))]>,
1582 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1583 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1584 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1586 X86_COND_LE, EFLAGS))]>,
1588 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1589 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1590 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1592 X86_COND_LE, EFLAGS))]>,
1594 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1595 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1596 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1598 X86_COND_G, EFLAGS))]>,
1600 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1601 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1602 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1604 X86_COND_G, EFLAGS))]>,
1606 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1607 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1608 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1609 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1610 X86_COND_S, EFLAGS))]>,
1612 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1613 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1614 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1615 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1616 X86_COND_S, EFLAGS))]>,
1618 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1619 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1620 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1621 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1622 X86_COND_NS, EFLAGS))]>,
1624 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1625 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1626 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1627 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1628 X86_COND_NS, EFLAGS))]>,
1630 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1631 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1632 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1633 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1634 X86_COND_P, EFLAGS))]>,
1636 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1637 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1638 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1639 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1640 X86_COND_P, EFLAGS))]>,
1642 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1643 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1644 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1645 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1646 X86_COND_NP, EFLAGS))]>,
1648 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1649 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1650 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1651 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1652 X86_COND_NP, EFLAGS))]>,
1654 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1655 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1656 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1657 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1658 X86_COND_O, EFLAGS))]>,
1660 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1661 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1662 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1663 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1664 X86_COND_O, EFLAGS))]>,
1666 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1667 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1668 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1669 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1670 X86_COND_NO, EFLAGS))]>,
1672 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1673 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1674 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1675 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1676 X86_COND_NO, EFLAGS))]>,
1678 } // Predicates = [HasCMov]
1680 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1681 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1682 // however that requires promoting the operands, and can induce additional
1683 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1684 // clobber EFLAGS, because if one of the operands is zero, the expansion
1685 // could involve an xor.
1686 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1687 def CMOV_GR8 : I<0, Pseudo,
1688 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1689 "#CMOV_GR8 PSEUDO!",
1690 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1691 imm:$cond, EFLAGS))]>;
1693 let Predicates = [NoCMov] in {
1694 def CMOV_GR32 : I<0, Pseudo,
1695 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1696 "#CMOV_GR32* PSEUDO!",
1698 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1699 def CMOV_GR16 : I<0, Pseudo,
1700 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1701 "#CMOV_GR16* PSEUDO!",
1703 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1704 def CMOV_RFP32 : I<0, Pseudo,
1706 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1707 "#CMOV_RFP32 PSEUDO!",
1709 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1711 def CMOV_RFP64 : I<0, Pseudo,
1713 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1714 "#CMOV_RFP64 PSEUDO!",
1716 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1718 def CMOV_RFP80 : I<0, Pseudo,
1720 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1721 "#CMOV_RFP80 PSEUDO!",
1723 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1725 } // Predicates = [NoCMov]
1726 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1727 } // Uses = [EFLAGS]
1730 // unary instructions
1731 let CodeSize = 2 in {
1732 let Defs = [EFLAGS] in {
1733 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1735 [(set GR8:$dst, (ineg GR8:$src1)),
1736 (implicit EFLAGS)]>;
1737 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1739 [(set GR16:$dst, (ineg GR16:$src1)),
1740 (implicit EFLAGS)]>, OpSize;
1741 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1743 [(set GR32:$dst, (ineg GR32:$src1)),
1744 (implicit EFLAGS)]>;
1746 let Constraints = "" in {
1747 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1749 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1750 (implicit EFLAGS)]>;
1751 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1753 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1754 (implicit EFLAGS)]>, OpSize;
1755 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1757 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1758 (implicit EFLAGS)]>;
1759 } // Constraints = ""
1760 } // Defs = [EFLAGS]
1762 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1763 let AddedComplexity = 15 in {
1764 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1766 [(set GR8:$dst, (not GR8:$src1))]>;
1767 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1769 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1770 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1772 [(set GR32:$dst, (not GR32:$src1))]>;
1774 let Constraints = "" in {
1775 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1777 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1778 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1780 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1781 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1783 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1784 } // Constraints = ""
1787 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1788 let Defs = [EFLAGS] in {
1790 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1792 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1794 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1795 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1797 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1798 OpSize, Requires<[In32BitMode]>;
1799 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1801 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1802 Requires<[In32BitMode]>;
1804 let Constraints = "", CodeSize = 2 in {
1805 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1806 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1807 (implicit EFLAGS)]>;
1808 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1809 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1810 (implicit EFLAGS)]>,
1811 OpSize, Requires<[In32BitMode]>;
1812 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1813 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1814 (implicit EFLAGS)]>,
1815 Requires<[In32BitMode]>;
1816 } // Constraints = "", CodeSize = 2
1819 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1821 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1822 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1823 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1825 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1826 OpSize, Requires<[In32BitMode]>;
1827 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1829 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1830 Requires<[In32BitMode]>;
1833 let Constraints = "", CodeSize = 2 in {
1834 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1835 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1836 (implicit EFLAGS)]>;
1837 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1838 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1839 (implicit EFLAGS)]>,
1840 OpSize, Requires<[In32BitMode]>;
1841 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1842 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1843 (implicit EFLAGS)]>,
1844 Requires<[In32BitMode]>;
1845 } // Constraints = "", CodeSize = 2
1846 } // Defs = [EFLAGS]
1848 // Logical operators...
1849 let Defs = [EFLAGS] in {
1850 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1851 def AND8rr : I<0x20, MRMDestReg,
1852 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1853 "and{b}\t{$src2, $dst|$dst, $src2}",
1854 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1855 def AND16rr : I<0x21, MRMDestReg,
1856 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1857 "and{w}\t{$src2, $dst|$dst, $src2}",
1858 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1859 GR16:$src2))]>, OpSize;
1860 def AND32rr : I<0x21, MRMDestReg,
1861 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1862 "and{l}\t{$src2, $dst|$dst, $src2}",
1863 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1867 // AND instructions with the destination register in REG and the source register
1868 // in R/M. Included for the disassembler.
1869 let isCodeGenOnly = 1 in {
1870 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1871 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1872 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1873 (ins GR16:$src1, GR16:$src2),
1874 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1875 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1876 (ins GR32:$src1, GR32:$src2),
1877 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1880 def AND8rm : I<0x22, MRMSrcMem,
1881 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1882 "and{b}\t{$src2, $dst|$dst, $src2}",
1883 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1884 (loadi8 addr:$src2)))]>;
1885 def AND16rm : I<0x23, MRMSrcMem,
1886 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1887 "and{w}\t{$src2, $dst|$dst, $src2}",
1888 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1889 (loadi16 addr:$src2)))]>,
1891 def AND32rm : I<0x23, MRMSrcMem,
1892 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1893 "and{l}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1895 (loadi32 addr:$src2)))]>;
1897 def AND8ri : Ii8<0x80, MRM4r,
1898 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1899 "and{b}\t{$src2, $dst|$dst, $src2}",
1900 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1902 def AND16ri : Ii16<0x81, MRM4r,
1903 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1904 "and{w}\t{$src2, $dst|$dst, $src2}",
1905 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1906 imm:$src2))]>, OpSize;
1907 def AND32ri : Ii32<0x81, MRM4r,
1908 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1909 "and{l}\t{$src2, $dst|$dst, $src2}",
1910 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1912 def AND16ri8 : Ii8<0x83, MRM4r,
1913 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1914 "and{w}\t{$src2, $dst|$dst, $src2}",
1915 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1916 i16immSExt8:$src2))]>,
1918 def AND32ri8 : Ii8<0x83, MRM4r,
1919 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1920 "and{l}\t{$src2, $dst|$dst, $src2}",
1921 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1922 i32immSExt8:$src2))]>;
1924 let Constraints = "" in {
1925 def AND8mr : I<0x20, MRMDestMem,
1926 (outs), (ins i8mem :$dst, GR8 :$src),
1927 "and{b}\t{$src, $dst|$dst, $src}",
1928 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1929 (implicit EFLAGS)]>;
1930 def AND16mr : I<0x21, MRMDestMem,
1931 (outs), (ins i16mem:$dst, GR16:$src),
1932 "and{w}\t{$src, $dst|$dst, $src}",
1933 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1934 (implicit EFLAGS)]>,
1936 def AND32mr : I<0x21, MRMDestMem,
1937 (outs), (ins i32mem:$dst, GR32:$src),
1938 "and{l}\t{$src, $dst|$dst, $src}",
1939 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1940 (implicit EFLAGS)]>;
1941 def AND8mi : Ii8<0x80, MRM4m,
1942 (outs), (ins i8mem :$dst, i8imm :$src),
1943 "and{b}\t{$src, $dst|$dst, $src}",
1944 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1945 (implicit EFLAGS)]>;
1946 def AND16mi : Ii16<0x81, MRM4m,
1947 (outs), (ins i16mem:$dst, i16imm:$src),
1948 "and{w}\t{$src, $dst|$dst, $src}",
1949 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1950 (implicit EFLAGS)]>,
1952 def AND32mi : Ii32<0x81, MRM4m,
1953 (outs), (ins i32mem:$dst, i32imm:$src),
1954 "and{l}\t{$src, $dst|$dst, $src}",
1955 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1956 (implicit EFLAGS)]>;
1957 def AND16mi8 : Ii8<0x83, MRM4m,
1958 (outs), (ins i16mem:$dst, i16i8imm :$src),
1959 "and{w}\t{$src, $dst|$dst, $src}",
1960 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1961 (implicit EFLAGS)]>,
1963 def AND32mi8 : Ii8<0x83, MRM4m,
1964 (outs), (ins i32mem:$dst, i32i8imm :$src),
1965 "and{l}\t{$src, $dst|$dst, $src}",
1966 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1967 (implicit EFLAGS)]>;
1969 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1970 "and{b}\t{$src, %al|%al, $src}", []>;
1971 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1972 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1973 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1974 "and{l}\t{$src, %eax|%eax, $src}", []>;
1976 } // Constraints = ""
1979 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1980 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1981 (ins GR8 :$src1, GR8 :$src2),
1982 "or{b}\t{$src2, $dst|$dst, $src2}",
1983 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1984 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1985 (ins GR16:$src1, GR16:$src2),
1986 "or{w}\t{$src2, $dst|$dst, $src2}",
1987 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1989 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1990 (ins GR32:$src1, GR32:$src2),
1991 "or{l}\t{$src2, $dst|$dst, $src2}",
1992 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1995 // OR instructions with the destination register in REG and the source register
1996 // in R/M. Included for the disassembler.
1997 let isCodeGenOnly = 1 in {
1998 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1999 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
2000 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
2001 (ins GR16:$src1, GR16:$src2),
2002 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2003 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
2004 (ins GR32:$src1, GR32:$src2),
2005 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
2008 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
2009 (ins GR8 :$src1, i8mem :$src2),
2010 "or{b}\t{$src2, $dst|$dst, $src2}",
2011 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
2012 (load addr:$src2)))]>;
2013 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
2014 (ins GR16:$src1, i16mem:$src2),
2015 "or{w}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2017 (load addr:$src2)))]>,
2019 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
2020 (ins GR32:$src1, i32mem:$src2),
2021 "or{l}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2023 (load addr:$src2)))]>;
2025 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
2026 (ins GR8 :$src1, i8imm:$src2),
2027 "or{b}\t{$src2, $dst|$dst, $src2}",
2028 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
2029 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
2030 (ins GR16:$src1, i16imm:$src2),
2031 "or{w}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2033 imm:$src2))]>, OpSize;
2034 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
2035 (ins GR32:$src1, i32imm:$src2),
2036 "or{l}\t{$src2, $dst|$dst, $src2}",
2037 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2040 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
2041 (ins GR16:$src1, i16i8imm:$src2),
2042 "or{w}\t{$src2, $dst|$dst, $src2}",
2043 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2044 i16immSExt8:$src2))]>, OpSize;
2045 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
2046 (ins GR32:$src1, i32i8imm:$src2),
2047 "or{l}\t{$src2, $dst|$dst, $src2}",
2048 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2049 i32immSExt8:$src2))]>;
2050 let Constraints = "" in {
2051 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2052 "or{b}\t{$src, $dst|$dst, $src}",
2053 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
2054 (implicit EFLAGS)]>;
2055 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2056 "or{w}\t{$src, $dst|$dst, $src}",
2057 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
2058 (implicit EFLAGS)]>, OpSize;
2059 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2060 "or{l}\t{$src, $dst|$dst, $src}",
2061 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
2062 (implicit EFLAGS)]>;
2063 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2064 "or{b}\t{$src, $dst|$dst, $src}",
2065 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
2066 (implicit EFLAGS)]>;
2067 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
2068 "or{w}\t{$src, $dst|$dst, $src}",
2069 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
2070 (implicit EFLAGS)]>,
2072 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
2073 "or{l}\t{$src, $dst|$dst, $src}",
2074 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
2075 (implicit EFLAGS)]>;
2076 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
2077 "or{w}\t{$src, $dst|$dst, $src}",
2078 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2079 (implicit EFLAGS)]>,
2081 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2082 "or{l}\t{$src, $dst|$dst, $src}",
2083 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2084 (implicit EFLAGS)]>;
2086 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2087 "or{b}\t{$src, %al|%al, $src}", []>;
2088 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2089 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2090 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2091 "or{l}\t{$src, %eax|%eax, $src}", []>;
2092 } // Constraints = ""
2095 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2096 def XOR8rr : I<0x30, MRMDestReg,
2097 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2098 "xor{b}\t{$src2, $dst|$dst, $src2}",
2099 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2101 def XOR16rr : I<0x31, MRMDestReg,
2102 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2103 "xor{w}\t{$src2, $dst|$dst, $src2}",
2104 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2105 GR16:$src2))]>, OpSize;
2106 def XOR32rr : I<0x31, MRMDestReg,
2107 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2108 "xor{l}\t{$src2, $dst|$dst, $src2}",
2109 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2111 } // isCommutable = 1
2113 // XOR instructions with the destination register in REG and the source register
2114 // in R/M. Included for the disassembler.
2115 let isCodeGenOnly = 1 in {
2116 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2117 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2118 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2119 (ins GR16:$src1, GR16:$src2),
2120 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2121 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2122 (ins GR32:$src1, GR32:$src2),
2123 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2126 def XOR8rm : I<0x32, MRMSrcMem,
2127 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2128 "xor{b}\t{$src2, $dst|$dst, $src2}",
2129 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2130 (load addr:$src2)))]>;
2131 def XOR16rm : I<0x33, MRMSrcMem,
2132 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2133 "xor{w}\t{$src2, $dst|$dst, $src2}",
2134 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2135 (load addr:$src2)))]>,
2137 def XOR32rm : I<0x33, MRMSrcMem,
2138 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2139 "xor{l}\t{$src2, $dst|$dst, $src2}",
2140 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2141 (load addr:$src2)))]>;
2143 def XOR8ri : Ii8<0x80, MRM6r,
2144 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2145 "xor{b}\t{$src2, $dst|$dst, $src2}",
2146 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2147 def XOR16ri : Ii16<0x81, MRM6r,
2148 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2149 "xor{w}\t{$src2, $dst|$dst, $src2}",
2150 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2151 imm:$src2))]>, OpSize;
2152 def XOR32ri : Ii32<0x81, MRM6r,
2153 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2154 "xor{l}\t{$src2, $dst|$dst, $src2}",
2155 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2157 def XOR16ri8 : Ii8<0x83, MRM6r,
2158 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2159 "xor{w}\t{$src2, $dst|$dst, $src2}",
2160 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2161 i16immSExt8:$src2))]>,
2163 def XOR32ri8 : Ii8<0x83, MRM6r,
2164 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2165 "xor{l}\t{$src2, $dst|$dst, $src2}",
2166 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2167 i32immSExt8:$src2))]>;
2169 let Constraints = "" in {
2170 def XOR8mr : I<0x30, MRMDestMem,
2171 (outs), (ins i8mem :$dst, GR8 :$src),
2172 "xor{b}\t{$src, $dst|$dst, $src}",
2173 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2174 (implicit EFLAGS)]>;
2175 def XOR16mr : I<0x31, MRMDestMem,
2176 (outs), (ins i16mem:$dst, GR16:$src),
2177 "xor{w}\t{$src, $dst|$dst, $src}",
2178 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2179 (implicit EFLAGS)]>,
2181 def XOR32mr : I<0x31, MRMDestMem,
2182 (outs), (ins i32mem:$dst, GR32:$src),
2183 "xor{l}\t{$src, $dst|$dst, $src}",
2184 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2185 (implicit EFLAGS)]>;
2186 def XOR8mi : Ii8<0x80, MRM6m,
2187 (outs), (ins i8mem :$dst, i8imm :$src),
2188 "xor{b}\t{$src, $dst|$dst, $src}",
2189 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2190 (implicit EFLAGS)]>;
2191 def XOR16mi : Ii16<0x81, MRM6m,
2192 (outs), (ins i16mem:$dst, i16imm:$src),
2193 "xor{w}\t{$src, $dst|$dst, $src}",
2194 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2195 (implicit EFLAGS)]>,
2197 def XOR32mi : Ii32<0x81, MRM6m,
2198 (outs), (ins i32mem:$dst, i32imm:$src),
2199 "xor{l}\t{$src, $dst|$dst, $src}",
2200 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2201 (implicit EFLAGS)]>;
2202 def XOR16mi8 : Ii8<0x83, MRM6m,
2203 (outs), (ins i16mem:$dst, i16i8imm :$src),
2204 "xor{w}\t{$src, $dst|$dst, $src}",
2205 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2206 (implicit EFLAGS)]>,
2208 def XOR32mi8 : Ii8<0x83, MRM6m,
2209 (outs), (ins i32mem:$dst, i32i8imm :$src),
2210 "xor{l}\t{$src, $dst|$dst, $src}",
2211 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2212 (implicit EFLAGS)]>;
2214 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2215 "xor{b}\t{$src, %al|%al, $src}", []>;
2216 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2217 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2218 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2219 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2220 } // Constraints = ""
2221 } // Defs = [EFLAGS]
2223 // Shift instructions
2224 let Defs = [EFLAGS] in {
2225 let Uses = [CL] in {
2226 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2227 "shl{b}\t{%cl, $dst|$dst, CL}",
2228 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
2229 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2230 "shl{w}\t{%cl, $dst|$dst, CL}",
2231 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
2232 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2233 "shl{l}\t{%cl, $dst|$dst, CL}",
2234 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
2237 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2238 "shl{b}\t{$src2, $dst|$dst, $src2}",
2239 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2241 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2242 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2243 "shl{w}\t{$src2, $dst|$dst, $src2}",
2244 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2245 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2246 "shl{l}\t{$src2, $dst|$dst, $src2}",
2247 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2249 // NOTE: We don't include patterns for shifts of a register by one, because
2250 // 'add reg,reg' is cheaper.
2252 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2253 "shl{b}\t$dst", []>;
2254 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2255 "shl{w}\t$dst", []>, OpSize;
2256 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2257 "shl{l}\t$dst", []>;
2259 } // isConvertibleToThreeAddress = 1
2261 let Constraints = "" in {
2262 let Uses = [CL] in {
2263 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2264 "shl{b}\t{%cl, $dst|$dst, CL}",
2265 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2266 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2267 "shl{w}\t{%cl, $dst|$dst, CL}",
2268 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2269 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2270 "shl{l}\t{%cl, $dst|$dst, CL}",
2271 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2273 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2274 "shl{b}\t{$src, $dst|$dst, $src}",
2275 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2276 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2277 "shl{w}\t{$src, $dst|$dst, $src}",
2278 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2280 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2281 "shl{l}\t{$src, $dst|$dst, $src}",
2282 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2285 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2287 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2288 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2290 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2292 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2294 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2295 } // Constraints = ""
2297 let Uses = [CL] in {
2298 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
2299 "shr{b}\t{%cl, $dst|$dst, CL}",
2300 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
2301 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2302 "shr{w}\t{%cl, $dst|$dst, CL}",
2303 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
2304 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2305 "shr{l}\t{%cl, $dst|$dst, CL}",
2306 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
2309 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2310 "shr{b}\t{$src2, $dst|$dst, $src2}",
2311 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2312 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2313 "shr{w}\t{$src2, $dst|$dst, $src2}",
2314 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2315 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2316 "shr{l}\t{$src2, $dst|$dst, $src2}",
2317 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2320 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2322 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2323 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2325 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2326 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2328 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2330 let Constraints = "" in {
2331 let Uses = [CL] in {
2332 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2333 "shr{b}\t{%cl, $dst|$dst, CL}",
2334 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2335 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2336 "shr{w}\t{%cl, $dst|$dst, CL}",
2337 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2339 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2340 "shr{l}\t{%cl, $dst|$dst, CL}",
2341 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2343 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2344 "shr{b}\t{$src, $dst|$dst, $src}",
2345 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2346 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2347 "shr{w}\t{$src, $dst|$dst, $src}",
2348 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2350 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2351 "shr{l}\t{$src, $dst|$dst, $src}",
2352 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2355 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2357 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2358 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2360 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2361 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2363 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2364 } // Constraints = ""
2366 let Uses = [CL] in {
2367 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2368 "sar{b}\t{%cl, $dst|$dst, CL}",
2369 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2370 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2371 "sar{w}\t{%cl, $dst|$dst, CL}",
2372 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2373 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2374 "sar{l}\t{%cl, $dst|$dst, CL}",
2375 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2378 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2379 "sar{b}\t{$src2, $dst|$dst, $src2}",
2380 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2381 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2382 "sar{w}\t{$src2, $dst|$dst, $src2}",
2383 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2385 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2386 "sar{l}\t{$src2, $dst|$dst, $src2}",
2387 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2390 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2392 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2393 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2395 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2396 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2398 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2400 let Constraints = "" in {
2401 let Uses = [CL] in {
2402 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2403 "sar{b}\t{%cl, $dst|$dst, CL}",
2404 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2405 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2406 "sar{w}\t{%cl, $dst|$dst, CL}",
2407 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2408 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2409 "sar{l}\t{%cl, $dst|$dst, CL}",
2410 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2412 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2413 "sar{b}\t{$src, $dst|$dst, $src}",
2414 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2415 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2416 "sar{w}\t{$src, $dst|$dst, $src}",
2417 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2419 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2420 "sar{l}\t{$src, $dst|$dst, $src}",
2421 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2424 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2426 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2427 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2429 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2431 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2433 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2434 } // Constraints = ""
2436 // Rotate instructions
2438 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2439 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2440 let Uses = [CL] in {
2441 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2442 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2444 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2445 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2447 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2448 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2449 let Uses = [CL] in {
2450 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2451 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2453 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2454 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2456 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2457 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2458 let Uses = [CL] in {
2459 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2460 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2462 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2463 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2465 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2466 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2467 let Uses = [CL] in {
2468 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2469 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2471 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2472 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2474 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2475 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2476 let Uses = [CL] in {
2477 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2478 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2480 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2481 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2483 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2484 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2485 let Uses = [CL] in {
2486 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2487 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2489 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2490 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2492 let Constraints = "" in {
2493 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2494 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2495 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2496 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2497 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2498 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2499 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2500 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2501 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2502 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2503 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2504 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2505 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2506 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2507 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2508 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2509 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2510 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2511 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2512 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2513 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2514 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2515 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2516 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2518 let Uses = [CL] in {
2519 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2520 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2521 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2522 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2523 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2524 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2525 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2526 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2527 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2528 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2529 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2530 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2532 } // Constraints = ""
2534 // FIXME: provide shorter instructions when imm8 == 1
2535 let Uses = [CL] in {
2536 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2537 "rol{b}\t{%cl, $dst|$dst, CL}",
2538 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2539 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2540 "rol{w}\t{%cl, $dst|$dst, CL}",
2541 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2542 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2543 "rol{l}\t{%cl, $dst|$dst, CL}",
2544 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2547 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2548 "rol{b}\t{$src2, $dst|$dst, $src2}",
2549 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2550 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2551 "rol{w}\t{$src2, $dst|$dst, $src2}",
2552 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2554 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2555 "rol{l}\t{$src2, $dst|$dst, $src2}",
2556 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2559 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2561 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2562 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2564 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2565 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2567 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2569 let Constraints = "" in {
2570 let Uses = [CL] in {
2571 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2572 "rol{b}\t{%cl, $dst|$dst, CL}",
2573 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2574 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2575 "rol{w}\t{%cl, $dst|$dst, CL}",
2576 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2577 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2578 "rol{l}\t{%cl, $dst|$dst, CL}",
2579 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2581 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2582 "rol{b}\t{$src, $dst|$dst, $src}",
2583 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2584 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2585 "rol{w}\t{$src, $dst|$dst, $src}",
2586 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2588 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2589 "rol{l}\t{$src, $dst|$dst, $src}",
2590 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2593 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2595 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2596 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2598 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2600 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2602 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2603 } // Constraints = ""
2605 let Uses = [CL] in {
2606 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2607 "ror{b}\t{%cl, $dst|$dst, CL}",
2608 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2609 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2610 "ror{w}\t{%cl, $dst|$dst, CL}",
2611 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2612 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2613 "ror{l}\t{%cl, $dst|$dst, CL}",
2614 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2617 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2618 "ror{b}\t{$src2, $dst|$dst, $src2}",
2619 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2620 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2621 "ror{w}\t{$src2, $dst|$dst, $src2}",
2622 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2624 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2625 "ror{l}\t{$src2, $dst|$dst, $src2}",
2626 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2629 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2631 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2632 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2634 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2635 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2637 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2639 let Constraints = "" in {
2640 let Uses = [CL] in {
2641 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2642 "ror{b}\t{%cl, $dst|$dst, CL}",
2643 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2644 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2645 "ror{w}\t{%cl, $dst|$dst, CL}",
2646 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2647 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2648 "ror{l}\t{%cl, $dst|$dst, CL}",
2649 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2651 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2652 "ror{b}\t{$src, $dst|$dst, $src}",
2653 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2654 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2655 "ror{w}\t{$src, $dst|$dst, $src}",
2656 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2658 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2659 "ror{l}\t{$src, $dst|$dst, $src}",
2660 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2663 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2665 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2666 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2668 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2670 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2672 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2673 } // Constraints = ""
2676 // Double shift instructions (generalizations of rotate)
2677 let Uses = [CL] in {
2678 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2679 (ins GR32:$src1, GR32:$src2),
2680 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2681 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2682 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2683 (ins GR32:$src1, GR32:$src2),
2684 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2685 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2686 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2687 (ins GR16:$src1, GR16:$src2),
2688 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2689 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2691 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2692 (ins GR16:$src1, GR16:$src2),
2693 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2694 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2698 let isCommutable = 1 in { // These instructions commute to each other.
2699 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2701 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2702 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2703 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2706 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2708 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2709 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2710 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2713 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2715 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2716 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2717 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2720 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2722 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2723 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2724 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2729 let Constraints = "" in {
2730 let Uses = [CL] in {
2731 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2732 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2733 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2735 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2736 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2737 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2740 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2741 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2742 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2743 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2744 (i8 imm:$src3)), addr:$dst)]>,
2746 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2747 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2748 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2749 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2750 (i8 imm:$src3)), addr:$dst)]>,
2753 let Uses = [CL] in {
2754 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2755 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2756 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2757 addr:$dst)]>, TB, OpSize;
2758 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2759 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2760 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2761 addr:$dst)]>, TB, OpSize;
2763 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2764 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2765 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2766 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2767 (i8 imm:$src3)), addr:$dst)]>,
2769 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2770 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2771 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2772 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2773 (i8 imm:$src3)), addr:$dst)]>,
2775 } // Constraints = ""
2776 } // Defs = [EFLAGS]
2780 let Defs = [EFLAGS] in {
2781 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2782 // Register-Register Addition
2783 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2784 (ins GR8 :$src1, GR8 :$src2),
2785 "add{b}\t{$src2, $dst|$dst, $src2}",
2786 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2788 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2789 // Register-Register Addition
2790 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2791 (ins GR16:$src1, GR16:$src2),
2792 "add{w}\t{$src2, $dst|$dst, $src2}",
2793 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2794 GR16:$src2))]>, OpSize;
2795 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2796 (ins GR32:$src1, GR32:$src2),
2797 "add{l}\t{$src2, $dst|$dst, $src2}",
2798 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2800 } // end isConvertibleToThreeAddress
2801 } // end isCommutable
2803 // These are alternate spellings for use by the disassembler, we mark them as
2804 // code gen only to ensure they aren't matched by the assembler.
2805 let isCodeGenOnly = 1 in {
2806 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2807 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2808 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2809 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2810 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2811 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2814 // Register-Memory Addition
2815 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2816 (ins GR8 :$src1, i8mem :$src2),
2817 "add{b}\t{$src2, $dst|$dst, $src2}",
2818 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2819 (load addr:$src2)))]>;
2820 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2821 (ins GR16:$src1, i16mem:$src2),
2822 "add{w}\t{$src2, $dst|$dst, $src2}",
2823 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2824 (load addr:$src2)))]>, OpSize;
2825 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2826 (ins GR32:$src1, i32mem:$src2),
2827 "add{l}\t{$src2, $dst|$dst, $src2}",
2828 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2829 (load addr:$src2)))]>;
2831 // Register-Integer Addition
2832 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2833 "add{b}\t{$src2, $dst|$dst, $src2}",
2834 [(set GR8:$dst, EFLAGS,
2835 (X86add_flag GR8:$src1, imm:$src2))]>;
2837 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2838 // Register-Integer Addition
2839 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2840 (ins GR16:$src1, i16imm:$src2),
2841 "add{w}\t{$src2, $dst|$dst, $src2}",
2842 [(set GR16:$dst, EFLAGS,
2843 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2844 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2845 (ins GR32:$src1, i32imm:$src2),
2846 "add{l}\t{$src2, $dst|$dst, $src2}",
2847 [(set GR32:$dst, EFLAGS,
2848 (X86add_flag GR32:$src1, imm:$src2))]>;
2849 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2850 (ins GR16:$src1, i16i8imm:$src2),
2851 "add{w}\t{$src2, $dst|$dst, $src2}",
2852 [(set GR16:$dst, EFLAGS,
2853 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2854 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2855 (ins GR32:$src1, i32i8imm:$src2),
2856 "add{l}\t{$src2, $dst|$dst, $src2}",
2857 [(set GR32:$dst, EFLAGS,
2858 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2861 let Constraints = "" in {
2862 // Memory-Register Addition
2863 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2864 "add{b}\t{$src2, $dst|$dst, $src2}",
2865 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2866 (implicit EFLAGS)]>;
2867 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2868 "add{w}\t{$src2, $dst|$dst, $src2}",
2869 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2870 (implicit EFLAGS)]>, OpSize;
2871 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2872 "add{l}\t{$src2, $dst|$dst, $src2}",
2873 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2874 (implicit EFLAGS)]>;
2875 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2876 "add{b}\t{$src2, $dst|$dst, $src2}",
2877 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2878 (implicit EFLAGS)]>;
2879 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2880 "add{w}\t{$src2, $dst|$dst, $src2}",
2881 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2882 (implicit EFLAGS)]>, OpSize;
2883 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2884 "add{l}\t{$src2, $dst|$dst, $src2}",
2885 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2886 (implicit EFLAGS)]>;
2887 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2888 "add{w}\t{$src2, $dst|$dst, $src2}",
2889 [(store (add (load addr:$dst), i16immSExt8:$src2),
2891 (implicit EFLAGS)]>, OpSize;
2892 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2893 "add{l}\t{$src2, $dst|$dst, $src2}",
2894 [(store (add (load addr:$dst), i32immSExt8:$src2),
2896 (implicit EFLAGS)]>;
2899 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2900 "add{b}\t{$src, %al|%al, $src}", []>;
2901 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2902 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2903 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2904 "add{l}\t{$src, %eax|%eax, $src}", []>;
2905 } // Constraints = ""
2907 let Uses = [EFLAGS] in {
2908 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2909 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2910 "adc{b}\t{$src2, $dst|$dst, $src2}",
2911 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2912 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2913 (ins GR16:$src1, GR16:$src2),
2914 "adc{w}\t{$src2, $dst|$dst, $src2}",
2915 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2916 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2917 (ins GR32:$src1, GR32:$src2),
2918 "adc{l}\t{$src2, $dst|$dst, $src2}",
2919 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2922 let isCodeGenOnly = 1 in {
2923 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2924 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2925 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2926 (ins GR16:$src1, GR16:$src2),
2927 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2928 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2929 (ins GR32:$src1, GR32:$src2),
2930 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2933 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2934 (ins GR8:$src1, i8mem:$src2),
2935 "adc{b}\t{$src2, $dst|$dst, $src2}",
2936 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2937 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2938 (ins GR16:$src1, i16mem:$src2),
2939 "adc{w}\t{$src2, $dst|$dst, $src2}",
2940 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2942 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2943 (ins GR32:$src1, i32mem:$src2),
2944 "adc{l}\t{$src2, $dst|$dst, $src2}",
2945 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2946 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2947 "adc{b}\t{$src2, $dst|$dst, $src2}",
2948 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2949 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2950 (ins GR16:$src1, i16imm:$src2),
2951 "adc{w}\t{$src2, $dst|$dst, $src2}",
2952 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2953 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2954 (ins GR16:$src1, i16i8imm:$src2),
2955 "adc{w}\t{$src2, $dst|$dst, $src2}",
2956 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2958 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2959 (ins GR32:$src1, i32imm:$src2),
2960 "adc{l}\t{$src2, $dst|$dst, $src2}",
2961 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2962 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2963 (ins GR32:$src1, i32i8imm:$src2),
2964 "adc{l}\t{$src2, $dst|$dst, $src2}",
2965 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2967 let Constraints = "" in {
2968 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2969 "adc{b}\t{$src2, $dst|$dst, $src2}",
2970 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2971 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2972 "adc{w}\t{$src2, $dst|$dst, $src2}",
2973 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2975 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2976 "adc{l}\t{$src2, $dst|$dst, $src2}",
2977 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2978 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2979 "adc{b}\t{$src2, $dst|$dst, $src2}",
2980 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2981 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2982 "adc{w}\t{$src2, $dst|$dst, $src2}",
2983 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2985 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2986 "adc{w}\t{$src2, $dst|$dst, $src2}",
2987 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2989 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2990 "adc{l}\t{$src2, $dst|$dst, $src2}",
2991 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2992 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2993 "adc{l}\t{$src2, $dst|$dst, $src2}",
2994 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2996 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2997 "adc{b}\t{$src, %al|%al, $src}", []>;
2998 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2999 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3000 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
3001 "adc{l}\t{$src, %eax|%eax, $src}", []>;
3002 } // Constraints = ""
3003 } // Uses = [EFLAGS]
3005 // Register-Register Subtraction
3006 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3007 "sub{b}\t{$src2, $dst|$dst, $src2}",
3008 [(set GR8:$dst, EFLAGS,
3009 (X86sub_flag GR8:$src1, GR8:$src2))]>;
3010 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3011 "sub{w}\t{$src2, $dst|$dst, $src2}",
3012 [(set GR16:$dst, EFLAGS,
3013 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
3014 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3015 "sub{l}\t{$src2, $dst|$dst, $src2}",
3016 [(set GR32:$dst, EFLAGS,
3017 (X86sub_flag GR32:$src1, GR32:$src2))]>;
3019 let isCodeGenOnly = 1 in {
3020 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3021 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
3022 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
3023 (ins GR16:$src1, GR16:$src2),
3024 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3025 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
3026 (ins GR32:$src1, GR32:$src2),
3027 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
3030 // Register-Memory Subtraction
3031 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
3032 (ins GR8 :$src1, i8mem :$src2),
3033 "sub{b}\t{$src2, $dst|$dst, $src2}",
3034 [(set GR8:$dst, EFLAGS,
3035 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
3036 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
3037 (ins GR16:$src1, i16mem:$src2),
3038 "sub{w}\t{$src2, $dst|$dst, $src2}",
3039 [(set GR16:$dst, EFLAGS,
3040 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
3041 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
3042 (ins GR32:$src1, i32mem:$src2),
3043 "sub{l}\t{$src2, $dst|$dst, $src2}",
3044 [(set GR32:$dst, EFLAGS,
3045 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
3047 // Register-Integer Subtraction
3048 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
3049 (ins GR8:$src1, i8imm:$src2),
3050 "sub{b}\t{$src2, $dst|$dst, $src2}",
3051 [(set GR8:$dst, EFLAGS,
3052 (X86sub_flag GR8:$src1, imm:$src2))]>;
3053 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
3054 (ins GR16:$src1, i16imm:$src2),
3055 "sub{w}\t{$src2, $dst|$dst, $src2}",
3056 [(set GR16:$dst, EFLAGS,
3057 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
3058 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
3059 (ins GR32:$src1, i32imm:$src2),
3060 "sub{l}\t{$src2, $dst|$dst, $src2}",
3061 [(set GR32:$dst, EFLAGS,
3062 (X86sub_flag GR32:$src1, imm:$src2))]>;
3063 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
3064 (ins GR16:$src1, i16i8imm:$src2),
3065 "sub{w}\t{$src2, $dst|$dst, $src2}",
3066 [(set GR16:$dst, EFLAGS,
3067 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
3068 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
3069 (ins GR32:$src1, i32i8imm:$src2),
3070 "sub{l}\t{$src2, $dst|$dst, $src2}",
3071 [(set GR32:$dst, EFLAGS,
3072 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
3074 let Constraints = "" in {
3075 // Memory-Register Subtraction
3076 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3077 "sub{b}\t{$src2, $dst|$dst, $src2}",
3078 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
3079 (implicit EFLAGS)]>;
3080 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3081 "sub{w}\t{$src2, $dst|$dst, $src2}",
3082 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
3083 (implicit EFLAGS)]>, OpSize;
3084 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3085 "sub{l}\t{$src2, $dst|$dst, $src2}",
3086 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3087 (implicit EFLAGS)]>;
3089 // Memory-Integer Subtraction
3090 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3091 "sub{b}\t{$src2, $dst|$dst, $src2}",
3092 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3093 (implicit EFLAGS)]>;
3094 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3095 "sub{w}\t{$src2, $dst|$dst, $src2}",
3096 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3097 (implicit EFLAGS)]>, OpSize;
3098 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3099 "sub{l}\t{$src2, $dst|$dst, $src2}",
3100 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3101 (implicit EFLAGS)]>;
3102 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3103 "sub{w}\t{$src2, $dst|$dst, $src2}",
3104 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3106 (implicit EFLAGS)]>, OpSize;
3107 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3108 "sub{l}\t{$src2, $dst|$dst, $src2}",
3109 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3111 (implicit EFLAGS)]>;
3113 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3114 "sub{b}\t{$src, %al|%al, $src}", []>;
3115 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3116 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3117 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3118 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3119 } // Constraints = ""
3121 let Uses = [EFLAGS] in {
3122 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3123 (ins GR8:$src1, GR8:$src2),
3124 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3125 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3126 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3127 (ins GR16:$src1, GR16:$src2),
3128 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3129 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3130 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3131 (ins GR32:$src1, GR32:$src2),
3132 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3133 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3135 let Constraints = "" in {
3136 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3137 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3138 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3139 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3140 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3141 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3143 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3144 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3145 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3146 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3147 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3148 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3149 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3150 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3151 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3153 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3154 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3155 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3157 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3158 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3159 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3160 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3161 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3162 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3164 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3165 "sbb{b}\t{$src, %al|%al, $src}", []>;
3166 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3167 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3168 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3169 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3170 } // Constraints = ""
3172 let isCodeGenOnly = 1 in {
3173 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3174 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3175 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3176 (ins GR16:$src1, GR16:$src2),
3177 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3178 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3179 (ins GR32:$src1, GR32:$src2),
3180 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3183 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3184 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3185 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3186 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3187 (ins GR16:$src1, i16mem:$src2),
3188 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3189 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3191 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3192 (ins GR32:$src1, i32mem:$src2),
3193 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3194 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3195 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3196 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3197 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3198 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3199 (ins GR16:$src1, i16imm:$src2),
3200 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3201 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3202 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3203 (ins GR16:$src1, i16i8imm:$src2),
3204 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3205 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3207 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3208 (ins GR32:$src1, i32imm:$src2),
3209 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3210 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3211 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3212 (ins GR32:$src1, i32i8imm:$src2),
3213 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3214 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3215 } // Uses = [EFLAGS]
3216 } // Defs = [EFLAGS]
3218 let Defs = [EFLAGS] in {
3219 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3220 // Register-Register Signed Integer Multiply
3221 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3222 "imul{w}\t{$src2, $dst|$dst, $src2}",
3223 [(set GR16:$dst, EFLAGS,
3224 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3225 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3226 "imul{l}\t{$src2, $dst|$dst, $src2}",
3227 [(set GR32:$dst, EFLAGS,
3228 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3231 // Register-Memory Signed Integer Multiply
3232 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3233 (ins GR16:$src1, i16mem:$src2),
3234 "imul{w}\t{$src2, $dst|$dst, $src2}",
3235 [(set GR16:$dst, EFLAGS,
3236 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3238 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3239 (ins GR32:$src1, i32mem:$src2),
3240 "imul{l}\t{$src2, $dst|$dst, $src2}",
3241 [(set GR32:$dst, EFLAGS,
3242 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3243 } // Defs = [EFLAGS]
3244 } // end Two Address instructions
3246 // Suprisingly enough, these are not two address instructions!
3247 let Defs = [EFLAGS] in {
3248 // Register-Integer Signed Integer Multiply
3249 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3250 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3251 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3252 [(set GR16:$dst, EFLAGS,
3253 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3254 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3255 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3256 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3257 [(set GR32:$dst, EFLAGS,
3258 (X86smul_flag GR32:$src1, imm:$src2))]>;
3259 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3260 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3261 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3262 [(set GR16:$dst, EFLAGS,
3263 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3265 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3266 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3267 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3268 [(set GR32:$dst, EFLAGS,
3269 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3271 // Memory-Integer Signed Integer Multiply
3272 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3273 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3274 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3275 [(set GR16:$dst, EFLAGS,
3276 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3278 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3279 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3280 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3281 [(set GR32:$dst, EFLAGS,
3282 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3283 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3284 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3285 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3286 [(set GR16:$dst, EFLAGS,
3287 (X86smul_flag (load addr:$src1),
3288 i16immSExt8:$src2))]>, OpSize;
3289 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3290 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3291 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3292 [(set GR32:$dst, EFLAGS,
3293 (X86smul_flag (load addr:$src1),
3294 i32immSExt8:$src2))]>;
3295 } // Defs = [EFLAGS]
3297 //===----------------------------------------------------------------------===//
3298 // Test instructions are just like AND, except they don't generate a result.
3300 let Defs = [EFLAGS] in {
3301 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3302 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3303 "test{b}\t{$src2, $src1|$src1, $src2}",
3304 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3305 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3306 "test{w}\t{$src2, $src1|$src1, $src2}",
3307 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3310 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3311 "test{l}\t{$src2, $src1|$src1, $src2}",
3312 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3316 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3317 "test{b}\t{$src, %al|%al, $src}", []>;
3318 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3319 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3320 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3321 "test{l}\t{$src, %eax|%eax, $src}", []>;
3323 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3324 "test{b}\t{$src2, $src1|$src1, $src2}",
3325 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3327 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3328 "test{w}\t{$src2, $src1|$src1, $src2}",
3329 [(set EFLAGS, (X86cmp (and GR16:$src1,
3330 (loadi16 addr:$src2)), 0))]>, OpSize;
3331 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3332 "test{l}\t{$src2, $src1|$src1, $src2}",
3333 [(set EFLAGS, (X86cmp (and GR32:$src1,
3334 (loadi32 addr:$src2)), 0))]>;
3336 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3337 (outs), (ins GR8:$src1, i8imm:$src2),
3338 "test{b}\t{$src2, $src1|$src1, $src2}",
3339 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3340 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3341 (outs), (ins GR16:$src1, i16imm:$src2),
3342 "test{w}\t{$src2, $src1|$src1, $src2}",
3343 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3345 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3346 (outs), (ins GR32:$src1, i32imm:$src2),
3347 "test{l}\t{$src2, $src1|$src1, $src2}",
3348 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3350 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3351 (outs), (ins i8mem:$src1, i8imm:$src2),
3352 "test{b}\t{$src2, $src1|$src1, $src2}",
3353 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3355 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3356 (outs), (ins i16mem:$src1, i16imm:$src2),
3357 "test{w}\t{$src2, $src1|$src1, $src2}",
3358 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3360 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3361 (outs), (ins i32mem:$src1, i32imm:$src2),
3362 "test{l}\t{$src2, $src1|$src1, $src2}",
3363 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3365 } // Defs = [EFLAGS]
3368 // Condition code ops, incl. set if equal/not equal/...
3369 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3370 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3371 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3372 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3374 let Uses = [EFLAGS] in {
3375 // Use sbb to materialize carry bit.
3376 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3377 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3378 // However, Pat<> can't replicate the destination reg into the inputs of the
3380 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3382 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3383 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3384 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3385 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3387 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3388 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3391 def SETEr : I<0x94, MRM0r,
3392 (outs GR8 :$dst), (ins),
3394 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3396 def SETEm : I<0x94, MRM0m,
3397 (outs), (ins i8mem:$dst),
3399 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3402 def SETNEr : I<0x95, MRM0r,
3403 (outs GR8 :$dst), (ins),
3405 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3407 def SETNEm : I<0x95, MRM0m,
3408 (outs), (ins i8mem:$dst),
3410 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3413 def SETLr : I<0x9C, MRM0r,
3414 (outs GR8 :$dst), (ins),
3416 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3417 TB; // GR8 = < signed
3418 def SETLm : I<0x9C, MRM0m,
3419 (outs), (ins i8mem:$dst),
3421 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3422 TB; // [mem8] = < signed
3424 def SETGEr : I<0x9D, MRM0r,
3425 (outs GR8 :$dst), (ins),
3427 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3428 TB; // GR8 = >= signed
3429 def SETGEm : I<0x9D, MRM0m,
3430 (outs), (ins i8mem:$dst),
3432 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3433 TB; // [mem8] = >= signed
3435 def SETLEr : I<0x9E, MRM0r,
3436 (outs GR8 :$dst), (ins),
3438 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3439 TB; // GR8 = <= signed
3440 def SETLEm : I<0x9E, MRM0m,
3441 (outs), (ins i8mem:$dst),
3443 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3444 TB; // [mem8] = <= signed
3446 def SETGr : I<0x9F, MRM0r,
3447 (outs GR8 :$dst), (ins),
3449 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3450 TB; // GR8 = > signed
3451 def SETGm : I<0x9F, MRM0m,
3452 (outs), (ins i8mem:$dst),
3454 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3455 TB; // [mem8] = > signed
3457 def SETBr : I<0x92, MRM0r,
3458 (outs GR8 :$dst), (ins),
3460 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3461 TB; // GR8 = < unsign
3462 def SETBm : I<0x92, MRM0m,
3463 (outs), (ins i8mem:$dst),
3465 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3466 TB; // [mem8] = < unsign
3468 def SETAEr : I<0x93, MRM0r,
3469 (outs GR8 :$dst), (ins),
3471 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3472 TB; // GR8 = >= unsign
3473 def SETAEm : I<0x93, MRM0m,
3474 (outs), (ins i8mem:$dst),
3476 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3477 TB; // [mem8] = >= unsign
3479 def SETBEr : I<0x96, MRM0r,
3480 (outs GR8 :$dst), (ins),
3482 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3483 TB; // GR8 = <= unsign
3484 def SETBEm : I<0x96, MRM0m,
3485 (outs), (ins i8mem:$dst),
3487 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3488 TB; // [mem8] = <= unsign
3490 def SETAr : I<0x97, MRM0r,
3491 (outs GR8 :$dst), (ins),
3493 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3494 TB; // GR8 = > signed
3495 def SETAm : I<0x97, MRM0m,
3496 (outs), (ins i8mem:$dst),
3498 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3499 TB; // [mem8] = > signed
3501 def SETSr : I<0x98, MRM0r,
3502 (outs GR8 :$dst), (ins),
3504 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3505 TB; // GR8 = <sign bit>
3506 def SETSm : I<0x98, MRM0m,
3507 (outs), (ins i8mem:$dst),
3509 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3510 TB; // [mem8] = <sign bit>
3511 def SETNSr : I<0x99, MRM0r,
3512 (outs GR8 :$dst), (ins),
3514 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3515 TB; // GR8 = !<sign bit>
3516 def SETNSm : I<0x99, MRM0m,
3517 (outs), (ins i8mem:$dst),
3519 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3520 TB; // [mem8] = !<sign bit>
3522 def SETPr : I<0x9A, MRM0r,
3523 (outs GR8 :$dst), (ins),
3525 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3527 def SETPm : I<0x9A, MRM0m,
3528 (outs), (ins i8mem:$dst),
3530 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3531 TB; // [mem8] = parity
3532 def SETNPr : I<0x9B, MRM0r,
3533 (outs GR8 :$dst), (ins),
3535 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3536 TB; // GR8 = not parity
3537 def SETNPm : I<0x9B, MRM0m,
3538 (outs), (ins i8mem:$dst),
3540 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3541 TB; // [mem8] = not parity
3543 def SETOr : I<0x90, MRM0r,
3544 (outs GR8 :$dst), (ins),
3546 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3547 TB; // GR8 = overflow
3548 def SETOm : I<0x90, MRM0m,
3549 (outs), (ins i8mem:$dst),
3551 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3552 TB; // [mem8] = overflow
3553 def SETNOr : I<0x91, MRM0r,
3554 (outs GR8 :$dst), (ins),
3556 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3557 TB; // GR8 = not overflow
3558 def SETNOm : I<0x91, MRM0m,
3559 (outs), (ins i8mem:$dst),
3561 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3562 TB; // [mem8] = not overflow
3563 } // Uses = [EFLAGS]
3566 // Integer comparisons
3567 let Defs = [EFLAGS] in {
3568 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3569 "cmp{b}\t{$src, %al|%al, $src}", []>;
3570 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3571 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3572 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3573 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3575 def CMP8rr : I<0x38, MRMDestReg,
3576 (outs), (ins GR8 :$src1, GR8 :$src2),
3577 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3578 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3579 def CMP16rr : I<0x39, MRMDestReg,
3580 (outs), (ins GR16:$src1, GR16:$src2),
3581 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3582 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3583 def CMP32rr : I<0x39, MRMDestReg,
3584 (outs), (ins GR32:$src1, GR32:$src2),
3585 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3586 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3587 def CMP8mr : I<0x38, MRMDestMem,
3588 (outs), (ins i8mem :$src1, GR8 :$src2),
3589 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3590 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3591 def CMP16mr : I<0x39, MRMDestMem,
3592 (outs), (ins i16mem:$src1, GR16:$src2),
3593 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3594 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3596 def CMP32mr : I<0x39, MRMDestMem,
3597 (outs), (ins i32mem:$src1, GR32:$src2),
3598 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3599 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3600 def CMP8rm : I<0x3A, MRMSrcMem,
3601 (outs), (ins GR8 :$src1, i8mem :$src2),
3602 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3603 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3604 def CMP16rm : I<0x3B, MRMSrcMem,
3605 (outs), (ins GR16:$src1, i16mem:$src2),
3606 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3607 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3609 def CMP32rm : I<0x3B, MRMSrcMem,
3610 (outs), (ins GR32:$src1, i32mem:$src2),
3611 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3612 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3614 // These are alternate spellings for use by the disassembler, we mark them as
3615 // code gen only to ensure they aren't matched by the assembler.
3616 let isCodeGenOnly = 1 in {
3617 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3618 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3619 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3620 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3621 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3622 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3625 def CMP8ri : Ii8<0x80, MRM7r,
3626 (outs), (ins GR8:$src1, i8imm:$src2),
3627 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3628 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3629 def CMP16ri : Ii16<0x81, MRM7r,
3630 (outs), (ins GR16:$src1, i16imm:$src2),
3631 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3632 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3633 def CMP32ri : Ii32<0x81, MRM7r,
3634 (outs), (ins GR32:$src1, i32imm:$src2),
3635 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3636 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3637 def CMP8mi : Ii8 <0x80, MRM7m,
3638 (outs), (ins i8mem :$src1, i8imm :$src2),
3639 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3640 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3641 def CMP16mi : Ii16<0x81, MRM7m,
3642 (outs), (ins i16mem:$src1, i16imm:$src2),
3643 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3644 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3646 def CMP32mi : Ii32<0x81, MRM7m,
3647 (outs), (ins i32mem:$src1, i32imm:$src2),
3648 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3649 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3650 def CMP16ri8 : Ii8<0x83, MRM7r,
3651 (outs), (ins GR16:$src1, i16i8imm:$src2),
3652 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3653 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3655 def CMP16mi8 : Ii8<0x83, MRM7m,
3656 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3657 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3658 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3659 i16immSExt8:$src2))]>, OpSize;
3660 def CMP32mi8 : Ii8<0x83, MRM7m,
3661 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3662 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3663 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3664 i32immSExt8:$src2))]>;
3665 def CMP32ri8 : Ii8<0x83, MRM7r,
3666 (outs), (ins GR32:$src1, i32i8imm:$src2),
3667 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3668 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3669 } // Defs = [EFLAGS]
3672 // TODO: BTC, BTR, and BTS
3673 let Defs = [EFLAGS] in {
3674 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3675 "bt{w}\t{$src2, $src1|$src1, $src2}",
3676 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3677 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3678 "bt{l}\t{$src2, $src1|$src1, $src2}",
3679 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3681 // Unlike with the register+register form, the memory+register form of the
3682 // bt instruction does not ignore the high bits of the index. From ISel's
3683 // perspective, this is pretty bizarre. Make these instructions disassembly
3686 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3687 "bt{w}\t{$src2, $src1|$src1, $src2}",
3688 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3689 // (implicit EFLAGS)]
3691 >, OpSize, TB, Requires<[FastBTMem]>;
3692 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3693 "bt{l}\t{$src2, $src1|$src1, $src2}",
3694 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3695 // (implicit EFLAGS)]
3697 >, TB, Requires<[FastBTMem]>;
3699 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3700 "bt{w}\t{$src2, $src1|$src1, $src2}",
3701 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3703 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3704 "bt{l}\t{$src2, $src1|$src1, $src2}",
3705 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3706 // Note that these instructions don't need FastBTMem because that
3707 // only applies when the other operand is in a register. When it's
3708 // an immediate, bt is still fast.
3709 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3710 "bt{w}\t{$src2, $src1|$src1, $src2}",
3711 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3713 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3714 "bt{l}\t{$src2, $src1|$src1, $src2}",
3715 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3718 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3719 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3720 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3721 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3722 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3723 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3724 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3725 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3726 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3727 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3728 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3729 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3730 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3731 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3732 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3733 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3735 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3736 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3737 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3738 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3739 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3740 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3741 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3742 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3743 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3744 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3745 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3746 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3747 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3748 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3749 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3750 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3752 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3753 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3754 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3755 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3756 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3757 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3758 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3759 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3760 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3761 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3762 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3763 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3764 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3765 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3766 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3767 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3768 } // Defs = [EFLAGS]
3770 // Sign/Zero extenders
3771 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3772 // of the register here. This has a smaller encoding and avoids a
3773 // partial-register update. Actual movsbw included for the disassembler.
3774 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3775 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3776 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3777 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3778 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3779 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3780 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3781 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3782 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3783 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3784 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3785 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3786 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3787 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3788 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3789 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3790 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3791 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3792 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3793 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3795 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3796 // of the register here. This has a smaller encoding and avoids a
3797 // partial-register update. Actual movzbw included for the disassembler.
3798 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3799 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3800 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3801 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3802 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3803 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3804 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3805 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3806 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3807 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3808 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3809 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3810 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3811 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3812 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3813 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3814 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3815 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3816 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3817 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3819 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3820 // except that they use GR32_NOREX for the output operand register class
3821 // instead of GR32. This allows them to operate on h registers on x86-64.
3822 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3823 (outs GR32_NOREX:$dst), (ins GR8:$src),
3824 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3827 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3828 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3829 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3832 let neverHasSideEffects = 1 in {
3833 let Defs = [AX], Uses = [AL] in
3834 def CBW : I<0x98, RawFrm, (outs), (ins),
3835 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3836 let Defs = [EAX], Uses = [AX] in
3837 def CWDE : I<0x98, RawFrm, (outs), (ins),
3838 "{cwtl|cwde}", []>; // EAX = signext(AX)
3840 let Defs = [AX,DX], Uses = [AX] in
3841 def CWD : I<0x99, RawFrm, (outs), (ins),
3842 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3843 let Defs = [EAX,EDX], Uses = [EAX] in
3844 def CDQ : I<0x99, RawFrm, (outs), (ins),
3845 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3848 //===----------------------------------------------------------------------===//
3849 // Alias Instructions
3850 //===----------------------------------------------------------------------===//
3852 // Alias instructions that map movr0 to xor.
3853 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3854 // FIXME: Set encoding to pseudo.
3855 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3856 isCodeGenOnly = 1 in {
3857 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3858 [(set GR8:$dst, 0)]>;
3860 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3861 // encoding and avoids a partial-register update sometimes, but doing so
3862 // at isel time interferes with rematerialization in the current register
3863 // allocator. For now, this is rewritten when the instruction is lowered
3865 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3867 [(set GR16:$dst, 0)]>, OpSize;
3869 // FIXME: Set encoding to pseudo.
3870 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3871 [(set GR32:$dst, 0)]>;
3874 //===----------------------------------------------------------------------===//
3875 // Thread Local Storage Instructions
3879 // All calls clobber the non-callee saved registers. ESP is marked as
3880 // a use to prevent stack-pointer assignments that appear immediately
3881 // before calls from potentially appearing dead.
3882 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3883 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3884 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3885 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3887 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3888 "leal\t$sym, %eax; "
3889 "call\t___tls_get_addr@PLT",
3890 [(X86tlsaddr tls32addr:$sym)]>,
3891 Requires<[In32BitMode]>;
3893 // Darwin TLS Support
3894 // For i386, the address of the thunk is passed on the stack, on return the
3895 // address of the variable is in %eax. %ecx is trashed during the function
3896 // call. All other registers are preserved.
3897 let Defs = [EAX, ECX],
3899 usesCustomInserter = 1 in
3900 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3902 [(X86TLSCall addr:$sym)]>,
3903 Requires<[In32BitMode]>;
3905 let AddedComplexity = 5, isCodeGenOnly = 1 in
3906 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3907 "movl\t%gs:$src, $dst",
3908 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3910 let AddedComplexity = 5, isCodeGenOnly = 1 in
3911 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3912 "movl\t%fs:$src, $dst",
3913 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3915 //===----------------------------------------------------------------------===//
3916 // EH Pseudo Instructions
3918 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3919 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3920 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3921 "ret\t#eh_return, addr: $addr",
3922 [(X86ehret GR32:$addr)]>;
3926 //===----------------------------------------------------------------------===//
3931 let hasSideEffects = 1 in {
3932 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
3934 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
3936 // TODO: Get this to fold the constant into the instruction.
3938 def Int_MemBarrierNoSSE : I<0x0B, Pseudo, (outs), (ins GR32:$zero),
3940 "or{l}\t{$zero, (%esp)|(%esp), $zero}",
3941 [(X86MemBarrierNoSSE GR32:$zero)]>, LOCK;
3944 // Atomic swap. These are just normal xchg instructions. But since a memory
3945 // operand is referenced, the atomicity is ensured.
3946 let Constraints = "$val = $dst" in {
3947 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3948 (ins GR32:$val, i32mem:$ptr),
3949 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3950 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3951 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3952 (ins GR16:$val, i16mem:$ptr),
3953 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3954 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3956 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3957 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3958 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3960 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3961 "xchg{l}\t{$val, $src|$src, $val}", []>;
3962 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3963 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3964 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3965 "xchg{b}\t{$val, $src|$src, $val}", []>;
3968 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3969 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3970 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3971 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3973 // Atomic compare and swap.
3974 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3975 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3977 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3978 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3980 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3981 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3984 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3987 let Defs = [AX, EFLAGS], Uses = [AX] in {
3988 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3990 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3991 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3993 let Defs = [AL, EFLAGS], Uses = [AL] in {
3994 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3996 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3997 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
4000 // Atomic exchange and add
4001 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
4002 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
4004 "xadd{l}\t{$val, $ptr|$ptr, $val}",
4005 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
4007 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
4009 "xadd{w}\t{$val, $ptr|$ptr, $val}",
4010 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
4012 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
4014 "xadd{b}\t{$val, $ptr|$ptr, $val}",
4015 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
4019 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4020 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
4021 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4022 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4023 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4024 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4026 let mayLoad = 1, mayStore = 1 in {
4027 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4028 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
4029 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4030 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4031 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4032 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4035 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4036 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4037 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4038 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4039 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4040 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4042 let mayLoad = 1, mayStore = 1 in {
4043 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4044 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4045 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4046 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4047 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4048 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4051 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
4052 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
4053 "cmpxchg8b\t$dst", []>, TB;
4055 // Optimized codegen when the non-memory output is not used.
4056 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
4057 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
4058 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
4060 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4061 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4063 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4064 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4066 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4067 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
4069 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4070 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
4072 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4073 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
4075 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4076 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4078 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4079 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4081 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4083 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
4085 "inc{b}\t$dst", []>, LOCK;
4086 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
4088 "inc{w}\t$dst", []>, OpSize, LOCK;
4089 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
4091 "inc{l}\t$dst", []>, LOCK;
4093 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
4095 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4096 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4098 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4099 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4101 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4102 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
4104 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4105 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
4107 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4108 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
4110 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4111 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4113 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4114 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4116 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4118 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4120 "dec{b}\t$dst", []>, LOCK;
4121 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4123 "dec{w}\t$dst", []>, OpSize, LOCK;
4124 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4126 "dec{l}\t$dst", []>, LOCK;
4129 // Atomic exchange, and, or, xor
4130 let Constraints = "$val = $dst", Defs = [EFLAGS],
4131 usesCustomInserter = 1 in {
4132 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4133 "#ATOMAND32 PSEUDO!",
4134 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4135 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4136 "#ATOMOR32 PSEUDO!",
4137 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4138 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4139 "#ATOMXOR32 PSEUDO!",
4140 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4141 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4142 "#ATOMNAND32 PSEUDO!",
4143 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4144 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4145 "#ATOMMIN32 PSEUDO!",
4146 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4147 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4148 "#ATOMMAX32 PSEUDO!",
4149 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4150 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4151 "#ATOMUMIN32 PSEUDO!",
4152 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4153 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4154 "#ATOMUMAX32 PSEUDO!",
4155 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4157 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4158 "#ATOMAND16 PSEUDO!",
4159 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4160 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4161 "#ATOMOR16 PSEUDO!",
4162 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4163 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4164 "#ATOMXOR16 PSEUDO!",
4165 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4166 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4167 "#ATOMNAND16 PSEUDO!",
4168 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4169 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4170 "#ATOMMIN16 PSEUDO!",
4171 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4172 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4173 "#ATOMMAX16 PSEUDO!",
4174 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4175 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4176 "#ATOMUMIN16 PSEUDO!",
4177 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4178 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4179 "#ATOMUMAX16 PSEUDO!",
4180 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4182 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4183 "#ATOMAND8 PSEUDO!",
4184 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4185 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4187 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4188 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4189 "#ATOMXOR8 PSEUDO!",
4190 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4191 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4192 "#ATOMNAND8 PSEUDO!",
4193 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4196 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4197 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4198 Uses = [EAX, EBX, ECX, EDX],
4199 mayLoad = 1, mayStore = 1,
4200 usesCustomInserter = 1 in {
4201 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4202 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4203 "#ATOMAND6432 PSEUDO!", []>;
4204 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4205 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4206 "#ATOMOR6432 PSEUDO!", []>;
4207 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4208 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4209 "#ATOMXOR6432 PSEUDO!", []>;
4210 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4211 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4212 "#ATOMNAND6432 PSEUDO!", []>;
4213 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4214 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4215 "#ATOMADD6432 PSEUDO!", []>;
4216 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4217 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4218 "#ATOMSUB6432 PSEUDO!", []>;
4219 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4220 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4221 "#ATOMSWAP6432 PSEUDO!", []>;
4224 // Segmentation support instructions.
4226 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4227 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4228 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4229 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4231 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4232 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4233 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4234 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4235 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4237 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4238 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4239 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4240 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4241 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4242 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4243 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4244 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4246 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4248 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4249 "str{w}\t{$dst}", []>, TB;
4250 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4251 "str{w}\t{$dst}", []>, TB;
4252 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4253 "ltr{w}\t{$src}", []>, TB;
4254 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4255 "ltr{w}\t{$src}", []>, TB;
4257 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4258 "push{w}\t%fs", []>, OpSize, TB;
4259 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4260 "push{l}\t%fs", []>, TB;
4261 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4262 "push{w}\t%gs", []>, OpSize, TB;
4263 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4264 "push{l}\t%gs", []>, TB;
4266 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4267 "pop{w}\t%fs", []>, OpSize, TB;
4268 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4269 "pop{l}\t%fs", []>, TB;
4270 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4271 "pop{w}\t%gs", []>, OpSize, TB;
4272 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4273 "pop{l}\t%gs", []>, TB;
4275 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4276 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4277 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4278 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4279 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4280 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4281 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4282 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4283 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4284 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4285 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4286 "les{l}\t{$src, $dst|$dst, $src}", []>;
4287 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4288 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4289 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4290 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4291 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4292 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4293 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4294 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4296 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4297 "verr\t$seg", []>, TB;
4298 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4299 "verr\t$seg", []>, TB;
4300 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4301 "verw\t$seg", []>, TB;
4302 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4303 "verw\t$seg", []>, TB;
4305 // Descriptor-table support instructions
4307 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4308 "sgdt\t$dst", []>, TB;
4309 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4310 "sidt\t$dst", []>, TB;
4311 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4312 "sldt{w}\t$dst", []>, TB;
4313 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4314 "sldt{w}\t$dst", []>, TB;
4315 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4316 "lgdt\t$src", []>, TB;
4317 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4318 "lidt\t$src", []>, TB;
4319 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4320 "lldt{w}\t$src", []>, TB;
4321 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4322 "lldt{w}\t$src", []>, TB;
4324 // Lock instruction prefix
4325 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4327 // Repeat string operation instruction prefixes
4328 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4329 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4330 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4331 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4332 // Repeat while not equal (used with CMPS and SCAS)
4333 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4336 // Segment override instruction prefixes
4337 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4338 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4339 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4340 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4341 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4342 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4344 // String manipulation instructions
4346 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4347 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4348 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4350 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4351 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4352 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4354 // CPU flow control instructions
4356 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4357 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4359 // FPU control instructions
4361 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4363 // Flag instructions
4365 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4366 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4367 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4368 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4369 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4370 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4371 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4373 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4375 // Table lookup instructions
4377 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4379 // Specialized register support
4381 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4382 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4383 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4385 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4386 "smsw{w}\t$dst", []>, OpSize, TB;
4387 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4388 "smsw{l}\t$dst", []>, TB;
4389 // For memory operands, there is only a 16-bit form
4390 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4391 "smsw{w}\t$dst", []>, TB;
4393 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4394 "lmsw{w}\t$src", []>, TB;
4395 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4396 "lmsw{w}\t$src", []>, TB;
4398 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4400 // Cache instructions
4402 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4403 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4408 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4410 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4412 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4413 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4414 "vmclear\t$vmcs", []>, OpSize, TB;
4416 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4418 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4419 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4420 "vmptrld\t$vmcs", []>, TB;
4421 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4422 "vmptrst\t$vmcs", []>, TB;
4423 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4424 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4425 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4426 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4427 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4428 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4429 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4430 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4431 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4432 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4433 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4434 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4435 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4436 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4437 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4438 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4440 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4441 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4442 "vmxon\t{$vmxon}", []>, XS;
4444 //===----------------------------------------------------------------------===//
4445 // Non-Instruction Patterns
4446 //===----------------------------------------------------------------------===//
4448 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4449 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4450 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4451 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4452 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4453 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4454 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4456 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4457 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4458 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4459 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4460 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4461 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4462 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4463 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4464 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4465 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4467 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4468 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4469 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4470 (MOV32mi addr:$dst, texternalsym:$src)>;
4471 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4472 (MOV32mi addr:$dst, tblockaddress:$src)>;
4476 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4477 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4478 Requires<[In32BitMode]>;
4480 // FIXME: This is disabled for 32-bit PIC mode because the global base
4481 // register which is part of the address mode may be assigned a
4482 // callee-saved register.
4483 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4484 (TCRETURNmi addr:$dst, imm:$off)>,
4485 Requires<[In32BitMode, IsNotPIC]>;
4487 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4488 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4489 Requires<[In32BitMode]>;
4491 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4492 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4493 Requires<[In32BitMode]>;
4495 // Normal calls, with various flavors of addresses.
4496 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4497 (CALLpcrel32 tglobaladdr:$dst)>;
4498 def : Pat<(X86call (i32 texternalsym:$dst)),
4499 (CALLpcrel32 texternalsym:$dst)>;
4500 def : Pat<(X86call (i32 imm:$dst)),
4501 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4503 // X86 specific add which produces a flag.
4504 def : Pat<(addc GR32:$src1, GR32:$src2),
4505 (ADD32rr GR32:$src1, GR32:$src2)>;
4506 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4507 (ADD32rm GR32:$src1, addr:$src2)>;
4508 def : Pat<(addc GR32:$src1, imm:$src2),
4509 (ADD32ri GR32:$src1, imm:$src2)>;
4510 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4511 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4513 def : Pat<(subc GR32:$src1, GR32:$src2),
4514 (SUB32rr GR32:$src1, GR32:$src2)>;
4515 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4516 (SUB32rm GR32:$src1, addr:$src2)>;
4517 def : Pat<(subc GR32:$src1, imm:$src2),
4518 (SUB32ri GR32:$src1, imm:$src2)>;
4519 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4520 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4524 // TEST R,R is smaller than CMP R,0
4525 def : Pat<(X86cmp GR8:$src1, 0),
4526 (TEST8rr GR8:$src1, GR8:$src1)>;
4527 def : Pat<(X86cmp GR16:$src1, 0),
4528 (TEST16rr GR16:$src1, GR16:$src1)>;
4529 def : Pat<(X86cmp GR32:$src1, 0),
4530 (TEST32rr GR32:$src1, GR32:$src1)>;
4532 // Conditional moves with folded loads with operands swapped and conditions
4534 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4535 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4536 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4537 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4538 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4539 (CMOVB16rm GR16:$src2, addr:$src1)>;
4540 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4541 (CMOVB32rm GR32:$src2, addr:$src1)>;
4542 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4543 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4544 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4545 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4546 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4547 (CMOVE16rm GR16:$src2, addr:$src1)>;
4548 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4549 (CMOVE32rm GR32:$src2, addr:$src1)>;
4550 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4551 (CMOVA16rm GR16:$src2, addr:$src1)>;
4552 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4553 (CMOVA32rm GR32:$src2, addr:$src1)>;
4554 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4555 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4556 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4557 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4558 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4559 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4560 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4561 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4562 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4563 (CMOVL16rm GR16:$src2, addr:$src1)>;
4564 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4565 (CMOVL32rm GR32:$src2, addr:$src1)>;
4566 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4567 (CMOVG16rm GR16:$src2, addr:$src1)>;
4568 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4569 (CMOVG32rm GR32:$src2, addr:$src1)>;
4570 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4571 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4572 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4573 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4574 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4575 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4576 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4577 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4578 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4579 (CMOVP16rm GR16:$src2, addr:$src1)>;
4580 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4581 (CMOVP32rm GR32:$src2, addr:$src1)>;
4582 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4583 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4584 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4585 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4586 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4587 (CMOVS16rm GR16:$src2, addr:$src1)>;
4588 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4589 (CMOVS32rm GR32:$src2, addr:$src1)>;
4590 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4591 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4592 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4593 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4594 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4595 (CMOVO16rm GR16:$src2, addr:$src1)>;
4596 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4597 (CMOVO32rm GR32:$src2, addr:$src1)>;
4599 // zextload bool -> zextload byte
4600 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4601 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4602 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4604 // extload bool -> extload byte
4605 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4606 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4607 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4608 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4609 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4610 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4612 // anyext. Define these to do an explicit zero-extend to
4613 // avoid partial-register updates.
4614 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4615 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4617 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4618 def : Pat<(i32 (anyext GR16:$src)),
4619 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4622 //===----------------------------------------------------------------------===//
4624 //===----------------------------------------------------------------------===//
4626 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4627 // +128 doesn't, so in this special case use a sub instead of an add.
4628 def : Pat<(add GR16:$src1, 128),
4629 (SUB16ri8 GR16:$src1, -128)>;
4630 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4631 (SUB16mi8 addr:$dst, -128)>;
4632 def : Pat<(add GR32:$src1, 128),
4633 (SUB32ri8 GR32:$src1, -128)>;
4634 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4635 (SUB32mi8 addr:$dst, -128)>;
4637 // r & (2^16-1) ==> movz
4638 def : Pat<(and GR32:$src1, 0xffff),
4639 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4640 // r & (2^8-1) ==> movz
4641 def : Pat<(and GR32:$src1, 0xff),
4642 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4645 Requires<[In32BitMode]>;
4646 // r & (2^8-1) ==> movz
4647 def : Pat<(and GR16:$src1, 0xff),
4648 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4651 Requires<[In32BitMode]>;
4653 // sext_inreg patterns
4654 def : Pat<(sext_inreg GR32:$src, i16),
4655 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4656 def : Pat<(sext_inreg GR32:$src, i8),
4657 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4660 Requires<[In32BitMode]>;
4661 def : Pat<(sext_inreg GR16:$src, i8),
4662 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4665 Requires<[In32BitMode]>;
4668 def : Pat<(i16 (trunc GR32:$src)),
4669 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4670 def : Pat<(i8 (trunc GR32:$src)),
4671 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4673 Requires<[In32BitMode]>;
4674 def : Pat<(i8 (trunc GR16:$src)),
4675 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4677 Requires<[In32BitMode]>;
4679 // h-register tricks
4680 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4681 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4683 Requires<[In32BitMode]>;
4684 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4685 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4687 Requires<[In32BitMode]>;
4688 def : Pat<(srl GR16:$src, (i8 8)),
4691 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4694 Requires<[In32BitMode]>;
4695 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4696 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4699 Requires<[In32BitMode]>;
4700 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4701 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4704 Requires<[In32BitMode]>;
4705 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4706 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4709 Requires<[In32BitMode]>;
4710 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4711 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4714 Requires<[In32BitMode]>;
4716 // (shl x, 1) ==> (add x, x)
4717 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4718 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4719 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4721 // (shl x (and y, 31)) ==> (shl x, y)
4722 def : Pat<(shl GR8:$src1, (and CL, 31)),
4723 (SHL8rCL GR8:$src1)>;
4724 def : Pat<(shl GR16:$src1, (and CL, 31)),
4725 (SHL16rCL GR16:$src1)>;
4726 def : Pat<(shl GR32:$src1, (and CL, 31)),
4727 (SHL32rCL GR32:$src1)>;
4728 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4729 (SHL8mCL addr:$dst)>;
4730 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4731 (SHL16mCL addr:$dst)>;
4732 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4733 (SHL32mCL addr:$dst)>;
4735 def : Pat<(srl GR8:$src1, (and CL, 31)),
4736 (SHR8rCL GR8:$src1)>;
4737 def : Pat<(srl GR16:$src1, (and CL, 31)),
4738 (SHR16rCL GR16:$src1)>;
4739 def : Pat<(srl GR32:$src1, (and CL, 31)),
4740 (SHR32rCL GR32:$src1)>;
4741 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4742 (SHR8mCL addr:$dst)>;
4743 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4744 (SHR16mCL addr:$dst)>;
4745 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4746 (SHR32mCL addr:$dst)>;
4748 def : Pat<(sra GR8:$src1, (and CL, 31)),
4749 (SAR8rCL GR8:$src1)>;
4750 def : Pat<(sra GR16:$src1, (and CL, 31)),
4751 (SAR16rCL GR16:$src1)>;
4752 def : Pat<(sra GR32:$src1, (and CL, 31)),
4753 (SAR32rCL GR32:$src1)>;
4754 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4755 (SAR8mCL addr:$dst)>;
4756 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4757 (SAR16mCL addr:$dst)>;
4758 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4759 (SAR32mCL addr:$dst)>;
4761 // (anyext (setcc_carry)) -> (setcc_carry)
4762 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4764 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4766 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4769 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4770 let AddedComplexity = 5 in { // Try this before the selecting to OR
4771 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4772 (ADD16ri GR16:$src1, imm:$src2)>;
4773 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4774 (ADD32ri GR32:$src1, imm:$src2)>;
4775 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4776 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4777 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4778 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4779 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4780 (ADD16rr GR16:$src1, GR16:$src2)>;
4781 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4782 (ADD32rr GR32:$src1, GR32:$src2)>;
4783 } // AddedComplexity
4785 //===----------------------------------------------------------------------===//
4786 // EFLAGS-defining Patterns
4787 //===----------------------------------------------------------------------===//
4790 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4791 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4792 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4795 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4796 (ADD8rm GR8:$src1, addr:$src2)>;
4797 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4798 (ADD16rm GR16:$src1, addr:$src2)>;
4799 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4800 (ADD32rm GR32:$src1, addr:$src2)>;
4803 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4804 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4805 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4806 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4807 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4808 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4809 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4812 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4813 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4814 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4817 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4818 (SUB8rm GR8:$src1, addr:$src2)>;
4819 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4820 (SUB16rm GR16:$src1, addr:$src2)>;
4821 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4822 (SUB32rm GR32:$src1, addr:$src2)>;
4825 def : Pat<(sub GR8:$src1, imm:$src2),
4826 (SUB8ri GR8:$src1, imm:$src2)>;
4827 def : Pat<(sub GR16:$src1, imm:$src2),
4828 (SUB16ri GR16:$src1, imm:$src2)>;
4829 def : Pat<(sub GR32:$src1, imm:$src2),
4830 (SUB32ri GR32:$src1, imm:$src2)>;
4831 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4832 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4833 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4834 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4837 def : Pat<(mul GR16:$src1, GR16:$src2),
4838 (IMUL16rr GR16:$src1, GR16:$src2)>;
4839 def : Pat<(mul GR32:$src1, GR32:$src2),
4840 (IMUL32rr GR32:$src1, GR32:$src2)>;
4843 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4844 (IMUL16rm GR16:$src1, addr:$src2)>;
4845 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4846 (IMUL32rm GR32:$src1, addr:$src2)>;
4849 def : Pat<(mul GR16:$src1, imm:$src2),
4850 (IMUL16rri GR16:$src1, imm:$src2)>;
4851 def : Pat<(mul GR32:$src1, imm:$src2),
4852 (IMUL32rri GR32:$src1, imm:$src2)>;
4853 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4854 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4855 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4856 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4858 // reg = mul mem, imm
4859 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4860 (IMUL16rmi addr:$src1, imm:$src2)>;
4861 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4862 (IMUL32rmi addr:$src1, imm:$src2)>;
4863 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4864 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4865 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4866 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4868 // Optimize multiply by 2 with EFLAGS result.
4869 let AddedComplexity = 2 in {
4870 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4871 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4874 // Patterns for nodes that do not produce flags, for instructions that do.
4877 def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
4878 def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
4879 def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
4882 def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
4883 def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
4884 def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
4887 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4888 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4889 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4892 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4893 (OR8rm GR8:$src1, addr:$src2)>;
4894 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4895 (OR16rm GR16:$src1, addr:$src2)>;
4896 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4897 (OR32rm GR32:$src1, addr:$src2)>;
4900 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4901 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4902 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4903 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4904 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4905 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4906 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4909 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4910 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4911 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4914 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4915 (XOR8rm GR8:$src1, addr:$src2)>;
4916 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4917 (XOR16rm GR16:$src1, addr:$src2)>;
4918 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4919 (XOR32rm GR32:$src1, addr:$src2)>;
4922 def : Pat<(xor GR8:$src1, imm:$src2),
4923 (XOR8ri GR8:$src1, imm:$src2)>;
4924 def : Pat<(xor GR16:$src1, imm:$src2),
4925 (XOR16ri GR16:$src1, imm:$src2)>;
4926 def : Pat<(xor GR32:$src1, imm:$src2),
4927 (XOR32ri GR32:$src1, imm:$src2)>;
4928 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4929 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4930 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4931 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4934 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4935 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4936 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4939 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4940 (AND8rm GR8:$src1, addr:$src2)>;
4941 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4942 (AND16rm GR16:$src1, addr:$src2)>;
4943 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4944 (AND32rm GR32:$src1, addr:$src2)>;
4947 def : Pat<(and GR8:$src1, imm:$src2),
4948 (AND8ri GR8:$src1, imm:$src2)>;
4949 def : Pat<(and GR16:$src1, imm:$src2),
4950 (AND16ri GR16:$src1, imm:$src2)>;
4951 def : Pat<(and GR32:$src1, imm:$src2),
4952 (AND32ri GR32:$src1, imm:$src2)>;
4953 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4954 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4955 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4956 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4958 //===----------------------------------------------------------------------===//
4959 // Floating Point Stack Support
4960 //===----------------------------------------------------------------------===//
4962 include "X86InstrFPStack.td"
4964 //===----------------------------------------------------------------------===//
4966 //===----------------------------------------------------------------------===//
4968 include "X86Instr64bit.td"
4970 //===----------------------------------------------------------------------===//
4971 // SIMD support (SSE, MMX and AVX)
4972 //===----------------------------------------------------------------------===//
4974 include "X86InstrFragmentsSIMD.td"
4976 //===----------------------------------------------------------------------===//
4977 // FMA - Fused Multiply-Add support (requires FMA)
4978 //===----------------------------------------------------------------------===//
4980 include "X86InstrFMA.td"
4982 //===----------------------------------------------------------------------===//
4983 // XMM Floating point support (requires SSE / SSE2)
4984 //===----------------------------------------------------------------------===//
4986 include "X86InstrSSE.td"
4988 //===----------------------------------------------------------------------===//
4989 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4990 //===----------------------------------------------------------------------===//
4992 include "X86InstrMMX.td"