1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTUnaryArithOvf : SDTypeProfile<1, 1,
32 def SDTBinaryArithOvf : SDTypeProfile<1, 2,
33 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
36 def SDTX86BrCond : SDTypeProfile<0, 3,
37 [SDTCisVT<0, OtherVT>,
38 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
40 def SDTX86SetCC : SDTypeProfile<1, 2,
42 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
46 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
48 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
49 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
50 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
52 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
53 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
56 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
58 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
60 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
62 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
64 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
66 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
68 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
70 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
72 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
73 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
74 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
75 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
77 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
79 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
81 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
82 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
84 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
86 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
87 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
89 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
90 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
92 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
93 [SDNPHasChain, SDNPMayStore,
94 SDNPMayLoad, SDNPMemOperand]>;
95 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
96 [SDNPHasChain, SDNPMayStore,
97 SDNPMayLoad, SDNPMemOperand]>;
98 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
99 [SDNPHasChain, SDNPMayStore,
100 SDNPMayLoad, SDNPMemOperand]>;
101 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
114 [SDNPHasChain, SDNPOptInFlag]>;
116 def X86callseq_start :
117 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
118 [SDNPHasChain, SDNPOutFlag]>;
120 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
123 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
124 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
126 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
127 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
129 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
130 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
131 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
132 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
135 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
136 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
138 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
139 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
141 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
142 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
143 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
145 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
148 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
149 [SDNPHasChain, SDNPOptInFlag]>;
151 def X86add_ovf : SDNode<"X86ISD::ADD", SDTBinaryArithOvf>;
152 def X86sub_ovf : SDNode<"X86ISD::SUB", SDTBinaryArithOvf>;
153 def X86smul_ovf : SDNode<"X86ISD::SMUL", SDTBinaryArithOvf>;
154 def X86umul_ovf : SDNode<"X86ISD::UMUL", SDTUnaryArithOvf>;
156 //===----------------------------------------------------------------------===//
157 // X86 Operand Definitions.
160 // *mem - Operand definitions for the funky X86 addressing mode operands.
162 class X86MemOperand<string printMethod> : Operand<iPTR> {
163 let PrintMethod = printMethod;
164 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
167 def i8mem : X86MemOperand<"printi8mem">;
168 def i16mem : X86MemOperand<"printi16mem">;
169 def i32mem : X86MemOperand<"printi32mem">;
170 def i64mem : X86MemOperand<"printi64mem">;
171 def i128mem : X86MemOperand<"printi128mem">;
172 def f32mem : X86MemOperand<"printf32mem">;
173 def f64mem : X86MemOperand<"printf64mem">;
174 def f80mem : X86MemOperand<"printf80mem">;
175 def f128mem : X86MemOperand<"printf128mem">;
177 def lea32mem : Operand<i32> {
178 let PrintMethod = "printi32mem";
179 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
182 def SSECC : Operand<i8> {
183 let PrintMethod = "printSSECC";
186 def piclabel: Operand<i32> {
187 let PrintMethod = "printPICLabel";
190 // A couple of more descriptive operand definitions.
191 // 16-bits but only 8 bits are significant.
192 def i16i8imm : Operand<i16>;
193 // 32-bits but only 8 bits are significant.
194 def i32i8imm : Operand<i32>;
196 // Branch targets have OtherVT type.
197 def brtarget : Operand<OtherVT>;
199 //===----------------------------------------------------------------------===//
200 // X86 Complex Pattern Definitions.
203 // Define X86 specific addressing mode.
204 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
205 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
206 [add, mul, shl, or, frameindex], []>;
208 //===----------------------------------------------------------------------===//
209 // X86 Instruction Predicate Definitions.
210 def HasMMX : Predicate<"Subtarget->hasMMX()">;
211 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
212 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
213 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
214 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
215 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
216 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
217 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
218 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
219 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
220 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
221 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
222 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
223 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
224 def OptForSpeed : Predicate<"!OptForSize">;
226 //===----------------------------------------------------------------------===//
227 // X86 Instruction Format Definitions.
230 include "X86InstrFormats.td"
232 //===----------------------------------------------------------------------===//
233 // Pattern fragments...
236 // X86 specific condition code. These correspond to CondCode in
237 // X86InstrInfo.h. They must be kept in synch.
238 def X86_COND_A : PatLeaf<(i8 0)>;
239 def X86_COND_AE : PatLeaf<(i8 1)>;
240 def X86_COND_B : PatLeaf<(i8 2)>;
241 def X86_COND_BE : PatLeaf<(i8 3)>;
242 def X86_COND_E : PatLeaf<(i8 4)>;
243 def X86_COND_G : PatLeaf<(i8 5)>;
244 def X86_COND_GE : PatLeaf<(i8 6)>;
245 def X86_COND_L : PatLeaf<(i8 7)>;
246 def X86_COND_LE : PatLeaf<(i8 8)>;
247 def X86_COND_NE : PatLeaf<(i8 9)>;
248 def X86_COND_NO : PatLeaf<(i8 10)>;
249 def X86_COND_NP : PatLeaf<(i8 11)>;
250 def X86_COND_NS : PatLeaf<(i8 12)>;
251 def X86_COND_NC : PatLeaf<(i8 13)>;
252 def X86_COND_O : PatLeaf<(i8 14)>;
253 def X86_COND_P : PatLeaf<(i8 15)>;
254 def X86_COND_S : PatLeaf<(i8 16)>;
255 def X86_COND_C : PatLeaf<(i8 17)>;
257 def i16immSExt8 : PatLeaf<(i16 imm), [{
258 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
259 // sign extended field.
260 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
263 def i32immSExt8 : PatLeaf<(i32 imm), [{
264 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
265 // sign extended field.
266 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
269 // Helper fragments for loads.
270 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
271 // known to be 32-bit aligned or better. Ditto for i8 to i16.
272 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
273 LoadSDNode *LD = cast<LoadSDNode>(N);
274 ISD::LoadExtType ExtType = LD->getExtensionType();
275 if (ExtType == ISD::NON_EXTLOAD)
277 if (ExtType == ISD::EXTLOAD)
278 return LD->getAlignment() >= 2 && !LD->isVolatile();
282 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
283 LoadSDNode *LD = cast<LoadSDNode>(N);
284 ISD::LoadExtType ExtType = LD->getExtensionType();
285 if (ExtType == ISD::EXTLOAD)
286 return LD->getAlignment() >= 2 && !LD->isVolatile();
290 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
291 LoadSDNode *LD = cast<LoadSDNode>(N);
292 ISD::LoadExtType ExtType = LD->getExtensionType();
293 if (ExtType == ISD::NON_EXTLOAD)
295 if (ExtType == ISD::EXTLOAD)
296 return LD->getAlignment() >= 4 && !LD->isVolatile();
300 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
301 LoadSDNode *LD = cast<LoadSDNode>(N);
302 if (LD->isVolatile())
304 ISD::LoadExtType ExtType = LD->getExtensionType();
305 if (ExtType == ISD::NON_EXTLOAD)
307 if (ExtType == ISD::EXTLOAD)
308 return LD->getAlignment() >= 4;
312 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
313 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
315 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
316 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
317 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
319 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
320 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
321 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
323 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
324 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
325 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
326 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
327 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
328 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
330 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
331 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
332 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
333 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
334 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
335 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
338 // An 'and' node with a single use.
339 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
340 return N->hasOneUse();
343 // 'shld' and 'shrd' instruction patterns. Note that even though these have
344 // the srl and shl in their patterns, the C++ code must still check for them,
345 // because predicates are tested before children nodes are explored.
347 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
348 (or (srl node:$src1, node:$amt1),
349 (shl node:$src2, node:$amt2)), [{
350 assert(N->getOpcode() == ISD::OR);
351 return N->getOperand(0).getOpcode() == ISD::SRL &&
352 N->getOperand(1).getOpcode() == ISD::SHL &&
353 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
354 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
355 N->getOperand(0).getConstantOperandVal(1) ==
356 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
359 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
360 (or (shl node:$src1, node:$amt1),
361 (srl node:$src2, node:$amt2)), [{
362 assert(N->getOpcode() == ISD::OR);
363 return N->getOperand(0).getOpcode() == ISD::SHL &&
364 N->getOperand(1).getOpcode() == ISD::SRL &&
365 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
366 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
367 N->getOperand(0).getConstantOperandVal(1) ==
368 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
371 //===----------------------------------------------------------------------===//
372 // Instruction list...
375 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
376 // a stack adjustment and the codegen must know that they may modify the stack
377 // pointer before prolog-epilog rewriting occurs.
378 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
379 // sub / add which can clobber EFLAGS.
380 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
381 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
383 [(X86callseq_start timm:$amt)]>,
384 Requires<[In32BitMode]>;
385 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
387 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
388 Requires<[In32BitMode]>;
392 let neverHasSideEffects = 1 in
393 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
396 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
397 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
398 "call\t$label\n\tpop{l}\t$reg", []>;
400 //===----------------------------------------------------------------------===//
401 // Control Flow Instructions...
404 // Return instructions.
405 let isTerminator = 1, isReturn = 1, isBarrier = 1,
406 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
407 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
410 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
412 [(X86retflag imm:$amt)]>;
415 // All branches are RawFrm, Void, Branch, and Terminators
416 let isBranch = 1, isTerminator = 1 in
417 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
418 I<opcode, RawFrm, (outs), ins, asm, pattern>;
420 let isBranch = 1, isBarrier = 1 in
421 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
424 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
425 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
426 [(brind GR32:$dst)]>;
427 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
428 [(brind (loadi32 addr:$dst))]>;
431 // Conditional branches
432 let Uses = [EFLAGS] in {
433 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
434 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
435 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
436 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
437 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
438 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
439 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
440 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
441 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
442 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
443 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
444 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
446 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
447 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
448 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
449 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
450 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
451 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
452 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
453 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
455 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
456 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
457 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
458 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
459 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
460 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
461 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
462 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
463 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
464 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
465 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
466 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
467 def JC : IBr<0x82, (ins brtarget:$dst), "jc\t$dst",
468 [(X86brcond bb:$dst, X86_COND_C, EFLAGS)]>, TB;
469 def JNC : IBr<0x83, (ins brtarget:$dst), "jnc\t$dst",
470 [(X86brcond bb:$dst, X86_COND_NC, EFLAGS)]>, TB;
473 //===----------------------------------------------------------------------===//
474 // Call Instructions...
477 // All calls clobber the non-callee saved registers. ESP is marked as
478 // a use to prevent stack-pointer assignments that appear immediately
479 // before calls from potentially appearing dead. Uses for argument
480 // registers are added manually.
481 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
482 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
483 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
484 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
486 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
487 "call\t${dst:call}", []>;
488 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
489 "call\t{*}$dst", [(X86call GR32:$dst)]>;
490 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
491 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
496 def TAILCALL : I<0, Pseudo, (outs), (ins),
500 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
501 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
502 "#TC_RETURN $dst $offset",
505 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
506 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
507 "#TC_RETURN $dst $offset",
510 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
512 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
514 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
515 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
517 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
518 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
519 "jmp\t{*}$dst # TAILCALL", []>;
521 //===----------------------------------------------------------------------===//
522 // Miscellaneous Instructions...
524 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
525 def LEAVE : I<0xC9, RawFrm,
526 (outs), (ins), "leave", []>;
528 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
530 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
533 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
536 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
537 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
538 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
539 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
541 let isTwoAddress = 1 in // GR32 = bswap GR32
542 def BSWAP32r : I<0xC8, AddRegFrm,
543 (outs GR32:$dst), (ins GR32:$src),
545 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
548 // Bit scan instructions.
549 let Defs = [EFLAGS] in {
550 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
551 "bsf{w}\t{$src, $dst|$dst, $src}",
552 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
553 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
554 "bsf{w}\t{$src, $dst|$dst, $src}",
555 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
556 (implicit EFLAGS)]>, TB;
557 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
558 "bsf{l}\t{$src, $dst|$dst, $src}",
559 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
560 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
561 "bsf{l}\t{$src, $dst|$dst, $src}",
562 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
563 (implicit EFLAGS)]>, TB;
565 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
566 "bsr{w}\t{$src, $dst|$dst, $src}",
567 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
568 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
569 "bsr{w}\t{$src, $dst|$dst, $src}",
570 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
571 (implicit EFLAGS)]>, TB;
572 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
573 "bsr{l}\t{$src, $dst|$dst, $src}",
574 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
575 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
576 "bsr{l}\t{$src, $dst|$dst, $src}",
577 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
578 (implicit EFLAGS)]>, TB;
581 let neverHasSideEffects = 1 in
582 def LEA16r : I<0x8D, MRMSrcMem,
583 (outs GR16:$dst), (ins i32mem:$src),
584 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
585 let isReMaterializable = 1 in
586 def LEA32r : I<0x8D, MRMSrcMem,
587 (outs GR32:$dst), (ins lea32mem:$src),
588 "lea{l}\t{$src|$dst}, {$dst|$src}",
589 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
591 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
592 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
593 [(X86rep_movs i8)]>, REP;
594 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
595 [(X86rep_movs i16)]>, REP, OpSize;
596 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
597 [(X86rep_movs i32)]>, REP;
600 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
601 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
602 [(X86rep_stos i8)]>, REP;
603 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
604 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
605 [(X86rep_stos i16)]>, REP, OpSize;
606 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
607 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
608 [(X86rep_stos i32)]>, REP;
610 let Defs = [RAX, RDX] in
611 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
614 let isBarrier = 1, hasCtrlDep = 1 in {
615 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
618 //===----------------------------------------------------------------------===//
619 // Input/Output Instructions...
621 let Defs = [AL], Uses = [DX] in
622 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
623 "in{b}\t{%dx, %al|%AL, %DX}", []>;
624 let Defs = [AX], Uses = [DX] in
625 def IN16rr : I<0xED, RawFrm, (outs), (ins),
626 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
627 let Defs = [EAX], Uses = [DX] in
628 def IN32rr : I<0xED, RawFrm, (outs), (ins),
629 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
632 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
633 "in{b}\t{$port, %al|%AL, $port}", []>;
635 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
636 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
638 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
639 "in{l}\t{$port, %eax|%EAX, $port}", []>;
641 let Uses = [DX, AL] in
642 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
643 "out{b}\t{%al, %dx|%DX, %AL}", []>;
644 let Uses = [DX, AX] in
645 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
646 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
647 let Uses = [DX, EAX] in
648 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
649 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
652 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
653 "out{b}\t{%al, $port|$port, %AL}", []>;
655 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
656 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
658 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
659 "out{l}\t{%eax, $port|$port, %EAX}", []>;
661 //===----------------------------------------------------------------------===//
662 // Move Instructions...
664 let neverHasSideEffects = 1 in {
665 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
666 "mov{b}\t{$src, $dst|$dst, $src}", []>;
667 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
668 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
669 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
670 "mov{l}\t{$src, $dst|$dst, $src}", []>;
672 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
673 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
674 "mov{b}\t{$src, $dst|$dst, $src}",
675 [(set GR8:$dst, imm:$src)]>;
676 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
677 "mov{w}\t{$src, $dst|$dst, $src}",
678 [(set GR16:$dst, imm:$src)]>, OpSize;
679 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
680 "mov{l}\t{$src, $dst|$dst, $src}",
681 [(set GR32:$dst, imm:$src)]>;
683 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
684 "mov{b}\t{$src, $dst|$dst, $src}",
685 [(store (i8 imm:$src), addr:$dst)]>;
686 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
687 "mov{w}\t{$src, $dst|$dst, $src}",
688 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
689 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
690 "mov{l}\t{$src, $dst|$dst, $src}",
691 [(store (i32 imm:$src), addr:$dst)]>;
693 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
694 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
695 "mov{b}\t{$src, $dst|$dst, $src}",
696 [(set GR8:$dst, (load addr:$src))]>;
697 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
698 "mov{w}\t{$src, $dst|$dst, $src}",
699 [(set GR16:$dst, (load addr:$src))]>, OpSize;
700 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
701 "mov{l}\t{$src, $dst|$dst, $src}",
702 [(set GR32:$dst, (load addr:$src))]>;
705 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
706 "mov{b}\t{$src, $dst|$dst, $src}",
707 [(store GR8:$src, addr:$dst)]>;
708 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
709 "mov{w}\t{$src, $dst|$dst, $src}",
710 [(store GR16:$src, addr:$dst)]>, OpSize;
711 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
712 "mov{l}\t{$src, $dst|$dst, $src}",
713 [(store GR32:$src, addr:$dst)]>;
715 //===----------------------------------------------------------------------===//
716 // Fixed-Register Multiplication and Division Instructions...
719 // Extra precision multiplication
720 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
721 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
722 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
723 // This probably ought to be moved to a def : Pat<> if the
724 // syntax can be accepted.
725 [(set AL, (mul AL, GR8:$src)),
726 (implicit EFLAGS)]>; // AL,AH = AL*GR8
728 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
729 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
731 []>, OpSize; // AX,DX = AX*GR16
733 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
734 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
736 []>; // EAX,EDX = EAX*GR32
738 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
739 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
741 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
742 // This probably ought to be moved to a def : Pat<> if the
743 // syntax can be accepted.
744 [(set AL, (mul AL, (loadi8 addr:$src))),
745 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
747 let mayLoad = 1, neverHasSideEffects = 1 in {
748 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
749 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
751 []>, OpSize; // AX,DX = AX*[mem16]
753 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
754 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
756 []>; // EAX,EDX = EAX*[mem32]
759 let neverHasSideEffects = 1 in {
760 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
761 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
763 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
764 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
765 OpSize; // AX,DX = AX*GR16
766 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
767 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
768 // EAX,EDX = EAX*GR32
770 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
771 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
772 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
773 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
774 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
775 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
776 let Defs = [EAX,EDX], Uses = [EAX] in
777 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
778 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
780 } // neverHasSideEffects
782 // unsigned division/remainder
783 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
784 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
786 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
787 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
788 "div{w}\t$src", []>, OpSize;
789 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
790 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
793 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
794 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
796 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
797 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
798 "div{w}\t$src", []>, OpSize;
799 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
800 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
804 // Signed division/remainder.
805 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
806 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
807 "idiv{b}\t$src", []>;
808 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
809 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
810 "idiv{w}\t$src", []>, OpSize;
811 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
812 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
813 "idiv{l}\t$src", []>;
814 let mayLoad = 1, mayLoad = 1 in {
815 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
816 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
817 "idiv{b}\t$src", []>;
818 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
819 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
820 "idiv{w}\t$src", []>, OpSize;
821 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
822 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
823 "idiv{l}\t$src", []>;
826 //===----------------------------------------------------------------------===//
827 // Two address Instructions.
829 let isTwoAddress = 1 in {
832 let Uses = [EFLAGS] in {
833 let isCommutable = 1 in {
834 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
835 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
836 "cmovb\t{$src2, $dst|$dst, $src2}",
837 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
838 X86_COND_B, EFLAGS))]>,
840 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
841 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
842 "cmovb\t{$src2, $dst|$dst, $src2}",
843 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
844 X86_COND_B, EFLAGS))]>,
847 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
848 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
849 "cmovae\t{$src2, $dst|$dst, $src2}",
850 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
851 X86_COND_AE, EFLAGS))]>,
853 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
854 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
855 "cmovae\t{$src2, $dst|$dst, $src2}",
856 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
857 X86_COND_AE, EFLAGS))]>,
859 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
860 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
861 "cmove\t{$src2, $dst|$dst, $src2}",
862 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
863 X86_COND_E, EFLAGS))]>,
865 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
866 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
867 "cmove\t{$src2, $dst|$dst, $src2}",
868 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
869 X86_COND_E, EFLAGS))]>,
871 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
872 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
873 "cmovne\t{$src2, $dst|$dst, $src2}",
874 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
875 X86_COND_NE, EFLAGS))]>,
877 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
878 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
879 "cmovne\t{$src2, $dst|$dst, $src2}",
880 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
881 X86_COND_NE, EFLAGS))]>,
883 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
884 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
885 "cmovbe\t{$src2, $dst|$dst, $src2}",
886 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
887 X86_COND_BE, EFLAGS))]>,
889 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
890 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
891 "cmovbe\t{$src2, $dst|$dst, $src2}",
892 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
893 X86_COND_BE, EFLAGS))]>,
895 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
896 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
897 "cmova\t{$src2, $dst|$dst, $src2}",
898 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
899 X86_COND_A, EFLAGS))]>,
901 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
902 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
903 "cmova\t{$src2, $dst|$dst, $src2}",
904 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
905 X86_COND_A, EFLAGS))]>,
907 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
908 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
909 "cmovl\t{$src2, $dst|$dst, $src2}",
910 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
911 X86_COND_L, EFLAGS))]>,
913 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
914 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
915 "cmovl\t{$src2, $dst|$dst, $src2}",
916 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
917 X86_COND_L, EFLAGS))]>,
919 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
920 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
921 "cmovge\t{$src2, $dst|$dst, $src2}",
922 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
923 X86_COND_GE, EFLAGS))]>,
925 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
926 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
927 "cmovge\t{$src2, $dst|$dst, $src2}",
928 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
929 X86_COND_GE, EFLAGS))]>,
931 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
932 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
933 "cmovle\t{$src2, $dst|$dst, $src2}",
934 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
935 X86_COND_LE, EFLAGS))]>,
937 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
938 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
939 "cmovle\t{$src2, $dst|$dst, $src2}",
940 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
941 X86_COND_LE, EFLAGS))]>,
943 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
944 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
945 "cmovg\t{$src2, $dst|$dst, $src2}",
946 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
947 X86_COND_G, EFLAGS))]>,
949 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
950 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
951 "cmovg\t{$src2, $dst|$dst, $src2}",
952 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
953 X86_COND_G, EFLAGS))]>,
955 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
956 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
957 "cmovs\t{$src2, $dst|$dst, $src2}",
958 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
959 X86_COND_S, EFLAGS))]>,
961 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
962 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
963 "cmovs\t{$src2, $dst|$dst, $src2}",
964 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
965 X86_COND_S, EFLAGS))]>,
967 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
968 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
969 "cmovns\t{$src2, $dst|$dst, $src2}",
970 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
971 X86_COND_NS, EFLAGS))]>,
973 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
974 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
975 "cmovns\t{$src2, $dst|$dst, $src2}",
976 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
977 X86_COND_NS, EFLAGS))]>,
979 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
980 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
981 "cmovp\t{$src2, $dst|$dst, $src2}",
982 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
983 X86_COND_P, EFLAGS))]>,
985 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
986 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
987 "cmovp\t{$src2, $dst|$dst, $src2}",
988 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
989 X86_COND_P, EFLAGS))]>,
991 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
992 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
993 "cmovnp\t{$src2, $dst|$dst, $src2}",
994 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
995 X86_COND_NP, EFLAGS))]>,
997 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
998 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
999 "cmovnp\t{$src2, $dst|$dst, $src2}",
1000 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1001 X86_COND_NP, EFLAGS))]>,
1003 } // isCommutable = 1
1005 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1006 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1007 "cmovnp\t{$src2, $dst|$dst, $src2}",
1008 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1009 X86_COND_NP, EFLAGS))]>,
1012 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1013 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1014 "cmovb\t{$src2, $dst|$dst, $src2}",
1015 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1016 X86_COND_B, EFLAGS))]>,
1018 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1019 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1020 "cmovb\t{$src2, $dst|$dst, $src2}",
1021 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1022 X86_COND_B, EFLAGS))]>,
1024 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1025 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1026 "cmovae\t{$src2, $dst|$dst, $src2}",
1027 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1028 X86_COND_AE, EFLAGS))]>,
1030 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1031 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1032 "cmovae\t{$src2, $dst|$dst, $src2}",
1033 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1034 X86_COND_AE, EFLAGS))]>,
1036 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1037 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1038 "cmove\t{$src2, $dst|$dst, $src2}",
1039 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1040 X86_COND_E, EFLAGS))]>,
1042 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1043 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1044 "cmove\t{$src2, $dst|$dst, $src2}",
1045 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1046 X86_COND_E, EFLAGS))]>,
1048 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1049 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1050 "cmovne\t{$src2, $dst|$dst, $src2}",
1051 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1052 X86_COND_NE, EFLAGS))]>,
1054 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1055 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1056 "cmovne\t{$src2, $dst|$dst, $src2}",
1057 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1058 X86_COND_NE, EFLAGS))]>,
1060 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1061 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1062 "cmovbe\t{$src2, $dst|$dst, $src2}",
1063 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1064 X86_COND_BE, EFLAGS))]>,
1066 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1067 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1068 "cmovbe\t{$src2, $dst|$dst, $src2}",
1069 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1070 X86_COND_BE, EFLAGS))]>,
1072 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1073 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1074 "cmova\t{$src2, $dst|$dst, $src2}",
1075 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1076 X86_COND_A, EFLAGS))]>,
1078 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1079 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1080 "cmova\t{$src2, $dst|$dst, $src2}",
1081 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1082 X86_COND_A, EFLAGS))]>,
1084 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1085 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1086 "cmovl\t{$src2, $dst|$dst, $src2}",
1087 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1088 X86_COND_L, EFLAGS))]>,
1090 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1091 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1092 "cmovl\t{$src2, $dst|$dst, $src2}",
1093 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1094 X86_COND_L, EFLAGS))]>,
1096 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1097 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1098 "cmovge\t{$src2, $dst|$dst, $src2}",
1099 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1100 X86_COND_GE, EFLAGS))]>,
1102 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1103 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1104 "cmovge\t{$src2, $dst|$dst, $src2}",
1105 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1106 X86_COND_GE, EFLAGS))]>,
1108 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1109 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1110 "cmovle\t{$src2, $dst|$dst, $src2}",
1111 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1112 X86_COND_LE, EFLAGS))]>,
1114 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1115 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1116 "cmovle\t{$src2, $dst|$dst, $src2}",
1117 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1118 X86_COND_LE, EFLAGS))]>,
1120 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1121 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1122 "cmovg\t{$src2, $dst|$dst, $src2}",
1123 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1124 X86_COND_G, EFLAGS))]>,
1126 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1127 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1128 "cmovg\t{$src2, $dst|$dst, $src2}",
1129 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1130 X86_COND_G, EFLAGS))]>,
1132 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1133 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1134 "cmovs\t{$src2, $dst|$dst, $src2}",
1135 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1136 X86_COND_S, EFLAGS))]>,
1138 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1139 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1140 "cmovs\t{$src2, $dst|$dst, $src2}",
1141 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1142 X86_COND_S, EFLAGS))]>,
1144 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1145 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1146 "cmovns\t{$src2, $dst|$dst, $src2}",
1147 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1148 X86_COND_NS, EFLAGS))]>,
1150 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1151 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1152 "cmovns\t{$src2, $dst|$dst, $src2}",
1153 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1154 X86_COND_NS, EFLAGS))]>,
1156 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1157 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1158 "cmovp\t{$src2, $dst|$dst, $src2}",
1159 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1160 X86_COND_P, EFLAGS))]>,
1162 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1163 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1164 "cmovp\t{$src2, $dst|$dst, $src2}",
1165 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1166 X86_COND_P, EFLAGS))]>,
1168 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1169 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1170 "cmovnp\t{$src2, $dst|$dst, $src2}",
1171 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1172 X86_COND_NP, EFLAGS))]>,
1174 } // Uses = [EFLAGS]
1177 // unary instructions
1178 let CodeSize = 2 in {
1179 let Defs = [EFLAGS] in {
1180 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1181 [(set GR8:$dst, (ineg GR8:$src))]>;
1182 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1183 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1184 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1185 [(set GR32:$dst, (ineg GR32:$src))]>;
1186 let isTwoAddress = 0 in {
1187 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1188 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1189 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1190 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1191 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1192 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1195 } // Defs = [EFLAGS]
1197 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1198 [(set GR8:$dst, (not GR8:$src))]>;
1199 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1200 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1201 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1202 [(set GR32:$dst, (not GR32:$src))]>;
1203 let isTwoAddress = 0 in {
1204 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1205 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1206 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1207 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1208 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1209 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1213 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1214 let Defs = [EFLAGS] in {
1216 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1217 [(set GR8:$dst, (add GR8:$src, 1))]>;
1218 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1219 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1220 [(set GR16:$dst, (add GR16:$src, 1))]>,
1221 OpSize, Requires<[In32BitMode]>;
1222 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1223 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1225 let isTwoAddress = 0, CodeSize = 2 in {
1226 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1227 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1228 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1229 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1230 OpSize, Requires<[In32BitMode]>;
1231 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1232 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1233 Requires<[In32BitMode]>;
1237 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1238 [(set GR8:$dst, (add GR8:$src, -1))]>;
1239 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1240 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1241 [(set GR16:$dst, (add GR16:$src, -1))]>,
1242 OpSize, Requires<[In32BitMode]>;
1243 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1244 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1247 let isTwoAddress = 0, CodeSize = 2 in {
1248 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1249 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1250 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1251 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1252 OpSize, Requires<[In32BitMode]>;
1253 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1254 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1255 Requires<[In32BitMode]>;
1257 } // Defs = [EFLAGS]
1259 // Logical operators...
1260 let Defs = [EFLAGS] in {
1261 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1262 def AND8rr : I<0x20, MRMDestReg,
1263 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1264 "and{b}\t{$src2, $dst|$dst, $src2}",
1265 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1266 def AND16rr : I<0x21, MRMDestReg,
1267 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1268 "and{w}\t{$src2, $dst|$dst, $src2}",
1269 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1270 def AND32rr : I<0x21, MRMDestReg,
1271 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1272 "and{l}\t{$src2, $dst|$dst, $src2}",
1273 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1276 def AND8rm : I<0x22, MRMSrcMem,
1277 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1278 "and{b}\t{$src2, $dst|$dst, $src2}",
1279 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1280 def AND16rm : I<0x23, MRMSrcMem,
1281 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1282 "and{w}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1284 def AND32rm : I<0x23, MRMSrcMem,
1285 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1286 "and{l}\t{$src2, $dst|$dst, $src2}",
1287 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1289 def AND8ri : Ii8<0x80, MRM4r,
1290 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1291 "and{b}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1293 def AND16ri : Ii16<0x81, MRM4r,
1294 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1295 "and{w}\t{$src2, $dst|$dst, $src2}",
1296 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1297 def AND32ri : Ii32<0x81, MRM4r,
1298 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1299 "and{l}\t{$src2, $dst|$dst, $src2}",
1300 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1301 def AND16ri8 : Ii8<0x83, MRM4r,
1302 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1303 "and{w}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1306 def AND32ri8 : Ii8<0x83, MRM4r,
1307 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1308 "and{l}\t{$src2, $dst|$dst, $src2}",
1309 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1311 let isTwoAddress = 0 in {
1312 def AND8mr : I<0x20, MRMDestMem,
1313 (outs), (ins i8mem :$dst, GR8 :$src),
1314 "and{b}\t{$src, $dst|$dst, $src}",
1315 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1316 def AND16mr : I<0x21, MRMDestMem,
1317 (outs), (ins i16mem:$dst, GR16:$src),
1318 "and{w}\t{$src, $dst|$dst, $src}",
1319 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1321 def AND32mr : I<0x21, MRMDestMem,
1322 (outs), (ins i32mem:$dst, GR32:$src),
1323 "and{l}\t{$src, $dst|$dst, $src}",
1324 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1325 def AND8mi : Ii8<0x80, MRM4m,
1326 (outs), (ins i8mem :$dst, i8imm :$src),
1327 "and{b}\t{$src, $dst|$dst, $src}",
1328 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1329 def AND16mi : Ii16<0x81, MRM4m,
1330 (outs), (ins i16mem:$dst, i16imm:$src),
1331 "and{w}\t{$src, $dst|$dst, $src}",
1332 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1334 def AND32mi : Ii32<0x81, MRM4m,
1335 (outs), (ins i32mem:$dst, i32imm:$src),
1336 "and{l}\t{$src, $dst|$dst, $src}",
1337 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1338 def AND16mi8 : Ii8<0x83, MRM4m,
1339 (outs), (ins i16mem:$dst, i16i8imm :$src),
1340 "and{w}\t{$src, $dst|$dst, $src}",
1341 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1343 def AND32mi8 : Ii8<0x83, MRM4m,
1344 (outs), (ins i32mem:$dst, i32i8imm :$src),
1345 "and{l}\t{$src, $dst|$dst, $src}",
1346 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1350 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1351 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1352 "or{b}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1354 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1355 "or{w}\t{$src2, $dst|$dst, $src2}",
1356 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1357 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1358 "or{l}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1361 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1362 "or{b}\t{$src2, $dst|$dst, $src2}",
1363 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1364 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1365 "or{w}\t{$src2, $dst|$dst, $src2}",
1366 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1367 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1368 "or{l}\t{$src2, $dst|$dst, $src2}",
1369 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1371 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1372 "or{b}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1374 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1375 "or{w}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1377 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1378 "or{l}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1381 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1382 "or{w}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1384 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1385 "or{l}\t{$src2, $dst|$dst, $src2}",
1386 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1387 let isTwoAddress = 0 in {
1388 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1389 "or{b}\t{$src, $dst|$dst, $src}",
1390 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1391 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1392 "or{w}\t{$src, $dst|$dst, $src}",
1393 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1394 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1395 "or{l}\t{$src, $dst|$dst, $src}",
1396 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1397 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1398 "or{b}\t{$src, $dst|$dst, $src}",
1399 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1400 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1401 "or{w}\t{$src, $dst|$dst, $src}",
1402 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1404 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1405 "or{l}\t{$src, $dst|$dst, $src}",
1406 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1407 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1408 "or{w}\t{$src, $dst|$dst, $src}",
1409 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1411 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1412 "or{l}\t{$src, $dst|$dst, $src}",
1413 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1414 } // isTwoAddress = 0
1417 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1418 def XOR8rr : I<0x30, MRMDestReg,
1419 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1420 "xor{b}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1422 def XOR16rr : I<0x31, MRMDestReg,
1423 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1424 "xor{w}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1426 def XOR32rr : I<0x31, MRMDestReg,
1427 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1428 "xor{l}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1430 } // isCommutable = 1
1432 def XOR8rm : I<0x32, MRMSrcMem ,
1433 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1434 "xor{b}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1436 def XOR16rm : I<0x33, MRMSrcMem ,
1437 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1438 "xor{w}\t{$src2, $dst|$dst, $src2}",
1439 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>,
1441 def XOR32rm : I<0x33, MRMSrcMem ,
1442 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1443 "xor{l}\t{$src2, $dst|$dst, $src2}",
1444 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1446 def XOR8ri : Ii8<0x80, MRM6r,
1447 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1448 "xor{b}\t{$src2, $dst|$dst, $src2}",
1449 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1450 def XOR16ri : Ii16<0x81, MRM6r,
1451 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1452 "xor{w}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1454 def XOR32ri : Ii32<0x81, MRM6r,
1455 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1456 "xor{l}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1458 def XOR16ri8 : Ii8<0x83, MRM6r,
1459 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1460 "xor{w}\t{$src2, $dst|$dst, $src2}",
1461 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1463 def XOR32ri8 : Ii8<0x83, MRM6r,
1464 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1465 "xor{l}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1468 let isTwoAddress = 0 in {
1469 def XOR8mr : I<0x30, MRMDestMem,
1470 (outs), (ins i8mem :$dst, GR8 :$src),
1471 "xor{b}\t{$src, $dst|$dst, $src}",
1472 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1473 def XOR16mr : I<0x31, MRMDestMem,
1474 (outs), (ins i16mem:$dst, GR16:$src),
1475 "xor{w}\t{$src, $dst|$dst, $src}",
1476 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1478 def XOR32mr : I<0x31, MRMDestMem,
1479 (outs), (ins i32mem:$dst, GR32:$src),
1480 "xor{l}\t{$src, $dst|$dst, $src}",
1481 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1482 def XOR8mi : Ii8<0x80, MRM6m,
1483 (outs), (ins i8mem :$dst, i8imm :$src),
1484 "xor{b}\t{$src, $dst|$dst, $src}",
1485 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1486 def XOR16mi : Ii16<0x81, MRM6m,
1487 (outs), (ins i16mem:$dst, i16imm:$src),
1488 "xor{w}\t{$src, $dst|$dst, $src}",
1489 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1491 def XOR32mi : Ii32<0x81, MRM6m,
1492 (outs), (ins i32mem:$dst, i32imm:$src),
1493 "xor{l}\t{$src, $dst|$dst, $src}",
1494 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1495 def XOR16mi8 : Ii8<0x83, MRM6m,
1496 (outs), (ins i16mem:$dst, i16i8imm :$src),
1497 "xor{w}\t{$src, $dst|$dst, $src}",
1498 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1500 def XOR32mi8 : Ii8<0x83, MRM6m,
1501 (outs), (ins i32mem:$dst, i32i8imm :$src),
1502 "xor{l}\t{$src, $dst|$dst, $src}",
1503 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1504 } // isTwoAddress = 0
1505 } // Defs = [EFLAGS]
1507 // Shift instructions
1508 let Defs = [EFLAGS] in {
1509 let Uses = [CL] in {
1510 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1511 "shl{b}\t{%cl, $dst|$dst, %CL}",
1512 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1513 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1514 "shl{w}\t{%cl, $dst|$dst, %CL}",
1515 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1516 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1517 "shl{l}\t{%cl, $dst|$dst, %CL}",
1518 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1521 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1522 "shl{b}\t{$src2, $dst|$dst, $src2}",
1523 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1524 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1525 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1526 "shl{w}\t{$src2, $dst|$dst, $src2}",
1527 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1528 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1529 "shl{l}\t{$src2, $dst|$dst, $src2}",
1530 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1531 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1533 } // isConvertibleToThreeAddress = 1
1535 let isTwoAddress = 0 in {
1536 let Uses = [CL] in {
1537 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1538 "shl{b}\t{%cl, $dst|$dst, %CL}",
1539 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1540 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1541 "shl{w}\t{%cl, $dst|$dst, %CL}",
1542 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1543 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1544 "shl{l}\t{%cl, $dst|$dst, %CL}",
1545 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1547 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1548 "shl{b}\t{$src, $dst|$dst, $src}",
1549 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1550 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1551 "shl{w}\t{$src, $dst|$dst, $src}",
1552 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1554 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1555 "shl{l}\t{$src, $dst|$dst, $src}",
1556 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1559 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1561 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1562 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1564 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1566 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1568 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1571 let Uses = [CL] in {
1572 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1573 "shr{b}\t{%cl, $dst|$dst, %CL}",
1574 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1575 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1576 "shr{w}\t{%cl, $dst|$dst, %CL}",
1577 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1578 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1579 "shr{l}\t{%cl, $dst|$dst, %CL}",
1580 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1583 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1584 "shr{b}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1586 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1587 "shr{w}\t{$src2, $dst|$dst, $src2}",
1588 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1589 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1590 "shr{l}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1594 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1596 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1597 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1599 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1600 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1602 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1604 let isTwoAddress = 0 in {
1605 let Uses = [CL] in {
1606 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1607 "shr{b}\t{%cl, $dst|$dst, %CL}",
1608 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1609 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1610 "shr{w}\t{%cl, $dst|$dst, %CL}",
1611 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1613 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1614 "shr{l}\t{%cl, $dst|$dst, %CL}",
1615 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1617 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1618 "shr{b}\t{$src, $dst|$dst, $src}",
1619 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1620 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1621 "shr{w}\t{$src, $dst|$dst, $src}",
1622 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1624 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1625 "shr{l}\t{$src, $dst|$dst, $src}",
1626 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1629 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1631 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1632 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1634 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1635 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1637 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1640 let Uses = [CL] in {
1641 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1642 "sar{b}\t{%cl, $dst|$dst, %CL}",
1643 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1644 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1645 "sar{w}\t{%cl, $dst|$dst, %CL}",
1646 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1647 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1648 "sar{l}\t{%cl, $dst|$dst, %CL}",
1649 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1652 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1653 "sar{b}\t{$src2, $dst|$dst, $src2}",
1654 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1655 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1656 "sar{w}\t{$src2, $dst|$dst, $src2}",
1657 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1659 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1660 "sar{l}\t{$src2, $dst|$dst, $src2}",
1661 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1664 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1666 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1667 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1669 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1670 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1672 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1674 let isTwoAddress = 0 in {
1675 let Uses = [CL] in {
1676 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1677 "sar{b}\t{%cl, $dst|$dst, %CL}",
1678 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1679 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1680 "sar{w}\t{%cl, $dst|$dst, %CL}",
1681 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1682 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1683 "sar{l}\t{%cl, $dst|$dst, %CL}",
1684 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1686 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1687 "sar{b}\t{$src, $dst|$dst, $src}",
1688 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1689 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1690 "sar{w}\t{$src, $dst|$dst, $src}",
1691 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1693 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1694 "sar{l}\t{$src, $dst|$dst, $src}",
1695 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1698 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1700 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1701 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1703 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1705 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1707 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1710 // Rotate instructions
1711 // FIXME: provide shorter instructions when imm8 == 1
1712 let Uses = [CL] in {
1713 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1714 "rol{b}\t{%cl, $dst|$dst, %CL}",
1715 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1716 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1717 "rol{w}\t{%cl, $dst|$dst, %CL}",
1718 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1719 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1720 "rol{l}\t{%cl, $dst|$dst, %CL}",
1721 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1724 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1725 "rol{b}\t{$src2, $dst|$dst, $src2}",
1726 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1727 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1728 "rol{w}\t{$src2, $dst|$dst, $src2}",
1729 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1730 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1731 "rol{l}\t{$src2, $dst|$dst, $src2}",
1732 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1735 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1737 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1738 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1740 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1741 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1743 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1745 let isTwoAddress = 0 in {
1746 let Uses = [CL] in {
1747 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1748 "rol{b}\t{%cl, $dst|$dst, %CL}",
1749 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1750 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1751 "rol{w}\t{%cl, $dst|$dst, %CL}",
1752 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1753 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1754 "rol{l}\t{%cl, $dst|$dst, %CL}",
1755 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1757 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1758 "rol{b}\t{$src, $dst|$dst, $src}",
1759 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1760 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1761 "rol{w}\t{$src, $dst|$dst, $src}",
1762 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1764 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1765 "rol{l}\t{$src, $dst|$dst, $src}",
1766 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1769 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1771 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1772 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1774 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1776 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1778 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1781 let Uses = [CL] in {
1782 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1783 "ror{b}\t{%cl, $dst|$dst, %CL}",
1784 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1785 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1786 "ror{w}\t{%cl, $dst|$dst, %CL}",
1787 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1788 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1789 "ror{l}\t{%cl, $dst|$dst, %CL}",
1790 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1793 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1794 "ror{b}\t{$src2, $dst|$dst, $src2}",
1795 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1796 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1797 "ror{w}\t{$src2, $dst|$dst, $src2}",
1798 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1799 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1800 "ror{l}\t{$src2, $dst|$dst, $src2}",
1801 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1804 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1806 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1807 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1809 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1810 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1812 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1814 let isTwoAddress = 0 in {
1815 let Uses = [CL] in {
1816 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1817 "ror{b}\t{%cl, $dst|$dst, %CL}",
1818 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1819 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1820 "ror{w}\t{%cl, $dst|$dst, %CL}",
1821 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1822 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1823 "ror{l}\t{%cl, $dst|$dst, %CL}",
1824 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1826 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1827 "ror{b}\t{$src, $dst|$dst, $src}",
1828 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1829 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1830 "ror{w}\t{$src, $dst|$dst, $src}",
1831 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1833 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1834 "ror{l}\t{$src, $dst|$dst, $src}",
1835 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1838 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1840 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1841 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1843 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1845 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1847 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1852 // Double shift instructions (generalizations of rotate)
1853 let Uses = [CL] in {
1854 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1855 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1856 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1857 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1858 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1859 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1860 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1861 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1862 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1864 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1865 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1866 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1870 let isCommutable = 1 in { // These instructions commute to each other.
1871 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1872 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1873 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1874 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1877 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1878 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1879 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1880 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1883 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1884 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1885 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1886 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1889 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1890 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1891 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1892 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1897 let isTwoAddress = 0 in {
1898 let Uses = [CL] in {
1899 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1900 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1901 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1903 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1904 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1905 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1908 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1909 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1910 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1911 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1912 (i8 imm:$src3)), addr:$dst)]>,
1914 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1915 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1916 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1917 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1918 (i8 imm:$src3)), addr:$dst)]>,
1921 let Uses = [CL] in {
1922 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1923 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1924 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1925 addr:$dst)]>, TB, OpSize;
1926 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1927 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1928 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1929 addr:$dst)]>, TB, OpSize;
1931 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1932 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1933 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1934 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1935 (i8 imm:$src3)), addr:$dst)]>,
1937 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1938 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1939 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1940 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1941 (i8 imm:$src3)), addr:$dst)]>,
1944 } // Defs = [EFLAGS]
1948 let Defs = [EFLAGS] in {
1949 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1950 // Register-Register Addition
1951 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1952 (ins GR8 :$src1, GR8 :$src2),
1953 "add{b}\t{$src2, $dst|$dst, $src2}",
1954 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
1955 (implicit EFLAGS)]>;
1957 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1958 // Register-Register Addition
1959 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1960 (ins GR16:$src1, GR16:$src2),
1961 "add{w}\t{$src2, $dst|$dst, $src2}",
1962 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
1963 (implicit EFLAGS)]>, OpSize;
1964 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1965 (ins GR32:$src1, GR32:$src2),
1966 "add{l}\t{$src2, $dst|$dst, $src2}",
1967 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
1968 (implicit EFLAGS)]>;
1969 } // end isConvertibleToThreeAddress
1970 } // end isCommutable
1972 // Register-Memory Addition
1973 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1974 (ins GR8 :$src1, i8mem :$src2),
1975 "add{b}\t{$src2, $dst|$dst, $src2}",
1976 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
1977 (implicit EFLAGS)]>;
1978 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1979 (ins GR16:$src1, i16mem:$src2),
1980 "add{w}\t{$src2, $dst|$dst, $src2}",
1981 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
1982 (implicit EFLAGS)]>, OpSize;
1983 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1984 (ins GR32:$src1, i32mem:$src2),
1985 "add{l}\t{$src2, $dst|$dst, $src2}",
1986 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
1987 (implicit EFLAGS)]>;
1989 // Register-Integer Addition
1990 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1991 "add{b}\t{$src2, $dst|$dst, $src2}",
1992 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
1993 (implicit EFLAGS)]>;
1995 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1996 // Register-Integer Addition
1997 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1998 (ins GR16:$src1, i16imm:$src2),
1999 "add{w}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2001 (implicit EFLAGS)]>, OpSize;
2002 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2003 (ins GR32:$src1, i32imm:$src2),
2004 "add{l}\t{$src2, $dst|$dst, $src2}",
2005 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2006 (implicit EFLAGS)]>;
2007 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2008 (ins GR16:$src1, i16i8imm:$src2),
2009 "add{w}\t{$src2, $dst|$dst, $src2}",
2010 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2011 (implicit EFLAGS)]>, OpSize;
2012 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2013 (ins GR32:$src1, i32i8imm:$src2),
2014 "add{l}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2016 (implicit EFLAGS)]>;
2019 let isTwoAddress = 0 in {
2020 // Memory-Register Addition
2021 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2022 "add{b}\t{$src2, $dst|$dst, $src2}",
2023 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2024 (implicit EFLAGS)]>;
2025 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2026 "add{w}\t{$src2, $dst|$dst, $src2}",
2027 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2028 (implicit EFLAGS)]>, OpSize;
2029 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2030 "add{l}\t{$src2, $dst|$dst, $src2}",
2031 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2032 (implicit EFLAGS)]>;
2033 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2034 "add{b}\t{$src2, $dst|$dst, $src2}",
2035 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2036 (implicit EFLAGS)]>;
2037 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2038 "add{w}\t{$src2, $dst|$dst, $src2}",
2039 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2040 (implicit EFLAGS)]>, OpSize;
2041 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2042 "add{l}\t{$src2, $dst|$dst, $src2}",
2043 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2044 (implicit EFLAGS)]>;
2045 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2046 "add{w}\t{$src2, $dst|$dst, $src2}",
2047 [(store (add (load addr:$dst), i16immSExt8:$src2),
2049 (implicit EFLAGS)]>, OpSize;
2050 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2051 "add{l}\t{$src2, $dst|$dst, $src2}",
2052 [(store (add (load addr:$dst), i32immSExt8:$src2),
2054 (implicit EFLAGS)]>;
2057 let Uses = [EFLAGS] in {
2058 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2059 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2060 "adc{l}\t{$src2, $dst|$dst, $src2}",
2061 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2063 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2064 "adc{l}\t{$src2, $dst|$dst, $src2}",
2065 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2066 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2067 "adc{l}\t{$src2, $dst|$dst, $src2}",
2068 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2069 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2070 "adc{l}\t{$src2, $dst|$dst, $src2}",
2071 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2073 let isTwoAddress = 0 in {
2074 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2075 "adc{l}\t{$src2, $dst|$dst, $src2}",
2076 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2077 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2078 "adc{l}\t{$src2, $dst|$dst, $src2}",
2079 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2080 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2081 "adc{l}\t{$src2, $dst|$dst, $src2}",
2082 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2084 } // Uses = [EFLAGS]
2086 // Register-Register Subtraction
2087 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2088 "sub{b}\t{$src2, $dst|$dst, $src2}",
2089 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2090 (implicit EFLAGS)]>;
2091 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2092 "sub{w}\t{$src2, $dst|$dst, $src2}",
2093 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2094 (implicit EFLAGS)]>, OpSize;
2095 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2096 "sub{l}\t{$src2, $dst|$dst, $src2}",
2097 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2098 (implicit EFLAGS)]>;
2100 // Register-Memory Subtraction
2101 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2102 (ins GR8 :$src1, i8mem :$src2),
2103 "sub{b}\t{$src2, $dst|$dst, $src2}",
2104 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2105 (implicit EFLAGS)]>;
2106 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2107 (ins GR16:$src1, i16mem:$src2),
2108 "sub{w}\t{$src2, $dst|$dst, $src2}",
2109 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2110 (implicit EFLAGS)]>, OpSize;
2111 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2112 (ins GR32:$src1, i32mem:$src2),
2113 "sub{l}\t{$src2, $dst|$dst, $src2}",
2114 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2115 (implicit EFLAGS)]>;
2117 // Register-Integer Subtraction
2118 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2119 (ins GR8:$src1, i8imm:$src2),
2120 "sub{b}\t{$src2, $dst|$dst, $src2}",
2121 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2122 (implicit EFLAGS)]>;
2123 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2124 (ins GR16:$src1, i16imm:$src2),
2125 "sub{w}\t{$src2, $dst|$dst, $src2}",
2126 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2127 (implicit EFLAGS)]>, OpSize;
2128 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2129 (ins GR32:$src1, i32imm:$src2),
2130 "sub{l}\t{$src2, $dst|$dst, $src2}",
2131 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2132 (implicit EFLAGS)]>;
2133 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2134 (ins GR16:$src1, i16i8imm:$src2),
2135 "sub{w}\t{$src2, $dst|$dst, $src2}",
2136 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2137 (implicit EFLAGS)]>, OpSize;
2138 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2139 (ins GR32:$src1, i32i8imm:$src2),
2140 "sub{l}\t{$src2, $dst|$dst, $src2}",
2141 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2142 (implicit EFLAGS)]>;
2144 let isTwoAddress = 0 in {
2145 // Memory-Register Subtraction
2146 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2147 "sub{b}\t{$src2, $dst|$dst, $src2}",
2148 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2149 (implicit EFLAGS)]>;
2150 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2151 "sub{w}\t{$src2, $dst|$dst, $src2}",
2152 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2153 (implicit EFLAGS)]>, OpSize;
2154 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2155 "sub{l}\t{$src2, $dst|$dst, $src2}",
2156 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2157 (implicit EFLAGS)]>;
2159 // Memory-Integer Subtraction
2160 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2161 "sub{b}\t{$src2, $dst|$dst, $src2}",
2162 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2163 (implicit EFLAGS)]>;
2164 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2165 "sub{w}\t{$src2, $dst|$dst, $src2}",
2166 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2167 (implicit EFLAGS)]>, OpSize;
2168 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2169 "sub{l}\t{$src2, $dst|$dst, $src2}",
2170 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2171 (implicit EFLAGS)]>;
2172 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2173 "sub{w}\t{$src2, $dst|$dst, $src2}",
2174 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2176 (implicit EFLAGS)]>, OpSize;
2177 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2178 "sub{l}\t{$src2, $dst|$dst, $src2}",
2179 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2181 (implicit EFLAGS)]>;
2184 let Uses = [EFLAGS] in {
2185 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2186 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2187 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2189 let isTwoAddress = 0 in {
2190 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2191 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2192 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2193 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2194 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2195 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2196 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2197 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2198 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2199 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2200 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2201 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2203 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2204 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2205 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2206 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2207 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2208 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2209 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2210 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2211 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2212 } // Uses = [EFLAGS]
2213 } // Defs = [EFLAGS]
2215 let Defs = [EFLAGS] in {
2216 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2217 // Register-Register Signed Integer Multiply
2218 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2219 "imul{w}\t{$src2, $dst|$dst, $src2}",
2220 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2221 (implicit EFLAGS)]>, TB, OpSize;
2222 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2223 "imul{l}\t{$src2, $dst|$dst, $src2}",
2224 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2225 (implicit EFLAGS)]>, TB;
2228 // Register-Memory Signed Integer Multiply
2229 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2230 (ins GR16:$src1, i16mem:$src2),
2231 "imul{w}\t{$src2, $dst|$dst, $src2}",
2232 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2233 (implicit EFLAGS)]>, TB, OpSize;
2234 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2235 "imul{l}\t{$src2, $dst|$dst, $src2}",
2236 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2237 (implicit EFLAGS)]>, TB;
2238 } // Defs = [EFLAGS]
2239 } // end Two Address instructions
2241 // Suprisingly enough, these are not two address instructions!
2242 let Defs = [EFLAGS] in {
2243 // Register-Integer Signed Integer Multiply
2244 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2245 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2246 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2247 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2248 (implicit EFLAGS)]>, OpSize;
2249 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2250 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2251 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2252 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2253 (implicit EFLAGS)]>;
2254 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2255 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2256 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2257 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2258 (implicit EFLAGS)]>, OpSize;
2259 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2260 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2261 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2262 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2263 (implicit EFLAGS)]>;
2265 // Memory-Integer Signed Integer Multiply
2266 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2267 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2268 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2269 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2270 (implicit EFLAGS)]>, OpSize;
2271 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2272 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2273 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2274 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2275 (implicit EFLAGS)]>;
2276 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2277 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2278 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2279 [(set GR16:$dst, (mul (load addr:$src1),
2280 i16immSExt8:$src2)),
2281 (implicit EFLAGS)]>, OpSize;
2282 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2283 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2284 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2285 [(set GR32:$dst, (mul (load addr:$src1),
2286 i32immSExt8:$src2)),
2287 (implicit EFLAGS)]>;
2288 } // Defs = [EFLAGS]
2290 //===----------------------------------------------------------------------===//
2291 // Test instructions are just like AND, except they don't generate a result.
2293 let Defs = [EFLAGS] in {
2294 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2295 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2296 "test{b}\t{$src2, $src1|$src1, $src2}",
2297 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2298 (implicit EFLAGS)]>;
2299 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2300 "test{w}\t{$src2, $src1|$src1, $src2}",
2301 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2302 (implicit EFLAGS)]>,
2304 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2305 "test{l}\t{$src2, $src1|$src1, $src2}",
2306 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2307 (implicit EFLAGS)]>;
2310 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2311 "test{b}\t{$src2, $src1|$src1, $src2}",
2312 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2313 (implicit EFLAGS)]>;
2314 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2315 "test{w}\t{$src2, $src1|$src1, $src2}",
2316 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2317 (implicit EFLAGS)]>, OpSize;
2318 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2319 "test{l}\t{$src2, $src1|$src1, $src2}",
2320 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2321 (implicit EFLAGS)]>;
2323 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2324 (outs), (ins GR8:$src1, i8imm:$src2),
2325 "test{b}\t{$src2, $src1|$src1, $src2}",
2326 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2327 (implicit EFLAGS)]>;
2328 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2329 (outs), (ins GR16:$src1, i16imm:$src2),
2330 "test{w}\t{$src2, $src1|$src1, $src2}",
2331 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2332 (implicit EFLAGS)]>, OpSize;
2333 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2334 (outs), (ins GR32:$src1, i32imm:$src2),
2335 "test{l}\t{$src2, $src1|$src1, $src2}",
2336 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2337 (implicit EFLAGS)]>;
2339 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2340 (outs), (ins i8mem:$src1, i8imm:$src2),
2341 "test{b}\t{$src2, $src1|$src1, $src2}",
2342 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2343 (implicit EFLAGS)]>;
2344 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2345 (outs), (ins i16mem:$src1, i16imm:$src2),
2346 "test{w}\t{$src2, $src1|$src1, $src2}",
2347 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2348 (implicit EFLAGS)]>, OpSize;
2349 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2350 (outs), (ins i32mem:$src1, i32imm:$src2),
2351 "test{l}\t{$src2, $src1|$src1, $src2}",
2352 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2353 (implicit EFLAGS)]>;
2354 } // Defs = [EFLAGS]
2357 // Condition code ops, incl. set if equal/not equal/...
2358 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2359 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2360 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2361 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2363 let Uses = [EFLAGS] in {
2364 def SETEr : I<0x94, MRM0r,
2365 (outs GR8 :$dst), (ins),
2367 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2369 def SETEm : I<0x94, MRM0m,
2370 (outs), (ins i8mem:$dst),
2372 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2375 def SETNEr : I<0x95, MRM0r,
2376 (outs GR8 :$dst), (ins),
2378 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2380 def SETNEm : I<0x95, MRM0m,
2381 (outs), (ins i8mem:$dst),
2383 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2386 def SETLr : I<0x9C, MRM0r,
2387 (outs GR8 :$dst), (ins),
2389 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2390 TB; // GR8 = < signed
2391 def SETLm : I<0x9C, MRM0m,
2392 (outs), (ins i8mem:$dst),
2394 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2395 TB; // [mem8] = < signed
2397 def SETGEr : I<0x9D, MRM0r,
2398 (outs GR8 :$dst), (ins),
2400 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2401 TB; // GR8 = >= signed
2402 def SETGEm : I<0x9D, MRM0m,
2403 (outs), (ins i8mem:$dst),
2405 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2406 TB; // [mem8] = >= signed
2408 def SETLEr : I<0x9E, MRM0r,
2409 (outs GR8 :$dst), (ins),
2411 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2412 TB; // GR8 = <= signed
2413 def SETLEm : I<0x9E, MRM0m,
2414 (outs), (ins i8mem:$dst),
2416 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2417 TB; // [mem8] = <= signed
2419 def SETGr : I<0x9F, MRM0r,
2420 (outs GR8 :$dst), (ins),
2422 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2423 TB; // GR8 = > signed
2424 def SETGm : I<0x9F, MRM0m,
2425 (outs), (ins i8mem:$dst),
2427 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2428 TB; // [mem8] = > signed
2430 def SETBr : I<0x92, MRM0r,
2431 (outs GR8 :$dst), (ins),
2433 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2434 TB; // GR8 = < unsign
2435 def SETBm : I<0x92, MRM0m,
2436 (outs), (ins i8mem:$dst),
2438 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2439 TB; // [mem8] = < unsign
2441 def SETAEr : I<0x93, MRM0r,
2442 (outs GR8 :$dst), (ins),
2444 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2445 TB; // GR8 = >= unsign
2446 def SETAEm : I<0x93, MRM0m,
2447 (outs), (ins i8mem:$dst),
2449 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2450 TB; // [mem8] = >= unsign
2452 def SETBEr : I<0x96, MRM0r,
2453 (outs GR8 :$dst), (ins),
2455 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2456 TB; // GR8 = <= unsign
2457 def SETBEm : I<0x96, MRM0m,
2458 (outs), (ins i8mem:$dst),
2460 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2461 TB; // [mem8] = <= unsign
2463 def SETAr : I<0x97, MRM0r,
2464 (outs GR8 :$dst), (ins),
2466 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2467 TB; // GR8 = > signed
2468 def SETAm : I<0x97, MRM0m,
2469 (outs), (ins i8mem:$dst),
2471 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2472 TB; // [mem8] = > signed
2474 def SETSr : I<0x98, MRM0r,
2475 (outs GR8 :$dst), (ins),
2477 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2478 TB; // GR8 = <sign bit>
2479 def SETSm : I<0x98, MRM0m,
2480 (outs), (ins i8mem:$dst),
2482 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2483 TB; // [mem8] = <sign bit>
2484 def SETNSr : I<0x99, MRM0r,
2485 (outs GR8 :$dst), (ins),
2487 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2488 TB; // GR8 = !<sign bit>
2489 def SETNSm : I<0x99, MRM0m,
2490 (outs), (ins i8mem:$dst),
2492 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2493 TB; // [mem8] = !<sign bit>
2495 def SETPr : I<0x9A, MRM0r,
2496 (outs GR8 :$dst), (ins),
2498 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2500 def SETPm : I<0x9A, MRM0m,
2501 (outs), (ins i8mem:$dst),
2503 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2504 TB; // [mem8] = parity
2505 def SETNPr : I<0x9B, MRM0r,
2506 (outs GR8 :$dst), (ins),
2508 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2509 TB; // GR8 = not parity
2510 def SETNPm : I<0x9B, MRM0m,
2511 (outs), (ins i8mem:$dst),
2513 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2514 TB; // [mem8] = not parity
2516 def SETOr : I<0x90, MRM0r,
2517 (outs GR8 :$dst), (ins),
2519 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2520 TB; // GR8 = overflow
2521 def SETOm : I<0x90, MRM0m,
2522 (outs), (ins i8mem:$dst),
2524 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2525 TB; // [mem8] = overflow
2526 def SETNOr : I<0x91, MRM0r,
2527 (outs GR8 :$dst), (ins),
2529 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2530 TB; // GR8 = not overflow
2531 def SETNOm : I<0x91, MRM0m,
2532 (outs), (ins i8mem:$dst),
2534 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2535 TB; // [mem8] = not overflow
2537 def SETCr : I<0x92, MRM0r,
2538 (outs GR8 :$dst), (ins),
2540 [(set GR8:$dst, (X86setcc X86_COND_C, EFLAGS))]>,
2542 def SETCm : I<0x92, MRM0m,
2543 (outs), (ins i8mem:$dst),
2545 [(store (X86setcc X86_COND_C, EFLAGS), addr:$dst)]>,
2546 TB; // [mem8] = carry
2547 def SETNCr : I<0x93, MRM0r,
2548 (outs GR8 :$dst), (ins),
2550 [(set GR8:$dst, (X86setcc X86_COND_NC, EFLAGS))]>,
2551 TB; // GR8 = not carry
2552 def SETNCm : I<0x93, MRM0m,
2553 (outs), (ins i8mem:$dst),
2555 [(store (X86setcc X86_COND_NC, EFLAGS), addr:$dst)]>,
2556 TB; // [mem8] = not carry
2557 } // Uses = [EFLAGS]
2560 // Integer comparisons
2561 let Defs = [EFLAGS] in {
2562 def CMP8rr : I<0x38, MRMDestReg,
2563 (outs), (ins GR8 :$src1, GR8 :$src2),
2564 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2565 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2566 def CMP16rr : I<0x39, MRMDestReg,
2567 (outs), (ins GR16:$src1, GR16:$src2),
2568 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2569 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2570 def CMP32rr : I<0x39, MRMDestReg,
2571 (outs), (ins GR32:$src1, GR32:$src2),
2572 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2573 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2574 def CMP8mr : I<0x38, MRMDestMem,
2575 (outs), (ins i8mem :$src1, GR8 :$src2),
2576 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2577 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2578 (implicit EFLAGS)]>;
2579 def CMP16mr : I<0x39, MRMDestMem,
2580 (outs), (ins i16mem:$src1, GR16:$src2),
2581 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2582 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2583 (implicit EFLAGS)]>, OpSize;
2584 def CMP32mr : I<0x39, MRMDestMem,
2585 (outs), (ins i32mem:$src1, GR32:$src2),
2586 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2587 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2588 (implicit EFLAGS)]>;
2589 def CMP8rm : I<0x3A, MRMSrcMem,
2590 (outs), (ins GR8 :$src1, i8mem :$src2),
2591 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2592 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2593 (implicit EFLAGS)]>;
2594 def CMP16rm : I<0x3B, MRMSrcMem,
2595 (outs), (ins GR16:$src1, i16mem:$src2),
2596 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2597 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2598 (implicit EFLAGS)]>, OpSize;
2599 def CMP32rm : I<0x3B, MRMSrcMem,
2600 (outs), (ins GR32:$src1, i32mem:$src2),
2601 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2602 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2603 (implicit EFLAGS)]>;
2604 def CMP8ri : Ii8<0x80, MRM7r,
2605 (outs), (ins GR8:$src1, i8imm:$src2),
2606 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2607 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2608 def CMP16ri : Ii16<0x81, MRM7r,
2609 (outs), (ins GR16:$src1, i16imm:$src2),
2610 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2611 [(X86cmp GR16:$src1, imm:$src2),
2612 (implicit EFLAGS)]>, OpSize;
2613 def CMP32ri : Ii32<0x81, MRM7r,
2614 (outs), (ins GR32:$src1, i32imm:$src2),
2615 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2616 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2617 def CMP8mi : Ii8 <0x80, MRM7m,
2618 (outs), (ins i8mem :$src1, i8imm :$src2),
2619 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2620 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2621 (implicit EFLAGS)]>;
2622 def CMP16mi : Ii16<0x81, MRM7m,
2623 (outs), (ins i16mem:$src1, i16imm:$src2),
2624 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2625 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2626 (implicit EFLAGS)]>, OpSize;
2627 def CMP32mi : Ii32<0x81, MRM7m,
2628 (outs), (ins i32mem:$src1, i32imm:$src2),
2629 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2630 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2631 (implicit EFLAGS)]>;
2632 def CMP16ri8 : Ii8<0x83, MRM7r,
2633 (outs), (ins GR16:$src1, i16i8imm:$src2),
2634 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2635 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2636 (implicit EFLAGS)]>, OpSize;
2637 def CMP16mi8 : Ii8<0x83, MRM7m,
2638 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2639 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2640 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2641 (implicit EFLAGS)]>, OpSize;
2642 def CMP32mi8 : Ii8<0x83, MRM7m,
2643 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2644 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2645 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2646 (implicit EFLAGS)]>;
2647 def CMP32ri8 : Ii8<0x83, MRM7r,
2648 (outs), (ins GR32:$src1, i32i8imm:$src2),
2649 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2650 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2651 (implicit EFLAGS)]>;
2652 } // Defs = [EFLAGS]
2655 // TODO: BT with immediate operands
2656 // TODO: BTC, BTR, and BTS
2657 let Defs = [EFLAGS] in {
2658 def BT16rr : I<0xA3, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
2659 "bt{w}\t{$src2, $src1|$src1, $src2}",
2660 [(X86bt GR16:$src1, GR16:$src2),
2661 (implicit EFLAGS)]>, OpSize;
2662 def BT32rr : I<0xA3, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
2663 "bt{l}\t{$src2, $src1|$src1, $src2}",
2664 [(X86bt GR32:$src1, GR32:$src2),
2665 (implicit EFLAGS)]>;
2666 def BT16mr : I<0xA3, MRMSrcMem, (outs), (ins i16mem:$src1, GR16:$src2),
2667 "bt{w}\t{$src2, $src1|$src1, $src2}",
2668 [(X86bt addr:$src1, GR16:$src2),
2669 (implicit EFLAGS)]>, OpSize;
2670 def BT32mr : I<0xA3, MRMSrcMem, (outs), (ins i32mem:$src1, GR32:$src2),
2671 "bt{l}\t{$src2, $src1|$src1, $src2}",
2672 [(X86bt addr:$src1, GR32:$src2),
2673 (implicit EFLAGS)]>;
2674 } // Defs = [EFLAGS]
2676 // Sign/Zero extenders
2677 // Use movsbl intead of movsbw; we don't care about the high 16 bits
2678 // of the register here. This has a smaller encoding and avoids a
2679 // partial-register update.
2680 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2681 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2682 [(set GR16:$dst, (sext GR8:$src))]>, TB;
2683 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2684 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2685 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
2686 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2687 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2688 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2689 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2690 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2691 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2692 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2693 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2694 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2695 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2696 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2697 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2699 // Use movzbl intead of movzbw; we don't care about the high 16 bits
2700 // of the register here. This has a smaller encoding and avoids a
2701 // partial-register update.
2702 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2703 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2704 [(set GR16:$dst, (zext GR8:$src))]>, TB;
2705 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2706 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2707 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
2708 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2709 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2710 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2711 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2712 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2713 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2714 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2715 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2716 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2717 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2718 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2719 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2721 let neverHasSideEffects = 1 in {
2722 let Defs = [AX], Uses = [AL] in
2723 def CBW : I<0x98, RawFrm, (outs), (ins),
2724 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2725 let Defs = [EAX], Uses = [AX] in
2726 def CWDE : I<0x98, RawFrm, (outs), (ins),
2727 "{cwtl|cwde}", []>; // EAX = signext(AX)
2729 let Defs = [AX,DX], Uses = [AX] in
2730 def CWD : I<0x99, RawFrm, (outs), (ins),
2731 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2732 let Defs = [EAX,EDX], Uses = [EAX] in
2733 def CDQ : I<0x99, RawFrm, (outs), (ins),
2734 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2737 //===----------------------------------------------------------------------===//
2738 // Alias Instructions
2739 //===----------------------------------------------------------------------===//
2741 // Alias instructions that map movr0 to xor.
2742 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2743 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2744 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2745 "xor{b}\t$dst, $dst",
2746 [(set GR8:$dst, 0)]>;
2747 // Use xorl instead of xorw since we don't care about the high 16 bits,
2748 // it's smaller, and it avoids a partial-register update.
2749 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2750 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2751 [(set GR16:$dst, 0)]>;
2752 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2753 "xor{l}\t$dst, $dst",
2754 [(set GR32:$dst, 0)]>;
2757 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2758 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2759 let neverHasSideEffects = 1 in {
2760 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2761 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2762 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2763 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2765 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2766 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2767 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2768 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2769 } // neverHasSideEffects
2771 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2772 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2773 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2774 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2775 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2777 let mayStore = 1, neverHasSideEffects = 1 in {
2778 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2779 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2780 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2781 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2784 //===----------------------------------------------------------------------===//
2785 // Thread Local Storage Instructions
2789 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2790 "leal\t${sym:mem}(,%ebx,1), $dst",
2791 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2793 let AddedComplexity = 10 in
2794 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2795 "movl\t%gs:($src), $dst",
2796 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2798 let AddedComplexity = 15 in
2799 def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2800 "movl\t%gs:${src:mem}, $dst",
2802 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
2805 def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
2806 "movl\t%gs:0, $dst",
2807 [(set GR32:$dst, X86TLStp)]>, SegGS;
2809 //===----------------------------------------------------------------------===//
2810 // DWARF Pseudo Instructions
2813 def DWARF_LOC : I<0, Pseudo, (outs),
2814 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2815 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2816 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2819 //===----------------------------------------------------------------------===//
2820 // EH Pseudo Instructions
2822 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2824 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2825 "ret\t#eh_return, addr: $addr",
2826 [(X86ehret GR32:$addr)]>;
2830 //===----------------------------------------------------------------------===//
2834 // Atomic swap. These are just normal xchg instructions. But since a memory
2835 // operand is referenced, the atomicity is ensured.
2836 let Constraints = "$val = $dst" in {
2837 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2838 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2839 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2840 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2841 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2842 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2844 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2845 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2846 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2849 // Atomic compare and swap.
2850 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2851 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
2852 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
2853 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2855 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2856 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
2857 "lock\n\tcmpxchg8b\t$ptr",
2858 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2861 let Defs = [AX, EFLAGS], Uses = [AX] in {
2862 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
2863 "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
2864 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2866 let Defs = [AL, EFLAGS], Uses = [AL] in {
2867 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
2868 "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
2869 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2872 // Atomic exchange and add
2873 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2874 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2875 "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
2876 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
2878 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2879 "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
2880 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
2882 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2883 "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
2884 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
2888 // Atomic exchange, and, or, xor
2889 let Constraints = "$val = $dst", Defs = [EFLAGS],
2890 usesCustomDAGSchedInserter = 1 in {
2891 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2892 "#ATOMAND32 PSEUDO!",
2893 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
2894 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2895 "#ATOMOR32 PSEUDO!",
2896 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
2897 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2898 "#ATOMXOR32 PSEUDO!",
2899 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
2900 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2901 "#ATOMNAND32 PSEUDO!",
2902 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
2903 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2904 "#ATOMMIN32 PSEUDO!",
2905 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
2906 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2907 "#ATOMMAX32 PSEUDO!",
2908 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
2909 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2910 "#ATOMUMIN32 PSEUDO!",
2911 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
2912 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2913 "#ATOMUMAX32 PSEUDO!",
2914 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
2916 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2917 "#ATOMAND16 PSEUDO!",
2918 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
2919 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2920 "#ATOMOR16 PSEUDO!",
2921 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
2922 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2923 "#ATOMXOR16 PSEUDO!",
2924 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
2925 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2926 "#ATOMNAND16 PSEUDO!",
2927 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
2928 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2929 "#ATOMMIN16 PSEUDO!",
2930 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
2931 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2932 "#ATOMMAX16 PSEUDO!",
2933 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
2934 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2935 "#ATOMUMIN16 PSEUDO!",
2936 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
2937 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2938 "#ATOMUMAX16 PSEUDO!",
2939 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
2941 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2942 "#ATOMAND8 PSEUDO!",
2943 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
2944 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2946 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
2947 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2948 "#ATOMXOR8 PSEUDO!",
2949 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
2950 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2951 "#ATOMNAND8 PSEUDO!",
2952 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
2955 let Constraints = "$val1 = $dst1, $val2 = $dst2",
2956 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
2957 Uses = [EAX, EBX, ECX, EDX],
2958 mayLoad = 1, mayStore = 1,
2959 usesCustomDAGSchedInserter = 1 in {
2960 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2961 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2962 "#ATOMAND6432 PSEUDO!", []>;
2963 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2964 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2965 "#ATOMOR6432 PSEUDO!", []>;
2966 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2967 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2968 "#ATOMXOR6432 PSEUDO!", []>;
2969 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2970 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2971 "#ATOMNAND6432 PSEUDO!", []>;
2972 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2973 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2974 "#ATOMADD6432 PSEUDO!", []>;
2975 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2976 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2977 "#ATOMSUB6432 PSEUDO!", []>;
2978 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2979 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2980 "#ATOMSWAP6432 PSEUDO!", []>;
2983 //===----------------------------------------------------------------------===//
2984 // Non-Instruction Patterns
2985 //===----------------------------------------------------------------------===//
2987 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2988 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2989 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2990 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
2991 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2992 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2994 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2995 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2996 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2997 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2998 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2999 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3000 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3001 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3003 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3004 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3005 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3006 (MOV32mi addr:$dst, texternalsym:$src)>;
3010 def : Pat<(X86tailcall GR32:$dst),
3013 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3015 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3018 def : Pat<(X86tcret GR32:$dst, imm:$off),
3019 (TCRETURNri GR32:$dst, imm:$off)>;
3021 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3022 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3024 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3025 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3027 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3028 (CALLpcrel32 tglobaladdr:$dst)>;
3029 def : Pat<(X86call (i32 texternalsym:$dst)),
3030 (CALLpcrel32 texternalsym:$dst)>;
3032 // X86 specific add which produces a flag.
3033 def : Pat<(addc GR32:$src1, GR32:$src2),
3034 (ADD32rr GR32:$src1, GR32:$src2)>;
3035 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3036 (ADD32rm GR32:$src1, addr:$src2)>;
3037 def : Pat<(addc GR32:$src1, imm:$src2),
3038 (ADD32ri GR32:$src1, imm:$src2)>;
3039 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3040 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3042 def : Pat<(subc GR32:$src1, GR32:$src2),
3043 (SUB32rr GR32:$src1, GR32:$src2)>;
3044 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3045 (SUB32rm GR32:$src1, addr:$src2)>;
3046 def : Pat<(subc GR32:$src1, imm:$src2),
3047 (SUB32ri GR32:$src1, imm:$src2)>;
3048 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3049 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3053 // TEST R,R is smaller than CMP R,0
3054 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3055 (TEST8rr GR8:$src1, GR8:$src1)>;
3056 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3057 (TEST16rr GR16:$src1, GR16:$src1)>;
3058 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3059 (TEST32rr GR32:$src1, GR32:$src1)>;
3061 // zextload bool -> zextload byte
3062 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3063 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3064 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3066 // extload bool -> extload byte
3067 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3068 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3069 Requires<[In32BitMode]>;
3070 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3071 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3072 Requires<[In32BitMode]>;
3073 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3074 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3077 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3078 Requires<[In32BitMode]>;
3079 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3080 Requires<[In32BitMode]>;
3081 def : Pat<(i32 (anyext GR16:$src)),
3082 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3084 // (and (i32 load), 255) -> (zextload i8)
3085 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3086 (MOVZX32rm8 addr:$src)>;
3087 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3088 (MOVZX32rm16 addr:$src)>;
3090 //===----------------------------------------------------------------------===//
3092 //===----------------------------------------------------------------------===//
3094 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3095 // +128 doesn't, so in this special case use a sub instead of an add.
3096 def : Pat<(add GR16:$src1, 128),
3097 (SUB16ri8 GR16:$src1, -128)>;
3098 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3099 (SUB16mi8 addr:$dst, -128)>;
3100 def : Pat<(add GR32:$src1, 128),
3101 (SUB32ri8 GR32:$src1, -128)>;
3102 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3103 (SUB32mi8 addr:$dst, -128)>;
3105 // r & (2^16-1) ==> movz
3106 def : Pat<(and GR32:$src1, 0xffff),
3107 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
3108 // r & (2^8-1) ==> movz
3109 def : Pat<(and GR32:$src1, 0xff),
3110 (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
3111 x86_subreg_8bit)))>,
3112 Requires<[In32BitMode]>;
3113 // r & (2^8-1) ==> movz
3114 def : Pat<(and GR16:$src1, 0xff),
3115 (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
3116 x86_subreg_8bit)))>,
3117 Requires<[In32BitMode]>;
3119 // sext_inreg patterns
3120 def : Pat<(sext_inreg GR32:$src, i16),
3121 (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
3122 def : Pat<(sext_inreg GR32:$src, i8),
3123 (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
3124 x86_subreg_8bit)))>,
3125 Requires<[In32BitMode]>;
3126 def : Pat<(sext_inreg GR16:$src, i8),
3127 (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
3128 x86_subreg_8bit)))>,
3129 Requires<[In32BitMode]>;
3132 def : Pat<(i16 (trunc GR32:$src)),
3133 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3134 def : Pat<(i8 (trunc GR32:$src)),
3135 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
3136 Requires<[In32BitMode]>;
3137 def : Pat<(i8 (trunc GR16:$src)),
3138 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
3139 Requires<[In32BitMode]>;
3141 // (shl x, 1) ==> (add x, x)
3142 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3143 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3144 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3146 // (shl x (and y, 31)) ==> (shl x, y)
3147 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3148 (SHL8rCL GR8:$src1)>;
3149 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3150 (SHL16rCL GR16:$src1)>;
3151 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3152 (SHL32rCL GR32:$src1)>;
3153 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3154 (SHL8mCL addr:$dst)>;
3155 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3156 (SHL16mCL addr:$dst)>;
3157 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3158 (SHL32mCL addr:$dst)>;
3160 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3161 (SHR8rCL GR8:$src1)>;
3162 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3163 (SHR16rCL GR16:$src1)>;
3164 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3165 (SHR32rCL GR32:$src1)>;
3166 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3167 (SHR8mCL addr:$dst)>;
3168 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3169 (SHR16mCL addr:$dst)>;
3170 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3171 (SHR32mCL addr:$dst)>;
3173 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3174 (SAR8rCL GR8:$src1)>;
3175 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3176 (SAR16rCL GR16:$src1)>;
3177 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3178 (SAR32rCL GR32:$src1)>;
3179 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3180 (SAR8mCL addr:$dst)>;
3181 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3182 (SAR16mCL addr:$dst)>;
3183 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3184 (SAR32mCL addr:$dst)>;
3186 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3187 def : Pat<(or (srl GR32:$src1, CL:$amt),
3188 (shl GR32:$src2, (sub 32, CL:$amt))),
3189 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3191 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3192 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3193 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3195 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3196 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3197 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3199 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3200 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3202 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3204 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3205 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3207 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3208 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3209 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3211 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3212 def : Pat<(or (shl GR32:$src1, CL:$amt),
3213 (srl GR32:$src2, (sub 32, CL:$amt))),
3214 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3216 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3217 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3218 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3220 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3221 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3222 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3224 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3225 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3227 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3229 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3230 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3232 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3233 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3234 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3236 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3237 def : Pat<(or (srl GR16:$src1, CL:$amt),
3238 (shl GR16:$src2, (sub 16, CL:$amt))),
3239 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3241 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3242 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3243 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3245 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3246 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3247 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3249 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3250 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3252 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3254 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3255 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3257 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3258 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3259 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3261 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3262 def : Pat<(or (shl GR16:$src1, CL:$amt),
3263 (srl GR16:$src2, (sub 16, CL:$amt))),
3264 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3266 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3267 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3268 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3270 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3271 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3272 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3274 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3275 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3277 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3279 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3280 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3282 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3283 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3284 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3286 //===----------------------------------------------------------------------===//
3287 // Overflow Patterns
3288 //===----------------------------------------------------------------------===//
3290 // Register-Register Addition with Overflow
3291 def : Pat<(parallel (X86add_ovf GR8:$src1, GR8:$src2),
3293 (ADD8rr GR8:$src1, GR8:$src2)>;
3295 // Register-Register Addition with Overflow
3296 def : Pat<(parallel (X86add_ovf GR16:$src1, GR16:$src2),
3298 (ADD16rr GR16:$src1, GR16:$src2)>;
3299 def : Pat<(parallel (X86add_ovf GR32:$src1, GR32:$src2),
3301 (ADD32rr GR32:$src1, GR32:$src2)>;
3303 // Register-Memory Addition with Overflow
3304 def : Pat<(parallel (X86add_ovf GR8:$src1, (load addr:$src2)),
3306 (ADD8rm GR8:$src1, addr:$src2)>;
3307 def : Pat<(parallel (X86add_ovf GR16:$src1, (load addr:$src2)),
3309 (ADD16rm GR16:$src1, addr:$src2)>;
3310 def : Pat<(parallel (X86add_ovf GR32:$src1, (load addr:$src2)),
3312 (ADD32rm GR32:$src1, addr:$src2)>;
3314 // Register-Integer Addition with Overflow
3315 def : Pat<(parallel (X86add_ovf GR8:$src1, imm:$src2),
3317 (ADD8ri GR8:$src1, imm:$src2)>;
3319 // Register-Integer Addition with Overflow
3320 def : Pat<(parallel (X86add_ovf GR16:$src1, imm:$src2),
3322 (ADD16ri GR16:$src1, imm:$src2)>;
3323 def : Pat<(parallel (X86add_ovf GR32:$src1, imm:$src2),
3325 (ADD32ri GR32:$src1, imm:$src2)>;
3326 def : Pat<(parallel (X86add_ovf GR16:$src1, i16immSExt8:$src2),
3328 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3329 def : Pat<(parallel (X86add_ovf GR32:$src1, i32immSExt8:$src2),
3331 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3333 // Memory-Register Addition with Overflow
3334 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR8:$src2),
3337 (ADD8mr addr:$dst, GR8:$src2)>;
3338 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR16:$src2),
3341 (ADD16mr addr:$dst, GR16:$src2)>;
3342 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR32:$src2),
3345 (ADD32mr addr:$dst, GR32:$src2)>;
3346 def : Pat<(parallel (store (X86add_ovf (loadi8 addr:$dst), imm:$src2),
3349 (ADD8mi addr:$dst, imm:$src2)>;
3350 def : Pat<(parallel (store (X86add_ovf (loadi16 addr:$dst), imm:$src2),
3353 (ADD16mi addr:$dst, imm:$src2)>;
3354 def : Pat<(parallel (store (X86add_ovf (loadi32 addr:$dst), imm:$src2),
3357 (ADD32mi addr:$dst, imm:$src2)>;
3358 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i16immSExt8:$src2),
3361 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3362 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i32immSExt8:$src2),
3365 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3367 // Register-Register Subtraction with Overflow
3368 def : Pat<(parallel (X86sub_ovf GR8:$src1, GR8:$src2),
3370 (SUB8rr GR8:$src1, GR8:$src2)>;
3371 def : Pat<(parallel (X86sub_ovf GR16:$src1, GR16:$src2),
3373 (SUB16rr GR16:$src1, GR16:$src2)>;
3374 def : Pat<(parallel (X86sub_ovf GR32:$src1, GR32:$src2),
3376 (SUB32rr GR32:$src1, GR32:$src2)>;
3378 // Register-Memory Subtraction with Overflow
3379 def : Pat<(parallel (X86sub_ovf GR8:$src1, (load addr:$src2)),
3381 (SUB8rm GR8:$src1, addr:$src2)>;
3382 def : Pat<(parallel (X86sub_ovf GR16:$src1, (load addr:$src2)),
3384 (SUB16rm GR16:$src1, addr:$src2)>;
3385 def : Pat<(parallel (X86sub_ovf GR32:$src1, (load addr:$src2)),
3387 (SUB32rm GR32:$src1, addr:$src2)>;
3389 // Register-Integer Subtraction with Overflow
3390 def : Pat<(parallel (X86sub_ovf GR8:$src1, imm:$src2),
3392 (SUB8ri GR8:$src1, imm:$src2)>;
3393 def : Pat<(parallel (X86sub_ovf GR16:$src1, imm:$src2),
3395 (SUB16ri GR16:$src1, imm:$src2)>;
3396 def : Pat<(parallel (X86sub_ovf GR32:$src1, imm:$src2),
3398 (SUB32ri GR32:$src1, imm:$src2)>;
3399 def : Pat<(parallel (X86sub_ovf GR16:$src1, i16immSExt8:$src2),
3401 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3402 def : Pat<(parallel (X86sub_ovf GR32:$src1, i32immSExt8:$src2),
3404 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3406 // Memory-Register Subtraction with Overflow
3407 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR8:$src2),
3410 (SUB8mr addr:$dst, GR8:$src2)>;
3411 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR16:$src2),
3414 (SUB16mr addr:$dst, GR16:$src2)>;
3415 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR32:$src2),
3418 (SUB32mr addr:$dst, GR32:$src2)>;
3420 // Memory-Integer Subtraction with Overflow
3421 def : Pat<(parallel (store (X86sub_ovf (loadi8 addr:$dst), imm:$src2),
3424 (SUB8mi addr:$dst, imm:$src2)>;
3425 def : Pat<(parallel (store (X86sub_ovf (loadi16 addr:$dst), imm:$src2),
3428 (SUB16mi addr:$dst, imm:$src2)>;
3429 def : Pat<(parallel (store (X86sub_ovf (loadi32 addr:$dst), imm:$src2),
3432 (SUB32mi addr:$dst, imm:$src2)>;
3433 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i16immSExt8:$src2),
3436 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3437 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i32immSExt8:$src2),
3440 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3443 // Register-Register Signed Integer Multiply with Overflow
3444 def : Pat<(parallel (X86smul_ovf GR16:$src1, GR16:$src2),
3446 (IMUL16rr GR16:$src1, GR16:$src2)>;
3447 def : Pat<(parallel (X86smul_ovf GR32:$src1, GR32:$src2),
3449 (IMUL32rr GR32:$src1, GR32:$src2)>;
3451 // Register-Memory Signed Integer Multiply with Overflow
3452 def : Pat<(parallel (X86smul_ovf GR16:$src1, (load addr:$src2)),
3454 (IMUL16rm GR16:$src1, addr:$src2)>;
3455 def : Pat<(parallel (X86smul_ovf GR32:$src1, (load addr:$src2)),
3457 (IMUL32rm GR32:$src1, addr:$src2)>;
3459 // Register-Integer Signed Integer Multiply with Overflow
3460 def : Pat<(parallel (X86smul_ovf GR16:$src1, imm:$src2),
3462 (IMUL16rri GR16:$src1, imm:$src2)>;
3463 def : Pat<(parallel (X86smul_ovf GR32:$src1, imm:$src2),
3465 (IMUL32rri GR32:$src1, imm:$src2)>;
3466 def : Pat<(parallel (X86smul_ovf GR16:$src1, i16immSExt8:$src2),
3468 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
3469 def : Pat<(parallel (X86smul_ovf GR32:$src1, i32immSExt8:$src2),
3471 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3473 // Memory-Integer Signed Integer Multiply with Overflow
3474 def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
3476 (IMUL16rmi addr:$src1, imm:$src2)>;
3477 def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
3479 (IMUL32rmi addr:$src1, imm:$src2)>;
3480 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i16immSExt8:$src2),
3482 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
3483 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i32immSExt8:$src2),
3485 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3487 //===----------------------------------------------------------------------===//
3488 // Floating Point Stack Support
3489 //===----------------------------------------------------------------------===//
3491 include "X86InstrFPStack.td"
3493 //===----------------------------------------------------------------------===//
3495 //===----------------------------------------------------------------------===//
3497 include "X86Instr64bit.td"
3499 //===----------------------------------------------------------------------===//
3500 // XMM Floating point support (requires SSE / SSE2)
3501 //===----------------------------------------------------------------------===//
3503 include "X86InstrSSE.td"
3505 //===----------------------------------------------------------------------===//
3506 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3507 //===----------------------------------------------------------------------===//
3509 include "X86InstrMMX.td"