1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
67 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
69 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
75 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
80 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
83 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
85 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
87 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
111 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
114 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
128 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
130 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
131 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
132 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
133 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
136 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
137 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
139 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
140 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
142 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
143 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
144 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
145 SDT_X86SegmentBaseAddress, []>;
147 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
150 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
151 [SDNPHasChain, SDNPOptInFlag]>;
153 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
154 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
155 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
156 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
157 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
158 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
160 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
162 //===----------------------------------------------------------------------===//
163 // X86 Operand Definitions.
166 // *mem - Operand definitions for the funky X86 addressing mode operands.
168 class X86MemOperand<string printMethod> : Operand<iPTR> {
169 let PrintMethod = printMethod;
170 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
173 def i8mem : X86MemOperand<"printi8mem">;
174 def i16mem : X86MemOperand<"printi16mem">;
175 def i32mem : X86MemOperand<"printi32mem">;
176 def i64mem : X86MemOperand<"printi64mem">;
177 def i128mem : X86MemOperand<"printi128mem">;
178 def f32mem : X86MemOperand<"printf32mem">;
179 def f64mem : X86MemOperand<"printf64mem">;
180 def f80mem : X86MemOperand<"printf80mem">;
181 def f128mem : X86MemOperand<"printf128mem">;
183 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
184 // plain GR64, so that it doesn't potentially require a REX prefix.
185 def i8mem_NOREX : Operand<i64> {
186 let PrintMethod = "printi8mem";
187 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX, i32imm, i8imm);
190 def lea32mem : Operand<i32> {
191 let PrintMethod = "printlea32mem";
192 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
195 def SSECC : Operand<i8> {
196 let PrintMethod = "printSSECC";
199 def piclabel: Operand<i32> {
200 let PrintMethod = "printPICLabel";
203 // A couple of more descriptive operand definitions.
204 // 16-bits but only 8 bits are significant.
205 def i16i8imm : Operand<i16>;
206 // 32-bits but only 8 bits are significant.
207 def i32i8imm : Operand<i32>;
209 // Branch targets have OtherVT type.
210 def brtarget : Operand<OtherVT>;
212 //===----------------------------------------------------------------------===//
213 // X86 Complex Pattern Definitions.
216 // Define X86 specific addressing mode.
217 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
218 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
219 [add, sub, mul, shl, or, frameindex], []>;
221 //===----------------------------------------------------------------------===//
222 // X86 Instruction Predicate Definitions.
223 def HasMMX : Predicate<"Subtarget->hasMMX()">;
224 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
225 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
226 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
227 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
228 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
229 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
230 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
231 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
232 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
233 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
234 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
235 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
236 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
237 def OptForSpeed : Predicate<"!OptForSize">;
238 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
239 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
241 //===----------------------------------------------------------------------===//
242 // X86 Instruction Format Definitions.
245 include "X86InstrFormats.td"
247 //===----------------------------------------------------------------------===//
248 // Pattern fragments...
251 // X86 specific condition code. These correspond to CondCode in
252 // X86InstrInfo.h. They must be kept in synch.
253 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
254 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
255 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
256 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
257 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
258 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
259 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
260 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
261 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
262 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
263 def X86_COND_NO : PatLeaf<(i8 10)>;
264 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
265 def X86_COND_NS : PatLeaf<(i8 12)>;
266 def X86_COND_O : PatLeaf<(i8 13)>;
267 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
268 def X86_COND_S : PatLeaf<(i8 15)>;
270 def i16immSExt8 : PatLeaf<(i16 imm), [{
271 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
272 // sign extended field.
273 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
276 def i32immSExt8 : PatLeaf<(i32 imm), [{
277 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
278 // sign extended field.
279 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
282 // Helper fragments for loads.
283 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
284 // known to be 32-bit aligned or better. Ditto for i8 to i16.
285 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
286 LoadSDNode *LD = cast<LoadSDNode>(N);
287 if (const Value *Src = LD->getSrcValue())
288 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
289 if (PT->getAddressSpace() > 255)
291 ISD::LoadExtType ExtType = LD->getExtensionType();
292 if (ExtType == ISD::NON_EXTLOAD)
294 if (ExtType == ISD::EXTLOAD)
295 return LD->getAlignment() >= 2 && !LD->isVolatile();
299 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
300 LoadSDNode *LD = cast<LoadSDNode>(N);
301 if (const Value *Src = LD->getSrcValue())
302 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
303 if (PT->getAddressSpace() > 255)
305 ISD::LoadExtType ExtType = LD->getExtensionType();
306 if (ExtType == ISD::EXTLOAD)
307 return LD->getAlignment() >= 2 && !LD->isVolatile();
311 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
312 LoadSDNode *LD = cast<LoadSDNode>(N);
313 if (const Value *Src = LD->getSrcValue())
314 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
315 if (PT->getAddressSpace() > 255)
317 ISD::LoadExtType ExtType = LD->getExtensionType();
318 if (ExtType == ISD::NON_EXTLOAD)
320 if (ExtType == ISD::EXTLOAD)
321 return LD->getAlignment() >= 4 && !LD->isVolatile();
325 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
326 LoadSDNode *LD = cast<LoadSDNode>(N);
327 if (const Value *Src = LD->getSrcValue())
328 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
329 if (PT->getAddressSpace() > 255)
331 if (LD->isVolatile())
333 ISD::LoadExtType ExtType = LD->getExtensionType();
334 if (ExtType == ISD::NON_EXTLOAD)
336 if (ExtType == ISD::EXTLOAD)
337 return LD->getAlignment() >= 4;
341 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
342 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
343 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
344 return PT->getAddressSpace() == 256;
348 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
349 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
350 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
351 return PT->getAddressSpace() == 257;
355 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
356 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
357 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
358 if (PT->getAddressSpace() > 255)
362 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
363 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
365 if (PT->getAddressSpace() > 255)
370 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
371 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
372 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
373 if (PT->getAddressSpace() > 255)
377 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
378 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
384 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
385 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
386 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
387 if (PT->getAddressSpace() > 255)
392 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
393 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
394 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
396 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
397 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
398 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
399 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
400 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
401 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
403 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
404 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
405 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
406 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
407 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
408 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
411 // An 'and' node with a single use.
412 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
413 return N->hasOneUse();
415 // An 'srl' node with a single use.
416 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
417 return N->hasOneUse();
419 // An 'trunc' node with a single use.
420 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
421 return N->hasOneUse();
424 // 'shld' and 'shrd' instruction patterns. Note that even though these have
425 // the srl and shl in their patterns, the C++ code must still check for them,
426 // because predicates are tested before children nodes are explored.
428 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
429 (or (srl node:$src1, node:$amt1),
430 (shl node:$src2, node:$amt2)), [{
431 assert(N->getOpcode() == ISD::OR);
432 return N->getOperand(0).getOpcode() == ISD::SRL &&
433 N->getOperand(1).getOpcode() == ISD::SHL &&
434 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
435 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
436 N->getOperand(0).getConstantOperandVal(1) ==
437 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
440 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
441 (or (shl node:$src1, node:$amt1),
442 (srl node:$src2, node:$amt2)), [{
443 assert(N->getOpcode() == ISD::OR);
444 return N->getOperand(0).getOpcode() == ISD::SHL &&
445 N->getOperand(1).getOpcode() == ISD::SRL &&
446 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
447 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
448 N->getOperand(0).getConstantOperandVal(1) ==
449 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
452 //===----------------------------------------------------------------------===//
453 // Instruction list...
456 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
457 // a stack adjustment and the codegen must know that they may modify the stack
458 // pointer before prolog-epilog rewriting occurs.
459 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
460 // sub / add which can clobber EFLAGS.
461 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
462 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
464 [(X86callseq_start timm:$amt)]>,
465 Requires<[In32BitMode]>;
466 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
468 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
469 Requires<[In32BitMode]>;
473 let neverHasSideEffects = 1 in
474 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
477 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
478 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
482 //===----------------------------------------------------------------------===//
483 // Control Flow Instructions...
486 // Return instructions.
487 let isTerminator = 1, isReturn = 1, isBarrier = 1,
488 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
489 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
492 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
494 [(X86retflag imm:$amt)]>;
497 // All branches are RawFrm, Void, Branch, and Terminators
498 let isBranch = 1, isTerminator = 1 in
499 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
500 I<opcode, RawFrm, (outs), ins, asm, pattern>;
502 let isBranch = 1, isBarrier = 1 in
503 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
506 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
507 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
508 [(brind GR32:$dst)]>;
509 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
510 [(brind (loadi32 addr:$dst))]>;
513 // Conditional branches
514 let Uses = [EFLAGS] in {
515 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
516 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
517 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
518 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
519 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
520 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
521 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
522 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
523 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
524 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
525 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
526 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
528 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
529 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
530 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
531 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
532 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
533 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
534 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
535 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
537 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
538 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
539 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
540 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
541 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
542 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
543 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
544 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
545 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
546 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
547 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
548 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
551 //===----------------------------------------------------------------------===//
552 // Call Instructions...
555 // All calls clobber the non-callee saved registers. ESP is marked as
556 // a use to prevent stack-pointer assignments that appear immediately
557 // before calls from potentially appearing dead. Uses for argument
558 // registers are added manually.
559 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
560 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
561 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
562 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
564 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
565 "call\t${dst:call}", []>;
566 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
567 "call\t{*}$dst", [(X86call GR32:$dst)]>;
568 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
569 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
574 def TAILCALL : I<0, Pseudo, (outs), (ins),
578 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
579 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
580 "#TC_RETURN $dst $offset",
583 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
584 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
585 "#TC_RETURN $dst $offset",
588 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
590 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
592 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
593 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
595 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
596 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
597 "jmp\t{*}$dst # TAILCALL", []>;
599 //===----------------------------------------------------------------------===//
600 // Miscellaneous Instructions...
602 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
603 def LEAVE : I<0xC9, RawFrm,
604 (outs), (ins), "leave", []>;
606 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
608 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
611 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
614 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
615 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
616 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
617 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
619 let isTwoAddress = 1 in // GR32 = bswap GR32
620 def BSWAP32r : I<0xC8, AddRegFrm,
621 (outs GR32:$dst), (ins GR32:$src),
623 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
626 // Bit scan instructions.
627 let Defs = [EFLAGS] in {
628 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
629 "bsf{w}\t{$src, $dst|$dst, $src}",
630 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
631 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
632 "bsf{w}\t{$src, $dst|$dst, $src}",
633 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
634 (implicit EFLAGS)]>, TB;
635 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
636 "bsf{l}\t{$src, $dst|$dst, $src}",
637 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
638 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
639 "bsf{l}\t{$src, $dst|$dst, $src}",
640 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
641 (implicit EFLAGS)]>, TB;
643 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
644 "bsr{w}\t{$src, $dst|$dst, $src}",
645 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
646 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
647 "bsr{w}\t{$src, $dst|$dst, $src}",
648 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
649 (implicit EFLAGS)]>, TB;
650 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
651 "bsr{l}\t{$src, $dst|$dst, $src}",
652 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
653 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
654 "bsr{l}\t{$src, $dst|$dst, $src}",
655 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
656 (implicit EFLAGS)]>, TB;
659 let neverHasSideEffects = 1 in
660 def LEA16r : I<0x8D, MRMSrcMem,
661 (outs GR16:$dst), (ins i32mem:$src),
662 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
663 let isReMaterializable = 1 in
664 def LEA32r : I<0x8D, MRMSrcMem,
665 (outs GR32:$dst), (ins lea32mem:$src),
666 "lea{l}\t{$src|$dst}, {$dst|$src}",
667 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
669 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
670 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
671 [(X86rep_movs i8)]>, REP;
672 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
673 [(X86rep_movs i16)]>, REP, OpSize;
674 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
675 [(X86rep_movs i32)]>, REP;
678 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
679 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
680 [(X86rep_stos i8)]>, REP;
681 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
682 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
683 [(X86rep_stos i16)]>, REP, OpSize;
684 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
685 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
686 [(X86rep_stos i32)]>, REP;
688 let Defs = [RAX, RDX] in
689 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
692 let isBarrier = 1, hasCtrlDep = 1 in {
693 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
696 //===----------------------------------------------------------------------===//
697 // Input/Output Instructions...
699 let Defs = [AL], Uses = [DX] in
700 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
701 "in{b}\t{%dx, %al|%AL, %DX}", []>;
702 let Defs = [AX], Uses = [DX] in
703 def IN16rr : I<0xED, RawFrm, (outs), (ins),
704 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
705 let Defs = [EAX], Uses = [DX] in
706 def IN32rr : I<0xED, RawFrm, (outs), (ins),
707 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
710 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
711 "in{b}\t{$port, %al|%AL, $port}", []>;
713 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
714 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
716 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
717 "in{l}\t{$port, %eax|%EAX, $port}", []>;
719 let Uses = [DX, AL] in
720 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
721 "out{b}\t{%al, %dx|%DX, %AL}", []>;
722 let Uses = [DX, AX] in
723 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
724 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
725 let Uses = [DX, EAX] in
726 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
727 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
730 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
731 "out{b}\t{%al, $port|$port, %AL}", []>;
733 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
734 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
736 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
737 "out{l}\t{%eax, $port|$port, %EAX}", []>;
739 //===----------------------------------------------------------------------===//
740 // Move Instructions...
742 let neverHasSideEffects = 1 in {
743 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
744 "mov{b}\t{$src, $dst|$dst, $src}", []>;
745 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
746 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
747 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
748 "mov{l}\t{$src, $dst|$dst, $src}", []>;
750 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
751 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
752 "mov{b}\t{$src, $dst|$dst, $src}",
753 [(set GR8:$dst, imm:$src)]>;
754 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
755 "mov{w}\t{$src, $dst|$dst, $src}",
756 [(set GR16:$dst, imm:$src)]>, OpSize;
757 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
758 "mov{l}\t{$src, $dst|$dst, $src}",
759 [(set GR32:$dst, imm:$src)]>;
761 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
762 "mov{b}\t{$src, $dst|$dst, $src}",
763 [(store (i8 imm:$src), addr:$dst)]>;
764 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
765 "mov{w}\t{$src, $dst|$dst, $src}",
766 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
767 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
768 "mov{l}\t{$src, $dst|$dst, $src}",
769 [(store (i32 imm:$src), addr:$dst)]>;
771 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
772 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
773 "mov{b}\t{$src, $dst|$dst, $src}",
774 [(set GR8:$dst, (loadi8 addr:$src))]>;
775 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
776 "mov{w}\t{$src, $dst|$dst, $src}",
777 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
778 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
779 "mov{l}\t{$src, $dst|$dst, $src}",
780 [(set GR32:$dst, (loadi32 addr:$src))]>;
783 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
784 "mov{b}\t{$src, $dst|$dst, $src}",
785 [(store GR8:$src, addr:$dst)]>;
786 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
787 "mov{w}\t{$src, $dst|$dst, $src}",
788 [(store GR16:$src, addr:$dst)]>, OpSize;
789 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
790 "mov{l}\t{$src, $dst|$dst, $src}",
791 [(store GR32:$src, addr:$dst)]>;
793 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
794 // that they can be used for copying and storing h registers, which can't be
795 // encoded when a REX prefix is present.
796 let neverHasSideEffects = 1 in
797 def MOV8rr_NOREX : I<0x88, MRMDestReg,
798 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
799 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
801 def MOV8mr_NOREX : I<0x88, MRMDestMem,
802 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
803 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
805 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
806 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
807 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
808 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
810 //===----------------------------------------------------------------------===//
811 // Fixed-Register Multiplication and Division Instructions...
814 // Extra precision multiplication
815 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
816 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
817 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
818 // This probably ought to be moved to a def : Pat<> if the
819 // syntax can be accepted.
820 [(set AL, (mul AL, GR8:$src)),
821 (implicit EFLAGS)]>; // AL,AH = AL*GR8
823 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
824 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
826 []>, OpSize; // AX,DX = AX*GR16
828 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
829 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
831 []>; // EAX,EDX = EAX*GR32
833 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
834 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
836 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
837 // This probably ought to be moved to a def : Pat<> if the
838 // syntax can be accepted.
839 [(set AL, (mul AL, (loadi8 addr:$src))),
840 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
842 let mayLoad = 1, neverHasSideEffects = 1 in {
843 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
844 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
846 []>, OpSize; // AX,DX = AX*[mem16]
848 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
849 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
851 []>; // EAX,EDX = EAX*[mem32]
854 let neverHasSideEffects = 1 in {
855 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
856 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
858 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
859 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
860 OpSize; // AX,DX = AX*GR16
861 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
862 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
863 // EAX,EDX = EAX*GR32
865 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
866 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
867 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
868 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
869 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
870 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
871 let Defs = [EAX,EDX], Uses = [EAX] in
872 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
873 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
875 } // neverHasSideEffects
877 // unsigned division/remainder
878 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
879 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
881 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
882 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
883 "div{w}\t$src", []>, OpSize;
884 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
885 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
888 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
889 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
891 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
892 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
893 "div{w}\t$src", []>, OpSize;
894 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
895 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
899 // Signed division/remainder.
900 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
901 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
902 "idiv{b}\t$src", []>;
903 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
904 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
905 "idiv{w}\t$src", []>, OpSize;
906 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
907 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
908 "idiv{l}\t$src", []>;
909 let mayLoad = 1, mayLoad = 1 in {
910 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
911 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
912 "idiv{b}\t$src", []>;
913 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
914 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
915 "idiv{w}\t$src", []>, OpSize;
916 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
917 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
918 "idiv{l}\t$src", []>;
921 //===----------------------------------------------------------------------===//
922 // Two address Instructions.
924 let isTwoAddress = 1 in {
927 let Uses = [EFLAGS] in {
928 let isCommutable = 1 in {
929 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
930 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
931 "cmovb\t{$src2, $dst|$dst, $src2}",
932 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
933 X86_COND_B, EFLAGS))]>,
935 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
936 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
937 "cmovb\t{$src2, $dst|$dst, $src2}",
938 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
939 X86_COND_B, EFLAGS))]>,
941 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
942 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
943 "cmovae\t{$src2, $dst|$dst, $src2}",
944 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
945 X86_COND_AE, EFLAGS))]>,
947 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
948 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
949 "cmovae\t{$src2, $dst|$dst, $src2}",
950 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
951 X86_COND_AE, EFLAGS))]>,
953 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
954 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
955 "cmove\t{$src2, $dst|$dst, $src2}",
956 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
957 X86_COND_E, EFLAGS))]>,
959 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
960 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
961 "cmove\t{$src2, $dst|$dst, $src2}",
962 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
963 X86_COND_E, EFLAGS))]>,
965 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
966 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
967 "cmovne\t{$src2, $dst|$dst, $src2}",
968 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
969 X86_COND_NE, EFLAGS))]>,
971 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
972 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
973 "cmovne\t{$src2, $dst|$dst, $src2}",
974 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
975 X86_COND_NE, EFLAGS))]>,
977 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
978 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
979 "cmovbe\t{$src2, $dst|$dst, $src2}",
980 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
981 X86_COND_BE, EFLAGS))]>,
983 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
984 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
985 "cmovbe\t{$src2, $dst|$dst, $src2}",
986 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
987 X86_COND_BE, EFLAGS))]>,
989 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
990 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
991 "cmova\t{$src2, $dst|$dst, $src2}",
992 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
993 X86_COND_A, EFLAGS))]>,
995 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
996 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
997 "cmova\t{$src2, $dst|$dst, $src2}",
998 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
999 X86_COND_A, EFLAGS))]>,
1001 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1002 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1003 "cmovl\t{$src2, $dst|$dst, $src2}",
1004 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1005 X86_COND_L, EFLAGS))]>,
1007 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1008 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1009 "cmovl\t{$src2, $dst|$dst, $src2}",
1010 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1011 X86_COND_L, EFLAGS))]>,
1013 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1014 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1015 "cmovge\t{$src2, $dst|$dst, $src2}",
1016 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1017 X86_COND_GE, EFLAGS))]>,
1019 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1020 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1021 "cmovge\t{$src2, $dst|$dst, $src2}",
1022 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1023 X86_COND_GE, EFLAGS))]>,
1025 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1026 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1027 "cmovle\t{$src2, $dst|$dst, $src2}",
1028 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1029 X86_COND_LE, EFLAGS))]>,
1031 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1032 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1033 "cmovle\t{$src2, $dst|$dst, $src2}",
1034 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1035 X86_COND_LE, EFLAGS))]>,
1037 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1038 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1039 "cmovg\t{$src2, $dst|$dst, $src2}",
1040 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1041 X86_COND_G, EFLAGS))]>,
1043 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1044 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1045 "cmovg\t{$src2, $dst|$dst, $src2}",
1046 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1047 X86_COND_G, EFLAGS))]>,
1049 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1050 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1051 "cmovs\t{$src2, $dst|$dst, $src2}",
1052 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1053 X86_COND_S, EFLAGS))]>,
1055 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1056 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1057 "cmovs\t{$src2, $dst|$dst, $src2}",
1058 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1059 X86_COND_S, EFLAGS))]>,
1061 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1062 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1063 "cmovns\t{$src2, $dst|$dst, $src2}",
1064 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1065 X86_COND_NS, EFLAGS))]>,
1067 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1068 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1069 "cmovns\t{$src2, $dst|$dst, $src2}",
1070 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1071 X86_COND_NS, EFLAGS))]>,
1073 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1074 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1075 "cmovp\t{$src2, $dst|$dst, $src2}",
1076 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1077 X86_COND_P, EFLAGS))]>,
1079 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1080 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1081 "cmovp\t{$src2, $dst|$dst, $src2}",
1082 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1083 X86_COND_P, EFLAGS))]>,
1085 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1086 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1087 "cmovnp\t{$src2, $dst|$dst, $src2}",
1088 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1089 X86_COND_NP, EFLAGS))]>,
1091 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1092 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1093 "cmovnp\t{$src2, $dst|$dst, $src2}",
1094 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1095 X86_COND_NP, EFLAGS))]>,
1097 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1098 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1099 "cmovo\t{$src2, $dst|$dst, $src2}",
1100 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1101 X86_COND_O, EFLAGS))]>,
1103 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1104 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1105 "cmovo\t{$src2, $dst|$dst, $src2}",
1106 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1107 X86_COND_O, EFLAGS))]>,
1109 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1110 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1111 "cmovno\t{$src2, $dst|$dst, $src2}",
1112 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1113 X86_COND_NO, EFLAGS))]>,
1115 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1116 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1117 "cmovno\t{$src2, $dst|$dst, $src2}",
1118 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1119 X86_COND_NO, EFLAGS))]>,
1121 } // isCommutable = 1
1123 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1124 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1125 "cmovb\t{$src2, $dst|$dst, $src2}",
1126 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1127 X86_COND_B, EFLAGS))]>,
1129 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1130 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1131 "cmovb\t{$src2, $dst|$dst, $src2}",
1132 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1133 X86_COND_B, EFLAGS))]>,
1135 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1136 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1137 "cmovae\t{$src2, $dst|$dst, $src2}",
1138 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1139 X86_COND_AE, EFLAGS))]>,
1141 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1142 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1143 "cmovae\t{$src2, $dst|$dst, $src2}",
1144 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1145 X86_COND_AE, EFLAGS))]>,
1147 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1148 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1149 "cmove\t{$src2, $dst|$dst, $src2}",
1150 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1151 X86_COND_E, EFLAGS))]>,
1153 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1154 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1155 "cmove\t{$src2, $dst|$dst, $src2}",
1156 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1157 X86_COND_E, EFLAGS))]>,
1159 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1160 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1161 "cmovne\t{$src2, $dst|$dst, $src2}",
1162 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1163 X86_COND_NE, EFLAGS))]>,
1165 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1166 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1167 "cmovne\t{$src2, $dst|$dst, $src2}",
1168 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1169 X86_COND_NE, EFLAGS))]>,
1171 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1172 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1173 "cmovbe\t{$src2, $dst|$dst, $src2}",
1174 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1175 X86_COND_BE, EFLAGS))]>,
1177 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1178 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1179 "cmovbe\t{$src2, $dst|$dst, $src2}",
1180 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1181 X86_COND_BE, EFLAGS))]>,
1183 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1184 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1185 "cmova\t{$src2, $dst|$dst, $src2}",
1186 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1187 X86_COND_A, EFLAGS))]>,
1189 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1190 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1191 "cmova\t{$src2, $dst|$dst, $src2}",
1192 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1193 X86_COND_A, EFLAGS))]>,
1195 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1196 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1197 "cmovl\t{$src2, $dst|$dst, $src2}",
1198 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1199 X86_COND_L, EFLAGS))]>,
1201 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1202 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1203 "cmovl\t{$src2, $dst|$dst, $src2}",
1204 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1205 X86_COND_L, EFLAGS))]>,
1207 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1208 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1209 "cmovge\t{$src2, $dst|$dst, $src2}",
1210 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1211 X86_COND_GE, EFLAGS))]>,
1213 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1214 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1215 "cmovge\t{$src2, $dst|$dst, $src2}",
1216 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1217 X86_COND_GE, EFLAGS))]>,
1219 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1220 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1221 "cmovle\t{$src2, $dst|$dst, $src2}",
1222 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1223 X86_COND_LE, EFLAGS))]>,
1225 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1226 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1227 "cmovle\t{$src2, $dst|$dst, $src2}",
1228 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1229 X86_COND_LE, EFLAGS))]>,
1231 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1232 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1233 "cmovg\t{$src2, $dst|$dst, $src2}",
1234 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1235 X86_COND_G, EFLAGS))]>,
1237 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1238 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1239 "cmovg\t{$src2, $dst|$dst, $src2}",
1240 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1241 X86_COND_G, EFLAGS))]>,
1243 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1244 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1245 "cmovs\t{$src2, $dst|$dst, $src2}",
1246 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1247 X86_COND_S, EFLAGS))]>,
1249 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1250 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1251 "cmovs\t{$src2, $dst|$dst, $src2}",
1252 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1253 X86_COND_S, EFLAGS))]>,
1255 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1256 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1257 "cmovns\t{$src2, $dst|$dst, $src2}",
1258 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1259 X86_COND_NS, EFLAGS))]>,
1261 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1262 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1263 "cmovns\t{$src2, $dst|$dst, $src2}",
1264 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1265 X86_COND_NS, EFLAGS))]>,
1267 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1268 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1269 "cmovp\t{$src2, $dst|$dst, $src2}",
1270 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1271 X86_COND_P, EFLAGS))]>,
1273 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1274 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1275 "cmovp\t{$src2, $dst|$dst, $src2}",
1276 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1277 X86_COND_P, EFLAGS))]>,
1279 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1280 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1281 "cmovnp\t{$src2, $dst|$dst, $src2}",
1282 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1283 X86_COND_NP, EFLAGS))]>,
1285 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1286 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1287 "cmovnp\t{$src2, $dst|$dst, $src2}",
1288 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1289 X86_COND_NP, EFLAGS))]>,
1291 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1292 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1293 "cmovo\t{$src2, $dst|$dst, $src2}",
1294 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1295 X86_COND_O, EFLAGS))]>,
1297 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1298 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1299 "cmovo\t{$src2, $dst|$dst, $src2}",
1300 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1301 X86_COND_O, EFLAGS))]>,
1303 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1304 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1305 "cmovno\t{$src2, $dst|$dst, $src2}",
1306 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1307 X86_COND_NO, EFLAGS))]>,
1309 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1310 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1311 "cmovno\t{$src2, $dst|$dst, $src2}",
1312 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1313 X86_COND_NO, EFLAGS))]>,
1315 } // Uses = [EFLAGS]
1318 // unary instructions
1319 let CodeSize = 2 in {
1320 let Defs = [EFLAGS] in {
1321 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1322 [(set GR8:$dst, (ineg GR8:$src)),
1323 (implicit EFLAGS)]>;
1324 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1325 [(set GR16:$dst, (ineg GR16:$src)),
1326 (implicit EFLAGS)]>, OpSize;
1327 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1328 [(set GR32:$dst, (ineg GR32:$src)),
1329 (implicit EFLAGS)]>;
1330 let isTwoAddress = 0 in {
1331 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1332 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1333 (implicit EFLAGS)]>;
1334 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1335 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1336 (implicit EFLAGS)]>, OpSize;
1337 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1339 (implicit EFLAGS)]>;
1341 } // Defs = [EFLAGS]
1343 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1344 let AddedComplexity = 15 in {
1345 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1346 [(set GR8:$dst, (not GR8:$src))]>;
1347 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1348 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1349 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1350 [(set GR32:$dst, (not GR32:$src))]>;
1352 let isTwoAddress = 0 in {
1353 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1354 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1355 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1356 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1357 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1358 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1362 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1363 let Defs = [EFLAGS] in {
1365 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1366 [(set GR8:$dst, (add GR8:$src, 1)),
1367 (implicit EFLAGS)]>;
1368 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1369 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1370 [(set GR16:$dst, (add GR16:$src, 1)),
1371 (implicit EFLAGS)]>,
1372 OpSize, Requires<[In32BitMode]>;
1373 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1374 [(set GR32:$dst, (add GR32:$src, 1)),
1375 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1377 let isTwoAddress = 0, CodeSize = 2 in {
1378 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1379 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1380 (implicit EFLAGS)]>;
1381 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1382 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1383 (implicit EFLAGS)]>,
1384 OpSize, Requires<[In32BitMode]>;
1385 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1386 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1387 (implicit EFLAGS)]>,
1388 Requires<[In32BitMode]>;
1392 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1393 [(set GR8:$dst, (add GR8:$src, -1)),
1394 (implicit EFLAGS)]>;
1395 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1396 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1397 [(set GR16:$dst, (add GR16:$src, -1)),
1398 (implicit EFLAGS)]>,
1399 OpSize, Requires<[In32BitMode]>;
1400 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1401 [(set GR32:$dst, (add GR32:$src, -1)),
1402 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1405 let isTwoAddress = 0, CodeSize = 2 in {
1406 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1407 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1408 (implicit EFLAGS)]>;
1409 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1410 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1411 (implicit EFLAGS)]>,
1412 OpSize, Requires<[In32BitMode]>;
1413 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1414 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1415 (implicit EFLAGS)]>,
1416 Requires<[In32BitMode]>;
1418 } // Defs = [EFLAGS]
1420 // Logical operators...
1421 let Defs = [EFLAGS] in {
1422 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1423 def AND8rr : I<0x20, MRMDestReg,
1424 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1425 "and{b}\t{$src2, $dst|$dst, $src2}",
1426 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1427 (implicit EFLAGS)]>;
1428 def AND16rr : I<0x21, MRMDestReg,
1429 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1430 "and{w}\t{$src2, $dst|$dst, $src2}",
1431 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1432 (implicit EFLAGS)]>, OpSize;
1433 def AND32rr : I<0x21, MRMDestReg,
1434 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1435 "and{l}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1437 (implicit EFLAGS)]>;
1440 def AND8rm : I<0x22, MRMSrcMem,
1441 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1442 "and{b}\t{$src2, $dst|$dst, $src2}",
1443 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1444 (implicit EFLAGS)]>;
1445 def AND16rm : I<0x23, MRMSrcMem,
1446 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1447 "and{w}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1449 (implicit EFLAGS)]>, OpSize;
1450 def AND32rm : I<0x23, MRMSrcMem,
1451 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1452 "and{l}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1454 (implicit EFLAGS)]>;
1456 def AND8ri : Ii8<0x80, MRM4r,
1457 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1458 "and{b}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1460 (implicit EFLAGS)]>;
1461 def AND16ri : Ii16<0x81, MRM4r,
1462 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1463 "and{w}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1465 (implicit EFLAGS)]>, OpSize;
1466 def AND32ri : Ii32<0x81, MRM4r,
1467 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1468 "and{l}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1470 (implicit EFLAGS)]>;
1471 def AND16ri8 : Ii8<0x83, MRM4r,
1472 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1473 "and{w}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1475 (implicit EFLAGS)]>,
1477 def AND32ri8 : Ii8<0x83, MRM4r,
1478 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1479 "and{l}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1481 (implicit EFLAGS)]>;
1483 let isTwoAddress = 0 in {
1484 def AND8mr : I<0x20, MRMDestMem,
1485 (outs), (ins i8mem :$dst, GR8 :$src),
1486 "and{b}\t{$src, $dst|$dst, $src}",
1487 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1488 (implicit EFLAGS)]>;
1489 def AND16mr : I<0x21, MRMDestMem,
1490 (outs), (ins i16mem:$dst, GR16:$src),
1491 "and{w}\t{$src, $dst|$dst, $src}",
1492 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1493 (implicit EFLAGS)]>,
1495 def AND32mr : I<0x21, MRMDestMem,
1496 (outs), (ins i32mem:$dst, GR32:$src),
1497 "and{l}\t{$src, $dst|$dst, $src}",
1498 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1499 (implicit EFLAGS)]>;
1500 def AND8mi : Ii8<0x80, MRM4m,
1501 (outs), (ins i8mem :$dst, i8imm :$src),
1502 "and{b}\t{$src, $dst|$dst, $src}",
1503 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1504 (implicit EFLAGS)]>;
1505 def AND16mi : Ii16<0x81, MRM4m,
1506 (outs), (ins i16mem:$dst, i16imm:$src),
1507 "and{w}\t{$src, $dst|$dst, $src}",
1508 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1509 (implicit EFLAGS)]>,
1511 def AND32mi : Ii32<0x81, MRM4m,
1512 (outs), (ins i32mem:$dst, i32imm:$src),
1513 "and{l}\t{$src, $dst|$dst, $src}",
1514 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1515 (implicit EFLAGS)]>;
1516 def AND16mi8 : Ii8<0x83, MRM4m,
1517 (outs), (ins i16mem:$dst, i16i8imm :$src),
1518 "and{w}\t{$src, $dst|$dst, $src}",
1519 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1520 (implicit EFLAGS)]>,
1522 def AND32mi8 : Ii8<0x83, MRM4m,
1523 (outs), (ins i32mem:$dst, i32i8imm :$src),
1524 "and{l}\t{$src, $dst|$dst, $src}",
1525 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1526 (implicit EFLAGS)]>;
1530 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1531 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1532 "or{b}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1534 (implicit EFLAGS)]>;
1535 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1536 "or{w}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1538 (implicit EFLAGS)]>, OpSize;
1539 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1540 "or{l}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1542 (implicit EFLAGS)]>;
1544 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1545 "or{b}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1547 (implicit EFLAGS)]>;
1548 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1549 "or{w}\t{$src2, $dst|$dst, $src2}",
1550 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1551 (implicit EFLAGS)]>, OpSize;
1552 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1553 "or{l}\t{$src2, $dst|$dst, $src2}",
1554 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1555 (implicit EFLAGS)]>;
1557 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1558 "or{b}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1560 (implicit EFLAGS)]>;
1561 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1562 "or{w}\t{$src2, $dst|$dst, $src2}",
1563 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1564 (implicit EFLAGS)]>, OpSize;
1565 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1566 "or{l}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1568 (implicit EFLAGS)]>;
1570 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1571 "or{w}\t{$src2, $dst|$dst, $src2}",
1572 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1573 (implicit EFLAGS)]>, OpSize;
1574 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1575 "or{l}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1577 (implicit EFLAGS)]>;
1578 let isTwoAddress = 0 in {
1579 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1580 "or{b}\t{$src, $dst|$dst, $src}",
1581 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1582 (implicit EFLAGS)]>;
1583 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1584 "or{w}\t{$src, $dst|$dst, $src}",
1585 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1586 (implicit EFLAGS)]>, OpSize;
1587 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1588 "or{l}\t{$src, $dst|$dst, $src}",
1589 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1590 (implicit EFLAGS)]>;
1591 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1592 "or{b}\t{$src, $dst|$dst, $src}",
1593 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1594 (implicit EFLAGS)]>;
1595 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1596 "or{w}\t{$src, $dst|$dst, $src}",
1597 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1598 (implicit EFLAGS)]>,
1600 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1601 "or{l}\t{$src, $dst|$dst, $src}",
1602 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1603 (implicit EFLAGS)]>;
1604 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1605 "or{w}\t{$src, $dst|$dst, $src}",
1606 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1607 (implicit EFLAGS)]>,
1609 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1610 "or{l}\t{$src, $dst|$dst, $src}",
1611 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1612 (implicit EFLAGS)]>;
1613 } // isTwoAddress = 0
1616 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1617 def XOR8rr : I<0x30, MRMDestReg,
1618 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1619 "xor{b}\t{$src2, $dst|$dst, $src2}",
1620 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1621 (implicit EFLAGS)]>;
1622 def XOR16rr : I<0x31, MRMDestReg,
1623 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1624 "xor{w}\t{$src2, $dst|$dst, $src2}",
1625 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1626 (implicit EFLAGS)]>, OpSize;
1627 def XOR32rr : I<0x31, MRMDestReg,
1628 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1629 "xor{l}\t{$src2, $dst|$dst, $src2}",
1630 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1631 (implicit EFLAGS)]>;
1632 } // isCommutable = 1
1634 def XOR8rm : I<0x32, MRMSrcMem ,
1635 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1636 "xor{b}\t{$src2, $dst|$dst, $src2}",
1637 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1638 (implicit EFLAGS)]>;
1639 def XOR16rm : I<0x33, MRMSrcMem ,
1640 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1641 "xor{w}\t{$src2, $dst|$dst, $src2}",
1642 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1643 (implicit EFLAGS)]>,
1645 def XOR32rm : I<0x33, MRMSrcMem ,
1646 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1647 "xor{l}\t{$src2, $dst|$dst, $src2}",
1648 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1649 (implicit EFLAGS)]>;
1651 def XOR8ri : Ii8<0x80, MRM6r,
1652 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1653 "xor{b}\t{$src2, $dst|$dst, $src2}",
1654 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1655 (implicit EFLAGS)]>;
1656 def XOR16ri : Ii16<0x81, MRM6r,
1657 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1658 "xor{w}\t{$src2, $dst|$dst, $src2}",
1659 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1660 (implicit EFLAGS)]>, OpSize;
1661 def XOR32ri : Ii32<0x81, MRM6r,
1662 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1663 "xor{l}\t{$src2, $dst|$dst, $src2}",
1664 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1665 (implicit EFLAGS)]>;
1666 def XOR16ri8 : Ii8<0x83, MRM6r,
1667 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1668 "xor{w}\t{$src2, $dst|$dst, $src2}",
1669 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1670 (implicit EFLAGS)]>,
1672 def XOR32ri8 : Ii8<0x83, MRM6r,
1673 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1674 "xor{l}\t{$src2, $dst|$dst, $src2}",
1675 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1676 (implicit EFLAGS)]>;
1678 let isTwoAddress = 0 in {
1679 def XOR8mr : I<0x30, MRMDestMem,
1680 (outs), (ins i8mem :$dst, GR8 :$src),
1681 "xor{b}\t{$src, $dst|$dst, $src}",
1682 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1683 (implicit EFLAGS)]>;
1684 def XOR16mr : I<0x31, MRMDestMem,
1685 (outs), (ins i16mem:$dst, GR16:$src),
1686 "xor{w}\t{$src, $dst|$dst, $src}",
1687 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1688 (implicit EFLAGS)]>,
1690 def XOR32mr : I<0x31, MRMDestMem,
1691 (outs), (ins i32mem:$dst, GR32:$src),
1692 "xor{l}\t{$src, $dst|$dst, $src}",
1693 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1694 (implicit EFLAGS)]>;
1695 def XOR8mi : Ii8<0x80, MRM6m,
1696 (outs), (ins i8mem :$dst, i8imm :$src),
1697 "xor{b}\t{$src, $dst|$dst, $src}",
1698 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1699 (implicit EFLAGS)]>;
1700 def XOR16mi : Ii16<0x81, MRM6m,
1701 (outs), (ins i16mem:$dst, i16imm:$src),
1702 "xor{w}\t{$src, $dst|$dst, $src}",
1703 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1704 (implicit EFLAGS)]>,
1706 def XOR32mi : Ii32<0x81, MRM6m,
1707 (outs), (ins i32mem:$dst, i32imm:$src),
1708 "xor{l}\t{$src, $dst|$dst, $src}",
1709 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1710 (implicit EFLAGS)]>;
1711 def XOR16mi8 : Ii8<0x83, MRM6m,
1712 (outs), (ins i16mem:$dst, i16i8imm :$src),
1713 "xor{w}\t{$src, $dst|$dst, $src}",
1714 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1715 (implicit EFLAGS)]>,
1717 def XOR32mi8 : Ii8<0x83, MRM6m,
1718 (outs), (ins i32mem:$dst, i32i8imm :$src),
1719 "xor{l}\t{$src, $dst|$dst, $src}",
1720 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1721 (implicit EFLAGS)]>;
1722 } // isTwoAddress = 0
1723 } // Defs = [EFLAGS]
1725 // Shift instructions
1726 let Defs = [EFLAGS] in {
1727 let Uses = [CL] in {
1728 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1729 "shl{b}\t{%cl, $dst|$dst, %CL}",
1730 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1731 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1732 "shl{w}\t{%cl, $dst|$dst, %CL}",
1733 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1734 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1735 "shl{l}\t{%cl, $dst|$dst, %CL}",
1736 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1739 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1740 "shl{b}\t{$src2, $dst|$dst, $src2}",
1741 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1742 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1743 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1744 "shl{w}\t{$src2, $dst|$dst, $src2}",
1745 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1746 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1747 "shl{l}\t{$src2, $dst|$dst, $src2}",
1748 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1749 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1751 } // isConvertibleToThreeAddress = 1
1753 let isTwoAddress = 0 in {
1754 let Uses = [CL] in {
1755 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1756 "shl{b}\t{%cl, $dst|$dst, %CL}",
1757 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1758 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1759 "shl{w}\t{%cl, $dst|$dst, %CL}",
1760 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1761 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1762 "shl{l}\t{%cl, $dst|$dst, %CL}",
1763 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1765 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1766 "shl{b}\t{$src, $dst|$dst, $src}",
1767 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1768 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1769 "shl{w}\t{$src, $dst|$dst, $src}",
1770 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1772 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1773 "shl{l}\t{$src, $dst|$dst, $src}",
1774 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1777 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1779 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1780 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1782 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1784 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1786 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1789 let Uses = [CL] in {
1790 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1791 "shr{b}\t{%cl, $dst|$dst, %CL}",
1792 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1793 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1794 "shr{w}\t{%cl, $dst|$dst, %CL}",
1795 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1796 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1797 "shr{l}\t{%cl, $dst|$dst, %CL}",
1798 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1801 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1802 "shr{b}\t{$src2, $dst|$dst, $src2}",
1803 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1804 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1805 "shr{w}\t{$src2, $dst|$dst, $src2}",
1806 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1807 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1808 "shr{l}\t{$src2, $dst|$dst, $src2}",
1809 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1812 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1814 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1815 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1817 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1818 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1820 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1822 let isTwoAddress = 0 in {
1823 let Uses = [CL] in {
1824 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1825 "shr{b}\t{%cl, $dst|$dst, %CL}",
1826 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1827 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1828 "shr{w}\t{%cl, $dst|$dst, %CL}",
1829 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1831 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1832 "shr{l}\t{%cl, $dst|$dst, %CL}",
1833 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1835 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1836 "shr{b}\t{$src, $dst|$dst, $src}",
1837 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1838 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1839 "shr{w}\t{$src, $dst|$dst, $src}",
1840 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1842 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1843 "shr{l}\t{$src, $dst|$dst, $src}",
1844 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1847 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1849 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1850 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1852 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1853 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1855 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1858 let Uses = [CL] in {
1859 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1860 "sar{b}\t{%cl, $dst|$dst, %CL}",
1861 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1862 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1863 "sar{w}\t{%cl, $dst|$dst, %CL}",
1864 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1865 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1866 "sar{l}\t{%cl, $dst|$dst, %CL}",
1867 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1870 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1871 "sar{b}\t{$src2, $dst|$dst, $src2}",
1872 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1873 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1874 "sar{w}\t{$src2, $dst|$dst, $src2}",
1875 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1877 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1878 "sar{l}\t{$src2, $dst|$dst, $src2}",
1879 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1882 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1884 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1885 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1887 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1888 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1890 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1892 let isTwoAddress = 0 in {
1893 let Uses = [CL] in {
1894 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1895 "sar{b}\t{%cl, $dst|$dst, %CL}",
1896 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1897 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1898 "sar{w}\t{%cl, $dst|$dst, %CL}",
1899 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1900 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1901 "sar{l}\t{%cl, $dst|$dst, %CL}",
1902 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1904 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1905 "sar{b}\t{$src, $dst|$dst, $src}",
1906 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1907 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1908 "sar{w}\t{$src, $dst|$dst, $src}",
1909 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1911 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1912 "sar{l}\t{$src, $dst|$dst, $src}",
1913 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1916 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1918 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1919 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1921 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1923 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1925 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1928 // Rotate instructions
1929 // FIXME: provide shorter instructions when imm8 == 1
1930 let Uses = [CL] in {
1931 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1932 "rol{b}\t{%cl, $dst|$dst, %CL}",
1933 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1934 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1935 "rol{w}\t{%cl, $dst|$dst, %CL}",
1936 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1937 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1938 "rol{l}\t{%cl, $dst|$dst, %CL}",
1939 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1942 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1943 "rol{b}\t{$src2, $dst|$dst, $src2}",
1944 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1945 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1946 "rol{w}\t{$src2, $dst|$dst, $src2}",
1947 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1948 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1949 "rol{l}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1953 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1955 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1956 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1958 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1959 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1961 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1963 let isTwoAddress = 0 in {
1964 let Uses = [CL] in {
1965 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1966 "rol{b}\t{%cl, $dst|$dst, %CL}",
1967 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1968 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1969 "rol{w}\t{%cl, $dst|$dst, %CL}",
1970 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1971 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1972 "rol{l}\t{%cl, $dst|$dst, %CL}",
1973 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1975 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1976 "rol{b}\t{$src, $dst|$dst, $src}",
1977 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1978 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1979 "rol{w}\t{$src, $dst|$dst, $src}",
1980 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1982 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1983 "rol{l}\t{$src, $dst|$dst, $src}",
1984 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1987 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1989 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1990 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1992 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1994 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1996 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1999 let Uses = [CL] in {
2000 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2001 "ror{b}\t{%cl, $dst|$dst, %CL}",
2002 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2003 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2004 "ror{w}\t{%cl, $dst|$dst, %CL}",
2005 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2006 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2007 "ror{l}\t{%cl, $dst|$dst, %CL}",
2008 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2011 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2012 "ror{b}\t{$src2, $dst|$dst, $src2}",
2013 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2014 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2015 "ror{w}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2017 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2018 "ror{l}\t{$src2, $dst|$dst, $src2}",
2019 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2022 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2024 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2025 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2027 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2028 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2030 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2032 let isTwoAddress = 0 in {
2033 let Uses = [CL] in {
2034 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2035 "ror{b}\t{%cl, $dst|$dst, %CL}",
2036 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2037 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2038 "ror{w}\t{%cl, $dst|$dst, %CL}",
2039 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2040 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2041 "ror{l}\t{%cl, $dst|$dst, %CL}",
2042 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2044 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2045 "ror{b}\t{$src, $dst|$dst, $src}",
2046 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2047 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2048 "ror{w}\t{$src, $dst|$dst, $src}",
2049 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2051 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2052 "ror{l}\t{$src, $dst|$dst, $src}",
2053 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2056 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2058 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2059 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2061 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2063 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2065 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2070 // Double shift instructions (generalizations of rotate)
2071 let Uses = [CL] in {
2072 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2073 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2074 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2075 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2076 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2077 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2078 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2079 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2080 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2082 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2083 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2084 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2088 let isCommutable = 1 in { // These instructions commute to each other.
2089 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2090 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2091 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2092 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2095 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2096 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2097 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2098 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2101 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2102 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2103 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2104 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2107 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2108 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2109 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2110 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2115 let isTwoAddress = 0 in {
2116 let Uses = [CL] in {
2117 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2118 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2119 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2121 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2122 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2123 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2126 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2127 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2128 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2129 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2130 (i8 imm:$src3)), addr:$dst)]>,
2132 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2133 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2134 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2135 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2136 (i8 imm:$src3)), addr:$dst)]>,
2139 let Uses = [CL] in {
2140 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2141 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2142 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2143 addr:$dst)]>, TB, OpSize;
2144 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2145 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2146 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2147 addr:$dst)]>, TB, OpSize;
2149 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2150 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2151 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2152 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2153 (i8 imm:$src3)), addr:$dst)]>,
2155 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2156 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2157 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2158 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2159 (i8 imm:$src3)), addr:$dst)]>,
2162 } // Defs = [EFLAGS]
2166 let Defs = [EFLAGS] in {
2167 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2168 // Register-Register Addition
2169 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2170 (ins GR8 :$src1, GR8 :$src2),
2171 "add{b}\t{$src2, $dst|$dst, $src2}",
2172 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2173 (implicit EFLAGS)]>;
2175 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2176 // Register-Register Addition
2177 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2178 (ins GR16:$src1, GR16:$src2),
2179 "add{w}\t{$src2, $dst|$dst, $src2}",
2180 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2181 (implicit EFLAGS)]>, OpSize;
2182 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2183 (ins GR32:$src1, GR32:$src2),
2184 "add{l}\t{$src2, $dst|$dst, $src2}",
2185 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2186 (implicit EFLAGS)]>;
2187 } // end isConvertibleToThreeAddress
2188 } // end isCommutable
2190 // Register-Memory Addition
2191 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2192 (ins GR8 :$src1, i8mem :$src2),
2193 "add{b}\t{$src2, $dst|$dst, $src2}",
2194 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2195 (implicit EFLAGS)]>;
2196 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2197 (ins GR16:$src1, i16mem:$src2),
2198 "add{w}\t{$src2, $dst|$dst, $src2}",
2199 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2200 (implicit EFLAGS)]>, OpSize;
2201 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2202 (ins GR32:$src1, i32mem:$src2),
2203 "add{l}\t{$src2, $dst|$dst, $src2}",
2204 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2205 (implicit EFLAGS)]>;
2207 // Register-Integer Addition
2208 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2209 "add{b}\t{$src2, $dst|$dst, $src2}",
2210 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2211 (implicit EFLAGS)]>;
2213 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2214 // Register-Integer Addition
2215 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2216 (ins GR16:$src1, i16imm:$src2),
2217 "add{w}\t{$src2, $dst|$dst, $src2}",
2218 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2219 (implicit EFLAGS)]>, OpSize;
2220 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2221 (ins GR32:$src1, i32imm:$src2),
2222 "add{l}\t{$src2, $dst|$dst, $src2}",
2223 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2224 (implicit EFLAGS)]>;
2225 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2226 (ins GR16:$src1, i16i8imm:$src2),
2227 "add{w}\t{$src2, $dst|$dst, $src2}",
2228 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2229 (implicit EFLAGS)]>, OpSize;
2230 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2231 (ins GR32:$src1, i32i8imm:$src2),
2232 "add{l}\t{$src2, $dst|$dst, $src2}",
2233 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2234 (implicit EFLAGS)]>;
2237 let isTwoAddress = 0 in {
2238 // Memory-Register Addition
2239 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2240 "add{b}\t{$src2, $dst|$dst, $src2}",
2241 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2242 (implicit EFLAGS)]>;
2243 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2244 "add{w}\t{$src2, $dst|$dst, $src2}",
2245 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2246 (implicit EFLAGS)]>, OpSize;
2247 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2248 "add{l}\t{$src2, $dst|$dst, $src2}",
2249 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2250 (implicit EFLAGS)]>;
2251 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2252 "add{b}\t{$src2, $dst|$dst, $src2}",
2253 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2254 (implicit EFLAGS)]>;
2255 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2256 "add{w}\t{$src2, $dst|$dst, $src2}",
2257 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2258 (implicit EFLAGS)]>, OpSize;
2259 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2260 "add{l}\t{$src2, $dst|$dst, $src2}",
2261 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2262 (implicit EFLAGS)]>;
2263 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2264 "add{w}\t{$src2, $dst|$dst, $src2}",
2265 [(store (add (load addr:$dst), i16immSExt8:$src2),
2267 (implicit EFLAGS)]>, OpSize;
2268 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2269 "add{l}\t{$src2, $dst|$dst, $src2}",
2270 [(store (add (load addr:$dst), i32immSExt8:$src2),
2272 (implicit EFLAGS)]>;
2275 let Uses = [EFLAGS] in {
2276 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2277 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2278 "adc{b}\t{$src2, $dst|$dst, $src2}",
2279 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2280 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2281 (ins GR16:$src1, GR16:$src2),
2282 "adc{w}\t{$src2, $dst|$dst, $src2}",
2283 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2284 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2285 (ins GR32:$src1, GR32:$src2),
2286 "adc{l}\t{$src2, $dst|$dst, $src2}",
2287 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2289 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2290 (ins GR8:$src1, i8mem:$src2),
2291 "adc{b}\t{$src2, $dst|$dst, $src2}",
2292 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2293 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2294 (ins GR16:$src1, i16mem:$src2),
2295 "adc{w}\t{$src2, $dst|$dst, $src2}",
2296 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2298 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2299 (ins GR32:$src1, i32mem:$src2),
2300 "adc{l}\t{$src2, $dst|$dst, $src2}",
2301 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2302 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2303 "adc{b}\t{$src2, $dst|$dst, $src2}",
2304 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2305 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2306 (ins GR16:$src1, i16imm:$src2),
2307 "adc{w}\t{$src2, $dst|$dst, $src2}",
2308 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2309 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2310 (ins GR16:$src1, i16i8imm:$src2),
2311 "adc{w}\t{$src2, $dst|$dst, $src2}",
2312 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2314 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2315 (ins GR32:$src1, i32imm:$src2),
2316 "adc{l}\t{$src2, $dst|$dst, $src2}",
2317 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2318 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2319 (ins GR32:$src1, i32i8imm:$src2),
2320 "adc{l}\t{$src2, $dst|$dst, $src2}",
2321 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2323 let isTwoAddress = 0 in {
2324 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2325 "adc{b}\t{$src2, $dst|$dst, $src2}",
2326 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2327 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2328 "adc{w}\t{$src2, $dst|$dst, $src2}",
2329 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2331 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2332 "adc{l}\t{$src2, $dst|$dst, $src2}",
2333 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2334 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2335 "adc{b}\t{$src2, $dst|$dst, $src2}",
2336 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2337 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2338 "adc{w}\t{$src2, $dst|$dst, $src2}",
2339 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2341 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2342 "adc{w}\t{$src2, $dst|$dst, $src2}",
2343 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2345 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2346 "adc{l}\t{$src2, $dst|$dst, $src2}",
2347 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2348 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2349 "adc{l}\t{$src2, $dst|$dst, $src2}",
2350 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2352 } // Uses = [EFLAGS]
2354 // Register-Register Subtraction
2355 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2356 "sub{b}\t{$src2, $dst|$dst, $src2}",
2357 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2358 (implicit EFLAGS)]>;
2359 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2360 "sub{w}\t{$src2, $dst|$dst, $src2}",
2361 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2362 (implicit EFLAGS)]>, OpSize;
2363 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2364 "sub{l}\t{$src2, $dst|$dst, $src2}",
2365 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2366 (implicit EFLAGS)]>;
2368 // Register-Memory Subtraction
2369 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2370 (ins GR8 :$src1, i8mem :$src2),
2371 "sub{b}\t{$src2, $dst|$dst, $src2}",
2372 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2373 (implicit EFLAGS)]>;
2374 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2375 (ins GR16:$src1, i16mem:$src2),
2376 "sub{w}\t{$src2, $dst|$dst, $src2}",
2377 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2378 (implicit EFLAGS)]>, OpSize;
2379 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2380 (ins GR32:$src1, i32mem:$src2),
2381 "sub{l}\t{$src2, $dst|$dst, $src2}",
2382 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2383 (implicit EFLAGS)]>;
2385 // Register-Integer Subtraction
2386 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2387 (ins GR8:$src1, i8imm:$src2),
2388 "sub{b}\t{$src2, $dst|$dst, $src2}",
2389 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2390 (implicit EFLAGS)]>;
2391 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2392 (ins GR16:$src1, i16imm:$src2),
2393 "sub{w}\t{$src2, $dst|$dst, $src2}",
2394 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2395 (implicit EFLAGS)]>, OpSize;
2396 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2397 (ins GR32:$src1, i32imm:$src2),
2398 "sub{l}\t{$src2, $dst|$dst, $src2}",
2399 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2400 (implicit EFLAGS)]>;
2401 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2402 (ins GR16:$src1, i16i8imm:$src2),
2403 "sub{w}\t{$src2, $dst|$dst, $src2}",
2404 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2405 (implicit EFLAGS)]>, OpSize;
2406 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2407 (ins GR32:$src1, i32i8imm:$src2),
2408 "sub{l}\t{$src2, $dst|$dst, $src2}",
2409 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2410 (implicit EFLAGS)]>;
2412 let isTwoAddress = 0 in {
2413 // Memory-Register Subtraction
2414 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2415 "sub{b}\t{$src2, $dst|$dst, $src2}",
2416 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2417 (implicit EFLAGS)]>;
2418 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2419 "sub{w}\t{$src2, $dst|$dst, $src2}",
2420 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2421 (implicit EFLAGS)]>, OpSize;
2422 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2423 "sub{l}\t{$src2, $dst|$dst, $src2}",
2424 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2425 (implicit EFLAGS)]>;
2427 // Memory-Integer Subtraction
2428 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2429 "sub{b}\t{$src2, $dst|$dst, $src2}",
2430 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2431 (implicit EFLAGS)]>;
2432 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2433 "sub{w}\t{$src2, $dst|$dst, $src2}",
2434 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2435 (implicit EFLAGS)]>, OpSize;
2436 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2437 "sub{l}\t{$src2, $dst|$dst, $src2}",
2438 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2439 (implicit EFLAGS)]>;
2440 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2441 "sub{w}\t{$src2, $dst|$dst, $src2}",
2442 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2444 (implicit EFLAGS)]>, OpSize;
2445 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2446 "sub{l}\t{$src2, $dst|$dst, $src2}",
2447 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2449 (implicit EFLAGS)]>;
2452 let Uses = [EFLAGS] in {
2453 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2454 (ins GR8:$src1, GR8:$src2),
2455 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2456 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2457 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2458 (ins GR16:$src1, GR16:$src2),
2459 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2460 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2461 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2462 (ins GR32:$src1, GR32:$src2),
2463 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2464 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2466 let isTwoAddress = 0 in {
2467 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2468 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2469 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2470 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2471 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2472 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2474 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2475 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2476 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2477 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2478 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2479 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2480 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2481 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2482 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2484 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2485 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2486 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2488 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2489 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2490 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2491 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2492 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2493 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2495 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2496 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2497 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2498 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2499 (ins GR16:$src1, i16mem:$src2),
2500 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2501 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2503 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2504 (ins GR32:$src1, i32mem:$src2),
2505 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2506 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2507 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2508 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2509 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2510 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2511 (ins GR16:$src1, i16imm:$src2),
2512 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2513 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2514 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2515 (ins GR16:$src1, i16i8imm:$src2),
2516 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2517 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2519 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2520 (ins GR32:$src1, i32imm:$src2),
2521 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2522 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2523 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2524 (ins GR32:$src1, i32i8imm:$src2),
2525 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2526 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2527 } // Uses = [EFLAGS]
2528 } // Defs = [EFLAGS]
2530 let Defs = [EFLAGS] in {
2531 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2532 // Register-Register Signed Integer Multiply
2533 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2534 "imul{w}\t{$src2, $dst|$dst, $src2}",
2535 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2536 (implicit EFLAGS)]>, TB, OpSize;
2537 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2538 "imul{l}\t{$src2, $dst|$dst, $src2}",
2539 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2540 (implicit EFLAGS)]>, TB;
2543 // Register-Memory Signed Integer Multiply
2544 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2545 (ins GR16:$src1, i16mem:$src2),
2546 "imul{w}\t{$src2, $dst|$dst, $src2}",
2547 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2548 (implicit EFLAGS)]>, TB, OpSize;
2549 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2550 "imul{l}\t{$src2, $dst|$dst, $src2}",
2551 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2552 (implicit EFLAGS)]>, TB;
2553 } // Defs = [EFLAGS]
2554 } // end Two Address instructions
2556 // Suprisingly enough, these are not two address instructions!
2557 let Defs = [EFLAGS] in {
2558 // Register-Integer Signed Integer Multiply
2559 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2560 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2561 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2562 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2563 (implicit EFLAGS)]>, OpSize;
2564 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2565 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2566 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2567 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2568 (implicit EFLAGS)]>;
2569 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2570 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2571 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2572 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2573 (implicit EFLAGS)]>, OpSize;
2574 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2575 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2576 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2577 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2578 (implicit EFLAGS)]>;
2580 // Memory-Integer Signed Integer Multiply
2581 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2582 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2583 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2584 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2585 (implicit EFLAGS)]>, OpSize;
2586 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2587 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2588 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2589 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2590 (implicit EFLAGS)]>;
2591 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2592 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2593 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2594 [(set GR16:$dst, (mul (load addr:$src1),
2595 i16immSExt8:$src2)),
2596 (implicit EFLAGS)]>, OpSize;
2597 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2598 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2599 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2600 [(set GR32:$dst, (mul (load addr:$src1),
2601 i32immSExt8:$src2)),
2602 (implicit EFLAGS)]>;
2603 } // Defs = [EFLAGS]
2605 //===----------------------------------------------------------------------===//
2606 // Test instructions are just like AND, except they don't generate a result.
2608 let Defs = [EFLAGS] in {
2609 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2610 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2611 "test{b}\t{$src2, $src1|$src1, $src2}",
2612 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2613 (implicit EFLAGS)]>;
2614 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2615 "test{w}\t{$src2, $src1|$src1, $src2}",
2616 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2617 (implicit EFLAGS)]>,
2619 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2620 "test{l}\t{$src2, $src1|$src1, $src2}",
2621 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2622 (implicit EFLAGS)]>;
2625 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2626 "test{b}\t{$src2, $src1|$src1, $src2}",
2627 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2628 (implicit EFLAGS)]>;
2629 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2630 "test{w}\t{$src2, $src1|$src1, $src2}",
2631 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2632 (implicit EFLAGS)]>, OpSize;
2633 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2634 "test{l}\t{$src2, $src1|$src1, $src2}",
2635 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2636 (implicit EFLAGS)]>;
2638 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2639 (outs), (ins GR8:$src1, i8imm:$src2),
2640 "test{b}\t{$src2, $src1|$src1, $src2}",
2641 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2642 (implicit EFLAGS)]>;
2643 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2644 (outs), (ins GR16:$src1, i16imm:$src2),
2645 "test{w}\t{$src2, $src1|$src1, $src2}",
2646 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2647 (implicit EFLAGS)]>, OpSize;
2648 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2649 (outs), (ins GR32:$src1, i32imm:$src2),
2650 "test{l}\t{$src2, $src1|$src1, $src2}",
2651 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2652 (implicit EFLAGS)]>;
2654 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2655 (outs), (ins i8mem:$src1, i8imm:$src2),
2656 "test{b}\t{$src2, $src1|$src1, $src2}",
2657 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2658 (implicit EFLAGS)]>;
2659 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2660 (outs), (ins i16mem:$src1, i16imm:$src2),
2661 "test{w}\t{$src2, $src1|$src1, $src2}",
2662 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2663 (implicit EFLAGS)]>, OpSize;
2664 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2665 (outs), (ins i32mem:$src1, i32imm:$src2),
2666 "test{l}\t{$src2, $src1|$src1, $src2}",
2667 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2668 (implicit EFLAGS)]>;
2669 } // Defs = [EFLAGS]
2672 // Condition code ops, incl. set if equal/not equal/...
2673 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2674 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2675 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2676 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2678 let Uses = [EFLAGS] in {
2679 def SETEr : I<0x94, MRM0r,
2680 (outs GR8 :$dst), (ins),
2682 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2684 def SETEm : I<0x94, MRM0m,
2685 (outs), (ins i8mem:$dst),
2687 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2690 def SETNEr : I<0x95, MRM0r,
2691 (outs GR8 :$dst), (ins),
2693 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2695 def SETNEm : I<0x95, MRM0m,
2696 (outs), (ins i8mem:$dst),
2698 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2701 def SETLr : I<0x9C, MRM0r,
2702 (outs GR8 :$dst), (ins),
2704 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2705 TB; // GR8 = < signed
2706 def SETLm : I<0x9C, MRM0m,
2707 (outs), (ins i8mem:$dst),
2709 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2710 TB; // [mem8] = < signed
2712 def SETGEr : I<0x9D, MRM0r,
2713 (outs GR8 :$dst), (ins),
2715 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2716 TB; // GR8 = >= signed
2717 def SETGEm : I<0x9D, MRM0m,
2718 (outs), (ins i8mem:$dst),
2720 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2721 TB; // [mem8] = >= signed
2723 def SETLEr : I<0x9E, MRM0r,
2724 (outs GR8 :$dst), (ins),
2726 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2727 TB; // GR8 = <= signed
2728 def SETLEm : I<0x9E, MRM0m,
2729 (outs), (ins i8mem:$dst),
2731 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2732 TB; // [mem8] = <= signed
2734 def SETGr : I<0x9F, MRM0r,
2735 (outs GR8 :$dst), (ins),
2737 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2738 TB; // GR8 = > signed
2739 def SETGm : I<0x9F, MRM0m,
2740 (outs), (ins i8mem:$dst),
2742 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2743 TB; // [mem8] = > signed
2745 def SETBr : I<0x92, MRM0r,
2746 (outs GR8 :$dst), (ins),
2748 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2749 TB; // GR8 = < unsign
2750 def SETBm : I<0x92, MRM0m,
2751 (outs), (ins i8mem:$dst),
2753 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2754 TB; // [mem8] = < unsign
2756 def SETAEr : I<0x93, MRM0r,
2757 (outs GR8 :$dst), (ins),
2759 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2760 TB; // GR8 = >= unsign
2761 def SETAEm : I<0x93, MRM0m,
2762 (outs), (ins i8mem:$dst),
2764 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2765 TB; // [mem8] = >= unsign
2767 def SETBEr : I<0x96, MRM0r,
2768 (outs GR8 :$dst), (ins),
2770 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2771 TB; // GR8 = <= unsign
2772 def SETBEm : I<0x96, MRM0m,
2773 (outs), (ins i8mem:$dst),
2775 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2776 TB; // [mem8] = <= unsign
2778 def SETAr : I<0x97, MRM0r,
2779 (outs GR8 :$dst), (ins),
2781 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2782 TB; // GR8 = > signed
2783 def SETAm : I<0x97, MRM0m,
2784 (outs), (ins i8mem:$dst),
2786 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2787 TB; // [mem8] = > signed
2789 def SETSr : I<0x98, MRM0r,
2790 (outs GR8 :$dst), (ins),
2792 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2793 TB; // GR8 = <sign bit>
2794 def SETSm : I<0x98, MRM0m,
2795 (outs), (ins i8mem:$dst),
2797 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2798 TB; // [mem8] = <sign bit>
2799 def SETNSr : I<0x99, MRM0r,
2800 (outs GR8 :$dst), (ins),
2802 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2803 TB; // GR8 = !<sign bit>
2804 def SETNSm : I<0x99, MRM0m,
2805 (outs), (ins i8mem:$dst),
2807 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2808 TB; // [mem8] = !<sign bit>
2810 def SETPr : I<0x9A, MRM0r,
2811 (outs GR8 :$dst), (ins),
2813 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2815 def SETPm : I<0x9A, MRM0m,
2816 (outs), (ins i8mem:$dst),
2818 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2819 TB; // [mem8] = parity
2820 def SETNPr : I<0x9B, MRM0r,
2821 (outs GR8 :$dst), (ins),
2823 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2824 TB; // GR8 = not parity
2825 def SETNPm : I<0x9B, MRM0m,
2826 (outs), (ins i8mem:$dst),
2828 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2829 TB; // [mem8] = not parity
2831 def SETOr : I<0x90, MRM0r,
2832 (outs GR8 :$dst), (ins),
2834 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2835 TB; // GR8 = overflow
2836 def SETOm : I<0x90, MRM0m,
2837 (outs), (ins i8mem:$dst),
2839 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2840 TB; // [mem8] = overflow
2841 def SETNOr : I<0x91, MRM0r,
2842 (outs GR8 :$dst), (ins),
2844 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2845 TB; // GR8 = not overflow
2846 def SETNOm : I<0x91, MRM0m,
2847 (outs), (ins i8mem:$dst),
2849 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2850 TB; // [mem8] = not overflow
2851 } // Uses = [EFLAGS]
2854 // Integer comparisons
2855 let Defs = [EFLAGS] in {
2856 def CMP8rr : I<0x38, MRMDestReg,
2857 (outs), (ins GR8 :$src1, GR8 :$src2),
2858 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2859 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2860 def CMP16rr : I<0x39, MRMDestReg,
2861 (outs), (ins GR16:$src1, GR16:$src2),
2862 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2863 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2864 def CMP32rr : I<0x39, MRMDestReg,
2865 (outs), (ins GR32:$src1, GR32:$src2),
2866 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2867 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2868 def CMP8mr : I<0x38, MRMDestMem,
2869 (outs), (ins i8mem :$src1, GR8 :$src2),
2870 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2871 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2872 (implicit EFLAGS)]>;
2873 def CMP16mr : I<0x39, MRMDestMem,
2874 (outs), (ins i16mem:$src1, GR16:$src2),
2875 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2876 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2877 (implicit EFLAGS)]>, OpSize;
2878 def CMP32mr : I<0x39, MRMDestMem,
2879 (outs), (ins i32mem:$src1, GR32:$src2),
2880 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2881 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2882 (implicit EFLAGS)]>;
2883 def CMP8rm : I<0x3A, MRMSrcMem,
2884 (outs), (ins GR8 :$src1, i8mem :$src2),
2885 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2886 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2887 (implicit EFLAGS)]>;
2888 def CMP16rm : I<0x3B, MRMSrcMem,
2889 (outs), (ins GR16:$src1, i16mem:$src2),
2890 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2891 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2892 (implicit EFLAGS)]>, OpSize;
2893 def CMP32rm : I<0x3B, MRMSrcMem,
2894 (outs), (ins GR32:$src1, i32mem:$src2),
2895 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2896 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2897 (implicit EFLAGS)]>;
2898 def CMP8ri : Ii8<0x80, MRM7r,
2899 (outs), (ins GR8:$src1, i8imm:$src2),
2900 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2901 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2902 def CMP16ri : Ii16<0x81, MRM7r,
2903 (outs), (ins GR16:$src1, i16imm:$src2),
2904 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2905 [(X86cmp GR16:$src1, imm:$src2),
2906 (implicit EFLAGS)]>, OpSize;
2907 def CMP32ri : Ii32<0x81, MRM7r,
2908 (outs), (ins GR32:$src1, i32imm:$src2),
2909 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2910 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2911 def CMP8mi : Ii8 <0x80, MRM7m,
2912 (outs), (ins i8mem :$src1, i8imm :$src2),
2913 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2914 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2915 (implicit EFLAGS)]>;
2916 def CMP16mi : Ii16<0x81, MRM7m,
2917 (outs), (ins i16mem:$src1, i16imm:$src2),
2918 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2919 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2920 (implicit EFLAGS)]>, OpSize;
2921 def CMP32mi : Ii32<0x81, MRM7m,
2922 (outs), (ins i32mem:$src1, i32imm:$src2),
2923 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2924 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2925 (implicit EFLAGS)]>;
2926 def CMP16ri8 : Ii8<0x83, MRM7r,
2927 (outs), (ins GR16:$src1, i16i8imm:$src2),
2928 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2929 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2930 (implicit EFLAGS)]>, OpSize;
2931 def CMP16mi8 : Ii8<0x83, MRM7m,
2932 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2933 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2934 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2935 (implicit EFLAGS)]>, OpSize;
2936 def CMP32mi8 : Ii8<0x83, MRM7m,
2937 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2938 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2939 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2940 (implicit EFLAGS)]>;
2941 def CMP32ri8 : Ii8<0x83, MRM7r,
2942 (outs), (ins GR32:$src1, i32i8imm:$src2),
2943 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2944 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2945 (implicit EFLAGS)]>;
2946 } // Defs = [EFLAGS]
2949 // TODO: BTC, BTR, and BTS
2950 let Defs = [EFLAGS] in {
2951 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2952 "bt{w}\t{$src2, $src1|$src1, $src2}",
2953 [(X86bt GR16:$src1, GR16:$src2),
2954 (implicit EFLAGS)]>, OpSize, TB;
2955 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2956 "bt{l}\t{$src2, $src1|$src1, $src2}",
2957 [(X86bt GR32:$src1, GR32:$src2),
2958 (implicit EFLAGS)]>, TB;
2960 // Unlike with the register+register form, the memory+register form of the
2961 // bt instruction does not ignore the high bits of the index. From ISel's
2962 // perspective, this is pretty bizarre. Disable these instructions for now.
2963 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2964 // "bt{w}\t{$src2, $src1|$src1, $src2}",
2965 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
2966 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2967 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2968 // "bt{l}\t{$src2, $src1|$src1, $src2}",
2969 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
2970 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
2972 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2973 "bt{w}\t{$src2, $src1|$src1, $src2}",
2974 [(X86bt GR16:$src1, i16immSExt8:$src2),
2975 (implicit EFLAGS)]>, OpSize, TB;
2976 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2977 "bt{l}\t{$src2, $src1|$src1, $src2}",
2978 [(X86bt GR32:$src1, i32immSExt8:$src2),
2979 (implicit EFLAGS)]>, TB;
2980 // Note that these instructions don't need FastBTMem because that
2981 // only applies when the other operand is in a register. When it's
2982 // an immediate, bt is still fast.
2983 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2984 "bt{w}\t{$src2, $src1|$src1, $src2}",
2985 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
2986 (implicit EFLAGS)]>, OpSize, TB;
2987 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2988 "bt{l}\t{$src2, $src1|$src1, $src2}",
2989 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
2990 (implicit EFLAGS)]>, TB;
2991 } // Defs = [EFLAGS]
2993 // Sign/Zero extenders
2994 // Use movsbl intead of movsbw; we don't care about the high 16 bits
2995 // of the register here. This has a smaller encoding and avoids a
2996 // partial-register update.
2997 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2998 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2999 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3000 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3001 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3002 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3003 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3004 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3005 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3006 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3007 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3008 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3009 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3010 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3011 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3012 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3013 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3014 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3016 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3017 // of the register here. This has a smaller encoding and avoids a
3018 // partial-register update.
3019 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3020 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3021 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3022 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3023 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3024 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3025 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3026 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3027 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3028 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3029 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3030 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3031 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3032 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3033 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3034 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3035 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3036 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3038 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3039 // except that they use GR32_NOREX for the output operand register class
3040 // instead of GR32. This allows them to operate on h registers on x86-64.
3041 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3042 (outs GR32_NOREX:$dst), (ins GR8:$src),
3043 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3046 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3047 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3048 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3051 let neverHasSideEffects = 1 in {
3052 let Defs = [AX], Uses = [AL] in
3053 def CBW : I<0x98, RawFrm, (outs), (ins),
3054 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3055 let Defs = [EAX], Uses = [AX] in
3056 def CWDE : I<0x98, RawFrm, (outs), (ins),
3057 "{cwtl|cwde}", []>; // EAX = signext(AX)
3059 let Defs = [AX,DX], Uses = [AX] in
3060 def CWD : I<0x99, RawFrm, (outs), (ins),
3061 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3062 let Defs = [EAX,EDX], Uses = [EAX] in
3063 def CDQ : I<0x99, RawFrm, (outs), (ins),
3064 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3067 //===----------------------------------------------------------------------===//
3068 // Alias Instructions
3069 //===----------------------------------------------------------------------===//
3071 // Alias instructions that map movr0 to xor.
3072 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3073 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3074 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3075 "xor{b}\t$dst, $dst",
3076 [(set GR8:$dst, 0)]>;
3077 // Use xorl instead of xorw since we don't care about the high 16 bits,
3078 // it's smaller, and it avoids a partial-register update.
3079 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3080 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3081 [(set GR16:$dst, 0)]>;
3082 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3083 "xor{l}\t$dst, $dst",
3084 [(set GR32:$dst, 0)]>;
3087 //===----------------------------------------------------------------------===//
3088 // Thread Local Storage Instructions
3091 // All calls clobber the non-callee saved registers. ESP is marked as
3092 // a use to prevent stack-pointer assignments that appear immediately
3093 // before calls from potentially appearing dead.
3094 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3095 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3096 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3097 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3098 Uses = [ESP, EBX] in
3099 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32imm:$sym),
3100 "leal\t${sym:mem}(,%ebx,1), %eax; "
3101 "call\t___tls_get_addr@PLT",
3102 [(X86tlsaddr tglobaltlsaddr:$sym)]>,
3103 Requires<[In32BitMode]>;
3105 let AddedComplexity = 5 in
3106 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3107 "movl\t%gs:$src, $dst",
3108 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3110 let AddedComplexity = 5 in
3111 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3112 "movl\t%fs:$src, $dst",
3113 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3115 //===----------------------------------------------------------------------===//
3116 // DWARF Pseudo Instructions
3119 def DWARF_LOC : I<0, Pseudo, (outs),
3120 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3121 ".loc\t${file:debug} ${line:debug} ${col:debug}",
3122 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3125 //===----------------------------------------------------------------------===//
3126 // EH Pseudo Instructions
3128 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3130 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3131 "ret\t#eh_return, addr: $addr",
3132 [(X86ehret GR32:$addr)]>;
3136 //===----------------------------------------------------------------------===//
3140 // Atomic swap. These are just normal xchg instructions. But since a memory
3141 // operand is referenced, the atomicity is ensured.
3142 let Constraints = "$val = $dst" in {
3143 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3144 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3145 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3146 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3147 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3148 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3150 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3151 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3152 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3155 // Atomic compare and swap.
3156 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3157 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3159 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3160 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3162 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3163 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3166 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3169 let Defs = [AX, EFLAGS], Uses = [AX] in {
3170 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3172 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3173 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3175 let Defs = [AL, EFLAGS], Uses = [AL] in {
3176 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3178 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3179 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3182 // Atomic exchange and add
3183 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3184 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3186 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3187 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3189 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3191 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3192 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3194 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3196 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3197 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3201 // Atomic exchange, and, or, xor
3202 let Constraints = "$val = $dst", Defs = [EFLAGS],
3203 usesCustomDAGSchedInserter = 1 in {
3204 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3205 "#ATOMAND32 PSEUDO!",
3206 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3207 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3208 "#ATOMOR32 PSEUDO!",
3209 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3210 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3211 "#ATOMXOR32 PSEUDO!",
3212 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3213 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3214 "#ATOMNAND32 PSEUDO!",
3215 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3216 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3217 "#ATOMMIN32 PSEUDO!",
3218 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3219 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3220 "#ATOMMAX32 PSEUDO!",
3221 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3222 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3223 "#ATOMUMIN32 PSEUDO!",
3224 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3225 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3226 "#ATOMUMAX32 PSEUDO!",
3227 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3229 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3230 "#ATOMAND16 PSEUDO!",
3231 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3232 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3233 "#ATOMOR16 PSEUDO!",
3234 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3235 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3236 "#ATOMXOR16 PSEUDO!",
3237 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3238 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3239 "#ATOMNAND16 PSEUDO!",
3240 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3241 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3242 "#ATOMMIN16 PSEUDO!",
3243 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3244 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3245 "#ATOMMAX16 PSEUDO!",
3246 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3247 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3248 "#ATOMUMIN16 PSEUDO!",
3249 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3250 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3251 "#ATOMUMAX16 PSEUDO!",
3252 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3254 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3255 "#ATOMAND8 PSEUDO!",
3256 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3257 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3259 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3260 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3261 "#ATOMXOR8 PSEUDO!",
3262 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3263 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3264 "#ATOMNAND8 PSEUDO!",
3265 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3268 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3269 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3270 Uses = [EAX, EBX, ECX, EDX],
3271 mayLoad = 1, mayStore = 1,
3272 usesCustomDAGSchedInserter = 1 in {
3273 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3274 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3275 "#ATOMAND6432 PSEUDO!", []>;
3276 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3277 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3278 "#ATOMOR6432 PSEUDO!", []>;
3279 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3280 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3281 "#ATOMXOR6432 PSEUDO!", []>;
3282 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3283 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3284 "#ATOMNAND6432 PSEUDO!", []>;
3285 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3286 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3287 "#ATOMADD6432 PSEUDO!", []>;
3288 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3289 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3290 "#ATOMSUB6432 PSEUDO!", []>;
3291 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3292 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3293 "#ATOMSWAP6432 PSEUDO!", []>;
3296 //===----------------------------------------------------------------------===//
3297 // Non-Instruction Patterns
3298 //===----------------------------------------------------------------------===//
3300 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3301 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3302 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3303 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3304 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3305 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3307 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3308 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3309 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3310 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3311 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3312 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3313 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3314 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3316 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3317 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3318 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3319 (MOV32mi addr:$dst, texternalsym:$src)>;
3323 def : Pat<(X86tailcall GR32:$dst),
3326 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3328 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3331 def : Pat<(X86tcret GR32:$dst, imm:$off),
3332 (TCRETURNri GR32:$dst, imm:$off)>;
3334 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3335 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3337 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3338 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3340 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3341 (CALLpcrel32 tglobaladdr:$dst)>;
3342 def : Pat<(X86call (i32 texternalsym:$dst)),
3343 (CALLpcrel32 texternalsym:$dst)>;
3344 def : Pat<(X86call (i32 imm:$dst)),
3345 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3347 // X86 specific add which produces a flag.
3348 def : Pat<(addc GR32:$src1, GR32:$src2),
3349 (ADD32rr GR32:$src1, GR32:$src2)>;
3350 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3351 (ADD32rm GR32:$src1, addr:$src2)>;
3352 def : Pat<(addc GR32:$src1, imm:$src2),
3353 (ADD32ri GR32:$src1, imm:$src2)>;
3354 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3355 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3357 def : Pat<(subc GR32:$src1, GR32:$src2),
3358 (SUB32rr GR32:$src1, GR32:$src2)>;
3359 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3360 (SUB32rm GR32:$src1, addr:$src2)>;
3361 def : Pat<(subc GR32:$src1, imm:$src2),
3362 (SUB32ri GR32:$src1, imm:$src2)>;
3363 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3364 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3368 // TEST R,R is smaller than CMP R,0
3369 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3370 (TEST8rr GR8:$src1, GR8:$src1)>;
3371 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3372 (TEST16rr GR16:$src1, GR16:$src1)>;
3373 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3374 (TEST32rr GR32:$src1, GR32:$src1)>;
3376 // Conditional moves with folded loads with operands swapped and conditions
3378 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3379 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3380 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3381 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3382 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3383 (CMOVB16rm GR16:$src2, addr:$src1)>;
3384 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3385 (CMOVB32rm GR32:$src2, addr:$src1)>;
3386 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3387 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3388 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3389 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3390 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3391 (CMOVE16rm GR16:$src2, addr:$src1)>;
3392 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3393 (CMOVE32rm GR32:$src2, addr:$src1)>;
3394 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3395 (CMOVA16rm GR16:$src2, addr:$src1)>;
3396 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3397 (CMOVA32rm GR32:$src2, addr:$src1)>;
3398 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3399 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3400 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3401 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3402 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3403 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3404 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3405 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3406 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3407 (CMOVL16rm GR16:$src2, addr:$src1)>;
3408 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3409 (CMOVL32rm GR32:$src2, addr:$src1)>;
3410 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3411 (CMOVG16rm GR16:$src2, addr:$src1)>;
3412 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3413 (CMOVG32rm GR32:$src2, addr:$src1)>;
3414 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3415 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3416 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3417 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3418 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3419 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3420 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3421 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3422 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3423 (CMOVP16rm GR16:$src2, addr:$src1)>;
3424 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3425 (CMOVP32rm GR32:$src2, addr:$src1)>;
3426 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3427 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3428 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3429 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3430 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3431 (CMOVS16rm GR16:$src2, addr:$src1)>;
3432 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3433 (CMOVS32rm GR32:$src2, addr:$src1)>;
3434 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3435 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3436 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3437 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3438 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3439 (CMOVO16rm GR16:$src2, addr:$src1)>;
3440 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3441 (CMOVO32rm GR32:$src2, addr:$src1)>;
3443 // zextload bool -> zextload byte
3444 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3445 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3446 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3448 // extload bool -> extload byte
3449 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3450 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3451 Requires<[In32BitMode]>;
3452 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3453 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3454 Requires<[In32BitMode]>;
3455 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3456 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3459 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3460 Requires<[In32BitMode]>;
3461 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3462 Requires<[In32BitMode]>;
3463 def : Pat<(i32 (anyext GR16:$src)),
3464 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3466 // (and (i32 load), 255) -> (zextload i8)
3467 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3468 (MOVZX32rm8 addr:$src)>;
3469 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3470 (MOVZX32rm16 addr:$src)>;
3472 //===----------------------------------------------------------------------===//
3474 //===----------------------------------------------------------------------===//
3476 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3477 // +128 doesn't, so in this special case use a sub instead of an add.
3478 def : Pat<(add GR16:$src1, 128),
3479 (SUB16ri8 GR16:$src1, -128)>;
3480 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3481 (SUB16mi8 addr:$dst, -128)>;
3482 def : Pat<(add GR32:$src1, 128),
3483 (SUB32ri8 GR32:$src1, -128)>;
3484 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3485 (SUB32mi8 addr:$dst, -128)>;
3487 // r & (2^16-1) ==> movz
3488 def : Pat<(and GR32:$src1, 0xffff),
3489 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3490 // r & (2^8-1) ==> movz
3491 def : Pat<(and GR32:$src1, 0xff),
3492 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3494 Requires<[In32BitMode]>;
3495 // r & (2^8-1) ==> movz
3496 def : Pat<(and GR16:$src1, 0xff),
3497 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3499 Requires<[In32BitMode]>;
3501 // sext_inreg patterns
3502 def : Pat<(sext_inreg GR32:$src, i16),
3503 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3504 def : Pat<(sext_inreg GR32:$src, i8),
3505 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3507 Requires<[In32BitMode]>;
3508 def : Pat<(sext_inreg GR16:$src, i8),
3509 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3511 Requires<[In32BitMode]>;
3514 def : Pat<(i16 (trunc GR32:$src)),
3515 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3516 def : Pat<(i8 (trunc GR32:$src)),
3517 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3519 Requires<[In32BitMode]>;
3520 def : Pat<(i8 (trunc GR16:$src)),
3521 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3523 Requires<[In32BitMode]>;
3525 // h-register tricks
3526 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3527 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3528 x86_subreg_8bit_hi)>,
3529 Requires<[In32BitMode]>;
3530 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3531 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3532 x86_subreg_8bit_hi)>,
3533 Requires<[In32BitMode]>;
3534 def : Pat<(srl_su GR16:$src, (i8 8)),
3537 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3538 x86_subreg_8bit_hi)),
3540 Requires<[In32BitMode]>;
3541 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3542 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3543 x86_subreg_8bit_hi))>,
3544 Requires<[In32BitMode]>;
3545 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3546 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3547 x86_subreg_8bit_hi))>,
3548 Requires<[In32BitMode]>;
3550 // (shl x, 1) ==> (add x, x)
3551 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3552 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3553 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3555 // (shl x (and y, 31)) ==> (shl x, y)
3556 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3557 (SHL8rCL GR8:$src1)>;
3558 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3559 (SHL16rCL GR16:$src1)>;
3560 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3561 (SHL32rCL GR32:$src1)>;
3562 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3563 (SHL8mCL addr:$dst)>;
3564 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3565 (SHL16mCL addr:$dst)>;
3566 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3567 (SHL32mCL addr:$dst)>;
3569 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3570 (SHR8rCL GR8:$src1)>;
3571 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3572 (SHR16rCL GR16:$src1)>;
3573 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3574 (SHR32rCL GR32:$src1)>;
3575 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3576 (SHR8mCL addr:$dst)>;
3577 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3578 (SHR16mCL addr:$dst)>;
3579 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3580 (SHR32mCL addr:$dst)>;
3582 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3583 (SAR8rCL GR8:$src1)>;
3584 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3585 (SAR16rCL GR16:$src1)>;
3586 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3587 (SAR32rCL GR32:$src1)>;
3588 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3589 (SAR8mCL addr:$dst)>;
3590 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3591 (SAR16mCL addr:$dst)>;
3592 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3593 (SAR32mCL addr:$dst)>;
3595 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3596 def : Pat<(or (srl GR32:$src1, CL:$amt),
3597 (shl GR32:$src2, (sub 32, CL:$amt))),
3598 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3600 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3601 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3602 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3604 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3605 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3606 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3608 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3609 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3611 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3613 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3614 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3616 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3617 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3618 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3620 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3621 def : Pat<(or (shl GR32:$src1, CL:$amt),
3622 (srl GR32:$src2, (sub 32, CL:$amt))),
3623 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3625 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3626 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3627 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3629 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3630 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3631 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3633 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3634 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3636 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3638 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3639 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3641 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3642 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3643 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3645 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3646 def : Pat<(or (srl GR16:$src1, CL:$amt),
3647 (shl GR16:$src2, (sub 16, CL:$amt))),
3648 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3650 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3651 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3652 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3654 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3655 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3656 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3658 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3659 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3661 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3663 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3664 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3666 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3667 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3668 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3670 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3671 def : Pat<(or (shl GR16:$src1, CL:$amt),
3672 (srl GR16:$src2, (sub 16, CL:$amt))),
3673 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3675 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3676 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3677 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3679 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3680 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3681 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3683 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3684 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3686 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3688 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3689 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3691 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3692 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3693 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3695 //===----------------------------------------------------------------------===//
3696 // EFLAGS-defining Patterns
3697 //===----------------------------------------------------------------------===//
3699 // Register-Register Addition with EFLAGS result
3700 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3702 (ADD8rr GR8:$src1, GR8:$src2)>;
3703 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3705 (ADD16rr GR16:$src1, GR16:$src2)>;
3706 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3708 (ADD32rr GR32:$src1, GR32:$src2)>;
3710 // Register-Memory Addition with EFLAGS result
3711 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3713 (ADD8rm GR8:$src1, addr:$src2)>;
3714 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3716 (ADD16rm GR16:$src1, addr:$src2)>;
3717 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3719 (ADD32rm GR32:$src1, addr:$src2)>;
3721 // Register-Integer Addition with EFLAGS result
3722 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3724 (ADD8ri GR8:$src1, imm:$src2)>;
3725 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3727 (ADD16ri GR16:$src1, imm:$src2)>;
3728 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3730 (ADD32ri GR32:$src1, imm:$src2)>;
3731 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3733 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3734 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3736 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3738 // Memory-Register Addition with EFLAGS result
3739 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3742 (ADD8mr addr:$dst, GR8:$src2)>;
3743 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3746 (ADD16mr addr:$dst, GR16:$src2)>;
3747 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3750 (ADD32mr addr:$dst, GR32:$src2)>;
3752 // Memory-Integer Addition with EFLAGS result
3753 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3756 (ADD8mi addr:$dst, imm:$src2)>;
3757 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3760 (ADD16mi addr:$dst, imm:$src2)>;
3761 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3764 (ADD32mi addr:$dst, imm:$src2)>;
3765 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3768 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3769 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3772 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3774 // Register-Register Subtraction with EFLAGS result
3775 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3777 (SUB8rr GR8:$src1, GR8:$src2)>;
3778 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3780 (SUB16rr GR16:$src1, GR16:$src2)>;
3781 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3783 (SUB32rr GR32:$src1, GR32:$src2)>;
3785 // Register-Memory Subtraction with EFLAGS result
3786 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3788 (SUB8rm GR8:$src1, addr:$src2)>;
3789 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3791 (SUB16rm GR16:$src1, addr:$src2)>;
3792 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3794 (SUB32rm GR32:$src1, addr:$src2)>;
3796 // Register-Integer Subtraction with EFLAGS result
3797 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3799 (SUB8ri GR8:$src1, imm:$src2)>;
3800 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3802 (SUB16ri GR16:$src1, imm:$src2)>;
3803 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
3805 (SUB32ri GR32:$src1, imm:$src2)>;
3806 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
3808 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3809 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
3811 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3813 // Memory-Register Subtraction with EFLAGS result
3814 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
3817 (SUB8mr addr:$dst, GR8:$src2)>;
3818 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
3821 (SUB16mr addr:$dst, GR16:$src2)>;
3822 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
3825 (SUB32mr addr:$dst, GR32:$src2)>;
3827 // Memory-Integer Subtraction with EFLAGS result
3828 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
3831 (SUB8mi addr:$dst, imm:$src2)>;
3832 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
3835 (SUB16mi addr:$dst, imm:$src2)>;
3836 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
3839 (SUB32mi addr:$dst, imm:$src2)>;
3840 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3843 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3844 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3847 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3850 // Register-Register Signed Integer Multiply with EFLAGS result
3851 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
3853 (IMUL16rr GR16:$src1, GR16:$src2)>;
3854 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
3856 (IMUL32rr GR32:$src1, GR32:$src2)>;
3858 // Register-Memory Signed Integer Multiply with EFLAGS result
3859 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
3861 (IMUL16rm GR16:$src1, addr:$src2)>;
3862 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
3864 (IMUL32rm GR32:$src1, addr:$src2)>;
3866 // Register-Integer Signed Integer Multiply with EFLAGS result
3867 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
3869 (IMUL16rri GR16:$src1, imm:$src2)>;
3870 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
3872 (IMUL32rri GR32:$src1, imm:$src2)>;
3873 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
3875 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
3876 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
3878 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3880 // Memory-Integer Signed Integer Multiply with EFLAGS result
3881 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
3883 (IMUL16rmi addr:$src1, imm:$src2)>;
3884 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
3886 (IMUL32rmi addr:$src1, imm:$src2)>;
3887 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
3889 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
3890 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
3892 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3894 // Optimize multiply by 2 with EFLAGS result.
3895 let AddedComplexity = 2 in {
3896 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
3898 (ADD16rr GR16:$src1, GR16:$src1)>;
3900 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
3902 (ADD32rr GR32:$src1, GR32:$src1)>;
3905 // INC and DEC with EFLAGS result. Note that these do not set CF.
3906 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
3908 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
3911 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
3913 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
3917 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
3918 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
3919 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
3921 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
3922 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
3923 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
3924 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
3926 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
3928 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
3929 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
3930 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
3932 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
3933 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
3934 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
3935 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
3937 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
3939 //===----------------------------------------------------------------------===//
3940 // Floating Point Stack Support
3941 //===----------------------------------------------------------------------===//
3943 include "X86InstrFPStack.td"
3945 //===----------------------------------------------------------------------===//
3947 //===----------------------------------------------------------------------===//
3949 include "X86Instr64bit.td"
3951 //===----------------------------------------------------------------------===//
3952 // XMM Floating point support (requires SSE / SSE2)
3953 //===----------------------------------------------------------------------===//
3955 include "X86InstrSSE.td"
3957 //===----------------------------------------------------------------------===//
3958 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3959 //===----------------------------------------------------------------------===//
3961 include "X86InstrMMX.td"