1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
73 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
75 def SDTX86Void : SDTypeProfile<0, 0, []>;
77 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
79 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
83 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
85 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
87 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
88 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
90 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
92 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
94 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
96 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
98 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
102 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
103 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
104 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
105 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
107 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
108 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
110 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
111 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
113 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
114 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
116 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
117 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
120 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
123 [SDNPHasChain, SDNPMayStore,
124 SDNPMayLoad, SDNPMemOperand]>;
125 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
126 [SDNPHasChain, SDNPMayStore,
127 SDNPMayLoad, SDNPMemOperand]>;
128 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
129 [SDNPHasChain, SDNPMayStore,
130 SDNPMayLoad, SDNPMemOperand]>;
131 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
132 [SDNPHasChain, SDNPMayStore,
133 SDNPMayLoad, SDNPMemOperand]>;
134 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
135 [SDNPHasChain, SDNPMayStore,
136 SDNPMayLoad, SDNPMemOperand]>;
137 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
138 [SDNPHasChain, SDNPMayStore,
139 SDNPMayLoad, SDNPMemOperand]>;
140 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
141 [SDNPHasChain, SDNPMayStore,
142 SDNPMayLoad, SDNPMemOperand]>;
143 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
144 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
146 def X86vastart_save_xmm_regs :
147 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
148 SDT_X86VASTART_SAVE_XMM_REGS,
149 [SDNPHasChain, SDNPVariadic]>;
151 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
152 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
154 def X86callseq_start :
155 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
156 [SDNPHasChain, SDNPOutFlag]>;
158 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
159 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
161 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
162 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
165 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
166 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
167 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
168 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
171 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
172 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
174 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
175 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
177 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
178 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
180 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
183 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
184 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
186 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
188 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
189 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
191 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
194 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
195 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
196 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
198 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
200 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
203 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
205 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
206 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
208 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
211 //===----------------------------------------------------------------------===//
212 // X86 Operand Definitions.
215 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
216 // the index operand of an address, to conform to x86 encoding restrictions.
217 def ptr_rc_nosp : PointerLikeRegClass<1>;
219 // *mem - Operand definitions for the funky X86 addressing mode operands.
221 def X86MemAsmOperand : AsmOperandClass {
223 let SuperClasses = [];
225 def X86AbsMemAsmOperand : AsmOperandClass {
227 let SuperClasses = [X86MemAsmOperand];
229 class X86MemOperand<string printMethod> : Operand<iPTR> {
230 let PrintMethod = printMethod;
231 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
232 let ParserMatchClass = X86MemAsmOperand;
235 def opaque32mem : X86MemOperand<"printopaquemem">;
236 def opaque48mem : X86MemOperand<"printopaquemem">;
237 def opaque80mem : X86MemOperand<"printopaquemem">;
238 def opaque512mem : X86MemOperand<"printopaquemem">;
240 def i8mem : X86MemOperand<"printi8mem">;
241 def i16mem : X86MemOperand<"printi16mem">;
242 def i32mem : X86MemOperand<"printi32mem">;
243 def i64mem : X86MemOperand<"printi64mem">;
244 def i128mem : X86MemOperand<"printi128mem">;
245 def i256mem : X86MemOperand<"printi256mem">;
246 def f32mem : X86MemOperand<"printf32mem">;
247 def f64mem : X86MemOperand<"printf64mem">;
248 def f80mem : X86MemOperand<"printf80mem">;
249 def f128mem : X86MemOperand<"printf128mem">;
250 def f256mem : X86MemOperand<"printf256mem">;
252 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
253 // plain GR64, so that it doesn't potentially require a REX prefix.
254 def i8mem_NOREX : Operand<i64> {
255 let PrintMethod = "printi8mem";
256 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
257 let ParserMatchClass = X86MemAsmOperand;
260 // Special i32mem for addresses of load folding tail calls. These are not
261 // allowed to use callee-saved registers since they must be scheduled
262 // after callee-saved register are popped.
263 def i32mem_TC : Operand<i32> {
264 let PrintMethod = "printi32mem";
265 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
266 let ParserMatchClass = X86MemAsmOperand;
269 // Special i64mem for addresses of load folding tail calls. These are not
270 // allowed to use callee-saved registers since they must be scheduled
271 // after callee-saved register are popped.
272 def i64mem_TC : Operand<i64> {
273 let PrintMethod = "printi64mem";
274 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
275 let ParserMatchClass = X86MemAsmOperand;
278 let ParserMatchClass = X86AbsMemAsmOperand,
279 PrintMethod = "print_pcrel_imm" in {
280 def i32imm_pcrel : Operand<i32>;
281 def i16imm_pcrel : Operand<i16>;
283 def offset8 : Operand<i64>;
284 def offset16 : Operand<i64>;
285 def offset32 : Operand<i64>;
286 def offset64 : Operand<i64>;
288 // Branch targets have OtherVT type and print as pc-relative values.
289 def brtarget : Operand<OtherVT>;
290 def brtarget8 : Operand<OtherVT>;
294 def SSECC : Operand<i8> {
295 let PrintMethod = "printSSECC";
298 class ImmSExtAsmOperandClass : AsmOperandClass {
299 let SuperClasses = [ImmAsmOperand];
300 let RenderMethod = "addImmOperands";
303 // Sign-extended immediate classes. We don't need to define the full lattice
304 // here because there is no instruction with an ambiguity between ImmSExti64i32
307 // The strange ranges come from the fact that the assembler always works with
308 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
309 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
312 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
313 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
314 let Name = "ImmSExti64i32";
317 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
318 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
319 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
320 let Name = "ImmSExti16i8";
321 let SuperClasses = [ImmSExti64i32AsmOperand];
324 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
325 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
326 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
327 let Name = "ImmSExti32i8";
331 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
332 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
333 let Name = "ImmSExti64i8";
334 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
335 ImmSExti64i32AsmOperand];
338 // A couple of more descriptive operand definitions.
339 // 16-bits but only 8 bits are significant.
340 def i16i8imm : Operand<i16> {
341 let ParserMatchClass = ImmSExti16i8AsmOperand;
343 // 32-bits but only 8 bits are significant.
344 def i32i8imm : Operand<i32> {
345 let ParserMatchClass = ImmSExti32i8AsmOperand;
348 // 64-bits but only 32 bits are significant.
349 def i64i32imm : Operand<i64> {
350 let ParserMatchClass = ImmSExti64i32AsmOperand;
353 // 64-bits but only 32 bits are significant, and those bits are treated as being
355 def i64i32imm_pcrel : Operand<i64> {
356 let PrintMethod = "print_pcrel_imm";
357 let ParserMatchClass = X86AbsMemAsmOperand;
360 // 64-bits but only 8 bits are significant.
361 def i64i8imm : Operand<i64> {
362 let ParserMatchClass = ImmSExti64i8AsmOperand;
365 def lea64_32mem : Operand<i32> {
366 let PrintMethod = "printi32mem";
367 let AsmOperandLowerMethod = "lower_lea64_32mem";
368 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
369 let ParserMatchClass = X86MemAsmOperand;
373 //===----------------------------------------------------------------------===//
374 // X86 Complex Pattern Definitions.
377 // Define X86 specific addressing mode.
378 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
379 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
380 [add, sub, mul, X86mul_imm, shl, or, frameindex],
382 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
383 [tglobaltlsaddr], []>;
385 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
386 [add, sub, mul, X86mul_imm, shl, or, frameindex,
389 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
390 [tglobaltlsaddr], []>;
392 //===----------------------------------------------------------------------===//
393 // X86 Instruction Predicate Definitions.
394 def HasCMov : Predicate<"Subtarget->hasCMov()">;
395 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
397 // FIXME: temporary hack to let codegen assert or generate poor code in case
398 // no AVX version of the desired intructions is present, this is better for
399 // incremental dev (without fallbacks it's easier to spot what's missing)
400 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
401 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
402 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
403 def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
404 def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
405 def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
406 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
407 def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
408 def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
409 def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
411 def HasAVX : Predicate<"Subtarget->hasAVX()">;
412 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
413 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
414 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
415 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
416 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
417 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
418 def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
419 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
420 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
421 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
422 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
423 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
424 "TM.getCodeModel() != CodeModel::Kernel">;
425 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
426 "TM.getCodeModel() == CodeModel::Kernel">;
427 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
428 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
429 def OptForSize : Predicate<"OptForSize">;
430 def OptForSpeed : Predicate<"!OptForSize">;
431 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
432 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
433 def HasAES : Predicate<"Subtarget->hasAES()">;
435 //===----------------------------------------------------------------------===//
436 // X86 Instruction Format Definitions.
439 include "X86InstrFormats.td"
441 //===----------------------------------------------------------------------===//
442 // Pattern fragments...
445 // X86 specific condition code. These correspond to CondCode in
446 // X86InstrInfo.h. They must be kept in synch.
447 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
448 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
449 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
450 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
451 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
452 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
453 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
454 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
455 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
456 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
457 def X86_COND_NO : PatLeaf<(i8 10)>;
458 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
459 def X86_COND_NS : PatLeaf<(i8 12)>;
460 def X86_COND_O : PatLeaf<(i8 13)>;
461 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
462 def X86_COND_S : PatLeaf<(i8 15)>;
464 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
466 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
467 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
468 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
469 def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
470 def i64immZExt32 : PatLeaf<(i64 imm), [{
471 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
472 // unsignedsign extended field.
473 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
476 def i64immZExt32SExt8 : PatLeaf<(i64 imm), [{
477 uint64_t v = N->getZExtValue();
478 return v == (uint32_t)v && (int32_t)v == (int8_t)v;
481 // Helper fragments for loads.
482 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
483 // known to be 32-bit aligned or better. Ditto for i8 to i16.
484 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
485 LoadSDNode *LD = cast<LoadSDNode>(N);
486 ISD::LoadExtType ExtType = LD->getExtensionType();
487 if (ExtType == ISD::NON_EXTLOAD)
489 if (ExtType == ISD::EXTLOAD)
490 return LD->getAlignment() >= 2 && !LD->isVolatile();
494 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
495 LoadSDNode *LD = cast<LoadSDNode>(N);
496 ISD::LoadExtType ExtType = LD->getExtensionType();
497 if (ExtType == ISD::EXTLOAD)
498 return LD->getAlignment() >= 2 && !LD->isVolatile();
502 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
503 LoadSDNode *LD = cast<LoadSDNode>(N);
504 ISD::LoadExtType ExtType = LD->getExtensionType();
505 if (ExtType == ISD::NON_EXTLOAD)
507 if (ExtType == ISD::EXTLOAD)
508 return LD->getAlignment() >= 4 && !LD->isVolatile();
512 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
513 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
514 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
515 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
516 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
518 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
519 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
520 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
521 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
522 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
523 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
525 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
526 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
527 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
528 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
529 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
530 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
531 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
532 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
533 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
534 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
536 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
537 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
538 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
539 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
540 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
541 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
542 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
543 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
544 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
545 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
548 // An 'and' node with a single use.
549 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
550 return N->hasOneUse();
552 // An 'srl' node with a single use.
553 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
554 return N->hasOneUse();
556 // An 'trunc' node with a single use.
557 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
558 return N->hasOneUse();
561 //===----------------------------------------------------------------------===//
566 let neverHasSideEffects = 1 in {
567 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
568 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
569 "nop{w}\t$zero", []>, TB, OpSize;
570 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
571 "nop{l}\t$zero", []>, TB;
575 // Constructing a stack frame.
576 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
577 "enter\t$len, $lvl", []>;
579 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
580 def LEAVE : I<0xC9, RawFrm,
581 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
583 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
584 def LEAVE64 : I<0xC9, RawFrm,
585 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
587 //===----------------------------------------------------------------------===//
588 // Miscellaneous Instructions.
591 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
593 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
595 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
596 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
598 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
600 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
601 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
603 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
604 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
605 Requires<[In32BitMode]>;
608 let mayStore = 1 in {
609 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
611 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
612 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
614 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
616 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
617 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
619 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
620 "push{l}\t$imm", []>;
621 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
622 "push{w}\t$imm", []>, OpSize;
623 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
624 "push{l}\t$imm", []>;
626 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
627 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
628 Requires<[In32BitMode]>;
633 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
635 def POP64r : I<0x58, AddRegFrm,
636 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
637 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
638 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
640 let mayStore = 1 in {
641 def PUSH64r : I<0x50, AddRegFrm,
642 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
643 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
644 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
648 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
649 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
650 "push{q}\t$imm", []>;
651 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
652 "push{q}\t$imm", []>;
653 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
654 "push{q}\t$imm", []>;
657 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
658 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
659 Requires<[In64BitMode]>;
660 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
661 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
662 Requires<[In64BitMode]>;
666 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
667 mayLoad=1, neverHasSideEffects=1 in {
668 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
669 Requires<[In32BitMode]>;
671 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
672 mayStore=1, neverHasSideEffects=1 in {
673 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
674 Requires<[In32BitMode]>;
677 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
678 def BSWAP32r : I<0xC8, AddRegFrm,
679 (outs GR32:$dst), (ins GR32:$src),
681 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
683 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
685 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
686 } // Constraints = "$src = $dst"
688 // Bit scan instructions.
689 let Defs = [EFLAGS] in {
690 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
691 "bsf{w}\t{$src, $dst|$dst, $src}",
692 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
693 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
694 "bsf{w}\t{$src, $dst|$dst, $src}",
695 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
697 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
698 "bsf{l}\t{$src, $dst|$dst, $src}",
699 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
700 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
701 "bsf{l}\t{$src, $dst|$dst, $src}",
702 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
703 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
704 "bsf{q}\t{$src, $dst|$dst, $src}",
705 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
706 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
707 "bsf{q}\t{$src, $dst|$dst, $src}",
708 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
710 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
711 "bsr{w}\t{$src, $dst|$dst, $src}",
712 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
713 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
714 "bsr{w}\t{$src, $dst|$dst, $src}",
715 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
717 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
718 "bsr{l}\t{$src, $dst|$dst, $src}",
719 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
720 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
721 "bsr{l}\t{$src, $dst|$dst, $src}",
722 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
723 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
724 "bsr{q}\t{$src, $dst|$dst, $src}",
725 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
726 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
727 "bsr{q}\t{$src, $dst|$dst, $src}",
728 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
732 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
733 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
734 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
735 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
736 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
737 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
740 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
741 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
742 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
743 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
744 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
745 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
746 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
747 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
748 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
750 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
751 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
752 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
753 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
755 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
756 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
757 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
758 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
761 //===----------------------------------------------------------------------===//
762 // Move Instructions.
765 let neverHasSideEffects = 1 in {
766 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
767 "mov{b}\t{$src, $dst|$dst, $src}", []>;
768 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
769 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
770 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
771 "mov{l}\t{$src, $dst|$dst, $src}", []>;
772 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
773 "mov{q}\t{$src, $dst|$dst, $src}", []>;
775 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
776 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
777 "mov{b}\t{$src, $dst|$dst, $src}",
778 [(set GR8:$dst, imm:$src)]>;
779 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
780 "mov{w}\t{$src, $dst|$dst, $src}",
781 [(set GR16:$dst, imm:$src)]>, OpSize;
782 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
783 "mov{l}\t{$src, $dst|$dst, $src}",
784 [(set GR32:$dst, imm:$src)]>;
785 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
786 "movabs{q}\t{$src, $dst|$dst, $src}",
787 [(set GR64:$dst, imm:$src)]>;
788 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
789 "mov{q}\t{$src, $dst|$dst, $src}",
790 [(set GR64:$dst, i64immSExt32:$src)]>;
793 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
794 "mov{b}\t{$src, $dst|$dst, $src}",
795 [(store (i8 imm:$src), addr:$dst)]>;
796 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
797 "mov{w}\t{$src, $dst|$dst, $src}",
798 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
799 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
800 "mov{l}\t{$src, $dst|$dst, $src}",
801 [(store (i32 imm:$src), addr:$dst)]>;
802 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
803 "mov{q}\t{$src, $dst|$dst, $src}",
804 [(store i64immSExt32:$src, addr:$dst)]>;
806 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
807 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
808 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
809 "mov{b}\t{$src, %al|%al, $src}", []>,
810 Requires<[In32BitMode]>;
811 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
812 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
813 Requires<[In32BitMode]>;
814 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
815 "mov{l}\t{$src, %eax|%eax, $src}", []>,
816 Requires<[In32BitMode]>;
817 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
818 "mov{b}\t{%al, $dst|$dst, %al}", []>,
819 Requires<[In32BitMode]>;
820 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
821 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
822 Requires<[In32BitMode]>;
823 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
824 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
825 Requires<[In32BitMode]>;
827 // FIXME: These definitions are utterly broken
828 // Just leave them commented out for now because they're useless outside
829 // of the large code model, and most compilers won't generate the instructions
832 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
833 "mov{q}\t{$src, %rax|%rax, $src}", []>;
834 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
835 "mov{q}\t{$src, %rax|%rax, $src}", []>;
836 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
837 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
838 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
839 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
843 let isCodeGenOnly = 1 in {
844 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
845 "mov{b}\t{$src, $dst|$dst, $src}", []>;
846 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
847 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
848 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
849 "mov{l}\t{$src, $dst|$dst, $src}", []>;
850 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
851 "mov{q}\t{$src, $dst|$dst, $src}", []>;
854 let canFoldAsLoad = 1, isReMaterializable = 1 in {
855 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
856 "mov{b}\t{$src, $dst|$dst, $src}",
857 [(set GR8:$dst, (loadi8 addr:$src))]>;
858 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
859 "mov{w}\t{$src, $dst|$dst, $src}",
860 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
861 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
862 "mov{l}\t{$src, $dst|$dst, $src}",
863 [(set GR32:$dst, (loadi32 addr:$src))]>;
864 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
865 "mov{q}\t{$src, $dst|$dst, $src}",
866 [(set GR64:$dst, (load addr:$src))]>;
869 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
870 "mov{b}\t{$src, $dst|$dst, $src}",
871 [(store GR8:$src, addr:$dst)]>;
872 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
873 "mov{w}\t{$src, $dst|$dst, $src}",
874 [(store GR16:$src, addr:$dst)]>, OpSize;
875 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
876 "mov{l}\t{$src, $dst|$dst, $src}",
877 [(store GR32:$src, addr:$dst)]>;
878 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
879 "mov{q}\t{$src, $dst|$dst, $src}",
880 [(store GR64:$src, addr:$dst)]>;
882 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
883 // that they can be used for copying and storing h registers, which can't be
884 // encoded when a REX prefix is present.
885 let isCodeGenOnly = 1 in {
886 let neverHasSideEffects = 1 in
887 def MOV8rr_NOREX : I<0x88, MRMDestReg,
888 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
889 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
891 def MOV8mr_NOREX : I<0x88, MRMDestMem,
892 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
893 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
895 canFoldAsLoad = 1, isReMaterializable = 1 in
896 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
897 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
898 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
902 // Condition code ops, incl. set if equal/not equal/...
903 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
904 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
905 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
906 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
909 //===----------------------------------------------------------------------===//
910 // Bit tests instructions: BT, BTS, BTR, BTC.
912 let Defs = [EFLAGS] in {
913 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
914 "bt{w}\t{$src2, $src1|$src1, $src2}",
915 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
916 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
917 "bt{l}\t{$src2, $src1|$src1, $src2}",
918 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
919 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
920 "bt{q}\t{$src2, $src1|$src1, $src2}",
921 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
923 // Unlike with the register+register form, the memory+register form of the
924 // bt instruction does not ignore the high bits of the index. From ISel's
925 // perspective, this is pretty bizarre. Make these instructions disassembly
928 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
929 "bt{w}\t{$src2, $src1|$src1, $src2}",
930 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
931 // (implicit EFLAGS)]
933 >, OpSize, TB, Requires<[FastBTMem]>;
934 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
935 "bt{l}\t{$src2, $src1|$src1, $src2}",
936 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
937 // (implicit EFLAGS)]
939 >, TB, Requires<[FastBTMem]>;
940 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
941 "bt{q}\t{$src2, $src1|$src1, $src2}",
942 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
943 // (implicit EFLAGS)]
947 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
948 "bt{w}\t{$src2, $src1|$src1, $src2}",
949 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
951 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
952 "bt{l}\t{$src2, $src1|$src1, $src2}",
953 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
954 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
955 "bt{q}\t{$src2, $src1|$src1, $src2}",
956 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
958 // Note that these instructions don't need FastBTMem because that
959 // only applies when the other operand is in a register. When it's
960 // an immediate, bt is still fast.
961 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
962 "bt{w}\t{$src2, $src1|$src1, $src2}",
963 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
965 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
966 "bt{l}\t{$src2, $src1|$src1, $src2}",
967 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
969 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
970 "bt{q}\t{$src2, $src1|$src1, $src2}",
971 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
972 i64immSExt8:$src2))]>, TB;
975 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
976 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
977 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
978 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
979 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
980 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
981 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
982 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
983 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
984 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
985 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
986 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
987 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
988 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
989 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
990 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
991 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
992 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
993 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
994 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
995 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
996 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
997 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
998 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1000 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1001 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1002 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1003 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1004 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1005 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1006 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1007 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1008 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1009 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1010 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1011 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1012 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1013 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1014 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1015 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1016 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1017 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1018 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1019 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1020 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1021 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1022 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1023 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1025 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1026 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1027 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1028 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1029 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1030 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1031 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1032 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1033 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1034 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1035 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1036 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1037 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1038 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1039 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1040 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1041 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1042 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1043 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1044 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1045 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1046 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1047 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1048 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1049 } // Defs = [EFLAGS]
1052 //===----------------------------------------------------------------------===//
1057 // Atomic swap. These are just normal xchg instructions. But since a memory
1058 // operand is referenced, the atomicity is ensured.
1059 let Constraints = "$val = $dst" in {
1060 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1061 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1062 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1063 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1064 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1065 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1067 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1068 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1069 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1070 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1071 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1072 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1074 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1075 "xchg{b}\t{$val, $src|$src, $val}", []>;
1076 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1077 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1078 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1079 "xchg{l}\t{$val, $src|$src, $val}", []>;
1080 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1081 "xchg{q}\t{$val, $src|$src, $val}", []>;
1084 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1085 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1086 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1087 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
1088 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1089 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1093 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1094 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1095 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1096 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1097 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1098 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1099 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1100 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1102 let mayLoad = 1, mayStore = 1 in {
1103 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1104 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1105 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1106 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1107 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1108 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1109 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1110 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1114 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1115 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1116 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1117 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1118 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1119 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1120 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1121 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1123 let mayLoad = 1, mayStore = 1 in {
1124 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1125 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1126 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1127 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1128 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1129 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1130 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1131 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1134 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1135 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1136 "cmpxchg8b\t$dst", []>, TB;
1138 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1139 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1140 "cmpxchg16b\t$dst", []>, TB;
1144 // Lock instruction prefix
1145 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1147 // Rex64 instruction prefix
1148 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1150 // Data16 instruction prefix
1151 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1153 // Repeat string operation instruction prefixes
1154 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1155 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1156 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1157 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1158 // Repeat while not equal (used with CMPS and SCAS)
1159 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1163 // String manipulation instructions
1164 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1165 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1166 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1167 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1169 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1170 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1171 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1174 // Flag instructions
1175 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1176 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1177 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1178 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1179 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1180 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1181 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1183 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1185 // Table lookup instructions
1186 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1188 // ASCII Adjust After Addition
1189 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1190 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1192 // ASCII Adjust AX Before Division
1193 // sets AL, AH and EFLAGS and uses AL and AH
1194 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1195 "aad\t$src", []>, Requires<[In32BitMode]>;
1197 // ASCII Adjust AX After Multiply
1198 // sets AL, AH and EFLAGS and uses AL
1199 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1200 "aam\t$src", []>, Requires<[In32BitMode]>;
1202 // ASCII Adjust AL After Subtraction - sets
1203 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1204 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1206 // Decimal Adjust AL after Addition
1207 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1208 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1210 // Decimal Adjust AL after Subtraction
1211 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1212 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1214 // Check Array Index Against Bounds
1215 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1216 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1217 Requires<[In32BitMode]>;
1218 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1219 "bound\t{$src, $dst|$dst, $src}", []>,
1220 Requires<[In32BitMode]>;
1222 // Adjust RPL Field of Segment Selector
1223 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1224 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1225 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1226 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1228 //===----------------------------------------------------------------------===//
1230 //===----------------------------------------------------------------------===//
1232 include "X86InstrArithmetic.td"
1233 include "X86InstrCMovSetCC.td"
1234 include "X86InstrExtension.td"
1235 include "X86InstrControl.td"
1236 include "X86InstrShiftRotate.td"
1238 // X87 Floating Point Stack.
1239 include "X86InstrFPStack.td"
1241 // SIMD support (SSE, MMX and AVX)
1242 include "X86InstrFragmentsSIMD.td"
1244 // FMA - Fused Multiply-Add support (requires FMA)
1245 include "X86InstrFMA.td"
1247 // SSE, MMX and 3DNow! vector support.
1248 include "X86InstrSSE.td"
1249 include "X86InstrMMX.td"
1250 include "X86Instr3DNow.td"
1252 include "X86InstrVMX.td"
1254 // System instructions.
1255 include "X86InstrSystem.td"
1257 // Compiler Pseudo Instructions and Pat Patterns
1258 include "X86InstrCompiler.td"
1260 //===----------------------------------------------------------------------===//
1261 // Assembler Mnemonic Aliases
1262 //===----------------------------------------------------------------------===//
1264 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1265 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1267 def : MnemonicAlias<"cbw", "cbtw">;
1268 def : MnemonicAlias<"cwd", "cwtd">;
1269 def : MnemonicAlias<"cdq", "cltd">;
1270 def : MnemonicAlias<"cwde", "cwtl">;
1271 def : MnemonicAlias<"cdqe", "cltq">;
1273 // lret maps to lretl, it is not ambiguous with lretq.
1274 def : MnemonicAlias<"lret", "lretl">;
1276 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1277 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1278 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1279 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1280 def : MnemonicAlias<"popfd", "popfl">;
1282 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1283 // all modes. However: "push (addr)" and "push $42" should default to
1284 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1285 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1286 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1287 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1288 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1289 def : MnemonicAlias<"pushfd", "pushfl">;
1291 def : MnemonicAlias<"repe", "rep">;
1292 def : MnemonicAlias<"repz", "rep">;
1293 def : MnemonicAlias<"repnz", "repne">;
1295 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1296 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1298 def : MnemonicAlias<"salb", "shlb">;
1299 def : MnemonicAlias<"salw", "shlw">;
1300 def : MnemonicAlias<"sall", "shll">;
1301 def : MnemonicAlias<"salq", "shlq">;
1303 def : MnemonicAlias<"smovb", "movsb">;
1304 def : MnemonicAlias<"smovw", "movsw">;
1305 def : MnemonicAlias<"smovl", "movsl">;
1306 def : MnemonicAlias<"smovq", "movsq">;
1308 def : MnemonicAlias<"ud2a", "ud2">;
1309 def : MnemonicAlias<"verrw", "verr">;
1311 // System instruction aliases.
1312 def : MnemonicAlias<"iret", "iretl">;
1313 def : MnemonicAlias<"sysret", "sysretl">;
1315 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1316 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1317 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1318 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1319 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1320 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1321 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1322 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1325 // Floating point stack aliases.
1326 def : MnemonicAlias<"fcmovz", "fcmove">;
1327 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1328 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1329 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1330 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1331 def : MnemonicAlias<"fcomip", "fcompi">;
1332 def : MnemonicAlias<"fildq", "fildll">;
1333 def : MnemonicAlias<"fldcww", "fldcw">;
1334 def : MnemonicAlias<"fnstcww", "fnstcw">;
1335 def : MnemonicAlias<"fnstsww", "fnstsw">;
1336 def : MnemonicAlias<"fucomip", "fucompi">;
1337 def : MnemonicAlias<"fwait", "wait">;
1340 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1341 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1342 !strconcat(Prefix, NewCond, Suffix)>;
1344 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1345 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1346 /// example "setz" -> "sete".
1347 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1348 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1349 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1350 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1351 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1352 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1353 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1354 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1355 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1356 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1357 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1359 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1360 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1361 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1362 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1365 // Aliases for set<CC>
1366 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1367 // Aliases for j<CC>
1368 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1369 // Aliases for cmov<CC>{w,l,q}
1370 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1371 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1372 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1375 //===----------------------------------------------------------------------===//
1376 // Assembler Instruction Aliases
1377 //===----------------------------------------------------------------------===//
1379 // aad/aam default to base 10 if no operand is specified.
1380 def : InstAlias<"aad", (AAD8i8 10)>;
1381 def : InstAlias<"aam", (AAM8i8 10)>;
1384 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1385 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1386 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1387 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1389 // div and idiv aliases for explicit A register.
1390 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1391 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1392 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1393 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1394 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1395 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1396 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1397 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1398 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1399 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1400 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1401 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1402 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1403 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1404 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1405 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1409 // Various unary fpstack operations default to operating on on ST1.
1410 // For example, "fxch" -> "fxch %st(1)"
1411 def : InstAlias<"faddp", (ADD_FPrST0 ST1)>;
1412 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1413 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1414 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1415 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1416 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1417 def : InstAlias<"fxch", (XCH_F ST1)>;
1418 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1419 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1420 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1421 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1422 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1423 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1425 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1426 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1427 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1429 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst> {
1430 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"), (Inst RST:$op)>;
1431 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"), (Inst ST0)>;
1434 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1435 defm : FpUnaryAlias<"faddp", ADD_FPrST0>;
1436 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1437 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1438 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1439 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1440 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1441 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1442 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1443 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1444 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1445 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1446 defm : FpUnaryAlias<"fcomi", COM_FIr>;
1447 defm : FpUnaryAlias<"fucomi", UCOM_FIr>;
1448 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1449 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1452 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1453 // commute. We also allow fdivrp/fsubrp even though they don't commute, solely
1454 // because gas supports it.
1455 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op)>;
1456 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1457 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1458 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1460 // We accepts "fnstsw %eax" even though it only writes %ax.
1461 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1462 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1463 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1465 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1466 // this is compatible with what GAS does.
1467 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1468 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1469 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1470 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1472 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1473 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1474 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1475 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1476 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1477 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1478 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1480 // inb %dx -> inb %al, %dx
1481 def : InstAlias<"inb %dx", (IN8rr)>;
1482 def : InstAlias<"inw %dx", (IN16rr)>;
1483 def : InstAlias<"inl %dx", (IN32rr)>;
1484 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1485 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1486 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1489 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1490 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1491 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1492 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1493 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1494 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1495 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1497 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1498 // the move. All segment/mem forms are equivalent, this has the shortest
1500 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1501 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1503 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1504 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1506 // Match 'movq GR64, MMX' as an alias for movd.
1507 def : InstAlias<"movq $src, $dst", (MMX_MOVD64to64rr VR64:$dst, GR64:$src)>;
1508 def : InstAlias<"movq $src, $dst", (MMX_MOVD64from64rr GR64:$dst, VR64:$src)>;
1510 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1511 // alias for movsl. (as in rep; movsd)
1512 def : InstAlias<"movsd", (MOVSD)>;
1515 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>;
1516 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
1517 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>;
1518 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>;
1519 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src)>;
1520 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src)>;
1521 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src)>;
1524 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>;
1525 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src)>;
1526 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src)>;
1527 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src)>;
1528 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>;
1529 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>;
1530 // Note: No GR32->GR64 movzx form.
1532 // outb %dx -> outb %al, %dx
1533 def : InstAlias<"outb %dx", (OUT8rr)>;
1534 def : InstAlias<"outw %dx", (OUT16rr)>;
1535 def : InstAlias<"outl %dx", (OUT32rr)>;
1536 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1537 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1538 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1540 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1541 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1542 // errors, since its encoding is the most compact.
1543 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1545 // shld/shrd op,op -> shld op, op, 1
1546 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1547 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1548 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1549 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1550 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1551 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1553 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1554 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1555 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1556 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1557 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1558 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1560 /* FIXME: This is disabled because the asm matcher is currently incapable of
1561 * matching a fixed immediate like $1.
1562 // "shl X, $1" is an alias for "shl X".
1563 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1564 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1565 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1566 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1567 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1568 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1569 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1570 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1571 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1572 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1573 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1574 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1575 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1576 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1577 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1578 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1579 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1582 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1583 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1584 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1585 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1588 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1589 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1590 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1591 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1592 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1594 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1595 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1596 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1597 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1598 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;